From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v6,7/7] dmaengine: xilinx_dma: Drop SG support for VDMA IP From: Andrea Merello Message-Id: <20181120153151.18024-7-andrea.merello@gmail.com> Date: Tue, 20 Nov 2018 16:31:51 +0100 To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello List-ID: eGlsaW54X3ZkbWFfc3RhcnRfdHJhbnNmZXIoKSBpcyB1c2VkIG9ubHkgZm9yIFZETUEgSVAsIHN0 aWxsIGl0IGNvbnRhaW5zCmNvbmRpdGlvbmFsIGNvZGUgb24gaGFzX3NnIHZhcmlhYmxlLiBoYXNf c2cgaXMgc2V0IG9ubHkgd2hlbmV2ZXIgdGhlIEhXCmRvZXMgc3VwcG9ydCBTRyBtb2RlLCB0aGF0 IGlzIG5ldmVyIHRydWUgZm9yIFZETUEgSVAuCgpUaGlzIHBhdGNoIGRyb3BzIHRoZSBuZXZlci10 YWtlbiBicmFuY2hlcy4KClNpZ25lZC1vZmYtYnk6IEFuZHJlYSBNZXJlbGxvIDxhbmRyZWEubWVy ZWxsb0BnbWFpbC5jb20+ClJldmlld2VkLWJ5OiBSYWRoZXkgU2h5YW0gUGFuZGV5IDxyYWRoZXku c2h5YW0ucGFuZGV5QHhpbGlueC5jb20+Ci0tLQpDaGFuZ2VzIGluIFY0OiBpbnRyb2R1Y2VkIHRo aXMgcGF0Y2ggaW4gc2VyaWVzCkNoYW5nZXMgaW4gdjU6CglOb25lCkNoYW5nZXMgaW4gdjY6CglO b25lCi0tLQogZHJpdmVycy9kbWEveGlsaW54L3hpbGlueF9kbWEuYyB8IDg0ICsrKysrKysrKysr KystLS0tLS0tLS0tLS0tLS0tLS0tLQogMSBmaWxlIGNoYW5nZWQsIDMyIGluc2VydGlvbnMoKyks IDUyIGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZG1hL3hpbGlueC94aWxpbnhf ZG1hLmMgYi9kcml2ZXJzL2RtYS94aWxpbngveGlsaW54X2RtYS5jCmluZGV4IDQxYmQ4Y2FjYTA5 ZS4uYTM3ZTI4YTQzODg1IDEwMDY0NAotLS0gYS9kcml2ZXJzL2RtYS94aWxpbngveGlsaW54X2Rt YS5jCisrKyBiL2RyaXZlcnMvZG1hL3hpbGlueC94aWxpbnhfZG1hLmMKQEAgLTExMDAsNiArMTEw MCw4IEBAIHN0YXRpYyB2b2lkIHhpbGlueF92ZG1hX3N0YXJ0X3RyYW5zZmVyKHN0cnVjdCB4aWxp bnhfZG1hX2NoYW4gKmNoYW4pCiAJc3RydWN0IHhpbGlueF9kbWFfdHhfZGVzY3JpcHRvciAqZGVz YywgKnRhaWxfZGVzYzsKIAl1MzIgcmVnLCBqOwogCXN0cnVjdCB4aWxpbnhfdmRtYV90eF9zZWdt ZW50ICp0YWlsX3NlZ21lbnQ7CisJc3RydWN0IHhpbGlueF92ZG1hX3R4X3NlZ21lbnQgKnNlZ21l bnQsICpsYXN0ID0gTlVMTDsKKwlpbnQgaSA9IDA7CiAKIAkvKiBUaGlzIGZ1bmN0aW9uIHdhcyBp bnZva2VkIHdpdGggbG9jayBoZWxkICovCiAJaWYgKGNoYW4tPmVycikKQEAgLTExMTksMTQgKzEx MjEsNiBAQCBzdGF0aWMgdm9pZCB4aWxpbnhfdmRtYV9zdGFydF90cmFuc2ZlcihzdHJ1Y3QgeGls aW54X2RtYV9jaGFuICpjaGFuKQogCXRhaWxfc2VnbWVudCA9IGxpc3RfbGFzdF9lbnRyeSgmdGFp bF9kZXNjLT5zZWdtZW50cywKIAkJCQkgICAgICAgc3RydWN0IHhpbGlueF92ZG1hX3R4X3NlZ21l bnQsIG5vZGUpOwogCi0JLyoKLQkgKiBJZiBoYXJkd2FyZSBpcyBpZGxlLCB0aGVuIGFsbCBkZXNj cmlwdG9ycyBvbiB0aGUgcnVubmluZyBsaXN0cyBhcmUKLQkgKiBkb25lLCBzdGFydCBuZXcgdHJh bnNmZXJzCi0JICovCi0JaWYgKGNoYW4tPmhhc19zZykKLQkJZG1hX2N0cmxfd3JpdGUoY2hhbiwg WElMSU5YX0RNQV9SRUdfQ1VSREVTQywKLQkJCQlkZXNjLT5hc3luY190eC5waHlzKTsKLQogCS8q IENvbmZpZ3VyZSB0aGUgaGFyZHdhcmUgdXNpbmcgaW5mbyBpbiB0aGUgY29uZmlnIHN0cnVjdHVy ZSAqLwogCWlmIChjaGFuLT5oYXNfdmZsaXApIHsKIAkJcmVnID0gZG1hX3JlYWQoY2hhbiwgWElM SU5YX1ZETUFfUkVHX0VOQUJMRV9WRVJUSUNBTF9GTElQKTsKQEAgLTExNDMsMTUgKzExMzcsMTEg QEAgc3RhdGljIHZvaWQgeGlsaW54X3ZkbWFfc3RhcnRfdHJhbnNmZXIoc3RydWN0IHhpbGlueF9k bWFfY2hhbiAqY2hhbikKIAllbHNlCiAJCXJlZyAmPSB+WElMSU5YX0RNQV9ETUFDUl9GUkFNRUNO VF9FTjsKIAotCS8qCi0JICogV2l0aCBTRywgc3RhcnQgd2l0aCBjaXJjdWxhciBtb2RlLCBzbyB0 aGF0IEJEcyBjYW4gYmUgZmV0Y2hlZC4KLQkgKiBJbiBkaXJlY3QgcmVnaXN0ZXIgbW9kZSwgaWYg bm90IHBhcmtpbmcsIGVuYWJsZSBjaXJjdWxhciBtb2RlCi0JICovCi0JaWYgKGNoYW4tPmhhc19z ZyB8fCAhY29uZmlnLT5wYXJrKQotCQlyZWcgfD0gWElMSU5YX0RNQV9ETUFDUl9DSVJDX0VOOwot CisJLyogSWYgbm90IHBhcmtpbmcsIGVuYWJsZSBjaXJjdWxhciBtb2RlICovCiAJaWYgKGNvbmZp Zy0+cGFyaykKIAkJcmVnICY9IH5YSUxJTlhfRE1BX0RNQUNSX0NJUkNfRU47CisJZWxzZQorCQly ZWcgfD0gWElMSU5YX0RNQV9ETUFDUl9DSVJDX0VOOwogCiAJZG1hX2N0cmxfd3JpdGUoY2hhbiwg WElMSU5YX0RNQV9SRUdfRE1BQ1IsIHJlZyk7CiAKQEAgLTExNzMsNDggKzExNjMsMzggQEAgc3Rh dGljIHZvaWQgeGlsaW54X3ZkbWFfc3RhcnRfdHJhbnNmZXIoc3RydWN0IHhpbGlueF9kbWFfY2hh biAqY2hhbikKIAkJcmV0dXJuOwogCiAJLyogU3RhcnQgdGhlIHRyYW5zZmVyICovCi0JaWYgKGNo YW4tPmhhc19zZykgewotCQlkbWFfY3RybF93cml0ZShjaGFuLCBYSUxJTlhfRE1BX1JFR19UQUlM REVTQywKLQkJCQl0YWlsX3NlZ21lbnQtPnBoeXMpOwotCQlsaXN0X3NwbGljZV90YWlsX2luaXQo JmNoYW4tPnBlbmRpbmdfbGlzdCwgJmNoYW4tPmFjdGl2ZV9saXN0KTsKLQkJY2hhbi0+ZGVzY19w ZW5kaW5nY291bnQgPSAwOwotCX0gZWxzZSB7Ci0JCXN0cnVjdCB4aWxpbnhfdmRtYV90eF9zZWdt ZW50ICpzZWdtZW50LCAqbGFzdCA9IE5VTEw7Ci0JCWludCBpID0gMDsKLQotCQlpZiAoY2hhbi0+ ZGVzY19zdWJtaXRjb3VudCA8IGNoYW4tPm51bV9mcm1zKQotCQkJaSA9IGNoYW4tPmRlc2Nfc3Vi bWl0Y291bnQ7Ci0KLQkJbGlzdF9mb3JfZWFjaF9lbnRyeShzZWdtZW50LCAmZGVzYy0+c2VnbWVu dHMsIG5vZGUpIHsKLQkJCWlmIChjaGFuLT5leHRfYWRkcikKLQkJCQl2ZG1hX2Rlc2Nfd3JpdGVf NjQoY2hhbiwKLQkJCQkJWElMSU5YX1ZETUFfUkVHX1NUQVJUX0FERFJFU1NfNjQoaSsrKSwKLQkJ CQkJc2VnbWVudC0+aHcuYnVmX2FkZHIsCi0JCQkJCXNlZ21lbnQtPmh3LmJ1Zl9hZGRyX21zYik7 Ci0JCQllbHNlCi0JCQkJdmRtYV9kZXNjX3dyaXRlKGNoYW4sCisJaWYgKGNoYW4tPmRlc2Nfc3Vi bWl0Y291bnQgPCBjaGFuLT5udW1fZnJtcykKKwkJaSA9IGNoYW4tPmRlc2Nfc3VibWl0Y291bnQ7 CisKKwlsaXN0X2Zvcl9lYWNoX2VudHJ5KHNlZ21lbnQsICZkZXNjLT5zZWdtZW50cywgbm9kZSkg eworCQlpZiAoY2hhbi0+ZXh0X2FkZHIpCisJCQl2ZG1hX2Rlc2Nfd3JpdGVfNjQoY2hhbiwKKwkJ CQkgICBYSUxJTlhfVkRNQV9SRUdfU1RBUlRfQUREUkVTU182NChpKyspLAorCQkJCSAgIHNlZ21l bnQtPmh3LmJ1Zl9hZGRyLAorCQkJCSAgIHNlZ21lbnQtPmh3LmJ1Zl9hZGRyX21zYik7CisJCWVs c2UKKwkJCXZkbWFfZGVzY193cml0ZShjaGFuLAogCQkJCQlYSUxJTlhfVkRNQV9SRUdfU1RBUlRf QUREUkVTUyhpKyspLAogCQkJCQlzZWdtZW50LT5ody5idWZfYWRkcik7CiAKLQkJCWxhc3QgPSBz ZWdtZW50OwotCQl9Ci0KLQkJaWYgKCFsYXN0KQotCQkJcmV0dXJuOworCQlsYXN0ID0gc2VnbWVu dDsKKwl9CiAKLQkJLyogSFcgZXhwZWN0cyB0aGVzZSBwYXJhbWV0ZXJzIHRvIGJlIHNhbWUgZm9y IG9uZSB0cmFuc2FjdGlvbiAqLwotCQl2ZG1hX2Rlc2Nfd3JpdGUoY2hhbiwgWElMSU5YX0RNQV9S RUdfSFNJWkUsIGxhc3QtPmh3LmhzaXplKTsKLQkJdmRtYV9kZXNjX3dyaXRlKGNoYW4sIFhJTElO WF9ETUFfUkVHX0ZSTURMWV9TVFJJREUsCi0JCQkJbGFzdC0+aHcuc3RyaWRlKTsKLQkJdmRtYV9k ZXNjX3dyaXRlKGNoYW4sIFhJTElOWF9ETUFfUkVHX1ZTSVpFLCBsYXN0LT5ody52c2l6ZSk7CisJ aWYgKCFsYXN0KQorCQlyZXR1cm47CiAKLQkJY2hhbi0+ZGVzY19zdWJtaXRjb3VudCsrOwotCQlj aGFuLT5kZXNjX3BlbmRpbmdjb3VudC0tOwotCQlsaXN0X2RlbCgmZGVzYy0+bm9kZSk7Ci0JCWxp c3RfYWRkX3RhaWwoJmRlc2MtPm5vZGUsICZjaGFuLT5hY3RpdmVfbGlzdCk7Ci0JCWlmIChjaGFu LT5kZXNjX3N1Ym1pdGNvdW50ID09IGNoYW4tPm51bV9mcm1zKQotCQkJY2hhbi0+ZGVzY19zdWJt aXRjb3VudCA9IDA7Ci0JfQorCS8qIEhXIGV4cGVjdHMgdGhlc2UgcGFyYW1ldGVycyB0byBiZSBz YW1lIGZvciBvbmUgdHJhbnNhY3Rpb24gKi8KKwl2ZG1hX2Rlc2Nfd3JpdGUoY2hhbiwgWElMSU5Y X0RNQV9SRUdfSFNJWkUsIGxhc3QtPmh3LmhzaXplKTsKKwl2ZG1hX2Rlc2Nfd3JpdGUoY2hhbiwg WElMSU5YX0RNQV9SRUdfRlJNRExZX1NUUklERSwKKwkJCWxhc3QtPmh3LnN0cmlkZSk7CisJdmRt YV9kZXNjX3dyaXRlKGNoYW4sIFhJTElOWF9ETUFfUkVHX1ZTSVpFLCBsYXN0LT5ody52c2l6ZSk7 CisKKwljaGFuLT5kZXNjX3N1Ym1pdGNvdW50Kys7CisJY2hhbi0+ZGVzY19wZW5kaW5nY291bnQt LTsKKwlsaXN0X2RlbCgmZGVzYy0+bm9kZSk7CisJbGlzdF9hZGRfdGFpbCgmZGVzYy0+bm9kZSwg JmNoYW4tPmFjdGl2ZV9saXN0KTsKKwlpZiAoY2hhbi0+ZGVzY19zdWJtaXRjb3VudCA9PSBjaGFu LT5udW1fZnJtcykKKwkJY2hhbi0+ZGVzY19zdWJtaXRjb3VudCA9IDA7CiAKIAljaGFuLT5pZGxl ID0gZmFsc2U7CiB9Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA698C28CF8 for ; Tue, 20 Nov 2018 15:32:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7CEC4208E3 for ; Tue, 20 Nov 2018 15:32:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ogB5lTFm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7CEC4208E3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730106AbeKUCBv (ORCPT ); Tue, 20 Nov 2018 21:01:51 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:36129 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727135AbeKUCBu (ORCPT ); Tue, 20 Nov 2018 21:01:50 -0500 Received: by mail-wr1-f67.google.com with SMTP id t3so2438827wrr.3; Tue, 20 Nov 2018 07:32:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4+qTUQgVrsH5WGyEnsnG2mHJoSQ0/3Ge4pcP7YNht8U=; b=ogB5lTFm7ZuZs4T50gjUg2yDDGIPay8vvwV4v8zHR8hLzsIjlFfzY684jd2+fDPIlN F6cC1RahcN/1utSO8sA6OwXEkpDJMhrLQqOK/ZejNh6jBtaqgwfJln5h39qk79BBw/IR mKOQXspeOWZRs+g4CwCZAroV7+ZrFvCZ4Pxaqfls6S6wQZbD6b0blGaatKxch0UgE5G3 TFf4BE6swiFxeX/hCrpNkMiDnK9lH4BK9jVzH+kAokmSO0gPVhY14XH4SWRm13EJEyRU j8e41l/AbH4jZIjK4m/+ABI2Z/GezqHGeOh7w1kMXJx0zjV53e25rPmDHraWFrJl4j9t Sp0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4+qTUQgVrsH5WGyEnsnG2mHJoSQ0/3Ge4pcP7YNht8U=; b=RH6EEQecYFyfXS8iyzeanD+WcwPKPWNhyWn5lXujBoG8/zVWv1v2D6udwuv7SJ2u++ spGJRQB3okfKx09qTxOEhZwaWpnsQeWJnL9eJwBQfIEow71zIDYzOfDjNSQ7aNXlOjia dSDZNOel9WhwvaRC+Q1mP8thX1PrFIiQxZhAMpQFQ4SVVOAiQ23+nVScIUOi564B2Beu FMGk4/yy44zVKwLr+ibC++mq0/ZsyHWyUG9BzGrFG48iGIZHqKncI40Rp9x18uKueKDv LOCCZz3lb/5dKZYNebjk6FuhHBZ4J7javRy1mlB8dikNjNzozYEMUZQJm5+ffz1NTWvI Tieg== X-Gm-Message-State: AA+aEWZYc04r429ojswiy7ZKi+d8WcINtK19IlvlEJksvkJ7oZmAEFbq jJhFay5nAfbbEJQVVMv83z8= X-Google-Smtp-Source: AFSGD/Wgwqu4mZOeo6gWd7BZixfMYcxFMWc9tWShv/oee9CWwCkPYGUBgcnI3b5OjnzuVxoG4r1i0A== X-Received: by 2002:adf:9cc2:: with SMTP id h2-v6mr2536834wre.322.1542727927050; Tue, 20 Nov 2018 07:32:07 -0800 (PST) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id k73sm14677464wmd.36.2018.11.20.07.32.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 07:32:06 -0800 (PST) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v6 7/7] dmaengine: xilinx_dma: Drop SG support for VDMA IP Date: Tue, 20 Nov 2018 16:31:51 +0100 Message-Id: <20181120153151.18024-7-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181120153151.18024-1-andrea.merello@gmail.com> References: <20181120153151.18024-1-andrea.merello@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org xilinx_vdma_start_transfer() is used only for VDMA IP, still it contains conditional code on has_sg variable. has_sg is set only whenever the HW does support SG mode, that is never true for VDMA IP. This patch drops the never-taken branches. Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in V4: introduced this patch in series Changes in v5: None Changes in v6: None --- drivers/dma/xilinx/xilinx_dma.c | 84 +++++++++++++-------------------- 1 file changed, 32 insertions(+), 52 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 41bd8caca09e..a37e28a43885 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1100,6 +1100,8 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) struct xilinx_dma_tx_descriptor *desc, *tail_desc; u32 reg, j; struct xilinx_vdma_tx_segment *tail_segment; + struct xilinx_vdma_tx_segment *segment, *last = NULL; + int i = 0; /* This function was invoked with lock held */ if (chan->err) @@ -1119,14 +1121,6 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) tail_segment = list_last_entry(&tail_desc->segments, struct xilinx_vdma_tx_segment, node); - /* - * If hardware is idle, then all descriptors on the running lists are - * done, start new transfers - */ - if (chan->has_sg) - dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, - desc->async_tx.phys); - /* Configure the hardware using info in the config structure */ if (chan->has_vflip) { reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); @@ -1143,15 +1137,11 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) else reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; - /* - * With SG, start with circular mode, so that BDs can be fetched. - * In direct register mode, if not parking, enable circular mode - */ - if (chan->has_sg || !config->park) - reg |= XILINX_DMA_DMACR_CIRC_EN; - + /* If not parking, enable circular mode */ if (config->park) reg &= ~XILINX_DMA_DMACR_CIRC_EN; + else + reg |= XILINX_DMA_DMACR_CIRC_EN; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); @@ -1173,48 +1163,38 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) return; /* Start the transfer */ - if (chan->has_sg) { - dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, - tail_segment->phys); - list_splice_tail_init(&chan->pending_list, &chan->active_list); - chan->desc_pendingcount = 0; - } else { - struct xilinx_vdma_tx_segment *segment, *last = NULL; - int i = 0; - - if (chan->desc_submitcount < chan->num_frms) - i = chan->desc_submitcount; - - list_for_each_entry(segment, &desc->segments, node) { - if (chan->ext_addr) - vdma_desc_write_64(chan, - XILINX_VDMA_REG_START_ADDRESS_64(i++), - segment->hw.buf_addr, - segment->hw.buf_addr_msb); - else - vdma_desc_write(chan, + if (chan->desc_submitcount < chan->num_frms) + i = chan->desc_submitcount; + + list_for_each_entry(segment, &desc->segments, node) { + if (chan->ext_addr) + vdma_desc_write_64(chan, + XILINX_VDMA_REG_START_ADDRESS_64(i++), + segment->hw.buf_addr, + segment->hw.buf_addr_msb); + else + vdma_desc_write(chan, XILINX_VDMA_REG_START_ADDRESS(i++), segment->hw.buf_addr); - last = segment; - } - - if (!last) - return; + last = segment; + } - /* HW expects these parameters to be same for one transaction */ - vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); - vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, - last->hw.stride); - vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + if (!last) + return; - chan->desc_submitcount++; - chan->desc_pendingcount--; - list_del(&desc->node); - list_add_tail(&desc->node, &chan->active_list); - if (chan->desc_submitcount == chan->num_frms) - chan->desc_submitcount = 0; - } + /* HW expects these parameters to be same for one transaction */ + vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); + vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, + last->hw.stride); + vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + + chan->desc_submitcount++; + chan->desc_pendingcount--; + list_del(&desc->node); + list_add_tail(&desc->node, &chan->active_list); + if (chan->desc_submitcount == chan->num_frms) + chan->desc_submitcount = 0; chan->idle = false; } -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: andrea.merello@gmail.com (Andrea Merello) Date: Tue, 20 Nov 2018 16:31:51 +0100 Subject: [PATCH v6 7/7] dmaengine: xilinx_dma: Drop SG support for VDMA IP In-Reply-To: <20181120153151.18024-1-andrea.merello@gmail.com> References: <20181120153151.18024-1-andrea.merello@gmail.com> Message-ID: <20181120153151.18024-7-andrea.merello@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org xilinx_vdma_start_transfer() is used only for VDMA IP, still it contains conditional code on has_sg variable. has_sg is set only whenever the HW does support SG mode, that is never true for VDMA IP. This patch drops the never-taken branches. Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in V4: introduced this patch in series Changes in v5: None Changes in v6: None --- drivers/dma/xilinx/xilinx_dma.c | 84 +++++++++++++-------------------- 1 file changed, 32 insertions(+), 52 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 41bd8caca09e..a37e28a43885 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1100,6 +1100,8 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) struct xilinx_dma_tx_descriptor *desc, *tail_desc; u32 reg, j; struct xilinx_vdma_tx_segment *tail_segment; + struct xilinx_vdma_tx_segment *segment, *last = NULL; + int i = 0; /* This function was invoked with lock held */ if (chan->err) @@ -1119,14 +1121,6 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) tail_segment = list_last_entry(&tail_desc->segments, struct xilinx_vdma_tx_segment, node); - /* - * If hardware is idle, then all descriptors on the running lists are - * done, start new transfers - */ - if (chan->has_sg) - dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, - desc->async_tx.phys); - /* Configure the hardware using info in the config structure */ if (chan->has_vflip) { reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); @@ -1143,15 +1137,11 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) else reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; - /* - * With SG, start with circular mode, so that BDs can be fetched. - * In direct register mode, if not parking, enable circular mode - */ - if (chan->has_sg || !config->park) - reg |= XILINX_DMA_DMACR_CIRC_EN; - + /* If not parking, enable circular mode */ if (config->park) reg &= ~XILINX_DMA_DMACR_CIRC_EN; + else + reg |= XILINX_DMA_DMACR_CIRC_EN; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); @@ -1173,48 +1163,38 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) return; /* Start the transfer */ - if (chan->has_sg) { - dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, - tail_segment->phys); - list_splice_tail_init(&chan->pending_list, &chan->active_list); - chan->desc_pendingcount = 0; - } else { - struct xilinx_vdma_tx_segment *segment, *last = NULL; - int i = 0; - - if (chan->desc_submitcount < chan->num_frms) - i = chan->desc_submitcount; - - list_for_each_entry(segment, &desc->segments, node) { - if (chan->ext_addr) - vdma_desc_write_64(chan, - XILINX_VDMA_REG_START_ADDRESS_64(i++), - segment->hw.buf_addr, - segment->hw.buf_addr_msb); - else - vdma_desc_write(chan, + if (chan->desc_submitcount < chan->num_frms) + i = chan->desc_submitcount; + + list_for_each_entry(segment, &desc->segments, node) { + if (chan->ext_addr) + vdma_desc_write_64(chan, + XILINX_VDMA_REG_START_ADDRESS_64(i++), + segment->hw.buf_addr, + segment->hw.buf_addr_msb); + else + vdma_desc_write(chan, XILINX_VDMA_REG_START_ADDRESS(i++), segment->hw.buf_addr); - last = segment; - } - - if (!last) - return; + last = segment; + } - /* HW expects these parameters to be same for one transaction */ - vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); - vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, - last->hw.stride); - vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + if (!last) + return; - chan->desc_submitcount++; - chan->desc_pendingcount--; - list_del(&desc->node); - list_add_tail(&desc->node, &chan->active_list); - if (chan->desc_submitcount == chan->num_frms) - chan->desc_submitcount = 0; - } + /* HW expects these parameters to be same for one transaction */ + vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); + vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, + last->hw.stride); + vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + + chan->desc_submitcount++; + chan->desc_pendingcount--; + list_del(&desc->node); + list_add_tail(&desc->node, &chan->active_list); + if (chan->desc_submitcount == chan->num_frms) + chan->desc_submitcount = 0; chan->idle = false; } -- 2.17.1