From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anup Patel Date: Mon, 26 Nov 2018 16:09:10 +0530 Subject: [U-Boot] [PATCH v5 4/4] riscv: Remove redundant a2 store on DRAM base in start.S In-Reply-To: <20181126103910.14457-1-anup@brainfault.org> References: <20181126103910.14457-1-anup@brainfault.org> Message-ID: <20181126103910.14457-5-anup@brainfault.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Currently, the RISC-V U-Boot is saving a2 register at CONFIG_SYS_DRAM_BASE in start.S which does not make sense because there is no information passed by previous booting stage in a2 register. This patch removes redundant a2 store on DRAM base. Signed-off-by: Anup Patel --- arch/riscv/cpu/start.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 704190f946..e4276e8e19 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -38,8 +38,6 @@ _start: mv s0, a0 mv s1, a1 - li t0, CONFIG_SYS_SDRAM_BASE - SREG a2, 0(t0) la t0, trap_entry #ifdef CONFIG_RISCV_SMODE csrw stvec, t0 -- 2.17.1