From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDEC8C4161B for ; Mon, 26 Nov 2018 16:54:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 850FA20865 for ; Mon, 26 Nov 2018 16:54:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="KB4/0fga"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="WPAGTV3u" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 850FA20865 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-clk-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727071AbeK0DtI (ORCPT ); Mon, 26 Nov 2018 22:49:08 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55612 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726588AbeK0DtH (ORCPT ); Mon, 26 Nov 2018 22:49:07 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6772060D88; Mon, 26 Nov 2018 16:54:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1543251265; bh=OjMRv6pXcTLlNXk8skoToltceq1fM+BRv+33qnwp1gQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KB4/0fga1bK/pqAGKWqHOPaOD/XuoRefhllDkteVO9J+WPM76uksRZv8dOnBQUtmz 6eWb6DK35Fyt7GtxbVhCoTPSzfn8mNQ3qQ6WvZweQBWB38lgN9b2tTj4TDADJM8fAP rLtFQX4fi0/MvErkgX1K2DVE5bceb/D5xc3QwDbI= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7705360B7F; Mon, 26 Nov 2018 16:54:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1543251264; bh=OjMRv6pXcTLlNXk8skoToltceq1fM+BRv+33qnwp1gQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WPAGTV3ujRaUeZJrK5mHRBvMrRou2Nyo2tMhABo2tKeN2vvCfN4sGvL3Vc3h7wuLl LaTTjNB+Ii2pCtDRWRNv+Ry8fD1zZ3vP3+kGvCOGJmSTEjsaM7M+5C9m4+ZW9q70nh ux1WIUwZq5f4bcFd0THnPCkqXsvISsoe8Oa3RUQk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7705360B7F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: sboyd@kernel.org, mturquette@baylibre.com Cc: andy.gross@linaro.org, david.brown@linaro.org, rnayak@codeaurora.org, okukatla@codeaurora.org, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/2] clk: qcom: Add a dummy enable function for GX gdsc Date: Mon, 26 Nov 2018 09:54:16 -0700 Message-Id: <20181126165416.32519-3-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181126165416.32519-1-jcrouse@codeaurora.org> References: <20181126165416.32519-1-jcrouse@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Most of the time the CPU should not be touching the GX domain on the GPU except for a very special use case when the CPU needs to force the GX headswitch off. Add a dummy enable function for the GX gdsc to simulate success so that the pm_runtime reference counting is correct. Signed-off-by: Jordan Crouse --- drivers/clk/qcom/gpucc-sdm845.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c index 11222f487a65..7266e9a1d77e 100644 --- a/drivers/clk/qcom/gpucc-sdm845.c +++ b/drivers/clk/qcom/gpucc-sdm845.c @@ -131,11 +131,37 @@ static struct gdsc gpu_cx_gdsc = { .flags = VOTABLE, }; +/* + * On SDM845 the GPU GX domain is *almost* entirely controlled by the GMU + * running in the CX domain so the CPU doesn't need to know anything about the + * GX domain EXCEPT.... + * + * Hardware constraints dictate that the GX be powered down before the CX. If + * the GMU crashes it could leave the GX on. In order to successfully bring back + * the device the CPU needs to disable the GX headswitch. There being no sane + * way to reach in and touch that register from deep inside the GPU driver we + * need to set up the infrastructure to be able to ensure that the GPU can + * ensure that the GX is off during this super special case. We do this by + * defining a GX gdsc with a dummy enable function and a "default" disable + * function. + * + * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU + * driver. During power up, nothing will happen from the CPU (and the GMU will + * power up normally but during power down this will ensure that the GX domain + * is *really* off - this gives us a semi standard way of doing what we need. + */ +static int gx_gdsc_enable(struct generic_pm_domain *domain) +{ + /* Do nothing but give genpd the impression that we were successful */ + return 0; +} + static struct gdsc gpu_gx_gdsc = { .gdscr = 0x100c, .clamp_io_ctrl = 0x1508, .pd = { .name = "gpu_gx_gdsc", + .power_on = gx_gdsc_enable, }, .pwrsts = PWRSTS_OFF_ON, .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, -- 2.18.0