[PATCH for-4.12 0/8] xen/arm: Workaround for Cortex-A76 erratum 1165522

[Julien Grall <julien.grall@arm.com>]

Hi all,

Early version of Cortex-A76 can end-up with corrupt TLBs if they
speculate an AT instruction while the S1/S2 system registers are in an
inconsistent state.

This can happen during guest context switch and when invalidating the
TLBs for other than the current VMID.

The workaround implemented in Xen will:
    - Use an empty stage-2 with a reserved VMID while context
      switching between 2 guests
    - Use an empty stage-2 with the VMID where TLBs need to
      be flushed

Cheers,

Julien Grall (8):
  xen/arm: Only set necessary flags when initializing HCR_EL2
  xen/arm: p2m: Provide an helper to generate the VTTBR
  xen/arm: p2m: Introduce an helper to allocate the root page-table
  xen/arm: domain_build: Don't switch to the guest P2M when copying data
  xen/arm: p2m: Only use isb() when it is necessary
  xen/arm: Implement workaround for Cortex-A76 erratum 1165522
  xen/arm: p2m: Clean-up headers included and order them alphabetically
  DO NOT APPLY Allow testing the new AT speculate workaround code

 docs/misc/arm/silicon-errata.txt |   1 +
 xen/arch/arm/cpuerrata.c         |  16 +++++
 xen/arch/arm/domain.c            |   8 ++-
 xen/arch/arm/domain_build.c      |  13 ----
 xen/arch/arm/p2m.c               | 138 ++++++++++++++++++++++++++++++++-------
 xen/arch/arm/traps.c             |   8 ++-
 xen/include/asm-arm/cpufeature.h |   3 +-
 xen/include/asm-arm/processor.h  |   2 +
 8 files changed, 146 insertions(+), 43 deletions(-)

-- 
2.11.0


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