Re: [PATCH 1/2] ARM: dts: r7s9210: Initial SoC device tree

From: Simon Horman <horms@verge.net.au>
To: Chris Brandt <Chris.Brandt@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-renesas-soc@vger.kernel.org"
	<linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH 1/2] ARM: dts: r7s9210: Initial SoC device tree
Date: Fri, 30 Nov 2018 13:22:35 +0100	[thread overview]
Message-ID: <20181130122229.4iv6qgsnjyswoiiq@verge.net.au> (raw)
In-Reply-To: <OSAPR01MB15534822E5E9CC52AA0BCE778AD30@OSAPR01MB1553.jpnprd01.prod.outlook.com>

On Fri, Nov 30, 2018 at 12:04:57PM +0000, Chris Brandt wrote:
> Hi Simon,
> 
> 
> On Friday, November 30, 2018, Simon Horman wrote:
> > > +	cpg: clock-controller@fcfe0020 {
> > > +		compatible = "renesas,r7s9210-cpg-mssr";
> > > +		reg = <0xfcfe0010 0x455>;
> > 
> > There is a discrepancy here between the base address, fcfe0020
> > and the start address of the register range, 0xfcfe0010.
> 
> Good catch! Thank you.
> 
> 
> > > +	ostm0: timer@e803b000 {
> > > +		compatible = "renesas,r7s9210-ostm", "renesas,ostm";
> > > +		reg = <0xe803b000 0x30>;
> > 
> > 
> > Its not clear to me why the size of the register range is 0x30.
> 
> Because when reviewing the bindings docs, I was putting in 'exact' 
> values, but Geert said "those are ugly, just round up to make it look
> nicer".
> So instead of 0x21, I put 0x30.
> 
> You know...the standard answer: Throw Geert under the bus ;)

Lets leave 0x30 :)