Re: 答复: [RFC] locking/rwsem: Avoid issuing wakeup before setting the reader waiter to nil

From: Peter Zijlstra <peterz@infradead.org>
To: "Liu,Qi(ACU-T1)" <liuqi16@baidu.com>
Cc: Waiman Long <longman@redhat.com>,
	Will Deacon <will.deacon@arm.com>,
	Yongji Xie <elohimes@gmail.com>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Xie,Yongji" <xieyongji@baidu.com>,
	"Zhang,Yu(ACU-T1)" <zhangyu31@baidu.com>,
	"Yuan,Linsi" <yuanlinsi01@baidu.com>, "Ni,Xun" <nixun@baidu.com>,
	"Li,Lin(ACU-T1)" <lilin24@baidu.com>,
	Davidlohr Bueso <dave@stgolabs.net>
Subject: Re: 答复: [RFC] locking/rwsem: Avoid issuing wakeup before setting the reader waiter to nil
Date: Fri, 30 Nov 2018 15:15:44 +0100	[thread overview]
Message-ID: <20181130141544.GK11632@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <c1c9d6b30d7745ea9ac5b752f9a506c3@baidu.com>

On Fri, Nov 30, 2018 at 09:34:19AM +0000, Liu,Qi(ACU-T1) wrote:
> Is there a semantic divergence between x86 instruction "LOCK cmpxchg"
> and the macro cmpxchg defined in linux kernel? The former guarantee
> full barrier in any case, and the latter only imply barrier in case of
> success?

> So, we use 	
>     smp_mb__before_atomic()
> 	cmpxchg_relaxed()  // no barrier
> to get rid of the redundant barrier
>    smp_mb__before_atomic()
>    cmpxchg()          // imply a redundant barrier when successing  

No, it is all horribly more complicated :-)

On x86: cmpxchg_relaxed() == cmpxchg() == LOCK CMPXCHG, however
smp_mb__{before,after}_atomic() is a no-op.

On say arm OTOH: cmpxchg_relaxed() == LL/SC, but then
smp_mb__{before,after}_atomic() is smp_mb(), such that: cmpxchg() := {
smp_mb__before_atomic(); cmpxchg_relaxed(); smp_mb__after_atomic(); }

The difference is that on x86 atomic instructions unconditionally imply
memory ordering; whereas on ARM they do not.