From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4089FC64EB4 for ; Mon, 3 Dec 2018 03:46:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1331F20848 for ; Mon, 3 Dec 2018 03:46:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1331F20848 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726093AbeLCDq4 (ORCPT ); Sun, 2 Dec 2018 22:46:56 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:16067 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725813AbeLCDpn (ORCPT ); Sun, 2 Dec 2018 22:45:43 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 16398BBCE13A7; Mon, 3 Dec 2018 11:45:37 +0800 (CST) Received: from vm100-107-113-134.huawei.com (100.107.113.134) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.408.0; Mon, 3 Dec 2018 11:45:31 +0800 From: Yu Chen To: , , CC: , , Yu Chen , Felipe Balbi , Greg Kroah-Hartman , John Stultz , "Binghui Wang" Subject: [PATCH v1 05/12] usb: dwc3: Add two quirks for Hisilicon Kirin Soc Platform Date: Mon, 3 Dec 2018 11:45:08 +0800 Message-ID: <20181203034515.91412-6-chenyu56@huawei.com> X-Mailer: git-send-email 2.15.0-rc2 In-Reply-To: <20181203034515.91412-1-chenyu56@huawei.com> References: <20181203034515.91412-1-chenyu56@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [100.107.113.134] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are tow quirks for DesignWare USB3 DRD Core of Hisilicon Kirin Soc. 1)SPLIT_BOUNDARY_DISABLE should be set for Host mode 2)A GCTL soft reset should be executed when switch mode Cc: Felipe Balbi Cc: Greg Kroah-Hartman Cc: John Stultz Cc: Binghui Wang Signed-off-by: Yu Chen --- drivers/usb/dwc3/core.c | 43 +++++++++++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 7 +++++++ drivers/usb/dwc3/gadget.c | 2 +- 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index becfbb87f791..b539bcc45d3b 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -111,11 +111,25 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) dwc->current_dr_role = mode; } +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc) +{ + int reg; + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= (DWC3_GCTL_CORESOFTRESET); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~(DWC3_GCTL_CORESOFTRESET); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); unsigned long flags; int ret; + int reg; if (dwc->dr_mode != USB_DR_MODE_OTG) return; @@ -155,6 +169,10 @@ static void __dwc3_set_mode(struct work_struct *work) dwc3_set_prtcap(dwc, dwc->desired_dr_role); + /* Execute a GCTL Core Soft Reset when switch mode */ + if (dwc->gctl_reset_quirk) + dwc3_gctl_core_soft_reset(dwc); + spin_unlock_irqrestore(&dwc->lock, flags); switch (dwc->desired_dr_role) { @@ -168,6 +186,11 @@ static void __dwc3_set_mode(struct work_struct *work) phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); phy_calibrate(dwc->usb2_generic_phy); + if (dwc->dis_split_quirk) { + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); + reg |= DWC3_GUCTL3_SPLITDISABLE; + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); + } } break; case DWC3_GCTL_PRTCAP_DEVICE: @@ -1298,6 +1321,11 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->dis_metastability_quirk = device_property_read_bool(dev, "snps,dis_metastability_quirk"); + dwc->dis_split_quirk = device_property_read_bool(dev, + "snps,dis-split-quirk"); + dwc->gctl_reset_quirk = device_property_read_bool(dev, + "snps,gctl-reset-quirk"); + dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; @@ -1815,10 +1843,25 @@ static int dwc3_resume(struct device *dev) return 0; } + +static void dwc3_complete(struct device *dev) +{ + struct dwc3 *dwc = dev_get_drvdata(dev); + u32 reg; + + if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && + dwc->dis_split_quirk) { + dev_dbg(dwc->dev, "set DWC3_GUCTL3_SPLITDISABLE\n"); + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); + reg |= DWC3_GUCTL3_SPLITDISABLE; + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); + } +} #endif /* CONFIG_PM_SLEEP */ static const struct dev_pm_ops dwc3_dev_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) + .complete = dwc3_complete, SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, dwc3_runtime_idle) }; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 5bfb62533e0f..b3cea95f7720 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -135,6 +135,7 @@ #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) #define DWC3_GHWPARAMS8 0xc600 +#define DWC3_GUCTL3 0xc60c #define DWC3_GFLADJ 0xc630 /* Device Registers */ @@ -359,6 +360,9 @@ /* Global User Control Register 2 */ #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) +/* Global User Control Register 3 */ +#define DWC3_GUCTL3_SPLITDISABLE BIT(14) + /* Device Configuration Register */ #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) @@ -1168,6 +1172,9 @@ struct dwc3 { unsigned dis_metastability_quirk:1; + unsigned dis_split_quirk:1; + unsigned gctl_reset_quirk:1; + u16 imod_interval; }; diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 679c12e14522..cd54ad3eaf01 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -269,7 +269,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, { const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; struct dwc3 *dwc = dep->dwc; - u32 timeout = 1000; + u32 timeout = 5000; u32 saved_config = 0; u32 reg; -- 2.15.0-rc2 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu Chen Subject: [PATCH v1 05/12] usb: dwc3: Add two quirks for Hisilicon Kirin Soc Platform Date: Mon, 3 Dec 2018 11:45:08 +0800 Message-ID: <20181203034515.91412-6-chenyu56@huawei.com> References: <20181203034515.91412-1-chenyu56@huawei.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20181203034515.91412-1-chenyu56@huawei.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: suzhuangluan@hisilicon.com, kongfei@hisilicon.com, Yu Chen , Felipe Balbi , Greg Kroah-Hartman , John Stultz , Binghui Wang List-Id: devicetree@vger.kernel.org There are tow quirks for DesignWare USB3 DRD Core of Hisilicon Kirin Soc. 1)SPLIT_BOUNDARY_DISABLE should be set for Host mode 2)A GCTL soft reset should be executed when switch mode Cc: Felipe Balbi Cc: Greg Kroah-Hartman Cc: John Stultz Cc: Binghui Wang Signed-off-by: Yu Chen --- drivers/usb/dwc3/core.c | 43 +++++++++++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 7 +++++++ drivers/usb/dwc3/gadget.c | 2 +- 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index becfbb87f791..b539bcc45d3b 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -111,11 +111,25 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) dwc->current_dr_role = mode; } +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc) +{ + int reg; + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= (DWC3_GCTL_CORESOFTRESET); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~(DWC3_GCTL_CORESOFTRESET); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); unsigned long flags; int ret; + int reg; if (dwc->dr_mode != USB_DR_MODE_OTG) return; @@ -155,6 +169,10 @@ static void __dwc3_set_mode(struct work_struct *work) dwc3_set_prtcap(dwc, dwc->desired_dr_role); + /* Execute a GCTL Core Soft Reset when switch mode */ + if (dwc->gctl_reset_quirk) + dwc3_gctl_core_soft_reset(dwc); + spin_unlock_irqrestore(&dwc->lock, flags); switch (dwc->desired_dr_role) { @@ -168,6 +186,11 @@ static void __dwc3_set_mode(struct work_struct *work) phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); phy_calibrate(dwc->usb2_generic_phy); + if (dwc->dis_split_quirk) { + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); + reg |= DWC3_GUCTL3_SPLITDISABLE; + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); + } } break; case DWC3_GCTL_PRTCAP_DEVICE: @@ -1298,6 +1321,11 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->dis_metastability_quirk = device_property_read_bool(dev, "snps,dis_metastability_quirk"); + dwc->dis_split_quirk = device_property_read_bool(dev, + "snps,dis-split-quirk"); + dwc->gctl_reset_quirk = device_property_read_bool(dev, + "snps,gctl-reset-quirk"); + dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; @@ -1815,10 +1843,25 @@ static int dwc3_resume(struct device *dev) return 0; } + +static void dwc3_complete(struct device *dev) +{ + struct dwc3 *dwc = dev_get_drvdata(dev); + u32 reg; + + if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && + dwc->dis_split_quirk) { + dev_dbg(dwc->dev, "set DWC3_GUCTL3_SPLITDISABLE\n"); + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); + reg |= DWC3_GUCTL3_SPLITDISABLE; + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); + } +} #endif /* CONFIG_PM_SLEEP */ static const struct dev_pm_ops dwc3_dev_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) + .complete = dwc3_complete, SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, dwc3_runtime_idle) }; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 5bfb62533e0f..b3cea95f7720 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -135,6 +135,7 @@ #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) #define DWC3_GHWPARAMS8 0xc600 +#define DWC3_GUCTL3 0xc60c #define DWC3_GFLADJ 0xc630 /* Device Registers */ @@ -359,6 +360,9 @@ /* Global User Control Register 2 */ #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) +/* Global User Control Register 3 */ +#define DWC3_GUCTL3_SPLITDISABLE BIT(14) + /* Device Configuration Register */ #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) @@ -1168,6 +1172,9 @@ struct dwc3 { unsigned dis_metastability_quirk:1; + unsigned dis_split_quirk:1; + unsigned gctl_reset_quirk:1; + u16 imod_interval; }; diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 679c12e14522..cd54ad3eaf01 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -269,7 +269,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, { const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; struct dwc3 *dwc = dep->dwc; - u32 timeout = 1000; + u32 timeout = 5000; u32 saved_config = 0; u32 reg; -- 2.15.0-rc2 From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v1,05/12] usb: dwc3: Add two quirks for Hisilicon Kirin Soc Platform From: Yu Chen Message-Id: <20181203034515.91412-6-chenyu56@huawei.com> Date: Mon, 3 Dec 2018 11:45:08 +0800 To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: suzhuangluan@hisilicon.com, kongfei@hisilicon.com, Yu Chen , Felipe Balbi , Greg Kroah-Hartman , John Stultz , Binghui Wang List-ID: VGhlcmUgYXJlIHRvdyBxdWlya3MgZm9yIERlc2lnbldhcmUgVVNCMyBEUkQgQ29yZSBvZiBIaXNp bGljb24gS2lyaW4gU29jLgoxKVNQTElUX0JPVU5EQVJZX0RJU0FCTEUgc2hvdWxkIGJlIHNldCBm b3IgSG9zdCBtb2RlCjIpQSBHQ1RMIHNvZnQgcmVzZXQgc2hvdWxkIGJlIGV4ZWN1dGVkIHdoZW4g c3dpdGNoIG1vZGUKCkNjOiBGZWxpcGUgQmFsYmkgPGJhbGJpQGtlcm5lbC5vcmc+CkNjOiBHcmVn IEtyb2FoLUhhcnRtYW4gPGdyZWdraEBsaW51eGZvdW5kYXRpb24ub3JnPgpDYzogSm9obiBTdHVs dHogPGpvaG4uc3R1bHR6QGxpbmFyby5vcmc+CkNjOiBCaW5naHVpIFdhbmcgPHdhbmdiaW5naHVp QGhpc2lsaWNvbi5jb20+ClNpZ25lZC1vZmYtYnk6IFl1IENoZW4gPGNoZW55dTU2QGh1YXdlaS5j b20+Ci0tLQogZHJpdmVycy91c2IvZHdjMy9jb3JlLmMgICB8IDQzICsrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrKysKIGRyaXZlcnMvdXNiL2R3YzMvY29yZS5oICAgfCAg NyArKysrKysrCiBkcml2ZXJzL3VzYi9kd2MzL2dhZGdldC5jIHwgIDIgKy0KIDMgZmlsZXMgY2hh bmdlZCwgNTEgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQoKZGlmZiAtLWdpdCBhL2RyaXZl cnMvdXNiL2R3YzMvY29yZS5jIGIvZHJpdmVycy91c2IvZHdjMy9jb3JlLmMKaW5kZXggYmVjZmJi ODdmNzkxLi5iNTM5YmNjNDVkM2IgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvdXNiL2R3YzMvY29yZS5j CisrKyBiL2RyaXZlcnMvdXNiL2R3YzMvY29yZS5jCkBAIC0xMTEsMTEgKzExMSwyNSBAQCB2b2lk IGR3YzNfc2V0X3BydGNhcChzdHJ1Y3QgZHdjMyAqZHdjLCB1MzIgbW9kZSkKIAlkd2MtPmN1cnJl bnRfZHJfcm9sZSA9IG1vZGU7CiB9CiAKK3N0YXRpYyB2b2lkIGR3YzNfZ2N0bF9jb3JlX3NvZnRf cmVzZXQoc3RydWN0IGR3YzMgKmR3YykKK3sKKwlpbnQgcmVnOworCisJcmVnID0gZHdjM19yZWFk bChkd2MtPnJlZ3MsIERXQzNfR0NUTCk7CisJcmVnIHw9IChEV0MzX0dDVExfQ09SRVNPRlRSRVNF VCk7CisJZHdjM193cml0ZWwoZHdjLT5yZWdzLCBEV0MzX0dDVEwsIHJlZyk7CisKKwlyZWcgPSBk d2MzX3JlYWRsKGR3Yy0+cmVncywgRFdDM19HQ1RMKTsKKwlyZWcgJj0gfihEV0MzX0dDVExfQ09S RVNPRlRSRVNFVCk7CisJZHdjM193cml0ZWwoZHdjLT5yZWdzLCBEV0MzX0dDVEwsIHJlZyk7Cit9 CisKIHN0YXRpYyB2b2lkIF9fZHdjM19zZXRfbW9kZShzdHJ1Y3Qgd29ya19zdHJ1Y3QgKndvcmsp CiB7CiAJc3RydWN0IGR3YzMgKmR3YyA9IHdvcmtfdG9fZHdjKHdvcmspOwogCXVuc2lnbmVkIGxv bmcgZmxhZ3M7CiAJaW50IHJldDsKKwlpbnQgcmVnOwogCiAJaWYgKGR3Yy0+ZHJfbW9kZSAhPSBV U0JfRFJfTU9ERV9PVEcpCiAJCXJldHVybjsKQEAgLTE1NSw2ICsxNjksMTAgQEAgc3RhdGljIHZv aWQgX19kd2MzX3NldF9tb2RlKHN0cnVjdCB3b3JrX3N0cnVjdCAqd29yaykKIAogCWR3YzNfc2V0 X3BydGNhcChkd2MsIGR3Yy0+ZGVzaXJlZF9kcl9yb2xlKTsKIAorCS8qIEV4ZWN1dGUgYSBHQ1RM IENvcmUgU29mdCBSZXNldCB3aGVuIHN3aXRjaCBtb2RlICovCisJaWYgKGR3Yy0+Z2N0bF9yZXNl dF9xdWlyaykKKwkJZHdjM19nY3RsX2NvcmVfc29mdF9yZXNldChkd2MpOworCiAJc3Bpbl91bmxv Y2tfaXJxcmVzdG9yZSgmZHdjLT5sb2NrLCBmbGFncyk7CiAKIAlzd2l0Y2ggKGR3Yy0+ZGVzaXJl ZF9kcl9yb2xlKSB7CkBAIC0xNjgsNiArMTg2LDExIEBAIHN0YXRpYyB2b2lkIF9fZHdjM19zZXRf bW9kZShzdHJ1Y3Qgd29ya19zdHJ1Y3QgKndvcmspCiAJCQlwaHlfc2V0X21vZGUoZHdjLT51c2Iy X2dlbmVyaWNfcGh5LCBQSFlfTU9ERV9VU0JfSE9TVCk7CiAJCQlwaHlfc2V0X21vZGUoZHdjLT51 c2IzX2dlbmVyaWNfcGh5LCBQSFlfTU9ERV9VU0JfSE9TVCk7CiAJCQlwaHlfY2FsaWJyYXRlKGR3 Yy0+dXNiMl9nZW5lcmljX3BoeSk7CisJCQlpZiAoZHdjLT5kaXNfc3BsaXRfcXVpcmspIHsKKwkJ CQlyZWcgPSBkd2MzX3JlYWRsKGR3Yy0+cmVncywgRFdDM19HVUNUTDMpOworCQkJCXJlZyB8PSBE V0MzX0dVQ1RMM19TUExJVERJU0FCTEU7CisJCQkJZHdjM193cml0ZWwoZHdjLT5yZWdzLCBEV0Mz X0dVQ1RMMywgcmVnKTsKKwkJCX0KIAkJfQogCQlicmVhazsKIAljYXNlIERXQzNfR0NUTF9QUlRD QVBfREVWSUNFOgpAQCAtMTI5OCw2ICsxMzIxLDExIEBAIHN0YXRpYyB2b2lkIGR3YzNfZ2V0X3By b3BlcnRpZXMoc3RydWN0IGR3YzMgKmR3YykKIAlkd2MtPmRpc19tZXRhc3RhYmlsaXR5X3F1aXJr ID0gZGV2aWNlX3Byb3BlcnR5X3JlYWRfYm9vbChkZXYsCiAJCQkJInNucHMsZGlzX21ldGFzdGFi aWxpdHlfcXVpcmsiKTsKIAorCWR3Yy0+ZGlzX3NwbGl0X3F1aXJrID0gZGV2aWNlX3Byb3BlcnR5 X3JlYWRfYm9vbChkZXYsCisJCQkJInNucHMsZGlzLXNwbGl0LXF1aXJrIik7CisJZHdjLT5nY3Rs X3Jlc2V0X3F1aXJrID0gZGV2aWNlX3Byb3BlcnR5X3JlYWRfYm9vbChkZXYsCisJCQkJInNucHMs Z2N0bC1yZXNldC1xdWlyayIpOworCiAJZHdjLT5scG1fbnlldF90aHJlc2hvbGQgPSBscG1fbnll dF90aHJlc2hvbGQ7CiAJZHdjLT50eF9kZV9lbXBoYXNpcyA9IHR4X2RlX2VtcGhhc2lzOwogCkBA IC0xODE1LDEwICsxODQzLDI1IEBAIHN0YXRpYyBpbnQgZHdjM19yZXN1bWUoc3RydWN0IGRldmlj ZSAqZGV2KQogCiAJcmV0dXJuIDA7CiB9CisKK3N0YXRpYyB2b2lkIGR3YzNfY29tcGxldGUoc3Ry dWN0IGRldmljZSAqZGV2KQoreworCXN0cnVjdCBkd2MzCSpkd2MgPSBkZXZfZ2V0X2RydmRhdGEo ZGV2KTsKKwl1MzIJCXJlZzsKKworCWlmIChkd2MtPmN1cnJlbnRfZHJfcm9sZSA9PSBEV0MzX0dD VExfUFJUQ0FQX0hPU1QgJiYKKwkJCWR3Yy0+ZGlzX3NwbGl0X3F1aXJrKSB7CisJCWRldl9kYmco ZHdjLT5kZXYsICJzZXQgRFdDM19HVUNUTDNfU1BMSVRESVNBQkxFXG4iKTsKKwkJcmVnID0gZHdj M19yZWFkbChkd2MtPnJlZ3MsIERXQzNfR1VDVEwzKTsKKwkJcmVnIHw9IERXQzNfR1VDVEwzX1NQ TElURElTQUJMRTsKKwkJZHdjM193cml0ZWwoZHdjLT5yZWdzLCBEV0MzX0dVQ1RMMywgcmVnKTsK Kwl9Cit9CiAjZW5kaWYgLyogQ09ORklHX1BNX1NMRUVQICovCiAKIHN0YXRpYyBjb25zdCBzdHJ1 Y3QgZGV2X3BtX29wcyBkd2MzX2Rldl9wbV9vcHMgPSB7CiAJU0VUX1NZU1RFTV9TTEVFUF9QTV9P UFMoZHdjM19zdXNwZW5kLCBkd2MzX3Jlc3VtZSkKKwkuY29tcGxldGUgPSBkd2MzX2NvbXBsZXRl LAogCVNFVF9SVU5USU1FX1BNX09QUyhkd2MzX3J1bnRpbWVfc3VzcGVuZCwgZHdjM19ydW50aW1l X3Jlc3VtZSwKIAkJCWR3YzNfcnVudGltZV9pZGxlKQogfTsKZGlmZiAtLWdpdCBhL2RyaXZlcnMv dXNiL2R3YzMvY29yZS5oIGIvZHJpdmVycy91c2IvZHdjMy9jb3JlLmgKaW5kZXggNWJmYjYyNTMz ZTBmLi5iM2NlYTk1Zjc3MjAgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvdXNiL2R3YzMvY29yZS5oCisr KyBiL2RyaXZlcnMvdXNiL2R3YzMvY29yZS5oCkBAIC0xMzUsNiArMTM1LDcgQEAKICNkZWZpbmUg RFdDM19HRVZOVENPVU5UKG4pCSgweGM0MGMgKyAoKG4pICogMHgxMCkpCiAKICNkZWZpbmUgRFdD M19HSFdQQVJBTVM4CQkweGM2MDAKKyNkZWZpbmUgRFdDM19HVUNUTDMJCTB4YzYwYwogI2RlZmlu ZSBEV0MzX0dGTEFESgkJMHhjNjMwCiAKIC8qIERldmljZSBSZWdpc3RlcnMgKi8KQEAgLTM1OSw2 ICszNjAsOSBAQAogLyogR2xvYmFsIFVzZXIgQ29udHJvbCBSZWdpc3RlciAyICovCiAjZGVmaW5l IERXQzNfR1VDVEwyX1JTVF9BQ1RCSVRMQVRFUgkJQklUKDE0KQogCisvKiBHbG9iYWwgVXNlciBD b250cm9sIFJlZ2lzdGVyIDMgKi8KKyNkZWZpbmUgRFdDM19HVUNUTDNfU1BMSVRESVNBQkxFCQlC SVQoMTQpCisKIC8qIERldmljZSBDb25maWd1cmF0aW9uIFJlZ2lzdGVyICovCiAjZGVmaW5lIERX QzNfRENGR19ERVZBRERSKGFkZHIpCSgoYWRkcikgPDwgMykKICNkZWZpbmUgRFdDM19EQ0ZHX0RF VkFERFJfTUFTSwlEV0MzX0RDRkdfREVWQUREUigweDdmKQpAQCAtMTE2OCw2ICsxMTcyLDkgQEAg c3RydWN0IGR3YzMgewogCiAJdW5zaWduZWQJCWRpc19tZXRhc3RhYmlsaXR5X3F1aXJrOjE7CiAK Kwl1bnNpZ25lZAkJZGlzX3NwbGl0X3F1aXJrOjE7CisJdW5zaWduZWQJCWdjdGxfcmVzZXRfcXVp cms6MTsKKwogCXUxNgkJCWltb2RfaW50ZXJ2YWw7CiB9OwogCmRpZmYgLS1naXQgYS9kcml2ZXJz L3VzYi9kd2MzL2dhZGdldC5jIGIvZHJpdmVycy91c2IvZHdjMy9nYWRnZXQuYwppbmRleCA2Nzlj MTJlMTQ1MjIuLmNkNTRhZDNlYWYwMSAxMDA2NDQKLS0tIGEvZHJpdmVycy91c2IvZHdjMy9nYWRn ZXQuYworKysgYi9kcml2ZXJzL3VzYi9kd2MzL2dhZGdldC5jCkBAIC0yNjksNyArMjY5LDcgQEAg aW50IGR3YzNfc2VuZF9nYWRnZXRfZXBfY21kKHN0cnVjdCBkd2MzX2VwICpkZXAsIHVuc2lnbmVk IGNtZCwKIHsKIAljb25zdCBzdHJ1Y3QgdXNiX2VuZHBvaW50X2Rlc2NyaXB0b3IgKmRlc2MgPSBk ZXAtPmVuZHBvaW50LmRlc2M7CiAJc3RydWN0IGR3YzMJCSpkd2MgPSBkZXAtPmR3YzsKLQl1MzIJ CQl0aW1lb3V0ID0gMTAwMDsKKwl1MzIJCQl0aW1lb3V0ID0gNTAwMDsKIAl1MzIJCQlzYXZlZF9j b25maWcgPSAwOwogCXUzMgkJCXJlZzsKIAo=