From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Andersson Subject: Re: [PATCH] clk: qcom: Fix MSM8998 resets Date: Mon, 3 Dec 2018 07:55:38 -0800 Message-ID: <20181203155538.GQ2225@minitux> References: <1543851298-32320-1-git-send-email-jhugo@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1543851298-32320-1-git-send-email-jhugo@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: Jeffrey Hugo Cc: andy.gross@linaro.org, david.brown@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org On Mon 03 Dec 07:34 PST 2018, Jeffrey Hugo wrote: > The offsets for the defined BCR reset registers does not match the hardware > documentation. Update the values to match the hardware documentation. > Sorry for not spotting this before. > Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver) > Signed-off-by: Jeffrey Hugo > --- > drivers/clk/qcom/gcc-msm8998.c | 38 +++++++++++++++++++------------------- > 1 file changed, 19 insertions(+), 19 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c > index 9f0ae40..01cc555 100644 > --- a/drivers/clk/qcom/gcc-msm8998.c > +++ b/drivers/clk/qcom/gcc-msm8998.c > @@ -2742,25 +2742,25 @@ enum { > }; > > static const struct qcom_reset_map gcc_msm8998_resets[] = { > - [GCC_BLSP1_QUP1_BCR] = { 0x102400 }, > - [GCC_BLSP1_QUP2_BCR] = { 0x110592 }, > - [GCC_BLSP1_QUP3_BCR] = { 0x118784 }, > - [GCC_BLSP1_QUP4_BCR] = { 0x126976 }, > - [GCC_BLSP1_QUP5_BCR] = { 0x135168 }, > - [GCC_BLSP1_QUP6_BCR] = { 0x143360 }, > - [GCC_BLSP2_QUP1_BCR] = { 0x155648 }, > - [GCC_BLSP2_QUP2_BCR] = { 0x163840 }, > - [GCC_BLSP2_QUP3_BCR] = { 0x172032 }, > - [GCC_BLSP2_QUP4_BCR] = { 0x180224 }, > - [GCC_BLSP2_QUP5_BCR] = { 0x188416 }, > - [GCC_BLSP2_QUP6_BCR] = { 0x196608 }, > - [GCC_PCIE_0_BCR] = { 0x438272 }, > - [GCC_PDM_BCR] = { 0x208896 }, > - [GCC_SDCC2_BCR] = { 0x81920 }, > - [GCC_SDCC4_BCR] = { 0x90112 }, > - [GCC_TSIF_BCR] = { 0x221184 }, > - [GCC_UFS_BCR] = { 0x479232 }, > - [GCC_USB_30_BCR] = { 0x61440 }, > + [GCC_BLSP1_QUP1_BCR] = { 0x19000 }, > + [GCC_BLSP1_QUP2_BCR] = { 0x1b000 }, > + [GCC_BLSP1_QUP3_BCR] = { 0x1d000 }, > + [GCC_BLSP1_QUP4_BCR] = { 0x1f000 }, > + [GCC_BLSP1_QUP5_BCR] = { 0x21000 }, > + [GCC_BLSP1_QUP6_BCR] = { 0x23000 }, > + [GCC_BLSP2_QUP1_BCR] = { 0x26000 }, > + [GCC_BLSP2_QUP2_BCR] = { 0x28000 }, > + [GCC_BLSP2_QUP3_BCR] = { 0x2a000 }, > + [GCC_BLSP2_QUP4_BCR] = { 0x2c000 }, > + [GCC_BLSP2_QUP5_BCR] = { 0x2e000 }, > + [GCC_BLSP2_QUP6_BCR] = { 0x30000 }, > + [GCC_PCIE_0_BCR] = { 0x6c01c }, I find GCC_PCIE_0_BCR at 0x6b000 and then GCC_PCIE_0_PHY_BCR at 0x6c01c. > + [GCC_PDM_BCR] = { 0x33000 }, > + [GCC_SDCC2_BCR] = { 0x14000 }, > + [GCC_SDCC4_BCR] = { 0x16000 }, > + [GCC_TSIF_BCR] = { 0x36000 }, > + [GCC_UFS_BCR] = { 0x75000 }, > + [GCC_USB_30_BCR] = { 0xf000 }, > }; With this updated, you have my Reviewed-by: Bjorn Andersson Regards, Bjorn