From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D145DC04EB9 for ; Wed, 5 Dec 2018 09:41:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 84F5D20851 for ; Wed, 5 Dec 2018 09:41:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="M9ITMcjk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 84F5D20851 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728925AbeLEJl3 (ORCPT ); Wed, 5 Dec 2018 04:41:29 -0500 Received: from mail.kernel.org ([198.145.29.99]:45922 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727908AbeLEJl1 (ORCPT ); Wed, 5 Dec 2018 04:41:27 -0500 Received: from sasha-vm.mshome.net (unknown [213.57.143.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 62B5520850; Wed, 5 Dec 2018 09:41:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1544002886; bh=WpPP2hVwF9+8ubCe+5BMooiw77D3Y1/Kr+KAdfgJRPw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M9ITMcjk1YS41BBpLumQKau0GZ7ITtQCRevDlnK3DqRkgosHuLfH2BgOqeDKEaCWU TqXfXjLzfslHIeP0YSrLgQl47CPJ1Jsm4KQiPGovLnsOR6RRVZsNl35TEv2XKloGHX /Wystriq7L8ytkS4Y5l1zsxoY0cRMEfkn05n9AIo= From: Sasha Levin To: stable@vger.kernel.org, linux-kernel@vger.kernel.org Cc: shaoyunl , Alex Deucher , Sasha Levin , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 4.19 099/123] drm/amdgpu: Add delay after enable RLC ucode Date: Wed, 5 Dec 2018 04:35:31 -0500 Message-Id: <20181205093555.5386-99-sashal@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181205093555.5386-1-sashal@kernel.org> References: <20181205093555.5386-1-sashal@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: shaoyunl [ Upstream commit ad97d9de45835b6a0f71983b0ae0cffd7306730a ] Driver shouldn't try to access any GFX registers until RLC is idle. During the test, it took 12 seconds for RLC to clear the BUSY bit in RLC_GPM_STAT register which is un-acceptable for driver. As per RLC engineer, it would take RLC Ucode less than 10,000 GFXCLK cycles to finish its critical section. In a lowest 300M enginer clock setting(default from vbios), 50 us delay is enough. This commit fix the hang when RLC introduce the work around for XGMI which requires more cycles to setup more registers than normal Signed-off-by: shaoyunl Acked-by: Felix Kuehling Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ef00d14f8645..325e2213cac5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2243,12 +2243,13 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) #endif WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); + udelay(50); /* carrizo do enable cp interrupt after cp inited */ - if (!(adev->flags & AMD_IS_APU)) + if (!(adev->flags & AMD_IS_APU)) { gfx_v9_0_enable_gui_idle_interrupt(adev, true); - - udelay(50); + udelay(50); + } #ifdef AMDGPU_RLC_DEBUG_RETRY /* RLC_GPM_GENERAL_6 : RLC Ucode version */ -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sasha Levin Subject: [PATCH AUTOSEL 4.19 099/123] drm/amdgpu: Add delay after enable RLC ucode Date: Wed, 5 Dec 2018 04:35:31 -0500 Message-ID: <20181205093555.5386-99-sashal@kernel.org> References: <20181205093555.5386-1-sashal@kernel.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20181205093555.5386-1-sashal-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Alex Deucher , Sasha Levin , dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, shaoyunl List-Id: dri-devel@lists.freedesktop.org RnJvbTogc2hhb3l1bmwgPHNoYW95dW4ubGl1QGFtZC5jb20+CgpbIFVwc3RyZWFtIGNvbW1pdCBh ZDk3ZDlkZTQ1ODM1YjZhMGY3MTk4M2IwYWUwY2ZmZDczMDY3MzBhIF0KCkRyaXZlciBzaG91bGRu J3QgdHJ5IHRvIGFjY2VzcyBhbnkgR0ZYIHJlZ2lzdGVycyB1bnRpbCBSTEMgaXMgaWRsZS4KRHVy aW5nIHRoZSB0ZXN0LCBpdCB0b29rIDEyIHNlY29uZHMgZm9yIFJMQyB0byBjbGVhciB0aGUgQlVT WSBiaXQKaW4gUkxDX0dQTV9TVEFUIHJlZ2lzdGVyIHdoaWNoIGlzIHVuLWFjY2VwdGFibGUgZm9y IGRyaXZlci4KQXMgcGVyIFJMQyBlbmdpbmVlciwgaXQgd291bGQgdGFrZSBSTEMgVWNvZGUgbGVz cyB0aGFuIDEwLDAwMCBHRlhDTEsKY3ljbGVzIHRvIGZpbmlzaCBpdHMgY3JpdGljYWwgc2VjdGlv bi4gSW4gYSBsb3dlc3QgMzAwTSBlbmdpbmVyIGNsb2NrCnNldHRpbmcoZGVmYXVsdCBmcm9tIHZi aW9zKSwgNTAgdXMgZGVsYXkgaXMgZW5vdWdoLgoKVGhpcyBjb21taXQgZml4IHRoZSBoYW5nIHdo ZW4gUkxDIGludHJvZHVjZSB0aGUgd29yayBhcm91bmQgZm9yIFhHTUkKd2hpY2ggcmVxdWlyZXMg bW9yZSBjeWNsZXMgdG8gc2V0dXAgbW9yZSByZWdpc3RlcnMgdGhhbiBub3JtYWwKClNpZ25lZC1v ZmYtYnk6IHNoYW95dW5sIDxzaGFveXVuLmxpdUBhbWQuY29tPgpBY2tlZC1ieTogRmVsaXggS3Vl aGxpbmcgPEZlbGl4Lkt1ZWhsaW5nQGFtZC5jb20+ClNpZ25lZC1vZmYtYnk6IEFsZXggRGV1Y2hl ciA8YWxleGFuZGVyLmRldWNoZXJAYW1kLmNvbT4KU2lnbmVkLW9mZi1ieTogU2FzaGEgTGV2aW4g PHNhc2hhbEBrZXJuZWwub3JnPgotLS0KIGRyaXZlcnMvZ3B1L2RybS9hbWQvYW1kZ3B1L2dmeF92 OV8wLmMgfCA3ICsrKystLS0KIDEgZmlsZSBjaGFuZ2VkLCA0IGluc2VydGlvbnMoKyksIDMgZGVs ZXRpb25zKC0pCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUvZ2Z4X3Y5 XzAuYyBiL2RyaXZlcnMvZ3B1L2RybS9hbWQvYW1kZ3B1L2dmeF92OV8wLmMKaW5kZXggZWYwMGQx NGY4NjQ1Li4zMjVlMjIxM2NhYzUgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9hbWQvYW1k Z3B1L2dmeF92OV8wLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUvZ2Z4X3Y5XzAu YwpAQCAtMjI0MywxMiArMjI0MywxMyBAQCBzdGF0aWMgdm9pZCBnZnhfdjlfMF9ybGNfc3RhcnQo c3RydWN0IGFtZGdwdV9kZXZpY2UgKmFkZXYpCiAjZW5kaWYKIAogCVdSRUczMl9GSUVMRDE1KEdD LCAwLCBSTENfQ05UTCwgUkxDX0VOQUJMRV9GMzIsIDEpOworCXVkZWxheSg1MCk7CiAKIAkvKiBj YXJyaXpvIGRvIGVuYWJsZSBjcCBpbnRlcnJ1cHQgYWZ0ZXIgY3AgaW5pdGVkICovCi0JaWYgKCEo YWRldi0+ZmxhZ3MgJiBBTURfSVNfQVBVKSkKKwlpZiAoIShhZGV2LT5mbGFncyAmIEFNRF9JU19B UFUpKSB7CiAJCWdmeF92OV8wX2VuYWJsZV9ndWlfaWRsZV9pbnRlcnJ1cHQoYWRldiwgdHJ1ZSk7 Ci0KLQl1ZGVsYXkoNTApOworCQl1ZGVsYXkoNTApOworCX0KIAogI2lmZGVmIEFNREdQVV9STENf REVCVUdfUkVUUlkKIAkvKiBSTENfR1BNX0dFTkVSQUxfNiA6IFJMQyBVY29kZSB2ZXJzaW9uICov Ci0tIAoyLjE3LjEKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fCmFtZC1nZnggbWFpbGluZyBsaXN0CmFtZC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0 dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vYW1kLWdmeAo=