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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id m89sm9918465otc.35.2018.12.19.06.09.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 Dec 2018 06:09:54 -0800 (PST) Date: Wed, 19 Dec 2018 08:09:54 -0600 From: Rob Herring To: Chen Yu Cc: Sergei Shtylyov , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, wangbinghui@hisilicon.com, suzhuangluan@hisilicon.com, kongfei@hisilicon.com, Greg Kroah-Hartman , Mark Rutland , John Stultz Subject: Re: [PATCH v1 01/12] dt-bindings: usb: add support for dwc3 controller on HiSilicon SoCs Message-ID: <20181219140953.GA9910@bogus> References: <20181203034515.91412-1-chenyu56@huawei.com> <20181203034515.91412-2-chenyu56@huawei.com> <33cda716-d09c-28e7-d4b4-26f246786f5e@huawei.com> <680c5b9f-e2c7-926d-7d10-4ce2cd091282@cogentembedded.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Dec 03, 2018 at 05:28:56PM +0800, Chen Yu wrote: > Hi, > > On 2018/12/3 16:59, Sergei Shtylyov wrote: > > On 03.12.2018 11:51, Chen Yu wrote: > > > >>>> This patch adds binding descriptions to support the dwc3 controller > >>>> on HiSilicon SoCs and boards like the HiKey960. > >>>> > >>>> Cc: Greg Kroah-Hartman > >>>> Cc: Rob Herring > >>>> Cc: Mark Rutland > >>>> Cc: John Stultz > >>>> Signed-off-by: Yu Chen > >>>> --- > >>>>    .../devicetree/bindings/usb/dwc3-hisi.txt          | 67 ++++++++++++++++++++++ > >>>>    1 file changed, 67 insertions(+) > >>>>    create mode 100644 Documentation/devicetree/bindings/usb/dwc3-hisi.txt > >>>> > >>>> diff --git a/Documentation/devicetree/bindings/usb/dwc3-hisi.txt b/Documentation/devicetree/bindings/usb/dwc3-hisi.txt > >>>> new file mode 100644 > >>>> index 000000000000..d32d2299a0a1 > >>>> --- /dev/null > >>>> +++ b/Documentation/devicetree/bindings/usb/dwc3-hisi.txt > >>>> @@ -0,0 +1,67 @@ > >>>> +HiSilicon DWC3 USB SoC controller > >>>> + > >>>> +This file documents the parameters for the dwc3-hisi driver. > >>>> + > >>>> +Required properties: > >>>> +- compatible:    should be "hisilicon,hi3660-dwc3" > >>>> +- clocks:    A list of phandle + clock-specifier pairs for the > >>>> +        clocks listed in clock-names > >>>> +- clock-names:    Specify clock names > >>>> +- resets:    list of phandle and reset specifier pairs. > >>>> + > >>>> +Sub-nodes: > >>>> +The dwc3 core should be added as subnode to HiSilicon DWC3 as shown in the > >>>> +example below. The DT binding details of dwc3 can be found in: > >>>> +Documentation/devicetree/bindings/usb/dwc3.txt > >>>> + > >>>> +Example: > >>>> +    usb3: hisi_dwc3 { > >>>> +        compatible = "hisilicon,hi3660-dwc3"; > >>>> +        #address-cells = <2>; > >>>> +        #size-cells = <2>; > >>>> +        ranges; > >>>> + > >>>> +        clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, > >>>> +             <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; > >>>> +        clock-names = "clk_usb3phy_ref", "aclk_usb3otg"; > >>>> +        assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; > >>>> +        assigned-clock-rates = <229000000>; > >>>> +        resets = <&crg_rst 0x90 8>, > >>>> +             <&crg_rst 0x90 7>, > >>>> +             <&crg_rst 0x90 6>, > >>>> +             <&crg_rst 0x90 5>; > >>>> + > >>>> +        dwc3: dwc3@ff100000 { Please combine these into a single node. Unless you have a wrapper with registers, you don't need these 2 nodes. Clocks and reset can go in the dwc3 node. > >>> > >>>      According to the DT spec, the node names should be generic, not chip specific, i.e. usb@ff100000 in this case. > >>> > >> > >> Do you mean it should be usb@ff100000: dwc3@ff100000 ? > > > >     dwc3: usb@ff100000 > > > >    "dwc3:" is a label, not name. > > I use the node name "dwc3@ff100000" according to Documentation/devicetree/bindings/usb/dwc3.txt > and documentations of vendor drivers, i.e. qcom,dwc3.txt, rockchip,dwc3.txt. > > In these documentations, the dwc3 sub-node name uses "dwc3@xxxxxxxx". > > I think it is better to be same as the other vendor's dwc3 drivers. It's not. The other bindings are wrong. Follow the DT Spec. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v1,01/12] dt-bindings: usb: add support for dwc3 controller on HiSilicon SoCs From: Rob Herring Message-Id: <20181219140953.GA9910@bogus> Date: Wed, 19 Dec 2018 08:09:54 -0600 To: Chen Yu Cc: Sergei Shtylyov , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, wangbinghui@hisilicon.com, suzhuangluan@hisilicon.com, kongfei@hisilicon.com, Greg Kroah-Hartman , Mark Rutland , John Stultz List-ID: T24gTW9uLCBEZWMgMDMsIDIwMTggYXQgMDU6Mjg6NTZQTSArMDgwMCwgQ2hlbiBZdSB3cm90ZToK PiBIaSwKPiAKPiBPbiAyMDE4LzEyLzMgMTY6NTksIFNlcmdlaSBTaHR5bHlvdiB3cm90ZToKPiA+ IE9uIDAzLjEyLjIwMTggMTE6NTEsIENoZW4gWXUgd3JvdGU6Cj4gPiAKPiA+Pj4+IFRoaXMgcGF0 Y2ggYWRkcyBiaW5kaW5nIGRlc2NyaXB0aW9ucyB0byBzdXBwb3J0IHRoZSBkd2MzIGNvbnRyb2xs ZXIKPiA+Pj4+IG9uIEhpU2lsaWNvbiBTb0NzIGFuZCBib2FyZHMgbGlrZSB0aGUgSGlLZXk5NjAu Cj4gPj4+Pgo+ID4+Pj4gQ2M6IEdyZWcgS3JvYWgtSGFydG1hbiA8Z3JlZ2toQGxpbnV4Zm91bmRh dGlvbi5vcmc+Cj4gPj4+PiBDYzogUm9iIEhlcnJpbmcgPHJvYmgrZHRAa2VybmVsLm9yZz4KPiA+ Pj4+IENjOiBNYXJrIFJ1dGxhbmQgPG1hcmsucnV0bGFuZEBhcm0uY29tPgo+ID4+Pj4gQ2M6IEpv aG4gU3R1bHR6IDxqb2huLnN0dWx0ekBsaW5hcm8ub3JnPgo+ID4+Pj4gU2lnbmVkLW9mZi1ieTog WXUgQ2hlbiA8Y2hlbnl1NTZAaHVhd2VpLmNvbT4KPiA+Pj4+IC0tLQo+ID4+Pj4gwqDCoCAuLi4v ZGV2aWNldHJlZS9iaW5kaW5ncy91c2IvZHdjMy1oaXNpLnR4dMKgwqDCoMKgwqDCoMKgwqDCoCB8 IDY3ICsrKysrKysrKysrKysrKysrKysrKysKPiA+Pj4+IMKgwqAgMSBmaWxlIGNoYW5nZWQsIDY3 IGluc2VydGlvbnMoKykKPiA+Pj4+IMKgwqAgY3JlYXRlIG1vZGUgMTAwNjQ0IERvY3VtZW50YXRp b24vZGV2aWNldHJlZS9iaW5kaW5ncy91c2IvZHdjMy1oaXNpLnR4dAo+ID4+Pj4KPiA+Pj4+IGRp ZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvdXNiL2R3YzMtaGlz aS50eHQgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvdXNiL2R3YzMtaGlzaS50 eHQKPiA+Pj4+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gPj4+PiBpbmRleCAwMDAwMDAwMDAwMDAu LmQzMmQyMjk5YTBhMQo+ID4+Pj4gLS0tIC9kZXYvbnVsbAo+ID4+Pj4gKysrIGIvRG9jdW1lbnRh dGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL3VzYi9kd2MzLWhpc2kudHh0Cj4gPj4+PiBAQCAtMCww ICsxLDY3IEBACj4gPj4+PiArSGlTaWxpY29uIERXQzMgVVNCIFNvQyBjb250cm9sbGVyCj4gPj4+ PiArCj4gPj4+PiArVGhpcyBmaWxlIGRvY3VtZW50cyB0aGUgcGFyYW1ldGVycyBmb3IgdGhlIGR3 YzMtaGlzaSBkcml2ZXIuCj4gPj4+PiArCj4gPj4+PiArUmVxdWlyZWQgcHJvcGVydGllczoKPiA+ Pj4+ICstIGNvbXBhdGlibGU6wqDCoMKgIHNob3VsZCBiZSAiaGlzaWxpY29uLGhpMzY2MC1kd2Mz Igo+ID4+Pj4gKy0gY2xvY2tzOsKgwqDCoCBBIGxpc3Qgb2YgcGhhbmRsZSArIGNsb2NrLXNwZWNp ZmllciBwYWlycyBmb3IgdGhlCj4gPj4+PiArwqDCoMKgwqDCoMKgwqAgY2xvY2tzIGxpc3RlZCBp biBjbG9jay1uYW1lcwo+ID4+Pj4gKy0gY2xvY2stbmFtZXM6wqDCoMKgIFNwZWNpZnkgY2xvY2sg bmFtZXMKPiA+Pj4+ICstIHJlc2V0czrCoMKgwqAgbGlzdCBvZiBwaGFuZGxlIGFuZCByZXNldCBz cGVjaWZpZXIgcGFpcnMuCj4gPj4+PiArCj4gPj4+PiArU3ViLW5vZGVzOgo+ID4+Pj4gK1RoZSBk d2MzIGNvcmUgc2hvdWxkIGJlIGFkZGVkIGFzIHN1Ym5vZGUgdG8gSGlTaWxpY29uIERXQzMgYXMg c2hvd24gaW4gdGhlCj4gPj4+PiArZXhhbXBsZSBiZWxvdy4gVGhlIERUIGJpbmRpbmcgZGV0YWls cyBvZiBkd2MzIGNhbiBiZSBmb3VuZCBpbjoKPiA+Pj4+ICtEb2N1bWVudGF0aW9uL2RldmljZXRy ZWUvYmluZGluZ3MvdXNiL2R3YzMudHh0Cj4gPj4+PiArCj4gPj4+PiArRXhhbXBsZToKPiA+Pj4+ ICvCoMKgwqAgdXNiMzogaGlzaV9kd2MzIHsKPiA+Pj4+ICvCoMKgwqDCoMKgwqDCoCBjb21wYXRp YmxlID0gImhpc2lsaWNvbixoaTM2NjAtZHdjMyI7Cj4gPj4+PiArwqDCoMKgwqDCoMKgwqAgI2Fk ZHJlc3MtY2VsbHMgPSA8Mj47Cj4gPj4+PiArwqDCoMKgwqDCoMKgwqAgI3NpemUtY2VsbHMgPSA8 Mj47Cj4gPj4+PiArwqDCoMKgwqDCoMKgwqAgcmFuZ2VzOwo+ID4+Pj4gKwo+ID4+Pj4gK8KgwqDC oMKgwqDCoMKgIGNsb2NrcyA9IDwmY3JnX2N0cmwgSEkzNjYwX0NMS19BQkJfVVNCPiwKPiA+Pj4+ ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgPCZjcmdfY3RybCBISTM2NjBfQUNMS19HQVRFX1VT QjNPVEc+Owo+ID4+Pj4gK8KgwqDCoMKgwqDCoMKgIGNsb2NrLW5hbWVzID0gImNsa191c2IzcGh5 X3JlZiIsICJhY2xrX3VzYjNvdGciOwo+ID4+Pj4gK8KgwqDCoMKgwqDCoMKgIGFzc2lnbmVkLWNs b2NrcyA9IDwmY3JnX2N0cmwgSEkzNjYwX0FDTEtfR0FURV9VU0IzT1RHPjsKPiA+Pj4+ICvCoMKg wqDCoMKgwqDCoCBhc3NpZ25lZC1jbG9jay1yYXRlcyA9IDwyMjkwMDAwMDA+Owo+ID4+Pj4gK8Kg wqDCoMKgwqDCoMKgIHJlc2V0cyA9IDwmY3JnX3JzdCAweDkwIDg+LAo+ID4+Pj4gK8KgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoCA8JmNyZ19yc3QgMHg5MCA3PiwKPiA+Pj4+ICvCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqAgPCZjcmdfcnN0IDB4OTAgNj4sCj4gPj4+PiArwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgIDwmY3JnX3JzdCAweDkwIDU+Owo+ID4+Pj4gKwo+ID4+Pj4gK8KgwqDCoMKgwqDCoMKg IGR3YzM6IGR3YzNAZmYxMDAwMDAgewoKUGxlYXNlIGNvbWJpbmUgdGhlc2UgaW50byBhIHNpbmds ZSBub2RlLiBVbmxlc3MgeW91IGhhdmUgYSB3cmFwcGVyIHdpdGggCnJlZ2lzdGVycywgeW91IGRv bid0IG5lZWQgdGhlc2UgMiBub2Rlcy4gQ2xvY2tzIGFuZCByZXNldCBjYW4gZ28gaW4gdGhlIApk d2MzIG5vZGUuCgo+ID4+Pgo+ID4+PiDCoMKgwqDCoCBBY2NvcmRpbmcgdG8gdGhlIERUIHNwZWMs IHRoZSBub2RlIG5hbWVzIHNob3VsZCBiZSBnZW5lcmljLCBub3QgY2hpcCBzcGVjaWZpYywgaS5l LiB1c2JAZmYxMDAwMDAgaW4gdGhpcyBjYXNlLgo+ID4+Pgo+ID4+Cj4gPj4gRG8geW91IG1lYW4g aXQgc2hvdWxkIGJlIHVzYkBmZjEwMDAwMDogZHdjM0BmZjEwMDAwMCA/Cj4gPiAKPiA+IMKgwqDC oMKgZHdjMzogdXNiQGZmMTAwMDAwCj4gPiAKPiA+IMKgwqAgImR3YzM6IiBpcyBhIGxhYmVsLCBu b3QgbmFtZS4KPiAKPiBJIHVzZSB0aGUgbm9kZSBuYW1lICJkd2MzQGZmMTAwMDAwIiBhY2NvcmRp bmcgdG8gRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL3VzYi9kd2MzLnR4dAo+IGFu ZCBkb2N1bWVudGF0aW9ucyBvZiB2ZW5kb3IgZHJpdmVycywgaS5lLiBxY29tLGR3YzMudHh0LCBy b2NrY2hpcCxkd2MzLnR4dC4KPiAKPiBJbiB0aGVzZSBkb2N1bWVudGF0aW9ucywgdGhlIGR3YzMg c3ViLW5vZGUgbmFtZSB1c2VzICJkd2MzQHh4eHh4eHh4Ii4KPiAKPiBJIHRoaW5rIGl0IGlzIGJl dHRlciB0byBiZSBzYW1lIGFzIHRoZSBvdGhlciB2ZW5kb3IncyBkd2MzIGRyaXZlcnMuCgpJdCdz IG5vdC4gVGhlIG90aGVyIGJpbmRpbmdzIGFyZSB3cm9uZy4gRm9sbG93IHRoZSBEVCBTcGVjLgoK Um9iCg==