From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [PATCH v3 1/3] drm/msm/a6xx: Add support for an interconnect path Date: Thu, 20 Dec 2018 10:30:24 -0700 Message-ID: <20181220173026.3857-2-jcrouse@codeaurora.org> References: <20181220173026.3857-1-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20181220173026.3857-1-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Kees Cook , Arnd Bergmann , David Airlie , linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Sharat Masetty , dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, Stephen Boyd , Rob Clark , Andy Gross , Colin Ian King , Johan Hovold , Bjorn Andersson , georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-arm-msm@vger.kernel.org VHJ5IHRvIGdldCB0aGUgaW50ZXJjb25uZWN0IHBhdGggZm9yIHRoZSBHUFUgYW5kIHZvdGUgZm9y IHRoZSBtYXhpbXVtCmJhbmR3aWR0aCB0byBzdXBwb3J0IGFsbCBmcmVxdWVuY2llcy4gVGhpcyBp cyBuZWVkZWQgZm9yIHBlcmZvcm1hbmNlLgpMYXRlciB3ZSB3aWxsIHdhbnQgdG8gc2NhbGUgdGhl IGJhbmR3aWR0aCBiYXNlZCBvbiB0aGUgZnJlcXVlbmN5IHRvCmFsc28gb3B0aW1pemUgZm9yIHBv d2VyIGJ1dCB0aGF0IHdpbGwgcmVxdWlyZSBzb21lIGRldmljZSB0cmVlCmluZnJhc3RydWN0dXJl IHRoYXQgZG9lcyBub3QgeWV0IGV4aXN0LgoKdjU6IFJlbW92ZSBoYXJkY29kZWQgaW50ZXJjb25u ZWN0IG5hbWUgYW5kIGp1c3QgdXNlIHRoZSBkZWZhdWx0CnY0OiBEb24ndCB1c2UgYSBwb3J0IHN0 cmluZyBhdCBhbGwgdG8gc2tpcCB0aGUgbmVlZCBmb3IgbmFtZXMgaW4gdGhlIERUCnYzOiBVc2Ug bWFjcm9zIGFuZCBjaGFuZ2UgcG9ydCBzdHJpbmcgcGVyIEdlb3JnaSBEamFrb3YKClNpZ25lZC1v ZmYtYnk6IEpvcmRhbiBDcm91c2UgPGpjcm91c2VAY29kZWF1cm9yYS5vcmc+Ci0tLQoKIGRyaXZl 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Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EABCDC43387 for ; Thu, 20 Dec 2018 17:30:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B130B217D8 for ; Thu, 20 Dec 2018 17:30:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="GBt0oD2a"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="jf/T79Zg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387718AbeLTRak (ORCPT ); Thu, 20 Dec 2018 12:30:40 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:34962 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732074AbeLTRah (ORCPT ); Thu, 20 Dec 2018 12:30:37 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0C21D608FB; Thu, 20 Dec 2018 17:30:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545327037; bh=o9cq5rWz5J2uy/X1Nr5z/QsG1L+CfT5Y5ZrC6Yu7VjY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GBt0oD2aohOpaXaCuVKs+i6FX+AJeYozoFIj1Z/+g+aKJT3ImN/reERcpzb6k1Lz3 lwCkjQNgASLXrPxXPyhDw5fnLdfGQfF2et9sGb8hbYTgegyOZqm2rRCQgK6KYhAdn0 IMLOxl1IGwJV30+fBBv5FNWmYFo0c/iz9/5YtQOc= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4126F607F1; Thu, 20 Dec 2018 17:30:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545327035; bh=o9cq5rWz5J2uy/X1Nr5z/QsG1L+CfT5Y5ZrC6Yu7VjY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jf/T79ZgRqey10F4fgBSjAI+jFB398M+lgm/dpQRuljyR4YTD4HFIjdszDerqnPx4 l2EwbUL8yRGuyG5IAOrfkjP/WqkDVaPJdL1o1kczK6iNkeYR45d4xGLoX/Udesk4ta CnJ2D1Izwo6K8qsIGOjXOLJsJOSkB6KrobcCM2kE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4126F607F1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, dianders@chromium.org, georgi.djakov@linaro.org, Bjorn Andersson , Arnd Bergmann , Stephen Boyd , Kees Cook , Sharat Masetty , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Andy Gross , Rob Clark , David Airlie , Johan Hovold , Colin Ian King Subject: [PATCH v3 1/3] drm/msm/a6xx: Add support for an interconnect path Date: Thu, 20 Dec 2018 10:30:24 -0700 Message-Id: <20181220173026.3857-2-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181220173026.3857-1-jcrouse@codeaurora.org> References: <20181220173026.3857-1-jcrouse@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Try to get the interconnect path for the GPU and vote for the maximum bandwidth to support all frequencies. This is needed for performance. Later we will want to scale the bandwidth based on the frequency to also optimize for power but that will require some device tree infrastructure that does not yet exist. v5: Remove hardcoded interconnect name and just use the default v4: Don't use a port string at all to skip the need for names in the DT v3: Use macros and change port string per Georgi Djakov Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20 ++++++++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++++++++ drivers/gpu/drm/msm/msm_gpu.h | 3 +++ 4 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 843a9d40c05e..990c4350f0c4 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -5,6 +5,7 @@ config DRM_MSM depends on ARCH_QCOM || (ARM && COMPILE_TEST) depends on OF && COMMON_CLK depends on MMU + depends on INTERCONNECT || !INTERCONNECT select QCOM_MDT_LOADER if ARCH_QCOM select REGULATOR select DRM_KMS_HELPER diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 0fb4718ef0df..781b601c6045 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2,6 +2,7 @@ /* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */ #include +#include #include #include @@ -63,6 +64,9 @@ static bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) { + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + struct msm_gpu *gpu = &adreno_gpu->base; int ret; gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); @@ -85,6 +89,12 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); gmu->freq = gmu->gpu_freqs[index]; + + /* + * Eventually we will want to scale the path vote with the frequency but + * for now leave it at max so that the performance is nominal. + */ + icc_set(gpu->icc_path, 0, MBps_to_icc(7216)); } void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) @@ -680,6 +690,8 @@ int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu) int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + struct msm_gpu *gpu = &adreno_gpu->base; struct a6xx_gmu *gmu = &a6xx_gpu->gmu; int status, ret; @@ -695,6 +707,9 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) if (ret) goto out; + /* Set the bus quota to a reasonable value for boot */ + icc_set(gpu->icc_path, 0, MBps_to_icc(3072)); + a6xx_gmu_irq_enable(gmu); /* Check to see if we are doing a cold or warm boot */ @@ -735,6 +750,8 @@ bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) { + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + struct msm_gpu *gpu = &adreno_gpu->base; struct a6xx_gmu *gmu = &a6xx_gpu->gmu; u32 val; @@ -781,6 +798,9 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) /* Tell RPMh to power off the GPU */ a6xx_rpmh_stop(gmu); + /* Remove the bus vote */ + icc_set(gpu->icc_path, 0, 0); + clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); pm_runtime_put_sync(gmu->dev); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index bfeea50fca8a..6629dc3506eb 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -18,6 +18,7 @@ */ #include +#include #include #include #include @@ -695,6 +696,11 @@ static int adreno_get_pwrlevels(struct device *dev, DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); + /* Check for an interconnect path for the bus */ + gpu->icc_path = of_icc_get(dev, NULL); + if (IS_ERR(gpu->icc_path)) + gpu->icc_path = NULL; + return 0; } @@ -732,10 +738,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) { + struct msm_gpu *gpu = &adreno_gpu->base; unsigned int i; for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) release_firmware(adreno_gpu->fw[i]); + icc_put(gpu->icc_path); + msm_gpu_cleanup(&adreno_gpu->base); } diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index fc4040e24a6b..66e0f28dfed8 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -19,6 +19,7 @@ #define __MSM_GPU_H__ #include +#include #include #include "msm_drv.h" @@ -118,6 +119,8 @@ struct msm_gpu { struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; uint32_t fast_rate; + struct icc_path *icc_path; + /* Hang and Inactivity Detection: */ #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ -- 2.18.0