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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
	richard.henderson@linaro.org, david@gibson.dropbear.id.au
Subject: [Qemu-devel] [PATCH v5 2/9] target/ppc: switch EXTRACT_HELPER macros over to use sextract32/extract32
Date: Wed,  2 Jan 2019 09:14:16 +0000	[thread overview]
Message-ID: <20190102091423.21155-3-mark.cave-ayland@ilande.co.uk> (raw)
In-Reply-To: <20190102091423.21155-1-mark.cave-ayland@ilande.co.uk>

These ensure that we consistently handle signed and unsigned extensions correctly
when decoding immediates from instruction opcodes.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/internal.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 8b35863549..5d460247e2 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -52,20 +52,20 @@ FUNC_MASK(mask_u64, uint64_t, 64, UINT64_MAX);
 #define EXTRACT_HELPER(name, shift, nb)                                       \
 static inline uint32_t name(uint32_t opcode)                                  \
 {                                                                             \
-    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
+    return extract32(opcode, shift, nb);                                      \
 }
 
 #define EXTRACT_SHELPER(name, shift, nb)                                      \
 static inline int32_t name(uint32_t opcode)                                   \
 {                                                                             \
-    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
+    return sextract32(opcode, shift, nb);                                     \
 }
 
 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2)                  \
 static inline uint32_t name(uint32_t opcode)                                  \
 {                                                                             \
-    return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) |             \
-            ((opcode >> (shift2)) & ((1 << (nb2)) - 1));                      \
+    return extract32(opcode, shift1, nb1) << nb2 |                            \
+               extract32(opcode, shift2, nb2);                                \
 }
 
 #define EXTRACT_HELPER_SPLIT_3(name,                                          \
-- 
2.11.0

  parent reply	other threads:[~2019-01-02  9:14 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-02  9:14 [Qemu-devel] [PATCH v5 0/9] target/ppc: prepare for conversion to TCG vector operations Mark Cave-Ayland
2019-01-02  9:14 ` [Qemu-devel] [PATCH v5 1/9] target/ppc: fix typo in SIMM5 extraction helper Mark Cave-Ayland
2019-01-02  9:14 ` Mark Cave-Ayland [this message]
2019-01-02  9:14 ` [Qemu-devel] [PATCH v5 3/9] target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access Mark Cave-Ayland
2019-01-02  9:14 ` [Qemu-devel] [PATCH v5 4/9] target/ppc: introduce get_avr64() and set_avr64() helpers for VMX " Mark Cave-Ayland
2019-01-02  9:14 ` [Qemu-devel] [PATCH v5 5/9] target/ppc: introduce get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() helpers for VSR " Mark Cave-Ayland
2019-01-02  9:14 ` [Qemu-devel] [PATCH v5 6/9] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env Mark Cave-Ayland
2019-01-02  9:14 ` [Qemu-devel] [PATCH v5 7/9] target/ppc: merge ppc_vsr_t and ppc_avr_t union types Mark Cave-Ayland
2019-01-02  9:14 ` [Qemu-devel] [PATCH v5 8/9] target/ppc: move FP and VMX registers into aligned vsr register array Mark Cave-Ayland
2019-01-02  9:14 ` [Qemu-devel] [PATCH v5 9/9] target/ppc: replace AVR* macros with Vsr* macros Mark Cave-Ayland
2019-01-03  0:23 ` [Qemu-devel] [PATCH v5 0/9] target/ppc: prepare for conversion to TCG vector operations David Gibson

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