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From: claudius.heine.ext@siemens.com
To: stable@vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Ley Foon Tan <lftan@altera.com>, Claudius Heine <ch@denx.de>
Subject: [PATCH v4.4 5/7] PCI: altera: Poll for link training status after retraining the link
Date: Mon,  7 Jan 2019 11:00:54 +0100	[thread overview]
Message-ID: <20190107100056.12721-6-claudius.heine.ext@siemens.com> (raw)
In-Reply-To: <20190107100056.12721-1-claudius.heine.ext@siemens.com>

From: Ley Foon Tan <lftan@altera.com>

commit 411dc32d8810e0a204c799ce5c97cb56990de1cb upstream

Poll for link training status is cleared before poll for link up status.
This can help to get the reliable link up status, especially when PCIe is
in Gen 3 speed.

Signed-off-by: Ley Foon Tan <lftan@altera.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Claudius Heine <ch@denx.de>
---
 drivers/pci/host/pcie-altera.c | 45 ++++++++++++++++++++++++++++------
 1 file changed, 37 insertions(+), 8 deletions(-)

diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index e4154b2a23ce..e0be9ac5701a 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -61,7 +61,8 @@
 #define TLP_LOOP			500
 #define RP_DEVFN			0
 
-#define LINK_UP_TIMEOUT			5000
+#define LINK_UP_TIMEOUT			HZ
+#define LINK_RETRAIN_TIMEOUT		HZ
 
 #define INTX_NUM			4
 
@@ -99,11 +100,44 @@ static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
 	return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
 }
 
+static void altera_wait_link_retrain(struct pci_dev *dev)
+{
+	u16 reg16;
+	unsigned long start_jiffies;
+	struct altera_pcie *pcie = dev->bus->sysdata;
+
+	/* Wait for link training end. */
+	start_jiffies = jiffies;
+	for (;;) {
+		pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &reg16);
+		if (!(reg16 & PCI_EXP_LNKSTA_LT))
+			break;
+
+		if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
+			dev_err(&pcie->pdev->dev, "link retrain timeout\n");
+			break;
+		}
+		udelay(100);
+	}
+
+	/* Wait for link is up */
+	start_jiffies = jiffies;
+	for (;;) {
+		if (altera_pcie_link_is_up(pcie))
+			break;
+
+		if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
+			dev_err(&pcie->pdev->dev, "link up timeout\n");
+			break;
+		}
+		udelay(100);
+	}
+}
+
 static void altera_pcie_retrain(struct pci_dev *dev)
 {
 	u16 linkcap, linkstat;
 	struct altera_pcie *pcie = dev->bus->sysdata;
-	int timeout =  0;
 
 	if (!altera_pcie_link_is_up(pcie))
 		return;
@@ -121,12 +155,7 @@ static void altera_pcie_retrain(struct pci_dev *dev)
 	if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
 		pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
 					 PCI_EXP_LNKCTL_RL);
-		while (!altera_pcie_link_is_up(pcie)) {
-			timeout++;
-			if (timeout > LINK_UP_TIMEOUT)
-				break;
-			udelay(5);
-		}
+		altera_wait_link_retrain(dev);
 	}
 }
 DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
-- 
2.19.2


  parent reply	other threads:[~2019-01-07 10:07 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-07 10:00 [PATCH v4.4 0/7] PCI: altera: survive warm reboot claudius.heine.ext
2019-01-07 10:00 ` [PATCH v4.4 1/7] PCI: altera: Fix altera_pcie_link_is_up() claudius.heine.ext
2019-01-07 10:00 ` [PATCH v4.4 2/7] PCI: altera: Reorder read/write functions claudius.heine.ext
2019-01-07 10:00 ` [PATCH v4.4 3/7] PCI: altera: Check link status before retrain link claudius.heine.ext
2019-01-07 10:00 ` [PATCH v4.4 4/7] PCI: altera: Poll for link up status after retraining the link claudius.heine.ext
2019-01-07 10:00 ` claudius.heine.ext [this message]
2019-01-07 10:00 ` [PATCH v4.4 6/7] PCI: altera: Rework config accessors for use without a struct pci_bus claudius.heine.ext
2019-01-07 10:00 ` [PATCH v4.4 7/7] PCI: altera: Move retrain from fixup to altera_pcie_host_init() claudius.heine.ext
2019-01-10 19:15 ` [PATCH v4.4 0/7] PCI: altera: survive warm reboot Greg KH
2019-01-14  8:24   ` Claudius Heine
2019-01-14 17:40     ` Greg KH
2019-01-15  8:34       ` Claudius Heine

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