On Mon, Jan 07, 2019 at 07:43:14PM +0100, Cédric Le Goater wrote: > The support for XIVE native exploitation mode in Linux/KVM needs a > couple more OPAL calls to configure the sPAPR guest and to get/set the > state of the XIVE internal structures. > > Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson > --- > arch/powerpc/include/asm/opal-api.h | 11 ++- > arch/powerpc/include/asm/opal.h | 7 ++ > arch/powerpc/include/asm/xive.h | 14 +++ > arch/powerpc/sysdev/xive/native.c | 99 +++++++++++++++++++ > .../powerpc/platforms/powernv/opal-wrappers.S | 3 + > 5 files changed, 130 insertions(+), 4 deletions(-) > > diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h > index 870fb7b239ea..cdfc54f78101 100644 > --- a/arch/powerpc/include/asm/opal-api.h > +++ b/arch/powerpc/include/asm/opal-api.h > @@ -186,8 +186,8 @@ > #define OPAL_XIVE_FREE_IRQ 140 > #define OPAL_XIVE_SYNC 141 > #define OPAL_XIVE_DUMP 142 > -#define OPAL_XIVE_RESERVED3 143 > -#define OPAL_XIVE_RESERVED4 144 > +#define OPAL_XIVE_GET_QUEUE_STATE 143 > +#define OPAL_XIVE_SET_QUEUE_STATE 144 > #define OPAL_SIGNAL_SYSTEM_RESET 145 > #define OPAL_NPU_INIT_CONTEXT 146 > #define OPAL_NPU_DESTROY_CONTEXT 147 > @@ -209,8 +209,11 @@ > #define OPAL_SENSOR_GROUP_ENABLE 163 > #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164 > #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165 > -#define OPAL_NX_COPROC_INIT 167 > -#define OPAL_LAST 167 > +#define OPAL_HANDLE_HMI2 166 > +#define OPAL_NX_COPROC_INIT 167 > +#define OPAL_NPU_SET_RELAXED_ORDER 168 > +#define OPAL_NPU_GET_RELAXED_ORDER 169 > +#define OPAL_XIVE_GET_VP_STATE 170 > > #define QUIESCE_HOLD 1 /* Spin all calls at entry */ > #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */ > diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h > index a55b01c90bb1..4e978d4dea5c 100644 > --- a/arch/powerpc/include/asm/opal.h > +++ b/arch/powerpc/include/asm/opal.h > @@ -279,6 +279,13 @@ int64_t opal_xive_allocate_irq(uint32_t chip_id); > int64_t opal_xive_free_irq(uint32_t girq); > int64_t opal_xive_sync(uint32_t type, uint32_t id); > int64_t opal_xive_dump(uint32_t type, uint32_t id); > +int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio, > + __be32 *out_qtoggle, > + __be32 *out_qindex); > +int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio, > + uint32_t qtoggle, > + uint32_t qindex); > +int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01); > int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target, > uint64_t desc, uint16_t pe_number); > > diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h > index 32f033bfbf42..d6be3e4d9fa4 100644 > --- a/arch/powerpc/include/asm/xive.h > +++ b/arch/powerpc/include/asm/xive.h > @@ -132,12 +132,26 @@ extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, > extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio); > > extern void xive_native_sync_source(u32 hw_irq); > +extern void xive_native_sync_queue(u32 hw_irq); > extern bool is_xive_irq(struct irq_chip *chip); > extern int xive_native_enable_vp(u32 vp_id, bool single_escalation); > extern int xive_native_disable_vp(u32 vp_id); > extern int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id); > extern bool xive_native_has_single_escalation(void); > > +extern int xive_native_get_queue_info(u32 vp_id, uint32_t prio, > + u64 *out_qpage, > + u64 *out_qsize, > + u64 *out_qeoi_page, > + u32 *out_escalate_irq, > + u64 *out_qflags); > + > +extern int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle, > + u32 *qindex); > +extern int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle, > + u32 qindex); > +extern int xive_native_get_vp_state(u32 vp_id, u64 *out_state); > + > #else > > static inline bool xive_enabled(void) { return false; } > diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c > index 1ca127d052a6..0c037e933e55 100644 > --- a/arch/powerpc/sysdev/xive/native.c > +++ b/arch/powerpc/sysdev/xive/native.c > @@ -437,6 +437,12 @@ void xive_native_sync_source(u32 hw_irq) > } > EXPORT_SYMBOL_GPL(xive_native_sync_source); > > +void xive_native_sync_queue(u32 hw_irq) > +{ > + opal_xive_sync(XIVE_SYNC_QUEUE, hw_irq); > +} > +EXPORT_SYMBOL_GPL(xive_native_sync_queue); > + > static const struct xive_ops xive_native_ops = { > .populate_irq_data = xive_native_populate_irq_data, > .configure_irq = xive_native_configure_irq, > @@ -711,3 +717,96 @@ bool xive_native_has_single_escalation(void) > return xive_has_single_esc; > } > EXPORT_SYMBOL_GPL(xive_native_has_single_escalation); > + > +int xive_native_get_queue_info(u32 vp_id, u32 prio, > + u64 *out_qpage, > + u64 *out_qsize, > + u64 *out_qeoi_page, > + u32 *out_escalate_irq, > + u64 *out_qflags) > +{ > + __be64 qpage; > + __be64 qsize; > + __be64 qeoi_page; > + __be32 escalate_irq; > + __be64 qflags; > + s64 rc; > + > + rc = opal_xive_get_queue_info(vp_id, prio, &qpage, &qsize, > + &qeoi_page, &escalate_irq, &qflags); > + if (rc) { > + pr_err("OPAL failed to get queue info for VCPU %d/%d : %lld\n", > + vp_id, prio, rc); > + return -EIO; > + } > + > + if (out_qpage) > + *out_qpage = be64_to_cpu(qpage); > + if (out_qsize) > + *out_qsize = be32_to_cpu(qsize); > + if (out_qeoi_page) > + *out_qeoi_page = be64_to_cpu(qeoi_page); > + if (out_escalate_irq) > + *out_escalate_irq = be32_to_cpu(escalate_irq); > + if (out_qflags) > + *out_qflags = be64_to_cpu(qflags); > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(xive_native_get_queue_info); > + > +int xive_native_get_queue_state(u32 vp_id, u32 prio, u32 *qtoggle, u32 *qindex) > +{ > + __be32 opal_qtoggle; > + __be32 opal_qindex; > + s64 rc; > + > + rc = opal_xive_get_queue_state(vp_id, prio, &opal_qtoggle, > + &opal_qindex); > + if (rc) { > + pr_err("OPAL failed to get queue state for VCPU %d/%d : %lld\n", > + vp_id, prio, rc); > + return -EIO; > + } > + > + if (qtoggle) > + *qtoggle = be32_to_cpu(opal_qtoggle); > + if (qindex) > + *qindex = be32_to_cpu(opal_qindex); > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(xive_native_get_queue_state); > + > +int xive_native_set_queue_state(u32 vp_id, u32 prio, u32 qtoggle, u32 qindex) > +{ > + s64 rc; > + > + rc = opal_xive_set_queue_state(vp_id, prio, qtoggle, qindex); > + if (rc) { > + pr_err("OPAL failed to set queue state for VCPU %d/%d : %lld\n", > + vp_id, prio, rc); > + return -EIO; > + } > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(xive_native_set_queue_state); > + > +int xive_native_get_vp_state(u32 vp_id, u64 *out_state) > +{ > + __be64 state; > + s64 rc; > + > + rc = opal_xive_get_vp_state(vp_id, &state); > + if (rc) { > + pr_err("OPAL failed to get vp state for VCPU %d : %lld\n", > + vp_id, rc); > + return -EIO; > + } > + > + if (out_state) > + *out_state = be64_to_cpu(state); > + return 0; > +} > +EXPORT_SYMBOL_GPL(xive_native_get_vp_state); > diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S > index f4875fe3f8ff..3179953d6b56 100644 > --- a/arch/powerpc/platforms/powernv/opal-wrappers.S > +++ b/arch/powerpc/platforms/powernv/opal-wrappers.S > @@ -309,6 +309,9 @@ OPAL_CALL(opal_xive_get_vp_info, OPAL_XIVE_GET_VP_INFO); > OPAL_CALL(opal_xive_set_vp_info, OPAL_XIVE_SET_VP_INFO); > OPAL_CALL(opal_xive_sync, OPAL_XIVE_SYNC); > OPAL_CALL(opal_xive_dump, OPAL_XIVE_DUMP); > +OPAL_CALL(opal_xive_get_queue_state, OPAL_XIVE_GET_QUEUE_STATE); > +OPAL_CALL(opal_xive_set_queue_state, OPAL_XIVE_SET_QUEUE_STATE); > +OPAL_CALL(opal_xive_get_vp_state, OPAL_XIVE_GET_VP_STATE); > OPAL_CALL(opal_signal_system_reset, OPAL_SIGNAL_SYSTEM_RESET); > OPAL_CALL(opal_npu_init_context, OPAL_NPU_INIT_CONTEXT); > OPAL_CALL(opal_npu_destroy_context, OPAL_NPU_DESTROY_CONTEXT); -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson