From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 09 Jan 2019 21:55:55 -0000 Received: from mga07.intel.com ([134.134.136.100]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1ghLpJ-0005DR-CR for speck@linutronix.de; Wed, 09 Jan 2019 22:55:54 +0100 Date: Wed, 9 Jan 2019 13:55:50 -0800 From: Andi Kleen Subject: [MODERATED] Re: qemu patch for mb_clear Message-ID: <20190109215550.GX6118@tassilo.jf.intel.com> References: <20181221003101.GA32181@tassilo.jf.intel.com> <20190109170919.GU23427@char.us.oracle.com> <2a833765-3d5a-3664-dd5e-3a256a29ff4b@redhat.com> MIME-Version: 1.0 In-Reply-To: <2a833765-3d5a-3664-dd5e-3a256a29ff4b@redhat.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: > >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c > >> index 677a3bd5fb25..77a1149e4bb3 100644 > >> --- a/target/i386/cpu.c > >> +++ b/target/i386/cpu.c > >> @@ -1038,7 +1038,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > >> .feat_names = { > >> NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", > >> NULL, NULL, NULL, NULL, > >> - NULL, NULL, NULL, NULL, > >> + NULL, NULL, "mbclear", NULL, > >> NULL, NULL, NULL, NULL, > >> NULL, NULL, "pconfig", NULL, > >> NULL, NULL, NULL, NULL, > > Are there any CPU families which will all have it (e.g. IceLake server, > Cascade Lake?). Prerelease/prototype silicon does not count. All the past ones which get the VERW microcode update (somewhere between Nehalem and Skylake) Future systems which don't have/need VERW won't have it in fact -Andi