From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE989C43612 for ; Fri, 11 Jan 2019 14:24:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BB0052177B for ; Fri, 11 Jan 2019 14:24:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388222AbfAKOY2 (ORCPT ); Fri, 11 Jan 2019 09:24:28 -0500 Received: from metis.ext.pengutronix.de ([85.220.165.71]:47479 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388023AbfAKOXX (ORCPT ); Fri, 11 Jan 2019 09:23:23 -0500 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1ghxiP-00054O-7A; Fri, 11 Jan 2019 15:23:17 +0100 Received: from ore by dude.hi.pengutronix.de with local (Exim 4.92-RC4) (envelope-from ) id 1ghxiO-0002wl-6W; Fri, 11 Jan 2019 15:23:16 +0100 From: Oleksij Rempel To: Paul Burton , Ralf Baechle , James Hogan , Rob Herring Cc: Felix Fietkau , John Crispin , Pengutronix Kernel Team , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v1 06/11] MIPS: ath79: export switch MDIO reference clock Date: Fri, 11 Jan 2019 15:22:35 +0100 Message-Id: <20190111142240.10908-7-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190111142240.10908-1-o.rempel@pengutronix.de> References: <20190111142240.10908-1-o.rempel@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Felix Fietkau On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz clock. If that feature is not used, it defaults to the main reference clock, like on all other SoC. Signed-off-by: Felix Fietkau Signed-off-by: John Crispin --- arch/mips/ath79/clock.c | 8 ++++++++ include/dt-bindings/clock/ath79-clk.h | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index c234818b30e1..699f00f096cb 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -42,6 +42,7 @@ static const char * const clk_names[ATH79_CLK_END] = { [ATH79_CLK_DDR] = "ddr", [ATH79_CLK_AHB] = "ahb", [ATH79_CLK_REF] = "ref", + [ATH79_CLK_MDIO] = "mdio", }; static const char * __init ath79_clk_name(int type) @@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(void __iomem *pll_base) ath79_set_clk(ATH79_CLK_DDR, ddr_rate); ath79_set_clk(ATH79_CLK_AHB, ahb_rate); + clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); + if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) + ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000); + iounmap(dpll_base); } @@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt(struct device_node *np) else if (of_device_is_compatible(np, "qca,qca9560-pll")) qca956x_clocks_init(pll_base); + if (!clks[ATH79_CLK_MDIO]) + clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF]; + if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { pr_err("%pOF: could not register clk provider\n", np); goto err_iounmap; diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h index 262d7c5eb248..dcc679a7ad85 100644 --- a/include/dt-bindings/clock/ath79-clk.h +++ b/include/dt-bindings/clock/ath79-clk.h @@ -14,7 +14,8 @@ #define ATH79_CLK_DDR 1 #define ATH79_CLK_AHB 2 #define ATH79_CLK_REF 3 +#define ATH79_CLK_MDIO 4 -#define ATH79_CLK_END 4 +#define ATH79_CLK_END 5 #endif /* __DT_BINDINGS_ATH79_CLK_H */ -- 2.20.1