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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Murali Karicheri <m-karicheri2@ti.com>,
	Jesper Nilsson <jesper.nilsson@axis.com>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-arm-kernel@axis.com>
Subject: [PATCH 22/24] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts
Date: Mon, 14 Jan 2019 18:54:22 +0530	[thread overview]
Message-ID: <20190114132424.6445-23-kishon@ti.com> (raw)
In-Reply-To: <20190114132424.6445-1-kishon@ti.com>

Certain platforms like K2G reguires the outbound ATU window to be
aligned. The alignment size is already present in mem->page_size.
Use the alignment size present in mem->page_size to configre a
aligned ATU window. In order to raise an interrupt, CPU has to write
to address offset from the start of the window unlike before where
writes were always to the beginning of the ATU window.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 47cc06bac91f..f557e83bc34c 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -397,6 +397,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 	struct pci_epc *epc = ep->epc;
+	unsigned int aligned_offset;
 	u16 msg_ctrl, msg_data;
 	u32 msg_addr_lower, msg_addr_upper, reg;
 	u64 msg_addr;
@@ -422,13 +423,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 		reg = ep->msi_cap + PCI_MSI_DATA_32;
 		msg_data = dw_pcie_readw_dbi(pci, reg);
 	}
-	msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
+	aligned_offset = msg_addr_lower & (epc->mem->page_size - 1);
+	msg_addr = ((u64)msg_addr_upper) << 32 |
+			(msg_addr_lower & ~aligned_offset);
 	ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
 				  epc->mem->page_size);
 	if (ret)
 		return ret;
 
-	writel(msg_data | (interrupt_num - 1), ep->msi_mem);
+	writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset);
 
 	dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
 
-- 
2.17.1


WARNING: multiple messages have this Message-ID
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Murali Karicheri <m-karicheri2@ti.com>,
	Jesper Nilsson <jesper.nilsson@axis.com>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-arm-kernel@axis.com
Subject: [PATCH 22/24] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts
Date: Mon, 14 Jan 2019 18:54:22 +0530	[thread overview]
Message-ID: <20190114132424.6445-23-kishon@ti.com> (raw)
In-Reply-To: <20190114132424.6445-1-kishon@ti.com>

Certain platforms like K2G reguires the outbound ATU window to be
aligned. The alignment size is already present in mem->page_size.
Use the alignment size present in mem->page_size to configre a
aligned ATU window. In order to raise an interrupt, CPU has to write
to address offset from the start of the window unlike before where
writes were always to the beginning of the ATU window.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 47cc06bac91f..f557e83bc34c 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -397,6 +397,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 	struct pci_epc *epc = ep->epc;
+	unsigned int aligned_offset;
 	u16 msg_ctrl, msg_data;
 	u32 msg_addr_lower, msg_addr_upper, reg;
 	u64 msg_addr;
@@ -422,13 +423,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 		reg = ep->msi_cap + PCI_MSI_DATA_32;
 		msg_data = dw_pcie_readw_dbi(pci, reg);
 	}
-	msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
+	aligned_offset = msg_addr_lower & (epc->mem->page_size - 1);
+	msg_addr = ((u64)msg_addr_upper) << 32 |
+			(msg_addr_lower & ~aligned_offset);
 	ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
 				  epc->mem->page_size);
 	if (ret)
 		return ret;
 
-	writel(msg_data | (interrupt_num - 1), ep->msi_mem);
+	writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset);
 
 	dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
 
-- 
2.17.1

WARNING: multiple messages have this Message-ID
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org,
	Jesper Nilsson <jesper.nilsson@axis.com>,
	Arnd Bergmann <arnd@arndb.de>, Jingoo Han <jingoohan1@gmail.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@axis.com, Kishon Vijay Abraham I <kishon@ti.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 22/24] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts
Date: Mon, 14 Jan 2019 18:54:22 +0530	[thread overview]
Message-ID: <20190114132424.6445-23-kishon@ti.com> (raw)
In-Reply-To: <20190114132424.6445-1-kishon@ti.com>

Certain platforms like K2G reguires the outbound ATU window to be
aligned. The alignment size is already present in mem->page_size.
Use the alignment size present in mem->page_size to configre a
aligned ATU window. In order to raise an interrupt, CPU has to write
to address offset from the start of the window unlike before where
writes were always to the beginning of the ATU window.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 47cc06bac91f..f557e83bc34c 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -397,6 +397,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 	struct pci_epc *epc = ep->epc;
+	unsigned int aligned_offset;
 	u16 msg_ctrl, msg_data;
 	u32 msg_addr_lower, msg_addr_upper, reg;
 	u64 msg_addr;
@@ -422,13 +423,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 		reg = ep->msi_cap + PCI_MSI_DATA_32;
 		msg_data = dw_pcie_readw_dbi(pci, reg);
 	}
-	msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
+	aligned_offset = msg_addr_lower & (epc->mem->page_size - 1);
+	msg_addr = ((u64)msg_addr_upper) << 32 |
+			(msg_addr_lower & ~aligned_offset);
 	ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
 				  epc->mem->page_size);
 	if (ret)
 		return ret;
 
-	writel(msg_data | (interrupt_num - 1), ep->msi_mem);
+	writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset);
 
 	dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
 
-- 
2.17.1


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  parent reply	other threads:[~2019-01-14 13:27 UTC|newest]

Thread overview: 100+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-14 13:24 [PATCH 00/24] Add support for PCIe RC and EP mode in TI's AM654 SoC Kishon Vijay Abraham I
2019-01-14 13:24 ` Kishon Vijay Abraham I
2019-01-14 13:24 ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 01/24] PCI: keystone: Add start_link/stop_link dw_pcie_ops Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 02/24] PCI: keystone: Cleanup error_irq configuration Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 03/24] dt-bindings: PCI: keystone: Add "reg-names" binding information Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-22  0:31   ` Rob Herring
2019-01-22  0:31     ` Rob Herring
2019-01-22  0:31     ` Rob Herring
2019-01-14 13:24 ` [PATCH 04/24] PCI: keystone: Perform host initialization in a single function Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 05/24] PCI: keystone: Use platform_get_resource_byname to get memory resources Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 06/24] PCI: keystone: Move initializations to appropriate places Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 07/24] dt-bindings: PCI: Add dt-binding to configure PCIe mode Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-22  0:32   ` Rob Herring
2019-01-22  0:32     ` Rob Herring
2019-01-22  0:32     ` Rob Herring
2019-01-14 13:24 ` [PATCH 08/24] PCI: keystone: Explicitly set the " Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 09/24] dt-bindings: PCI: Document "atu" reg-names Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-22  0:48   ` Rob Herring
2019-01-22  0:48     ` Rob Herring
2019-01-23 10:04     ` Kishon Vijay Abraham I
2019-01-23 10:04       ` Kishon Vijay Abraham I
2019-01-23 10:04       ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 10/24] PCI: dwc: Enable iATU unroll for endpoint too Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 11/24] PCI: dwc: Fix ATU identification for designware version >= 4.80 Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 12/24] PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 13/24] dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-22  0:48   ` Rob Herring
2019-01-22  0:48     ` Rob Herring
2019-01-22  0:48     ` Rob Herring
2019-01-14 13:24 ` [PATCH 14/24] PCI: keystone: Add support for PCIe RC in AM654x Platforms Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 15/24] PCI: keystone: Invoke phy_reset API before enabling PHY Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 16/24] PCI: endpoint: Add support to allocate aligned buffers to be mapped in BARs Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 17/24] PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 18/24] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-29  9:25   ` Gustavo Pimentel
2019-01-29  9:25     ` Gustavo Pimentel
2019-01-29  9:25     ` Gustavo Pimentel
2019-01-29 10:19     ` Kishon Vijay Abraham I
2019-01-29 10:19       ` Kishon Vijay Abraham I
2019-01-29 10:19       ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 19/24] PCI: dwc: Add callbacks for accessing dbi2 address space Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 20/24] PCI: keystone: Add support for PCIe EP in AM654x Platforms Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 21/24] PCI: designware-ep: Configure RESBAR to advertise the smallest size Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` Kishon Vijay Abraham I [this message]
2019-01-14 13:24   ` [PATCH 22/24] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 23/24] misc: pci_endpoint_test: Add support to test PCI EP in AM654x Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 24/24] misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-01-14 13:24   ` Kishon Vijay Abraham I
2019-02-04 16:40 ` [PATCH 00/24] Add support for PCIe RC and EP mode in TI's AM654 SoC Lorenzo Pieralisi
2019-02-04 16:40   ` Lorenzo Pieralisi
2019-02-06 12:50   ` Kishon Vijay Abraham I
2019-02-06 12:50     ` Kishon Vijay Abraham I
2019-02-06 12:50     ` Kishon Vijay Abraham I

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