From mboxrd@z Thu Jan 1 00:00:00 1970 From: Manivannan Sadhasivam Date: Thu, 17 Jan 2019 20:23:08 +0530 Subject: [U-Boot] [PATCH 1/3] poplar: sync up device tree with kernel 4.20 In-Reply-To: <20190117040952.4024-2-shawn.guo@linaro.org> References: <20190117040952.4024-1-shawn.guo@linaro.org> <20190117040952.4024-2-shawn.guo@linaro.org> Message-ID: <20190117145308.GA5283@Mani-XPS-13-9360> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Shawn, On Thu, Jan 17, 2019 at 12:09:50PM +0800, Shawn Guo wrote: > It adds missing pinctrl headers, updates clock header and sync up Poplar > device tree with kernel 4.20 release. > > Signed-off-by: Shawn Guo > --- > arch/arm/dts/hi3798cv200-poplar.dts | 68 ++++++-- > arch/arm/dts/hi3798cv200.dtsi | 221 +++++++++++++++++++++++- > arch/arm/dts/poplar-pinctrl.dtsi | 98 +++++++++++ > include/dt-bindings/clock/histb-clock.h | 56 +++--- > include/dt-bindings/pinctrl/hisi.h | 74 ++++++++ > 5 files changed, 482 insertions(+), 35 deletions(-) > create mode 100644 arch/arm/dts/poplar-pinctrl.dtsi > create mode 100644 include/dt-bindings/pinctrl/hisi.h > > diff --git a/arch/arm/dts/hi3798cv200-poplar.dts b/arch/arm/dts/hi3798cv200-poplar.dts > index 964326eae89b..d30f6eb8a5ee 100644 > --- a/arch/arm/dts/hi3798cv200-poplar.dts > +++ b/arch/arm/dts/hi3798cv200-poplar.dts > @@ -1,14 +1,17 @@ > -// SPDX-License-Identifier: GPL-2.0 > /* > * DTS File for HiSilicon Poplar Development Board > * > * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. > + * > + * Released under the GPLv2 only. > + * SPDX-License-Identifier: GPL-2.0 This is a malformed license identifier. Eventhough it is being imported from Linux kernel, we need to fix this (on both). > */ > > /dts-v1/; > > #include > #include "hi3798cv200.dtsi" > +#include "poplar-pinctrl.dtsi" > > / { > model = "HiSilicon Poplar Development Board"; > @@ -59,6 +62,33 @@ > default-state = "off"; > }; > }; > + > + reg_pcie: regulator-pcie { > + compatible = "regulator-fixed"; > + regulator-name = "3V3_PCIE0"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio6 7 0>; > + enable-active-high; > + }; > +}; > + > +&ehci { > + status = "okay"; > +}; > + > +&emmc { > + pinctrl-names = "default"; > + pinctrl-0 = <&emmc_pins_1 &emmc_pins_2 > + &emmc_pins_3 &emmc_pins_4>; > + fifo-depth = <256>; > + clock-frequency = <200000000>; > + cap-mmc-highspeed; > + mmc-ddr-1_8v; > + mmc-hs200-1_8v; > + non-removable; > + bus-width = <8>; > + status = "okay"; > }; > > &gmac1 { > @@ -76,17 +106,17 @@ > > &gpio1 { > status = "okay"; > - gpio-line-names = "LS-GPIO-E", "", > + gpio-line-names = "GPIO-E", "", > "", "", > - "", "LS-GPIO-F", > - "", "LS-GPIO-J"; > + "", "GPIO-F", > + "", "GPIO-J"; > }; > > &gpio2 { > status = "okay"; > - gpio-line-names = "LS-GPIO-H", "LS-GPIO-I", > - "LS-GPIO-L", "LS-GPIO-G", > - "LS-GPIO-K", "", > + gpio-line-names = "GPIO-H", "GPIO-I", > + "GPIO-L", "GPIO-G", > + "GPIO-K", "", > "", ""; > }; > > @@ -94,15 +124,15 @@ > status = "okay"; > gpio-line-names = "", "", > "", "", > - "LS-GPIO-C", "", > - "", "LS-GPIO-B"; > + "GPIO-C", "", > + "", "GPIO-B"; > }; > > &gpio4 { > status = "okay"; > gpio-line-names = "", "", > "", "", > - "", "LS-GPIO-D", > + "", "GPIO-D", > "", ""; > }; > > @@ -110,7 +140,7 @@ > status = "okay"; > gpio-line-names = "", "USER-LED-1", > "USER-LED-2", "", > - "", "LS-GPIO-A", > + "", "GPIO-A", > "", ""; > }; > > @@ -144,6 +174,22 @@ > status = "okay"; > }; > > +&ohci { > + status = "okay"; > +}; > + > +&pcie { > + reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; > + vpcie-supply = <®_pcie>; > + status = "okay"; > +}; > + > +&sd0 { > + bus-width = <4>; > + cap-sd-highspeed; > + status = "okay"; > +}; > + > &spi0 { > status = "okay"; > label = "LS-SPI0"; > diff --git a/arch/arm/dts/hi3798cv200.dtsi b/arch/arm/dts/hi3798cv200.dtsi > index 8b9c5ad05a19..7c0fddd7c8cf 100644 > --- a/arch/arm/dts/hi3798cv200.dtsi > +++ b/arch/arm/dts/hi3798cv200.dtsi > @@ -1,12 +1,16 @@ > -// SPDX-License-Identifier: GPL-2.0 > /* > * DTS File for HiSilicon Hi3798cv200 SoC. > * > * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. > + * > + * Released under the GPLv2 only. > + * SPDX-License-Identifier: GPL-2.0 Same as above. > */ > > #include > +#include > #include > +#include > #include > > / { > @@ -104,6 +108,113 @@ > #reset-cells = <2>; > }; > > + perictrl: peripheral-controller at 8a20000 { > + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", > + "simple-mfd"; > + reg = <0x8a20000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x8a20000 0x1000>; > + > + usb2_phy1: usb2-phy at 120 { > + compatible = "hisilicon,hi3798cv200-usb2-phy"; > + reg = <0x120 0x4>; > + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; > + resets = <&crg 0xbc 4>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + usb2_phy1_port0: phy at 0 { > + reg = <0>; > + #phy-cells = <0>; > + resets = <&crg 0xbc 8>; > + }; > + > + usb2_phy1_port1: phy at 1 { > + reg = <1>; > + #phy-cells = <0>; > + resets = <&crg 0xbc 9>; > + }; > + }; > + > + usb2_phy2: usb2-phy at 124 { > + compatible = "hisilicon,hi3798cv200-usb2-phy"; > + reg = <0x124 0x4>; > + clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; > + resets = <&crg 0xbc 6>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + usb2_phy2_port0: phy at 0 { > + reg = <0>; > + #phy-cells = <0>; > + resets = <&crg 0xbc 10>; > + }; > + }; > + > + combphy0: phy at 850 { > + compatible = "hisilicon,hi3798cv200-combphy"; > + reg = <0x850 0x8>; > + #phy-cells = <1>; > + clocks = <&crg HISTB_COMBPHY0_CLK>; > + resets = <&crg 0x188 4>; > + assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; > + assigned-clock-rates = <100000000>; > + hisilicon,fixed-mode = ; > + }; > + > + combphy1: phy at 858 { > + compatible = "hisilicon,hi3798cv200-combphy"; > + reg = <0x858 0x8>; > + #phy-cells = <1>; > + clocks = <&crg HISTB_COMBPHY1_CLK>; > + resets = <&crg 0x188 12>; > + assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; > + assigned-clock-rates = <100000000>; > + hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; > + }; > + }; > + > + pmx0: pinconf at 8a21000 { > + compatible = "pinconf-single"; > + reg = <0x8a21000 0x180>; > + pinctrl-single,register-width = <32>; > + pinctrl-single,function-mask = <7>; > + pinctrl-single,gpio-range = < > + &range 0 8 2 /* GPIO 0 */ > + &range 8 1 0 /* GPIO 1 */ > + &range 9 4 2 > + &range 13 1 0 > + &range 14 1 1 > + &range 15 1 0 > + &range 16 5 0 /* GPIO 2 */ > + &range 21 3 1 > + &range 24 4 1 /* GPIO 3 */ > + &range 28 2 2 > + &range 86 1 1 > + &range 87 1 0 > + &range 30 4 2 /* GPIO 4 */ > + &range 34 3 0 > + &range 37 1 2 > + &range 38 3 2 /* GPIO 6 */ > + &range 41 5 0 > + &range 46 8 1 /* GPIO 7 */ > + &range 54 8 1 /* GPIO 8 */ > + &range 64 7 1 /* GPIO 9 */ > + &range 71 1 0 > + &range 72 6 1 /* GPIO 10 */ > + &range 78 1 0 > + &range 79 1 1 > + &range 80 6 1 /* GPIO 11 */ > + &range 70 2 1 > + &range 88 8 0 /* GPIO 12 */ > + >; > + > + range: gpio-range { > + #pinctrl-single,gpio-range-cells = <3>; > + }; > + }; > + > uart0: serial at 8b00000 { > compatible = "arm,pl011", "arm,primecell"; > reg = <0x8b00000 0x1000>; > @@ -190,13 +301,30 @@ > status = "disabled"; > }; > > - emmc: mmc at 9830000 { > + sd0: mmc at 9820000 { > compatible = "snps,dw-mshc"; > + reg = <0x9820000 0x10000>; > + interrupts = ; > + clocks = <&crg HISTB_SDIO0_CIU_CLK>, > + <&crg HISTB_SDIO0_BIU_CLK>; > + clock-names = "ciu", "biu"; > + resets = <&crg 0x9c 4>; > + reset-names = "reset"; > + status = "disabled"; > + }; > + > + emmc: mmc at 9830000 { > + compatible = "hisilicon,hi3798cv200-dw-mshc"; > reg = <0x9830000 0x10000>; > interrupts = ; > clocks = <&crg HISTB_MMC_CIU_CLK>, > - <&crg HISTB_MMC_BIU_CLK>; > - clock-names = "ciu", "biu"; > + <&crg HISTB_MMC_BIU_CLK>, > + <&crg HISTB_MMC_SAMPLE_CLK>, > + <&crg HISTB_MMC_DRV_CLK>; > + clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; > + resets = <&crg 0xa0 4>; > + reset-names = "reset"; > + status = "disabled"; > }; > > gpio0: gpio at 8b20000 { > @@ -207,6 +335,7 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = <&pmx0 0 0 8>; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -220,6 +349,13 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = < > + &pmx0 0 8 1 > + &pmx0 1 9 4 > + &pmx0 5 13 1 > + &pmx0 6 14 1 > + &pmx0 7 15 1 > + >; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -233,6 +369,7 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -246,6 +383,12 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = < > + &pmx0 0 24 4 > + &pmx0 4 28 2 > + &pmx0 6 86 1 > + &pmx0 7 87 1 > + >; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -259,6 +402,7 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -285,6 +429,7 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -298,6 +443,7 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = <&pmx0 0 46 8>; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -311,6 +457,7 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = <&pmx0 0 54 8>; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -324,6 +471,7 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -337,6 +485,7 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -350,6 +499,7 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -363,6 +513,7 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + gpio-ranges = <&pmx0 0 88 8>; > clocks = <&crg HISTB_APB_CLK>; > clock-names = "apb_pclk"; > status = "disabled"; > @@ -405,5 +556,67 @@ > clocks = <&sysctrl HISTB_IR_CLK>; > status = "disabled"; > }; > + > + pcie: pcie at 9860000 { > + compatible = "hisilicon,hi3798cv200-pcie"; > + reg = <0x9860000 0x1000>, > + <0x0 0x2000>, > + <0x2000000 0x01000000>; > + reg-names = "control", "rc-dbi", "config"; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + bus-range = <0 15>; > + num-lanes = <1>; > + ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000 > + 0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>; > + interrupts = ; > + interrupt-names = "msi"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&crg HISTB_PCIE_AUX_CLK>, > + <&crg HISTB_PCIE_PIPE_CLK>, > + <&crg HISTB_PCIE_SYS_CLK>, > + <&crg HISTB_PCIE_BUS_CLK>; > + clock-names = "aux", "pipe", "sys", "bus"; > + resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; > + reset-names = "soft", "sys", "bus"; > + phys = <&combphy1 PHY_TYPE_PCIE>; > + phy-names = "phy"; > + status = "disabled"; > + }; > + > + ohci: ohci at 9880000 { > + compatible = "generic-ohci"; > + reg = <0x9880000 0x10000>; > + interrupts = ; > + clocks = <&crg HISTB_USB2_BUS_CLK>, > + <&crg HISTB_USB2_12M_CLK>, > + <&crg HISTB_USB2_48M_CLK>; > + clock-names = "bus", "clk12", "clk48"; > + resets = <&crg 0xb8 12>; > + reset-names = "bus"; > + phys = <&usb2_phy1_port0>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ehci: ehci at 9890000 { > + compatible = "generic-ehci"; > + reg = <0x9890000 0x10000>; > + interrupts = ; > + clocks = <&crg HISTB_USB2_BUS_CLK>, > + <&crg HISTB_USB2_PHY_CLK>, > + <&crg HISTB_USB2_UTMI_CLK>; > + clock-names = "bus", "phy", "utmi"; > + resets = <&crg 0xb8 12>, > + <&crg 0xb8 16>, > + <&crg 0xb8 13>; > + reset-names = "bus", "phy", "utmi"; > + phys = <&usb2_phy1_port0>; > + phy-names = "usb"; > + status = "disabled"; > + }; > }; > }; > diff --git a/arch/arm/dts/poplar-pinctrl.dtsi b/arch/arm/dts/poplar-pinctrl.dtsi > new file mode 100644 > index 000000000000..7bb19e4b084a > --- /dev/null > +++ b/arch/arm/dts/poplar-pinctrl.dtsi > @@ -0,0 +1,98 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Pinctrl dts file for HiSilicon Poplar board > + * > + * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd. > + */ > + > +#include > + > +/* value, enable bits, disable bits, mask */ > +#define PINCTRL_PULLDOWN(value, enable, disable, mask) \ > + (value << 13) (enable << 13) (disable << 13) (mask << 13) > +#define PINCTRL_PULLUP(value, enable, disable, mask) \ > + (value << 12) (enable << 12) (disable << 12) (mask << 12) > +#define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8) > +#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4) > + > +&pmx0 { > + emmc_pins_1: emmc-pins-1 { > + pinctrl-single,pins = < > + 0x000 MUX_M2 > + 0x004 MUX_M2 > + 0x008 MUX_M2 > + 0x00c MUX_M2 > + 0x010 MUX_M2 > + 0x014 MUX_M2 > + 0x018 MUX_M2 > + 0x01c MUX_M2 > + 0x024 MUX_M2 > + >; > + pinctrl-single,bias-pulldown = < > + PINCTRL_PULLDOWN(0, 1, 0, 1) > + >; > + pinctrl-single,bias-pullup = < > + PINCTRL_PULLUP(0, 1, 0, 1) > + >; > + pinctrl-single,slew-rate = < > + PINCTRL_SLEW_RATE(1, 1) > + >; > + pinctrl-single,drive-strength = < > + PINCTRL_DRV_STRENGTH(0xb, 0xf) > + >; > + }; > + > + emmc_pins_2: emmc-pins-2 { > + pinctrl-single,pins = < > + 0x028 MUX_M2 > + >; > + pinctrl-single,bias-pulldown = < > + PINCTRL_PULLDOWN(0, 1, 0, 1) > + >; > + pinctrl-single,bias-pullup = < > + PINCTRL_PULLUP(0, 1, 0, 1) > + >; > + pinctrl-single,slew-rate = < > + PINCTRL_SLEW_RATE(1, 1) > + >; > + pinctrl-single,drive-strength = < > + PINCTRL_DRV_STRENGTH(0x9, 0xf) > + >; > + }; > + > + emmc_pins_3: emmc-pins-3 { > + pinctrl-single,pins = < > + 0x02c MUX_M2 > + >; > + pinctrl-single,bias-pulldown = < > + PINCTRL_PULLDOWN(0, 1, 0, 1) > + >; > + pinctrl-single,bias-pullup = < > + PINCTRL_PULLUP(0, 1, 0, 1) > + >; > + pinctrl-single,slew-rate = < > + PINCTRL_SLEW_RATE(1, 1) > + >; > + pinctrl-single,drive-strength = < > + PINCTRL_DRV_STRENGTH(3, 3) > + >; > + }; > + > + emmc_pins_4: emmc-pins-4 { > + pinctrl-single,pins = < > + 0x030 MUX_M2 > + >; > + pinctrl-single,bias-pulldown = < > + PINCTRL_PULLDOWN(1, 1, 0, 1) > + >; > + pinctrl-single,bias-pullup = < > + PINCTRL_PULLUP(0, 1, 0, 1) > + >; > + pinctrl-single,slew-rate = < > + PINCTRL_SLEW_RATE(1, 1) > + >; > + pinctrl-single,drive-strength = < > + PINCTRL_DRV_STRENGTH(3, 3) > + >; > + }; > +}; > diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h > index 181c0f070f7c..136de24733be 100644 > --- a/include/dt-bindings/clock/histb-clock.h > +++ b/include/dt-bindings/clock/histb-clock.h > @@ -22,18 +22,18 @@ > #define HISTB_OSC_CLK 0 > #define HISTB_APB_CLK 1 > #define HISTB_AHB_CLK 2 > -#define HISTB_UART1_CLK 3 > -#define HISTB_UART2_CLK 4 > -#define HISTB_UART3_CLK 5 > -#define HISTB_I2C0_CLK 6 > -#define HISTB_I2C1_CLK 7 > -#define HISTB_I2C2_CLK 8 > -#define HISTB_I2C3_CLK 9 > -#define HISTB_I2C4_CLK 10 > -#define HISTB_I2C5_CLK 11 > -#define HISTB_SPI0_CLK 12 > -#define HISTB_SPI1_CLK 13 > -#define HISTB_SPI2_CLK 14 > +#define HISTB_UART1_CLK 3 > +#define HISTB_UART2_CLK 4 > +#define HISTB_UART3_CLK 5 > +#define HISTB_I2C0_CLK 6 > +#define HISTB_I2C1_CLK 7 > +#define HISTB_I2C2_CLK 8 > +#define HISTB_I2C3_CLK 9 > +#define HISTB_I2C4_CLK 10 > +#define HISTB_I2C5_CLK 11 > +#define HISTB_SPI0_CLK 12 > +#define HISTB_SPI1_CLK 13 > +#define HISTB_SPI2_CLK 14 > #define HISTB_SCI_CLK 15 > #define HISTB_FMC_CLK 16 > #define HISTB_MMC_BIU_CLK 17 > @@ -43,7 +43,7 @@ > #define HISTB_SDIO0_BIU_CLK 21 > #define HISTB_SDIO0_CIU_CLK 22 > #define HISTB_SDIO0_DRV_CLK 23 > -#define HISTB_SDIO0_SAMPLE_CLK 24 > +#define HISTB_SDIO0_SAMPLE_CLK 24 > #define HISTB_PCIE_AUX_CLK 25 > #define HISTB_PCIE_PIPE_CLK 26 > #define HISTB_PCIE_SYS_CLK 27 > @@ -53,14 +53,30 @@ > #define HISTB_ETH1_MAC_CLK 31 > #define HISTB_ETH1_MACIF_CLK 32 > #define HISTB_COMBPHY1_CLK 33 > - > +#define HISTB_USB2_BUS_CLK 34 > +#define HISTB_USB2_PHY_CLK 35 > +#define HISTB_USB2_UTMI_CLK 36 > +#define HISTB_USB2_12M_CLK 37 > +#define HISTB_USB2_48M_CLK 38 > +#define HISTB_USB2_OTG_UTMI_CLK 39 > +#define HISTB_USB2_PHY1_REF_CLK 40 > +#define HISTB_USB2_PHY2_REF_CLK 41 > +#define HISTB_COMBPHY0_CLK 42 > +#define HISTB_USB3_BUS_CLK 43 > +#define HISTB_USB3_UTMI_CLK 44 > +#define HISTB_USB3_PIPE_CLK 45 > +#define HISTB_USB3_SUSPEND_CLK 46 > +#define HISTB_USB3_BUS_CLK1 47 > +#define HISTB_USB3_UTMI_CLK1 48 > +#define HISTB_USB3_PIPE_CLK1 49 > +#define HISTB_USB3_SUSPEND_CLK1 50 > > /* clocks provided by mcu CRG */ > -#define HISTB_MCE_CLK 1 > -#define HISTB_IR_CLK 2 > -#define HISTB_TIMER01_CLK 3 > -#define HISTB_LEDC_CLK 4 > -#define HISTB_UART0_CLK 5 > -#define HISTB_LSADC_CLK 6 > +#define HISTB_MCE_CLK 1 > +#define HISTB_IR_CLK 2 > +#define HISTB_TIMER01_CLK 3 > +#define HISTB_LEDC_CLK 4 > +#define HISTB_UART0_CLK 5 > +#define HISTB_LSADC_CLK 6 > > #endif /* __DTS_HISTB_CLOCK_H */ > diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h > new file mode 100644 > index 000000000000..0359bfdc9119 > --- /dev/null > +++ b/include/dt-bindings/pinctrl/hisi.h > @@ -0,0 +1,74 @@ > +/* > + * This header provides constants for hisilicon pinctrl bindings. > + * > + * Copyright (c) 2015 Hisilicon Limited. > + * Copyright (c) 2015 Linaro Limited. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any > + * kind, whether express or implied; without even the implied warranty > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. New SPDX license identifier? Thanks, Mani > + */ > + > +#ifndef _DT_BINDINGS_PINCTRL_HISI_H > +#define _DT_BINDINGS_PINCTRL_HISI_H > + > +/* iomg bit definition */ > +#define MUX_M0 0 > +#define MUX_M1 1 > +#define MUX_M2 2 > +#define MUX_M3 3 > +#define MUX_M4 4 > +#define MUX_M5 5 > +#define MUX_M6 6 > +#define MUX_M7 7 > + > +/* iocg bit definition */ > +#define PULL_MASK (3) > +#define PULL_DIS (0) > +#define PULL_UP (1 << 0) > +#define PULL_DOWN (1 << 1) > + > +/* drive strength definition */ > +#define DRIVE_MASK (7 << 4) > +#define DRIVE1_02MA (0 << 4) > +#define DRIVE1_04MA (1 << 4) > +#define DRIVE1_08MA (2 << 4) > +#define DRIVE1_10MA (3 << 4) > +#define DRIVE2_02MA (0 << 4) > +#define DRIVE2_04MA (1 << 4) > +#define DRIVE2_08MA (2 << 4) > +#define DRIVE2_10MA (3 << 4) > +#define DRIVE3_04MA (0 << 4) > +#define DRIVE3_08MA (1 << 4) > +#define DRIVE3_12MA (2 << 4) > +#define DRIVE3_16MA (3 << 4) > +#define DRIVE3_20MA (4 << 4) > +#define DRIVE3_24MA (5 << 4) > +#define DRIVE3_32MA (6 << 4) > +#define DRIVE3_40MA (7 << 4) > +#define DRIVE4_02MA (0 << 4) > +#define DRIVE4_04MA (2 << 4) > +#define DRIVE4_08MA (4 << 4) > +#define DRIVE4_10MA (6 << 4) > + > +/* drive strength definition for hi3660 */ > +#define DRIVE6_MASK (15 << 4) > +#define DRIVE6_04MA (0 << 4) > +#define DRIVE6_12MA (4 << 4) > +#define DRIVE6_19MA (8 << 4) > +#define DRIVE6_27MA (10 << 4) > +#define DRIVE6_32MA (15 << 4) > +#define DRIVE7_02MA (0 << 4) > +#define DRIVE7_04MA (1 << 4) > +#define DRIVE7_06MA (2 << 4) > +#define DRIVE7_08MA (3 << 4) > +#define DRIVE7_10MA (4 << 4) > +#define DRIVE7_12MA (5 << 4) > +#define DRIVE7_14MA (6 << 4) > +#define DRIVE7_16MA (7 << 4) > +#endif > -- > 2.18.0 >