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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 17/49] target/arm: Decode PAuth within disas_uncond_b_reg
Date: Fri, 18 Jan 2019 14:57:33 +0000	[thread overview]
Message-ID: <20190118145805.6852-18-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190108223129.5570-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 81 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e6017530326..fa50003f0b0 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1982,6 +1982,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
 {
     unsigned int opc, op2, op3, rn, op4;
     TCGv_i64 dst;
+    TCGv_i64 modifier;
 
     opc = extract32(insn, 21, 4);
     op2 = extract32(insn, 16, 5);
@@ -1999,12 +2000,44 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
     case 2: /* RET */
         switch (op3) {
         case 0:
+            /* BR, BLR, RET */
             if (op4 != 0) {
                 goto do_unallocated;
             }
             dst = cpu_reg(s, rn);
             break;
 
+        case 2:
+        case 3:
+            if (!dc_isar_feature(aa64_pauth, s)) {
+                goto do_unallocated;
+            }
+            if (opc == 2) {
+                /* RETAA, RETAB */
+                if (rn != 0x1f || op4 != 0x1f) {
+                    goto do_unallocated;
+                }
+                rn = 30;
+                modifier = cpu_X[31];
+            } else {
+                /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
+                if (op4 != 0x1f) {
+                    goto do_unallocated;
+                }
+                modifier = new_tmp_a64_zero(s);
+            }
+            if (s->pauth_active) {
+                dst = new_tmp_a64(s);
+                if (op3 == 2) {
+                    gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
+                } else {
+                    gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier);
+                }
+            } else {
+                dst = cpu_reg(s, rn);
+            }
+            break;
+
         default:
             goto do_unallocated;
         }
@@ -2016,12 +2049,38 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
         }
         break;
 
+    case 8: /* BRAA */
+    case 9: /* BLRAA */
+        if (!dc_isar_feature(aa64_pauth, s)) {
+            goto do_unallocated;
+        }
+        if (op3 != 2 || op3 != 3) {
+            goto do_unallocated;
+        }
+        if (s->pauth_active) {
+            dst = new_tmp_a64(s);
+            modifier = cpu_reg_sp(s, op4);
+            if (op3 == 2) {
+                gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
+            } else {
+                gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier);
+            }
+        } else {
+            dst = cpu_reg(s, rn);
+        }
+        gen_a64_set_pc(s, dst);
+        /* BLRAA also needs to load return address */
+        if (opc == 9) {
+            tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
+        }
+        break;
+
     case 4: /* ERET */
         if (s->current_el == 0) {
             goto do_unallocated;
         }
         switch (op3) {
-        case 0:
+        case 0: /* ERET */
             if (op4 != 0) {
                 goto do_unallocated;
             }
@@ -2030,6 +2089,27 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
                            offsetof(CPUARMState, elr_el[s->current_el]));
             break;
 
+        case 2: /* ERETAA */
+        case 3: /* ERETAB */
+            if (!dc_isar_feature(aa64_pauth, s)) {
+                goto do_unallocated;
+            }
+            if (rn != 0x1f || op4 != 0x1f) {
+                goto do_unallocated;
+            }
+            dst = tcg_temp_new_i64();
+            tcg_gen_ld_i64(dst, cpu_env,
+                           offsetof(CPUARMState, elr_el[s->current_el]));
+            if (s->pauth_active) {
+                modifier = cpu_X[31];
+                if (op3 == 2) {
+                    gen_helper_autia(dst, cpu_env, dst, modifier);
+                } else {
+                    gen_helper_autib(dst, cpu_env, dst, modifier);
+                }
+            }
+            break;
+
         default:
             goto do_unallocated;
         }
-- 
2.20.1

  parent reply	other threads:[~2019-01-18 14:58 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-18 14:57 [Qemu-devel] [PULL 00/49] target-arm queue Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 01/49] hw/char/stm32f2xx_usart: Do not update data register when device is disabled Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 02/49] hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 03/49] target/arm: Allow Aarch32 exception return to switch from Mon->Hyp Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 04/49] ftgmac100: implement the new MDIO interface on Aspeed SoC Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 05/49] target/arm: Add state for the ARMv8.3-PAuth extension Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 06/49] target/arm: Add SCTLR bits through ARMv8.5 Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 07/49] target/arm: Add PAuth active bit to tbflags Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 08/49] target/arm: Introduce raise_exception_ra Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 09/49] target/arm: Add PAuth helpers Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 10/49] target/arm: Decode PAuth within system hint space Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 11/49] target/arm: Rearrange decode in disas_data_proc_1src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 12/49] target/arm: Decode PAuth within disas_data_proc_1src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 13/49] target/arm: Decode PAuth within disas_data_proc_2src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 14/49] target/arm: Move helper_exception_return to helper-a64.c Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 15/49] target/arm: Add new_pc argument to helper_exception_return Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 16/49] target/arm: Rearrange decode in disas_uncond_b_reg Peter Maydell
2019-01-18 14:57 ` Peter Maydell [this message]
2019-01-18 14:57 ` [Qemu-devel] [PULL 18/49] target/arm: Decode Load/store register (pac) Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 19/49] target/arm: Move cpu_mmu_index out of line Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 20/49] target/arm: Introduce arm_mmu_idx Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 21/49] target/arm: Introduce arm_stage1_mmu_idx Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 22/49] target/arm: Create ARMVAParameters and helpers Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 23/49] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 24/49] target/arm: Export aa64_va_parameters to internals.h Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 25/49] target/arm: Add aa64_va_parameters_both Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 26/49] target/arm: Decode TBID from TCR Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 27/49] target/arm: Reuse aa64_va_parameters for setting tbflags Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 28/49] target/arm: Implement pauth_strip Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 29/49] target/arm: Implement pauth_auth Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 30/49] target/arm: Implement pauth_addpac Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 31/49] target/arm: Implement pauth_computepac Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 32/49] target/arm: Add PAuth system registers Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 33/49] target/arm: Enable PAuth for -cpu max Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 34/49] target/arm: Enable PAuth for user-only Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 35/49] target/arm: Tidy TBI handling in gen_a64_set_pc Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 36/49] migration: Add post_save function to VMStateDescription Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 37/49] target/arm: Reorganize PMCCNTR accesses Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 38/49] target/arm: Swap PMU values before/after migrations Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 39/49] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Peter Maydell
2020-08-24 16:33   ` Peter Maydell
2020-08-25 14:41     ` Aaron Lindsay
2020-08-25 14:48     ` [PATCH] target/arm: Count PMU events when MDCR.SPME is set Aaron Lindsay
2020-09-11 14:13       ` Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 40/49] target/arm: Allow AArch32 access for PMCCFILTR Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 41/49] target/arm: Implement PMOVSSET Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 42/49] target/arm: Define FIELDs for ID_DFR0 Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 43/49] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 44/49] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 45/49] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 46/49] target/arm: PMU: Add instruction and cycle events Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 47/49] target/arm: PMU: Set PMCR.N to 4 Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 48/49] target/arm: Implement PMSWINC Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 49/49] tests/libqtest: Introduce qtest_init_with_serial() Peter Maydell
2019-01-31 17:48 ` [Qemu-devel] [PULL 00/49] target-arm queue no-reply

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