* [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Hi,
this patchset converts the RISC-V decoder to decodetree in four major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-16]:
Many of the gen_* functions are called by the decode functions for 16-bit
and 32-bit functions. If we move translation code from the gen_*
functions to the generated trans_* functions of decode-tree, we get a lot of
duplication. Therefore, we mostly generate calls to the old gen_* function
which are properly replaced after step 2).
Each of the trans_ functions are grouped into files corresponding to their
ISA extension, e.g. addi which is in RV32I is translated in the file
'trans_rvi.inc.c'.
2) Convert 16-bit instructions to decodetree [Patch 17-19]:
All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
we convert the arguments in the 16 bit trans_ function to the arguments of
the corresponding 32 bit instruction and call the 32 bit trans_ function.
3) Remove old manual decoding in gen_* function [Patch 20-30]:
this move all manual translation code into the trans_* instructions of
decode tree, such that we can remove the old decode_* functions.
4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
by Richard. [Patch 31-35]
full tree available at
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
Cheers,
Bastian
v4 -> v5:
- fixed rebase error
- moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
- removed extra sign extension of sraiw
- removed rs2 == 0 special cases in sraw/srlw
Bastian Koppelmann (35):
target/riscv: Move CPURISCVState pointer to DisasContext
target/riscv: Activate decodetree and implemnt LUI & AUIPC
target/riscv: Convert RVXI branch insns to decodetree
target/riscv: Convert RV32I load/store insns to decodetree
target/riscv: Convert RV64I load/store insns to decodetree
target/riscv: Convert RVXI arithmetic insns to decodetree
target/riscv: Convert RVXI fence insns to decodetree
target/riscv: Convert RVXI csr insns to decodetree
target/riscv: Convert RVXM insns to decodetree
target/riscv: Convert RV32A insns to decodetree
target/riscv: Convert RV64A insns to decodetree
target/riscv: Convert RV32F insns to decodetree
target/riscv: Convert RV64F insns to decodetree
target/riscv: Convert RV32D insns to decodetree
target/riscv: Convert RV64D insns to decodetree
target/riscv: Convert RV priv insns to decodetree
target/riscv: Convert quadrant 0 of RVXC insns to decodetree
target/riscv: Convert quadrant 1 of RVXC insns to decodetree
target/riscv: Convert quadrant 2 of RVXC insns to decodetree
target/riscv: Remove gen_jalr()
target/riscv: Remove manual decoding from gen_branch()
target/riscv: Remove manual decoding from gen_load()
target/riscv: Remove manual decoding from gen_store()
target/riscv: Move gen_arith_imm() decoding into trans_* functions
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
target/riscv: Remove shift and slt insn manual decoding
target/riscv: Remove manual decoding of RV32/64M insn
target/riscv: Rename trans_arith to gen_arith
target/riscv: Remove gen_system()
target/riscv: Remove decode_RV32_64G()
target/riscv: Convert @cs_2 insns to share translation functions
target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
target/riscv: Splice remaining compressed insn pairs for riscv32 vs
riscv64
target/riscv: Remaining rvc insn reuse 32 bit translators
target/riscv/Makefile.objs | 22 +
target/riscv/insn16-32.decode | 31 +
target/riscv/insn16-64.decode | 33 +
target/riscv/insn16.decode | 114 ++
target/riscv/insn32-64.decode | 72 +
target/riscv/insn32.decode | 203 ++
.../riscv/insn_trans/trans_privileged.inc.c | 110 +
target/riscv/insn_trans/trans_rva.inc.c | 207 ++
target/riscv/insn_trans/trans_rvc.inc.c | 149 ++
target/riscv/insn_trans/trans_rvd.inc.c | 388 ++++
target/riscv/insn_trans/trans_rvf.inc.c | 388 ++++
target/riscv/insn_trans/trans_rvi.inc.c | 568 ++++++
target/riscv/insn_trans/trans_rvm.inc.c | 107 +
target/riscv/translate.c | 1781 ++---------------
14 files changed, 2611 insertions(+), 1562 deletions(-)
create mode 100644 target/riscv/insn16-32.decode
create mode 100644 target/riscv/insn16-64.decode
create mode 100644 target/riscv/insn16.decode
create mode 100644 target/riscv/insn32-64.decode
create mode 100644 target/riscv/insn32.decode
create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c
--
2.20.1
^ permalink raw reply [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Hi,
this patchset converts the RISC-V decoder to decodetree in four major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-16]:
Many of the gen_* functions are called by the decode functions for 16-bit
and 32-bit functions. If we move translation code from the gen_*
functions to the generated trans_* functions of decode-tree, we get a lot of
duplication. Therefore, we mostly generate calls to the old gen_* function
which are properly replaced after step 2).
Each of the trans_ functions are grouped into files corresponding to their
ISA extension, e.g. addi which is in RV32I is translated in the file
'trans_rvi.inc.c'.
2) Convert 16-bit instructions to decodetree [Patch 17-19]:
All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
we convert the arguments in the 16 bit trans_ function to the arguments of
the corresponding 32 bit instruction and call the 32 bit trans_ function.
3) Remove old manual decoding in gen_* function [Patch 20-30]:
this move all manual translation code into the trans_* instructions of
decode tree, such that we can remove the old decode_* functions.
4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
by Richard. [Patch 31-35]
full tree available at
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
Cheers,
Bastian
v4 -> v5:
- fixed rebase error
- moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
- removed extra sign extension of sraiw
- removed rs2 == 0 special cases in sraw/srlw
Bastian Koppelmann (35):
target/riscv: Move CPURISCVState pointer to DisasContext
target/riscv: Activate decodetree and implemnt LUI & AUIPC
target/riscv: Convert RVXI branch insns to decodetree
target/riscv: Convert RV32I load/store insns to decodetree
target/riscv: Convert RV64I load/store insns to decodetree
target/riscv: Convert RVXI arithmetic insns to decodetree
target/riscv: Convert RVXI fence insns to decodetree
target/riscv: Convert RVXI csr insns to decodetree
target/riscv: Convert RVXM insns to decodetree
target/riscv: Convert RV32A insns to decodetree
target/riscv: Convert RV64A insns to decodetree
target/riscv: Convert RV32F insns to decodetree
target/riscv: Convert RV64F insns to decodetree
target/riscv: Convert RV32D insns to decodetree
target/riscv: Convert RV64D insns to decodetree
target/riscv: Convert RV priv insns to decodetree
target/riscv: Convert quadrant 0 of RVXC insns to decodetree
target/riscv: Convert quadrant 1 of RVXC insns to decodetree
target/riscv: Convert quadrant 2 of RVXC insns to decodetree
target/riscv: Remove gen_jalr()
target/riscv: Remove manual decoding from gen_branch()
target/riscv: Remove manual decoding from gen_load()
target/riscv: Remove manual decoding from gen_store()
target/riscv: Move gen_arith_imm() decoding into trans_* functions
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
target/riscv: Remove shift and slt insn manual decoding
target/riscv: Remove manual decoding of RV32/64M insn
target/riscv: Rename trans_arith to gen_arith
target/riscv: Remove gen_system()
target/riscv: Remove decode_RV32_64G()
target/riscv: Convert @cs_2 insns to share translation functions
target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
target/riscv: Splice remaining compressed insn pairs for riscv32 vs
riscv64
target/riscv: Remaining rvc insn reuse 32 bit translators
target/riscv/Makefile.objs | 22 +
target/riscv/insn16-32.decode | 31 +
target/riscv/insn16-64.decode | 33 +
target/riscv/insn16.decode | 114 ++
target/riscv/insn32-64.decode | 72 +
target/riscv/insn32.decode | 203 ++
.../riscv/insn_trans/trans_privileged.inc.c | 110 +
target/riscv/insn_trans/trans_rva.inc.c | 207 ++
target/riscv/insn_trans/trans_rvc.inc.c | 149 ++
target/riscv/insn_trans/trans_rvd.inc.c | 388 ++++
target/riscv/insn_trans/trans_rvf.inc.c | 388 ++++
target/riscv/insn_trans/trans_rvi.inc.c | 568 ++++++
target/riscv/insn_trans/trans_rvm.inc.c | 107 +
target/riscv/translate.c | 1781 ++---------------
14 files changed, 2611 insertions(+), 1562 deletions(-)
create mode 100644 target/riscv/insn16-32.decode
create mode 100644 target/riscv/insn16-64.decode
create mode 100644 target/riscv/insn16.decode
create mode 100644 target/riscv/insn32-64.decode
create mode 100644 target/riscv/insn32.decode
create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c
--
2.20.1
^ permalink raw reply [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
CPURISCVState is rarely used, so there is no need to pass it to every
translate function. This paves the way for decodetree which only passes
DisasContext to translate functions.
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/translate.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 312bf298b3..c4a4d8115c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -52,6 +52,7 @@ typedef struct DisasContext {
to any system register, which includes CSR_FRM, so we do not have
to reset this known value. */
int frm;
+ CPURISCVState *env;
} DisasContext;
/* convert riscv funct3 to qemu memop for load/store */
@@ -1797,19 +1798,19 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
}
}
-static void decode_opc(CPURISCVState *env, DisasContext *ctx)
+static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
if (extract32(ctx->opcode, 0, 2) != 3) {
- if (!riscv_has_ext(env, RVC)) {
+ if (!riscv_has_ext(ctx->env, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- decode_RV32_64C(env, ctx);
+ decode_RV32_64C(ctx->env, ctx);
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- decode_RV32_64G(env, ctx);
+ decode_RV32_64G(ctx->env, ctx);
}
}
@@ -1854,10 +1855,10 @@ static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cpu->env_ptr;
+ ctx->env = cpu->env_ptr;
- ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
- decode_opc(env, ctx);
+ ctx->opcode = cpu_ldl_code(ctx->env, ctx->base.pc_next);
+ decode_opc(ctx);
ctx->base.pc_next = ctx->pc_succ_insn;
if (ctx->base.is_jmp == DISAS_NEXT) {
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
CPURISCVState is rarely used, so there is no need to pass it to every
translate function. This paves the way for decodetree which only passes
DisasContext to translate functions.
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/translate.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 312bf298b3..c4a4d8115c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -52,6 +52,7 @@ typedef struct DisasContext {
to any system register, which includes CSR_FRM, so we do not have
to reset this known value. */
int frm;
+ CPURISCVState *env;
} DisasContext;
/* convert riscv funct3 to qemu memop for load/store */
@@ -1797,19 +1798,19 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
}
}
-static void decode_opc(CPURISCVState *env, DisasContext *ctx)
+static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
if (extract32(ctx->opcode, 0, 2) != 3) {
- if (!riscv_has_ext(env, RVC)) {
+ if (!riscv_has_ext(ctx->env, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- decode_RV32_64C(env, ctx);
+ decode_RV32_64C(ctx->env, ctx);
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- decode_RV32_64G(env, ctx);
+ decode_RV32_64G(ctx->env, ctx);
}
}
@@ -1854,10 +1855,10 @@ static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cpu->env_ptr;
+ ctx->env = cpu->env_ptr;
- ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
- decode_opc(env, ctx);
+ ctx->opcode = cpu_ldl_code(ctx->env, ctx->base.pc_next);
+ decode_opc(ctx);
ctx->base.pc_next = ctx->pc_succ_insn;
if (ctx->base.is_jmp == DISAS_NEXT) {
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/Makefile.objs | 10 +++++++
target/riscv/insn32.decode | 30 +++++++++++++++++++++
target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++++++++++++
target/riscv/translate.c | 31 ++++++++++++----------
4 files changed, 92 insertions(+), 14 deletions(-)
create mode 100644 target/riscv/insn32.decode
create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 4072abe3e4..bf0a268033 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1 +1,11 @@
obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o
+
+DECODETREE = $(SRC_PATH)/scripts/decodetree.py
+
+target/riscv/decode_insn32.inc.c: \
+ $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE)
+ $(call quiet-command, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \
+ "GEN", $(TARGET_DIR)$@)
+
+target/riscv/translate.o: target/riscv/decode_insn32.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
new file mode 100644
index 0000000000..44d4e922b6
--- /dev/null
+++ b/target/riscv/insn32.decode
@@ -0,0 +1,30 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Fields:
+%rd 7:5
+
+# immediates:
+%imm_u 12:s20 !function=ex_shift_12
+
+# Formats 32:
+@u .................... ..... ....... imm=%imm_u %rd
+
+# *** RV32I Base Instruction Set ***
+lui .................... ..... 0110111 @u
+auipc .................... ..... 0010111 @u
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
new file mode 100644
index 0000000000..9885a8d275
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -0,0 +1,35 @@
+/*
+ * RISC-V translation routines for the RVXI Base Integer Instruction Set.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_lui(DisasContext *ctx, arg_lui *a)
+{
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
+ }
+ return true;
+}
+
+static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
+{
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
+ }
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c4a4d8115c..99829a600d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1677,6 +1677,19 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
}
}
+#define EX_SH(amount) \
+ static int ex_shift_##amount(int imm) \
+ { \
+ return imm << amount; \
+ }
+EX_SH(12)
+
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
+/* Include the auto-generated decoder for 32 bit insn */
+#include "decode_insn32.inc.c"
+/* Include insn module translation function */
+#include "insn_trans/trans_rvi.inc.c"
+
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
int rs1;
@@ -1697,19 +1710,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_LUI:
- if (rd == 0) {
- break; /* NOP */
- }
- tcg_gen_movi_tl(cpu_gpr[rd], sextract64(ctx->opcode, 12, 20) << 12);
- break;
- case OPC_RISC_AUIPC:
- if (rd == 0) {
- break; /* NOP */
- }
- tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 12) +
- ctx->base.pc_next);
- break;
case OPC_RISC_JAL:
imm = GET_JAL_IMM(ctx->opcode);
gen_jal(env, ctx, rd, imm);
@@ -1810,7 +1810,10 @@ static void decode_opc(DisasContext *ctx)
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- decode_RV32_64G(ctx->env, ctx);
+ if (!decode_insn32(ctx, ctx->opcode)) {
+ /* fallback to old decoder */
+ decode_RV32_64G(ctx->env, ctx);
+ }
}
}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/Makefile.objs | 10 +++++++
target/riscv/insn32.decode | 30 +++++++++++++++++++++
target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++++++++++++
target/riscv/translate.c | 31 ++++++++++++----------
4 files changed, 92 insertions(+), 14 deletions(-)
create mode 100644 target/riscv/insn32.decode
create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 4072abe3e4..bf0a268033 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1 +1,11 @@
obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o
+
+DECODETREE = $(SRC_PATH)/scripts/decodetree.py
+
+target/riscv/decode_insn32.inc.c: \
+ $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE)
+ $(call quiet-command, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \
+ "GEN", $(TARGET_DIR)$@)
+
+target/riscv/translate.o: target/riscv/decode_insn32.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
new file mode 100644
index 0000000000..44d4e922b6
--- /dev/null
+++ b/target/riscv/insn32.decode
@@ -0,0 +1,30 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Fields:
+%rd 7:5
+
+# immediates:
+%imm_u 12:s20 !function=ex_shift_12
+
+# Formats 32:
+@u .................... ..... ....... imm=%imm_u %rd
+
+# *** RV32I Base Instruction Set ***
+lui .................... ..... 0110111 @u
+auipc .................... ..... 0010111 @u
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
new file mode 100644
index 0000000000..9885a8d275
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -0,0 +1,35 @@
+/*
+ * RISC-V translation routines for the RVXI Base Integer Instruction Set.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_lui(DisasContext *ctx, arg_lui *a)
+{
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
+ }
+ return true;
+}
+
+static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
+{
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
+ }
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c4a4d8115c..99829a600d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1677,6 +1677,19 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
}
}
+#define EX_SH(amount) \
+ static int ex_shift_##amount(int imm) \
+ { \
+ return imm << amount; \
+ }
+EX_SH(12)
+
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
+/* Include the auto-generated decoder for 32 bit insn */
+#include "decode_insn32.inc.c"
+/* Include insn module translation function */
+#include "insn_trans/trans_rvi.inc.c"
+
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
int rs1;
@@ -1697,19 +1710,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_LUI:
- if (rd == 0) {
- break; /* NOP */
- }
- tcg_gen_movi_tl(cpu_gpr[rd], sextract64(ctx->opcode, 12, 20) << 12);
- break;
- case OPC_RISC_AUIPC:
- if (rd == 0) {
- break; /* NOP */
- }
- tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 12) +
- ctx->base.pc_next);
- break;
case OPC_RISC_JAL:
imm = GET_JAL_IMM(ctx->opcode);
gen_jal(env, ctx, rd, imm);
@@ -1810,7 +1810,10 @@ static void decode_opc(DisasContext *ctx)
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- decode_RV32_64G(ctx->env, ctx);
+ if (!decode_insn32(ctx, ctx->opcode)) {
+ /* fallback to old decoder */
+ decode_RV32_64G(ctx->env, ctx);
+ }
}
}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 19 ++++++++++
target/riscv/insn_trans/trans_rvi.inc.c | 49 +++++++++++++++++++++++++
target/riscv/translate.c | 12 +-----
3 files changed, 69 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 44d4e922b6..81f56c16b4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -17,14 +17,33 @@
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
+%rs2 20:5
+%rs1 15:5
%rd 7:5
# immediates:
+%imm_i 20:s12
+%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
+%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
%imm_u 12:s20 !function=ex_shift_12
+# Argument sets:
+&b imm rs2 rs1
+
# Formats 32:
+@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
+@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
+@j .................... ..... ....... imm=%imm_j %rd
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
+jal .................... ..... 1101111 @j
+jalr ............ ..... 000 ..... 1100111 @i
+beq ....... ..... ..... 000 ..... 1100011 @b
+bne ....... ..... ..... 001 ..... 1100011 @b
+blt ....... ..... ..... 100 ..... 1100011 @b
+bge ....... ..... ..... 101 ..... 1100011 @b
+bltu ....... ..... ..... 110 ..... 1100011 @b
+bgeu ....... ..... ..... 111 ..... 1100011 @b
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 9885a8d275..0347461ee6 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -33,3 +33,52 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
}
return true;
}
+
+static bool trans_jal(DisasContext *ctx, arg_jal *a)
+{
+ gen_jal(ctx->env, ctx, a->rd, a->imm);
+ return true;
+}
+
+static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
+{
+ gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bne(DisasContext *ctx, arg_bne *a)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_blt(DisasContext *ctx, arg_blt *a)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bge(DisasContext *ctx, arg_bge *a)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
+{
+
+ gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 99829a600d..b81297f23e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1682,6 +1682,7 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
{ \
return imm << amount; \
}
+EX_SH(1)
EX_SH(12)
bool decode_insn32(DisasContext *ctx, uint32_t insn);
@@ -1710,17 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_JAL:
- imm = GET_JAL_IMM(ctx->opcode);
- gen_jal(env, ctx, rd, imm);
- break;
- case OPC_RISC_JALR:
- gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_BRANCH:
- gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
- GET_B_IMM(ctx->opcode));
- break;
case OPC_RISC_LOAD:
gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 19 ++++++++++
target/riscv/insn_trans/trans_rvi.inc.c | 49 +++++++++++++++++++++++++
target/riscv/translate.c | 12 +-----
3 files changed, 69 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 44d4e922b6..81f56c16b4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -17,14 +17,33 @@
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
+%rs2 20:5
+%rs1 15:5
%rd 7:5
# immediates:
+%imm_i 20:s12
+%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
+%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
%imm_u 12:s20 !function=ex_shift_12
+# Argument sets:
+&b imm rs2 rs1
+
# Formats 32:
+@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
+@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
+@j .................... ..... ....... imm=%imm_j %rd
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
+jal .................... ..... 1101111 @j
+jalr ............ ..... 000 ..... 1100111 @i
+beq ....... ..... ..... 000 ..... 1100011 @b
+bne ....... ..... ..... 001 ..... 1100011 @b
+blt ....... ..... ..... 100 ..... 1100011 @b
+bge ....... ..... ..... 101 ..... 1100011 @b
+bltu ....... ..... ..... 110 ..... 1100011 @b
+bgeu ....... ..... ..... 111 ..... 1100011 @b
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 9885a8d275..0347461ee6 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -33,3 +33,52 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
}
return true;
}
+
+static bool trans_jal(DisasContext *ctx, arg_jal *a)
+{
+ gen_jal(ctx->env, ctx, a->rd, a->imm);
+ return true;
+}
+
+static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
+{
+ gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bne(DisasContext *ctx, arg_bne *a)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_blt(DisasContext *ctx, arg_blt *a)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bge(DisasContext *ctx, arg_bge *a)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
+{
+ gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
+{
+
+ gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 99829a600d..b81297f23e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1682,6 +1682,7 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
{ \
return imm << amount; \
}
+EX_SH(1)
EX_SH(12)
bool decode_insn32(DisasContext *ctx, uint32_t insn);
@@ -1710,17 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_JAL:
- imm = GET_JAL_IMM(ctx->opcode);
- gen_jal(env, ctx, rd, imm);
- break;
- case OPC_RISC_JALR:
- gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_BRANCH:
- gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
- GET_B_IMM(ctx->opcode));
- break;
case OPC_RISC_LOAD:
gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 10 ++++++
target/riscv/insn_trans/trans_rvi.inc.c | 48 +++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 81f56c16b4..076de873c4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -23,6 +23,7 @@
# immediates:
%imm_i 20:s12
+%imm_s 25:s7 7:5
%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
%imm_u 12:s20 !function=ex_shift_12
@@ -33,6 +34,7 @@
# Formats 32:
@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
+@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
@j .................... ..... ....... imm=%imm_j %rd
@@ -47,3 +49,11 @@ blt ....... ..... ..... 100 ..... 1100011 @b
bge ....... ..... ..... 101 ..... 1100011 @b
bltu ....... ..... ..... 110 ..... 1100011 @b
bgeu ....... ..... ..... 111 ..... 1100011 @b
+lb ............ ..... 000 ..... 0000011 @i
+lh ............ ..... 001 ..... 0000011 @i
+lw ............ ..... 010 ..... 0000011 @i
+lbu ............ ..... 100 ..... 0000011 @i
+lhu ............ ..... 101 ..... 0000011 @i
+sb ....... ..... ..... 000 ..... 0100011 @s
+sh ....... ..... ..... 001 ..... 0100011 @s
+sw ....... ..... ..... 010 ..... 0100011 @s
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 0347461ee6..f3b88ebb69 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -82,3 +82,51 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
return true;
}
+
+static bool trans_lb(DisasContext *ctx, arg_lb *a)
+{
+ gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lh(DisasContext *ctx, arg_lh *a)
+{
+ gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lw(DisasContext *ctx, arg_lw *a)
+{
+ gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
+{
+ gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
+{
+ gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a)
+{
+ gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_sh(DisasContext *ctx, arg_sh *a)
+{
+ gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_sw(DisasContext *ctx, arg_sw *a)
+{
+ gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
+ return true;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 04/35] target/riscv: Convert RV32I load/store insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 10 ++++++
target/riscv/insn_trans/trans_rvi.inc.c | 48 +++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 81f56c16b4..076de873c4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -23,6 +23,7 @@
# immediates:
%imm_i 20:s12
+%imm_s 25:s7 7:5
%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
%imm_u 12:s20 !function=ex_shift_12
@@ -33,6 +34,7 @@
# Formats 32:
@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
+@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
@j .................... ..... ....... imm=%imm_j %rd
@@ -47,3 +49,11 @@ blt ....... ..... ..... 100 ..... 1100011 @b
bge ....... ..... ..... 101 ..... 1100011 @b
bltu ....... ..... ..... 110 ..... 1100011 @b
bgeu ....... ..... ..... 111 ..... 1100011 @b
+lb ............ ..... 000 ..... 0000011 @i
+lh ............ ..... 001 ..... 0000011 @i
+lw ............ ..... 010 ..... 0000011 @i
+lbu ............ ..... 100 ..... 0000011 @i
+lhu ............ ..... 101 ..... 0000011 @i
+sb ....... ..... ..... 000 ..... 0100011 @s
+sh ....... ..... ..... 001 ..... 0100011 @s
+sw ....... ..... ..... 010 ..... 0100011 @s
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 0347461ee6..f3b88ebb69 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -82,3 +82,51 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
return true;
}
+
+static bool trans_lb(DisasContext *ctx, arg_lb *a)
+{
+ gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lh(DisasContext *ctx, arg_lh *a)
+{
+ gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lw(DisasContext *ctx, arg_lw *a)
+{
+ gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
+{
+ gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
+{
+ gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a)
+{
+ gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_sh(DisasContext *ctx, arg_sh *a)
+{
+ gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
+ return true;
+}
+
+static bool trans_sw(DisasContext *ctx, arg_sw *a)
+{
+ gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
+ return true;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 05/35] target/riscv: Convert RV64I load/store insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/Makefile.objs | 8 +++++---
target/riscv/insn32-64.decode | 25 +++++++++++++++++++++++++
target/riscv/insn_trans/trans_rvi.inc.c | 20 ++++++++++++++++++++
target/riscv/translate.c | 7 -------
4 files changed, 50 insertions(+), 10 deletions(-)
create mode 100644 target/riscv/insn32-64.decode
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index bf0a268033..05087a91bb 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -2,10 +2,12 @@ obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
-target/riscv/decode_insn32.inc.c: \
- $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE)
+decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
+decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
+
+target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(call quiet-command, \
- $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
"GEN", $(TARGET_DIR)$@)
target/riscv/translate.o: target/riscv/decode_insn32.inc.c
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
new file mode 100644
index 0000000000..439d4e2c58
--- /dev/null
+++ b/target/riscv/insn32-64.decode
@@ -0,0 +1,25 @@
+#
+# RISC-V translation routines for the RV Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This is concatenated with insn32.decode for risc64 targets.
+# Most of the fields and formats are there.
+
+# *** RV64I Base Instruction Set (in addition to RV32I) ***
+lwu ............ ..... 110 ..... 0000011 @i
+ld ............ ..... 011 ..... 0000011 @i
+sd ....... ..... ..... 011 ..... 0100011 @s
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index f3b88ebb69..39a20a70e8 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -130,3 +130,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
return true;
}
+
+#ifdef TARGET_RISCV64
+static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
+{
+ gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+ gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_sd(DisasContext *ctx, arg_sd *a)
+{
+ gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
+ return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b81297f23e..609207f785 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1711,13 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_LOAD:
- gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_STORE:
- gen_store(ctx, MASK_OP_STORE(ctx->opcode), rs1, rs2,
- GET_STORE_IMM(ctx->opcode));
- break;
case OPC_RISC_ARITH_IMM:
#if defined(TARGET_RISCV64)
case OPC_RISC_ARITH_IMM_W:
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 05/35] target/riscv: Convert RV64I load/store insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/Makefile.objs | 8 +++++---
target/riscv/insn32-64.decode | 25 +++++++++++++++++++++++++
target/riscv/insn_trans/trans_rvi.inc.c | 20 ++++++++++++++++++++
target/riscv/translate.c | 7 -------
4 files changed, 50 insertions(+), 10 deletions(-)
create mode 100644 target/riscv/insn32-64.decode
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index bf0a268033..05087a91bb 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -2,10 +2,12 @@ obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
-target/riscv/decode_insn32.inc.c: \
- $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE)
+decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
+decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
+
+target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(call quiet-command, \
- $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
"GEN", $(TARGET_DIR)$@)
target/riscv/translate.o: target/riscv/decode_insn32.inc.c
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
new file mode 100644
index 0000000000..439d4e2c58
--- /dev/null
+++ b/target/riscv/insn32-64.decode
@@ -0,0 +1,25 @@
+#
+# RISC-V translation routines for the RV Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This is concatenated with insn32.decode for risc64 targets.
+# Most of the fields and formats are there.
+
+# *** RV64I Base Instruction Set (in addition to RV32I) ***
+lwu ............ ..... 110 ..... 0000011 @i
+ld ............ ..... 011 ..... 0000011 @i
+sd ....... ..... ..... 011 ..... 0100011 @s
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index f3b88ebb69..39a20a70e8 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -130,3 +130,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
return true;
}
+
+#ifdef TARGET_RISCV64
+static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
+{
+ gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+ gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_sd(DisasContext *ctx, arg_sd *a)
+{
+ gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
+ return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b81297f23e..609207f785 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1711,13 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_LOAD:
- gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_STORE:
- gen_store(ctx, MASK_OP_STORE(ctx->opcode), rs1, rs2,
- GET_STORE_IMM(ctx->opcode));
- break;
case OPC_RISC_ARITH_IMM:
#if defined(TARGET_RISCV64)
case OPC_RISC_ARITH_IMM_W:
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32-64.decode | 13 ++
target/riscv/insn32.decode | 25 ++++
target/riscv/insn_trans/trans_rvi.inc.c | 168 ++++++++++++++++++++++++
target/riscv/translate.c | 9 --
4 files changed, 206 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 439d4e2c58..9a35f2aa19 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -19,7 +19,20 @@
# This is concatenated with insn32.decode for risc64 targets.
# Most of the fields and formats are there.
+%sh5 20:5
+
+@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
+
# *** RV64I Base Instruction Set (in addition to RV32I) ***
lwu ............ ..... 110 ..... 0000011 @i
ld ............ ..... 011 ..... 0000011 @i
sd ....... ..... ..... 011 ..... 0100011 @s
+addiw ............ ..... 000 ..... 0011011 @i
+slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
+srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
+sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
+addw 0000000 ..... ..... 000 ..... 0111011 @r
+subw 0100000 ..... ..... 000 ..... 0111011 @r
+sllw 0000000 ..... ..... 001 ..... 0111011 @r
+srlw 0000000 ..... ..... 101 ..... 0111011 @r
+sraw 0100000 ..... ..... 101 ..... 0111011 @r
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 076de873c4..1f5bf1f6f9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -21,6 +21,8 @@
%rs1 15:5
%rd 7:5
+%sh10 20:10
+
# immediates:
%imm_i 20:s12
%imm_s 25:s7 7:5
@@ -30,14 +32,18 @@
# Argument sets:
&b imm rs2 rs1
+&shift shamt rs1 rd
# Formats 32:
+@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
@j .................... ..... ....... imm=%imm_j %rd
+@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
@@ -57,3 +63,22 @@ lhu ............ ..... 101 ..... 0000011 @i
sb ....... ..... ..... 000 ..... 0100011 @s
sh ....... ..... ..... 001 ..... 0100011 @s
sw ....... ..... ..... 010 ..... 0100011 @s
+addi ............ ..... 000 ..... 0010011 @i
+slti ............ ..... 010 ..... 0010011 @i
+sltiu ............ ..... 011 ..... 0010011 @i
+xori ............ ..... 100 ..... 0010011 @i
+ori ............ ..... 110 ..... 0010011 @i
+andi ............ ..... 111 ..... 0010011 @i
+slli 00.... ...... ..... 001 ..... 0010011 @sh
+srli 00.... ...... ..... 101 ..... 0010011 @sh
+srai 01.... ...... ..... 101 ..... 0010011 @sh
+add 0000000 ..... ..... 000 ..... 0110011 @r
+sub 0100000 ..... ..... 000 ..... 0110011 @r
+sll 0000000 ..... ..... 001 ..... 0110011 @r
+slt 0000000 ..... ..... 010 ..... 0110011 @r
+sltu 0000000 ..... ..... 011 ..... 0110011 @r
+xor 0000000 ..... ..... 100 ..... 0110011 @r
+srl 0000000 ..... ..... 101 ..... 0110011 @r
+sra 0100000 ..... ..... 101 ..... 0110011 @r
+or 0000000 ..... ..... 110 ..... 0110011 @r
+and 0000000 ..... ..... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 39a20a70e8..01f751650a 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -150,3 +150,171 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
return true;
}
#endif
+
+static bool trans_addi(DisasContext *ctx, arg_addi *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_slti(DisasContext *ctx, arg_slti *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_xori(DisasContext *ctx, arg_xori *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
+ return true;
+}
+static bool trans_ori(DisasContext *ctx, arg_ori *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm);
+ return true;
+}
+static bool trans_andi(DisasContext *ctx, arg_andi *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
+ return true;
+}
+static bool trans_slli(DisasContext *ctx, arg_slli *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_srli(DisasContext *ctx, arg_srli *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_srai(DisasContext *ctx, arg_srai *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0x400);
+ return true;
+}
+
+static bool trans_add(DisasContext *ctx, arg_add *a)
+{
+ gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sub(DisasContext *ctx, arg_sub *a)
+{
+ gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sll(DisasContext *ctx, arg_sll *a)
+{
+ gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_slt(DisasContext *ctx, arg_slt *a)
+{
+ gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
+{
+ gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_xor(DisasContext *ctx, arg_xor *a)
+{
+ gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_srl(DisasContext *ctx, arg_srl *a)
+{
+ gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sra(DisasContext *ctx, arg_sra *a)
+{
+ gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_or(DisasContext *ctx, arg_or *a)
+{
+ gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_and(DisasContext *ctx, arg_and *a)
+{
+ gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1,
+ a->shamt | 0x400);
+ return true;
+}
+
+static bool trans_addw(DisasContext *ctx, arg_addw *a)
+{
+ gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_subw(DisasContext *ctx, arg_subw *a)
+{
+ gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
+{
+ gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
+{
+ gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
+{
+ gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 609207f785..c16eba8ec8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1711,15 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_ARITH_IMM:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ARITH_IMM_W:
-#endif
- if (rd == 0) {
- break; /* NOP */
- }
- gen_arith_imm(ctx, MASK_OP_ARITH_IMM(ctx->opcode), rd, rs1, imm);
- break;
case OPC_RISC_ARITH:
#if defined(TARGET_RISCV64)
case OPC_RISC_ARITH_W:
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32-64.decode | 13 ++
target/riscv/insn32.decode | 25 ++++
target/riscv/insn_trans/trans_rvi.inc.c | 168 ++++++++++++++++++++++++
target/riscv/translate.c | 9 --
4 files changed, 206 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 439d4e2c58..9a35f2aa19 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -19,7 +19,20 @@
# This is concatenated with insn32.decode for risc64 targets.
# Most of the fields and formats are there.
+%sh5 20:5
+
+@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
+
# *** RV64I Base Instruction Set (in addition to RV32I) ***
lwu ............ ..... 110 ..... 0000011 @i
ld ............ ..... 011 ..... 0000011 @i
sd ....... ..... ..... 011 ..... 0100011 @s
+addiw ............ ..... 000 ..... 0011011 @i
+slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
+srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
+sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
+addw 0000000 ..... ..... 000 ..... 0111011 @r
+subw 0100000 ..... ..... 000 ..... 0111011 @r
+sllw 0000000 ..... ..... 001 ..... 0111011 @r
+srlw 0000000 ..... ..... 101 ..... 0111011 @r
+sraw 0100000 ..... ..... 101 ..... 0111011 @r
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 076de873c4..1f5bf1f6f9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -21,6 +21,8 @@
%rs1 15:5
%rd 7:5
+%sh10 20:10
+
# immediates:
%imm_i 20:s12
%imm_s 25:s7 7:5
@@ -30,14 +32,18 @@
# Argument sets:
&b imm rs2 rs1
+&shift shamt rs1 rd
# Formats 32:
+@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
@j .................... ..... ....... imm=%imm_j %rd
+@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
@@ -57,3 +63,22 @@ lhu ............ ..... 101 ..... 0000011 @i
sb ....... ..... ..... 000 ..... 0100011 @s
sh ....... ..... ..... 001 ..... 0100011 @s
sw ....... ..... ..... 010 ..... 0100011 @s
+addi ............ ..... 000 ..... 0010011 @i
+slti ............ ..... 010 ..... 0010011 @i
+sltiu ............ ..... 011 ..... 0010011 @i
+xori ............ ..... 100 ..... 0010011 @i
+ori ............ ..... 110 ..... 0010011 @i
+andi ............ ..... 111 ..... 0010011 @i
+slli 00.... ...... ..... 001 ..... 0010011 @sh
+srli 00.... ...... ..... 101 ..... 0010011 @sh
+srai 01.... ...... ..... 101 ..... 0010011 @sh
+add 0000000 ..... ..... 000 ..... 0110011 @r
+sub 0100000 ..... ..... 000 ..... 0110011 @r
+sll 0000000 ..... ..... 001 ..... 0110011 @r
+slt 0000000 ..... ..... 010 ..... 0110011 @r
+sltu 0000000 ..... ..... 011 ..... 0110011 @r
+xor 0000000 ..... ..... 100 ..... 0110011 @r
+srl 0000000 ..... ..... 101 ..... 0110011 @r
+sra 0100000 ..... ..... 101 ..... 0110011 @r
+or 0000000 ..... ..... 110 ..... 0110011 @r
+and 0000000 ..... ..... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 39a20a70e8..01f751650a 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -150,3 +150,171 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
return true;
}
#endif
+
+static bool trans_addi(DisasContext *ctx, arg_addi *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_slti(DisasContext *ctx, arg_slti *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_xori(DisasContext *ctx, arg_xori *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
+ return true;
+}
+static bool trans_ori(DisasContext *ctx, arg_ori *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm);
+ return true;
+}
+static bool trans_andi(DisasContext *ctx, arg_andi *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
+ return true;
+}
+static bool trans_slli(DisasContext *ctx, arg_slli *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_srli(DisasContext *ctx, arg_srli *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_srai(DisasContext *ctx, arg_srai *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0x400);
+ return true;
+}
+
+static bool trans_add(DisasContext *ctx, arg_add *a)
+{
+ gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sub(DisasContext *ctx, arg_sub *a)
+{
+ gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sll(DisasContext *ctx, arg_sll *a)
+{
+ gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_slt(DisasContext *ctx, arg_slt *a)
+{
+ gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
+{
+ gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_xor(DisasContext *ctx, arg_xor *a)
+{
+ gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_srl(DisasContext *ctx, arg_srl *a)
+{
+ gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sra(DisasContext *ctx, arg_sra *a)
+{
+ gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_or(DisasContext *ctx, arg_or *a)
+{
+ gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_and(DisasContext *ctx, arg_and *a)
+{
+ gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
+ return true;
+}
+
+static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW, a->rd, a->rs1, a->shamt);
+ return true;
+}
+
+static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
+{
+ gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1,
+ a->shamt | 0x400);
+ return true;
+}
+
+static bool trans_addw(DisasContext *ctx, arg_addw *a)
+{
+ gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_subw(DisasContext *ctx, arg_subw *a)
+{
+ gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
+{
+ gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
+{
+ gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
+{
+ gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 609207f785..c16eba8ec8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1711,15 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_ARITH_IMM:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ARITH_IMM_W:
-#endif
- if (rd == 0) {
- break; /* NOP */
- }
- gen_arith_imm(ctx, MASK_OP_ARITH_IMM(ctx->opcode), rd, rs1, imm);
- break;
case OPC_RISC_ARITH:
#if defined(TARGET_RISCV64)
case OPC_RISC_ARITH_W:
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 07/35] target/riscv: Convert RVXI fence insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v4 -> v5:
- fixed rebase error
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvi.inc.c | 19 +++++++++++++++++++
target/riscv/translate.c | 12 ------------
3 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1f5bf1f6f9..804b721ca5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -82,3 +82,5 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
sra 0100000 ..... ..... 101 ..... 0110011 @r
or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
+fence ---- pred:4 succ:4 ----- 000 ----- 0001111
+fence_i ---- ---- ---- ----- 001 ----- 0001111
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 01f751650a..b468a0ac0e 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -318,3 +318,22 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
return true;
}
#endif
+
+static bool trans_fence(DisasContext *ctx, arg_fence *a)
+{
+ /* FENCE is a full memory barrier. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+ return true;
+}
+
+static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
+{
+ /*
+ * FENCE_I is a no-op in QEMU,
+ * however we need to end the translation block
+ */
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ tcg_gen_exit_tb(NULL, 0);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c16eba8ec8..9899f10be4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1750,18 +1750,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
GET_RM(ctx->opcode));
break;
- case OPC_RISC_FENCE:
- if (ctx->opcode & 0x1000) {
- /* FENCE_I is a no-op in QEMU,
- * however we need to end the translation block */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- tcg_gen_exit_tb(NULL, 0);
- ctx->base.is_jmp = DISAS_NORETURN;
- } else {
- /* FENCE is a full memory barrier. */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- }
- break;
case OPC_RISC_SYSTEM:
gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 07/35] target/riscv: Convert RVXI fence insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v4 -> v5:
- fixed rebase error
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvi.inc.c | 19 +++++++++++++++++++
target/riscv/translate.c | 12 ------------
3 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1f5bf1f6f9..804b721ca5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -82,3 +82,5 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
sra 0100000 ..... ..... 101 ..... 0110011 @r
or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
+fence ---- pred:4 succ:4 ----- 000 ----- 0001111
+fence_i ---- ---- ---- ----- 001 ----- 0001111
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 01f751650a..b468a0ac0e 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -318,3 +318,22 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
return true;
}
#endif
+
+static bool trans_fence(DisasContext *ctx, arg_fence *a)
+{
+ /* FENCE is a full memory barrier. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+ return true;
+}
+
+static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
+{
+ /*
+ * FENCE_I is a no-op in QEMU,
+ * however we need to end the translation block
+ */
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ tcg_gen_exit_tb(NULL, 0);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c16eba8ec8..9899f10be4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1750,18 +1750,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
GET_RM(ctx->opcode));
break;
- case OPC_RISC_FENCE:
- if (ctx->opcode & 0x1000) {
- /* FENCE_I is a no-op in QEMU,
- * however we need to end the translation block */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- tcg_gen_exit_tb(NULL, 0);
- ctx->base.is_jmp = DISAS_NORETURN;
- } else {
- /* FENCE is a full memory barrier. */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- }
- break;
case OPC_RISC_SYSTEM:
gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 08/35] target/riscv: Convert RVXI csr insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79 +++++++++++++++++++++++++
target/riscv/translate.c | 43 +-------------
3 files changed, 88 insertions(+), 42 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 804b721ca5..977b1b10a3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -22,6 +22,7 @@
%rd 7:5
%sh10 20:10
+%csr 20:12
# immediates:
%imm_i 20:s12
@@ -43,6 +44,7 @@
@j .................... ..... ....... imm=%imm_j %rd
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
+@csr ............ ..... ... ..... ....... %csr %rs1 %rd
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
@@ -84,3 +86,9 @@ or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
fence ---- pred:4 succ:4 ----- 000 ----- 0001111
fence_i ---- ---- ---- ----- 001 ----- 0001111
+csrrw ............ ..... 001 ..... 1110011 @csr
+csrrs ............ ..... 010 ..... 1110011 @csr
+csrrc ............ ..... 011 ..... 1110011 @csr
+csrrwi ............ ..... 101 ..... 1110011 @csr
+csrrsi ............ ..... 110 ..... 1110011 @csr
+csrrci ............ ..... 111 ..... 1110011 @csr
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index b468a0ac0e..b0f35cef14 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -337,3 +337,82 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
+
+#define RISCV_OP_CSR_PRE do {\
+ source1 = tcg_temp_new(); \
+ csr_store = tcg_temp_new(); \
+ dest = tcg_temp_new(); \
+ rs1_pass = tcg_temp_new(); \
+ gen_get_gpr(source1, a->rs1); \
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
+ tcg_gen_movi_tl(rs1_pass, a->rs1); \
+ tcg_gen_movi_tl(csr_store, a->csr); \
+ gen_io_start();\
+} while (0)
+
+#define RISCV_OP_CSR_POST do {\
+ gen_io_end(); \
+ gen_set_gpr(a->rd, dest); \
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
+ tcg_gen_exit_tb(NULL, 0); \
+ ctx->base.is_jmp = DISAS_NORETURN; \
+ tcg_temp_free(source1); \
+ tcg_temp_free(csr_store); \
+ tcg_temp_free(dest); \
+ tcg_temp_free(rs1_pass); \
+} while (0)
+
+
+static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrw(dest, cpu_env, source1, csr_store);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9899f10be4..a020305556 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1279,16 +1279,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs1, int csr)
{
- TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
+ TCGv source1, dest;
source1 = tcg_temp_new();
- csr_store = tcg_temp_new();
dest = tcg_temp_new();
- rs1_pass = tcg_temp_new();
- imm_rs1 = tcg_temp_new();
gen_get_gpr(source1, rs1);
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- tcg_gen_movi_tl(rs1_pass, rs1);
- tcg_gen_movi_tl(csr_store, csr); /* copy into temp reg to feed to helper */
#ifndef CONFIG_USER_ONLY
/* Extract funct7 value and check whether it matches SFENCE.VMA */
@@ -1359,45 +1354,9 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
break;
}
break;
- default:
- tcg_gen_movi_tl(imm_rs1, rs1);
- gen_io_start();
- switch (opc) {
- case OPC_RISC_CSRRW:
- gen_helper_csrrw(dest, cpu_env, source1, csr_store);
- break;
- case OPC_RISC_CSRRS:
- gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRC:
- gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRWI:
- gen_helper_csrrw(dest, cpu_env, imm_rs1, csr_store);
- break;
- case OPC_RISC_CSRRSI:
- gen_helper_csrrs(dest, cpu_env, imm_rs1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRCI:
- gen_helper_csrrc(dest, cpu_env, imm_rs1, csr_store, rs1_pass);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
- gen_io_end();
- gen_set_gpr(rd, dest);
- /* end tb since we may be changing priv modes, to get mmu_index right */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
}
tcg_temp_free(source1);
- tcg_temp_free(csr_store);
tcg_temp_free(dest);
- tcg_temp_free(rs1_pass);
- tcg_temp_free(imm_rs1);
}
static void decode_RV32_64C0(DisasContext *ctx)
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 08/35] target/riscv: Convert RVXI csr insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79 +++++++++++++++++++++++++
target/riscv/translate.c | 43 +-------------
3 files changed, 88 insertions(+), 42 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 804b721ca5..977b1b10a3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -22,6 +22,7 @@
%rd 7:5
%sh10 20:10
+%csr 20:12
# immediates:
%imm_i 20:s12
@@ -43,6 +44,7 @@
@j .................... ..... ....... imm=%imm_j %rd
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
+@csr ............ ..... ... ..... ....... %csr %rs1 %rd
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
@@ -84,3 +86,9 @@ or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
fence ---- pred:4 succ:4 ----- 000 ----- 0001111
fence_i ---- ---- ---- ----- 001 ----- 0001111
+csrrw ............ ..... 001 ..... 1110011 @csr
+csrrs ............ ..... 010 ..... 1110011 @csr
+csrrc ............ ..... 011 ..... 1110011 @csr
+csrrwi ............ ..... 101 ..... 1110011 @csr
+csrrsi ............ ..... 110 ..... 1110011 @csr
+csrrci ............ ..... 111 ..... 1110011 @csr
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index b468a0ac0e..b0f35cef14 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -337,3 +337,82 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
+
+#define RISCV_OP_CSR_PRE do {\
+ source1 = tcg_temp_new(); \
+ csr_store = tcg_temp_new(); \
+ dest = tcg_temp_new(); \
+ rs1_pass = tcg_temp_new(); \
+ gen_get_gpr(source1, a->rs1); \
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
+ tcg_gen_movi_tl(rs1_pass, a->rs1); \
+ tcg_gen_movi_tl(csr_store, a->csr); \
+ gen_io_start();\
+} while (0)
+
+#define RISCV_OP_CSR_POST do {\
+ gen_io_end(); \
+ gen_set_gpr(a->rd, dest); \
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
+ tcg_gen_exit_tb(NULL, 0); \
+ ctx->base.is_jmp = DISAS_NORETURN; \
+ tcg_temp_free(source1); \
+ tcg_temp_free(csr_store); \
+ tcg_temp_free(dest); \
+ tcg_temp_free(rs1_pass); \
+} while (0)
+
+
+static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrw(dest, cpu_env, source1, csr_store);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9899f10be4..a020305556 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1279,16 +1279,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs1, int csr)
{
- TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
+ TCGv source1, dest;
source1 = tcg_temp_new();
- csr_store = tcg_temp_new();
dest = tcg_temp_new();
- rs1_pass = tcg_temp_new();
- imm_rs1 = tcg_temp_new();
gen_get_gpr(source1, rs1);
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- tcg_gen_movi_tl(rs1_pass, rs1);
- tcg_gen_movi_tl(csr_store, csr); /* copy into temp reg to feed to helper */
#ifndef CONFIG_USER_ONLY
/* Extract funct7 value and check whether it matches SFENCE.VMA */
@@ -1359,45 +1354,9 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
break;
}
break;
- default:
- tcg_gen_movi_tl(imm_rs1, rs1);
- gen_io_start();
- switch (opc) {
- case OPC_RISC_CSRRW:
- gen_helper_csrrw(dest, cpu_env, source1, csr_store);
- break;
- case OPC_RISC_CSRRS:
- gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRC:
- gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRWI:
- gen_helper_csrrw(dest, cpu_env, imm_rs1, csr_store);
- break;
- case OPC_RISC_CSRRSI:
- gen_helper_csrrs(dest, cpu_env, imm_rs1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRCI:
- gen_helper_csrrc(dest, cpu_env, imm_rs1, csr_store, rs1_pass);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
- gen_io_end();
- gen_set_gpr(rd, dest);
- /* end tb since we may be changing priv modes, to get mmu_index right */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
}
tcg_temp_free(source1);
- tcg_temp_free(csr_store);
tcg_temp_free(dest);
- tcg_temp_free(rs1_pass);
- tcg_temp_free(imm_rs1);
}
static void decode_RV32_64C0(DisasContext *ctx)
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 09/35] target/riscv: Convert RVXM insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32-64.decode | 7 ++
target/riscv/insn32.decode | 10 +++
target/riscv/insn_trans/trans_rvm.inc.c | 100 ++++++++++++++++++++++++
target/riscv/translate.c | 10 +--
4 files changed, 118 insertions(+), 9 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 9a35f2aa19..008f100546 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -36,3 +36,10 @@ subw 0100000 ..... ..... 000 ..... 0111011 @r
sllw 0000000 ..... ..... 001 ..... 0111011 @r
srlw 0000000 ..... ..... 101 ..... 0111011 @r
sraw 0100000 ..... ..... 101 ..... 0111011 @r
+
+# *** RV64M Standard Extension (in addition to RV32M) ***
+mulw 0000001 ..... ..... 000 ..... 0111011 @r
+divw 0000001 ..... ..... 100 ..... 0111011 @r
+divuw 0000001 ..... ..... 101 ..... 0111011 @r
+remw 0000001 ..... ..... 110 ..... 0111011 @r
+remuw 0000001 ..... ..... 111 ..... 0111011 @r
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 977b1b10a3..e53944bf0e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -92,3 +92,13 @@ csrrc ............ ..... 011 ..... 1110011 @csr
csrrwi ............ ..... 101 ..... 1110011 @csr
csrrsi ............ ..... 110 ..... 1110011 @csr
csrrci ............ ..... 111 ..... 1110011 @csr
+
+# *** RV32M Standard Extension ***
+mul 0000001 ..... ..... 000 ..... 0110011 @r
+mulh 0000001 ..... ..... 001 ..... 0110011 @r
+mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
+mulhu 0000001 ..... ..... 011 ..... 0110011 @r
+div 0000001 ..... ..... 100 ..... 0110011 @r
+divu 0000001 ..... ..... 101 ..... 0110011 @r
+rem 0000001 ..... ..... 110 ..... 0110011 @r
+remu 0000001 ..... ..... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c
new file mode 100644
index 0000000000..ec3197ede8
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -0,0 +1,100 @@
+/*
+ * RISC-V translation routines for the RV64M Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+static bool trans_mul(DisasContext *ctx, arg_mul *a)
+{
+ gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+{
+ gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
+{
+ gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+{
+ gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_div(DisasContext *ctx, arg_div *a)
+{
+ gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divu(DisasContext *ctx, arg_divu *a)
+{
+ gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_rem(DisasContext *ctx, arg_rem *a)
+{
+ gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remu(DisasContext *ctx, arg_remu *a)
+{
+ gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
+{
+ gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divw(DisasContext *ctx, arg_divw *a)
+{
+ gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
+{
+ gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remw(DisasContext *ctx, arg_remw *a)
+{
+ gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
+{
+ gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a020305556..666c039662 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1649,6 +1649,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "decode_insn32.inc.c"
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
+#include "insn_trans/trans_rvm.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
@@ -1670,15 +1671,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_ARITH:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ARITH_W:
-#endif
- if (rd == 0) {
- break; /* NOP */
- }
- gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2);
- break;
case OPC_RISC_FP_LOAD:
gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 09/35] target/riscv: Convert RVXM insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32-64.decode | 7 ++
target/riscv/insn32.decode | 10 +++
target/riscv/insn_trans/trans_rvm.inc.c | 100 ++++++++++++++++++++++++
target/riscv/translate.c | 10 +--
4 files changed, 118 insertions(+), 9 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 9a35f2aa19..008f100546 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -36,3 +36,10 @@ subw 0100000 ..... ..... 000 ..... 0111011 @r
sllw 0000000 ..... ..... 001 ..... 0111011 @r
srlw 0000000 ..... ..... 101 ..... 0111011 @r
sraw 0100000 ..... ..... 101 ..... 0111011 @r
+
+# *** RV64M Standard Extension (in addition to RV32M) ***
+mulw 0000001 ..... ..... 000 ..... 0111011 @r
+divw 0000001 ..... ..... 100 ..... 0111011 @r
+divuw 0000001 ..... ..... 101 ..... 0111011 @r
+remw 0000001 ..... ..... 110 ..... 0111011 @r
+remuw 0000001 ..... ..... 111 ..... 0111011 @r
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 977b1b10a3..e53944bf0e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -92,3 +92,13 @@ csrrc ............ ..... 011 ..... 1110011 @csr
csrrwi ............ ..... 101 ..... 1110011 @csr
csrrsi ............ ..... 110 ..... 1110011 @csr
csrrci ............ ..... 111 ..... 1110011 @csr
+
+# *** RV32M Standard Extension ***
+mul 0000001 ..... ..... 000 ..... 0110011 @r
+mulh 0000001 ..... ..... 001 ..... 0110011 @r
+mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
+mulhu 0000001 ..... ..... 011 ..... 0110011 @r
+div 0000001 ..... ..... 100 ..... 0110011 @r
+divu 0000001 ..... ..... 101 ..... 0110011 @r
+rem 0000001 ..... ..... 110 ..... 0110011 @r
+remu 0000001 ..... ..... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c
new file mode 100644
index 0000000000..ec3197ede8
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -0,0 +1,100 @@
+/*
+ * RISC-V translation routines for the RV64M Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+static bool trans_mul(DisasContext *ctx, arg_mul *a)
+{
+ gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+{
+ gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
+{
+ gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+{
+ gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_div(DisasContext *ctx, arg_div *a)
+{
+ gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divu(DisasContext *ctx, arg_divu *a)
+{
+ gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_rem(DisasContext *ctx, arg_rem *a)
+{
+ gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remu(DisasContext *ctx, arg_remu *a)
+{
+ gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
+{
+ gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divw(DisasContext *ctx, arg_divw *a)
+{
+ gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
+{
+ gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remw(DisasContext *ctx, arg_remw *a)
+{
+ gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
+{
+ gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a020305556..666c039662 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1649,6 +1649,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "decode_insn32.inc.c"
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
+#include "insn_trans/trans_rvm.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
@@ -1670,15 +1671,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_ARITH:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ARITH_W:
-#endif
- if (rd == 0) {
- break; /* NOP */
- }
- gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2);
- break;
case OPC_RISC_FP_LOAD:
gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 149 ++++++++++++++++++++++++
target/riscv/translate.c | 1 +
3 files changed, 167 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e53944bf0e..00b9e2d9a5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -34,6 +34,7 @@
# Argument sets:
&b imm rs2 rs1
&shift shamt rs1 rd
+&atomic aq rl rs2 rs1 rd
# Formats 32:
@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
@@ -46,6 +47,9 @@
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
+@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
+@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
@@ -102,3 +106,16 @@ div 0000001 ..... ..... 100 ..... 0110011 @r
divu 0000001 ..... ..... 101 ..... 0110011 @r
rem 0000001 ..... ..... 110 ..... 0110011 @r
remu 0000001 ..... ..... 111 ..... 0110011 @r
+
+# *** RV32A Standard Extension ***
+lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
+sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
+amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
+amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
+amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
+amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
+amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
+amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c
new file mode 100644
index 0000000000..ab6ccf0e90
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rva.inc.c
@@ -0,0 +1,149 @@
+/*
+ * RISC-V translation routines for the RV64A Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ /* Put addr in load_res, data in load_val. */
+ gen_get_gpr(src1, a->rs1);
+ if (a->rl) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
+ tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
+ if (a->aq) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
+ tcg_gen_mov_tl(load_res, src1);
+ gen_set_gpr(a->rd, load_val);
+
+ tcg_temp_free(src1);
+ return true;
+}
+
+static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+
+ gen_get_gpr(src1, a->rs1);
+ tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
+
+ gen_get_gpr(src2, a->rs2);
+ /*
+ * Note that the TCG atomic primitives are SC,
+ * so we can ignore AQ/RL along this path.
+ */
+ tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
+ ctx->mem_idx, mop);
+ tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
+ gen_set_gpr(a->rd, dat);
+ tcg_gen_br(l2);
+
+ gen_set_label(l1);
+ /*
+ * Address comparion failure. However, we still need to
+ * provide the memory barrier implied by AQ/RL.
+ */
+ tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
+ tcg_gen_movi_tl(dat, 1);
+ gen_set_gpr(a->rd, dat);
+
+ gen_set_label(l2);
+ tcg_temp_free(dat);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+ return true;
+}
+
+static bool gen_amo(DisasContext *ctx, arg_atomic *a,
+ void(*func)(TCGv, TCGv, TCGv, TCGArg, TCGMemOp),
+ TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_temp_new();
+
+ gen_get_gpr(src1, a->rs1);
+ gen_get_gpr(src2, a->rs2);
+
+ (*func)(src2, src1, src2, ctx->mem_idx, mop);
+
+ gen_set_gpr(a->rd, src2);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+ return true;
+}
+
+static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
+{
+ return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
+{
+ return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 666c039662..98180002ef 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1650,6 +1650,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
+#include "insn_trans/trans_rva.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 10/35] target/riscv: Convert RV32A insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 149 ++++++++++++++++++++++++
target/riscv/translate.c | 1 +
3 files changed, 167 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e53944bf0e..00b9e2d9a5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -34,6 +34,7 @@
# Argument sets:
&b imm rs2 rs1
&shift shamt rs1 rd
+&atomic aq rl rs2 rs1 rd
# Formats 32:
@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
@@ -46,6 +47,9 @@
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
+@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
+@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
@@ -102,3 +106,16 @@ div 0000001 ..... ..... 100 ..... 0110011 @r
divu 0000001 ..... ..... 101 ..... 0110011 @r
rem 0000001 ..... ..... 110 ..... 0110011 @r
remu 0000001 ..... ..... 111 ..... 0110011 @r
+
+# *** RV32A Standard Extension ***
+lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
+sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
+amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
+amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
+amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
+amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
+amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
+amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c
new file mode 100644
index 0000000000..ab6ccf0e90
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rva.inc.c
@@ -0,0 +1,149 @@
+/*
+ * RISC-V translation routines for the RV64A Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ /* Put addr in load_res, data in load_val. */
+ gen_get_gpr(src1, a->rs1);
+ if (a->rl) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
+ tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
+ if (a->aq) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
+ tcg_gen_mov_tl(load_res, src1);
+ gen_set_gpr(a->rd, load_val);
+
+ tcg_temp_free(src1);
+ return true;
+}
+
+static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+
+ gen_get_gpr(src1, a->rs1);
+ tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
+
+ gen_get_gpr(src2, a->rs2);
+ /*
+ * Note that the TCG atomic primitives are SC,
+ * so we can ignore AQ/RL along this path.
+ */
+ tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
+ ctx->mem_idx, mop);
+ tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
+ gen_set_gpr(a->rd, dat);
+ tcg_gen_br(l2);
+
+ gen_set_label(l1);
+ /*
+ * Address comparion failure. However, we still need to
+ * provide the memory barrier implied by AQ/RL.
+ */
+ tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
+ tcg_gen_movi_tl(dat, 1);
+ gen_set_gpr(a->rd, dat);
+
+ gen_set_label(l2);
+ tcg_temp_free(dat);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+ return true;
+}
+
+static bool gen_amo(DisasContext *ctx, arg_atomic *a,
+ void(*func)(TCGv, TCGv, TCGv, TCGArg, TCGMemOp),
+ TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_temp_new();
+
+ gen_get_gpr(src1, a->rs1);
+ gen_get_gpr(src2, a->rs2);
+
+ (*func)(src2, src1, src2, ctx->mem_idx, mop);
+
+ gen_set_gpr(a->rd, src2);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+ return true;
+}
+
+static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
+{
+ return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
+{
+ return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 666c039662..98180002ef 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1650,6 +1650,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
+#include "insn_trans/trans_rva.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 11/35] target/riscv: Convert RV64A insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32-64.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 58 ++++++++++
target/riscv/translate.c | 140 ------------------------
3 files changed, 71 insertions(+), 140 deletions(-)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 008f100546..0bee95c984 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -43,3 +43,16 @@ divw 0000001 ..... ..... 100 ..... 0111011 @r
divuw 0000001 ..... ..... 101 ..... 0111011 @r
remw 0000001 ..... ..... 110 ..... 0111011 @r
remuw 0000001 ..... ..... 111 ..... 0111011 @r
+
+# *** RV64A Standard Extension (in addition to RV32A) ***
+lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
+sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
+amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
+amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
+amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
+amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c
index ab6ccf0e90..11620e030e 100644
--- a/target/riscv/insn_trans/trans_rva.inc.c
+++ b/target/riscv/insn_trans/trans_rva.inc.c
@@ -147,3 +147,61 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
}
+
+#ifdef TARGET_RISCV64
+
+static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
+{
+ return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
+}
+
+static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
+{
+ return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 98180002ef..944836dd7c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,143 +711,6 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
tcg_temp_free(t0);
}
-static void gen_atomic(DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int rs2)
-{
- TCGv src1, src2, dat;
- TCGLabel *l1, *l2;
- TCGMemOp mop;
- bool aq, rl;
-
- /* Extract the size of the atomic operation. */
- switch (extract32(opc, 12, 3)) {
- case 2: /* 32-bit */
- mop = MO_ALIGN | MO_TESL;
- break;
-#if defined(TARGET_RISCV64)
- case 3: /* 64-bit */
- mop = MO_ALIGN | MO_TEQ;
- break;
-#endif
- default:
- gen_exception_illegal(ctx);
- return;
- }
- rl = extract32(opc, 25, 1);
- aq = extract32(opc, 26, 1);
-
- src1 = tcg_temp_new();
- src2 = tcg_temp_new();
-
- switch (MASK_OP_ATOMIC_NO_AQ_RL_SZ(opc)) {
- case OPC_RISC_LR:
- /* Put addr in load_res, data in load_val. */
- gen_get_gpr(src1, rs1);
- if (rl) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- }
- tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
- if (aq) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
- }
- tcg_gen_mov_tl(load_res, src1);
- gen_set_gpr(rd, load_val);
- break;
-
- case OPC_RISC_SC:
- l1 = gen_new_label();
- l2 = gen_new_label();
- dat = tcg_temp_new();
-
- gen_get_gpr(src1, rs1);
- tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
-
- gen_get_gpr(src2, rs2);
- /* Note that the TCG atomic primitives are SC,
- so we can ignore AQ/RL along this path. */
- tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
- ctx->mem_idx, mop);
- tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
- gen_set_gpr(rd, dat);
- tcg_gen_br(l2);
-
- gen_set_label(l1);
- /* Address comparion failure. However, we still need to
- provide the memory barrier implied by AQ/RL. */
- tcg_gen_mb(TCG_MO_ALL + aq * TCG_BAR_LDAQ + rl * TCG_BAR_STRL);
- tcg_gen_movi_tl(dat, 1);
- gen_set_gpr(rd, dat);
-
- gen_set_label(l2);
- tcg_temp_free(dat);
- break;
-
- case OPC_RISC_AMOSWAP:
- /* Note that the TCG atomic primitives are SC,
- so we can ignore AQ/RL along this path. */
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_xchg_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOADD:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_add_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOXOR:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_xor_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOAND:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_and_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOOR:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_or_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMIN:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_smin_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMAX:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_smax_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMINU:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_umin_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMAXU:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_umax_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
-
- tcg_temp_free(src1);
- tcg_temp_free(src2);
-}
-
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
@@ -1679,9 +1542,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2,
GET_STORE_IMM(ctx->opcode));
break;
- case OPC_RISC_ATOMIC:
- gen_atomic(ctx, MASK_OP_ATOMIC(ctx->opcode), rd, rs1, rs2);
- break;
case OPC_RISC_FMADD:
gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2,
GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 11/35] target/riscv: Convert RV64A insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32-64.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 58 ++++++++++
target/riscv/translate.c | 140 ------------------------
3 files changed, 71 insertions(+), 140 deletions(-)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 008f100546..0bee95c984 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -43,3 +43,16 @@ divw 0000001 ..... ..... 100 ..... 0111011 @r
divuw 0000001 ..... ..... 101 ..... 0111011 @r
remw 0000001 ..... ..... 110 ..... 0111011 @r
remuw 0000001 ..... ..... 111 ..... 0111011 @r
+
+# *** RV64A Standard Extension (in addition to RV32A) ***
+lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
+sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
+amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
+amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
+amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
+amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c
index ab6ccf0e90..11620e030e 100644
--- a/target/riscv/insn_trans/trans_rva.inc.c
+++ b/target/riscv/insn_trans/trans_rva.inc.c
@@ -147,3 +147,61 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
}
+
+#ifdef TARGET_RISCV64
+
+static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
+{
+ return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
+}
+
+static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
+{
+ return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 98180002ef..944836dd7c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,143 +711,6 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
tcg_temp_free(t0);
}
-static void gen_atomic(DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int rs2)
-{
- TCGv src1, src2, dat;
- TCGLabel *l1, *l2;
- TCGMemOp mop;
- bool aq, rl;
-
- /* Extract the size of the atomic operation. */
- switch (extract32(opc, 12, 3)) {
- case 2: /* 32-bit */
- mop = MO_ALIGN | MO_TESL;
- break;
-#if defined(TARGET_RISCV64)
- case 3: /* 64-bit */
- mop = MO_ALIGN | MO_TEQ;
- break;
-#endif
- default:
- gen_exception_illegal(ctx);
- return;
- }
- rl = extract32(opc, 25, 1);
- aq = extract32(opc, 26, 1);
-
- src1 = tcg_temp_new();
- src2 = tcg_temp_new();
-
- switch (MASK_OP_ATOMIC_NO_AQ_RL_SZ(opc)) {
- case OPC_RISC_LR:
- /* Put addr in load_res, data in load_val. */
- gen_get_gpr(src1, rs1);
- if (rl) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- }
- tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
- if (aq) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
- }
- tcg_gen_mov_tl(load_res, src1);
- gen_set_gpr(rd, load_val);
- break;
-
- case OPC_RISC_SC:
- l1 = gen_new_label();
- l2 = gen_new_label();
- dat = tcg_temp_new();
-
- gen_get_gpr(src1, rs1);
- tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
-
- gen_get_gpr(src2, rs2);
- /* Note that the TCG atomic primitives are SC,
- so we can ignore AQ/RL along this path. */
- tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
- ctx->mem_idx, mop);
- tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
- gen_set_gpr(rd, dat);
- tcg_gen_br(l2);
-
- gen_set_label(l1);
- /* Address comparion failure. However, we still need to
- provide the memory barrier implied by AQ/RL. */
- tcg_gen_mb(TCG_MO_ALL + aq * TCG_BAR_LDAQ + rl * TCG_BAR_STRL);
- tcg_gen_movi_tl(dat, 1);
- gen_set_gpr(rd, dat);
-
- gen_set_label(l2);
- tcg_temp_free(dat);
- break;
-
- case OPC_RISC_AMOSWAP:
- /* Note that the TCG atomic primitives are SC,
- so we can ignore AQ/RL along this path. */
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_xchg_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOADD:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_add_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOXOR:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_xor_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOAND:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_and_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOOR:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_or_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMIN:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_smin_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMAX:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_smax_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMINU:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_umin_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMAXU:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_umax_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
-
- tcg_temp_free(src1);
- tcg_temp_free(src2);
-}
-
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
@@ -1679,9 +1542,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2,
GET_STORE_IMM(ctx->opcode));
break;
- case OPC_RISC_ATOMIC:
- gen_atomic(ctx, MASK_OP_ATOMIC(ctx->opcode), rd, rs1, rs2);
- break;
case OPC_RISC_FMADD:
gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2,
GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 334 ++++++++++++++++++++++++
target/riscv/translate.c | 1 +
3 files changed, 370 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 00b9e2d9a5..e40836bf03 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -17,12 +17,14 @@
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
+%rs3 27:5
%rs2 20:5
%rs1 15:5
%rd 7:5
%sh10 20:10
%csr 20:12
+%rm 12:3
# immediates:
%imm_i 20:s12
@@ -50,6 +52,11 @@
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
+@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
+@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
+@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
+@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
@@ -119,3 +126,31 @@ amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
+
+# *** RV32F Standard Extension ***
+flw ............ ..... 010 ..... 0000111 @i
+fsw ....... ..... ..... 010 ..... 0100111 @s
+fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
+fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
+fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
+fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
+fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
+fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
+fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
+fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
+fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
+fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
+fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
+fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
+fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
+fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
+fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
+fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
+feq_s 1010000 ..... ..... 010 ..... 1010011 @r
+flt_s 1010000 ..... ..... 001 ..... 1010011 @r
+fle_s 1010000 ..... ..... 000 ..... 1010011 @r
+fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
+fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
+fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
new file mode 100644
index 0000000000..b101593ac4
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -0,0 +1,334 @@
+/*
+ * RISC-V translation routines for the RV64F Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_FPU do {\
+ if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) \
+ return false; \
+} while (0)
+
+static bool trans_flw(DisasContext *ctx, arg_flw *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
+ /* RISC-V requires NaN-boxing of narrower width floating point values */
+ tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+ return true;
+}
+
+static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FMOV */
+ tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ } else { /* FSGNJ */
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
+ 0, 31);
+ }
+ return true;
+}
+
+static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FNEG */
+ tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FABS */
+ tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN);
+ tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
+{
+ /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+
+#if defined(TARGET_RISCV64)
+ tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
+#else
+ tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
+#endif
+
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
+{
+ REQUIRE_FPU;
+ TCGv t0 = tcg_temp_new();
+ gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
+{
+ REQUIRE_FPU;
+ TCGv t0 = tcg_temp_new();
+ gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
+{
+ REQUIRE_FPU;
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+
+ gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
+
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
+{
+ /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+#if defined(TARGET_RISCV64)
+ tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
+#else
+ tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
+#endif
+
+ tcg_temp_free(t0);
+
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 944836dd7c..933ca9fb69 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1514,6 +1514,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
#include "insn_trans/trans_rva.inc.c"
+#include "insn_trans/trans_rvf.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 12/35] target/riscv: Convert RV32F insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 334 ++++++++++++++++++++++++
target/riscv/translate.c | 1 +
3 files changed, 370 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 00b9e2d9a5..e40836bf03 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -17,12 +17,14 @@
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
+%rs3 27:5
%rs2 20:5
%rs1 15:5
%rd 7:5
%sh10 20:10
%csr 20:12
+%rm 12:3
# immediates:
%imm_i 20:s12
@@ -50,6 +52,11 @@
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
+@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
+@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
+@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
+@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
@@ -119,3 +126,31 @@ amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
+
+# *** RV32F Standard Extension ***
+flw ............ ..... 010 ..... 0000111 @i
+fsw ....... ..... ..... 010 ..... 0100111 @s
+fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
+fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
+fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
+fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
+fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
+fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
+fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
+fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
+fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
+fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
+fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
+fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
+fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
+fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
+fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
+fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
+feq_s 1010000 ..... ..... 010 ..... 1010011 @r
+flt_s 1010000 ..... ..... 001 ..... 1010011 @r
+fle_s 1010000 ..... ..... 000 ..... 1010011 @r
+fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
+fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
+fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
new file mode 100644
index 0000000000..b101593ac4
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -0,0 +1,334 @@
+/*
+ * RISC-V translation routines for the RV64F Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_FPU do {\
+ if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) \
+ return false; \
+} while (0)
+
+static bool trans_flw(DisasContext *ctx, arg_flw *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
+ /* RISC-V requires NaN-boxing of narrower width floating point values */
+ tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+ return true;
+}
+
+static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FMOV */
+ tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ } else { /* FSGNJ */
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
+ 0, 31);
+ }
+ return true;
+}
+
+static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FNEG */
+ tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FABS */
+ tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN);
+ tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ return true;
+}
+
+static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
+{
+ /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+
+#if defined(TARGET_RISCV64)
+ tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
+#else
+ tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
+#endif
+
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
+{
+ REQUIRE_FPU;
+ TCGv t0 = tcg_temp_new();
+ gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
+{
+ REQUIRE_FPU;
+ TCGv t0 = tcg_temp_new();
+ gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
+{
+ REQUIRE_FPU;
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+
+ gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
+
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
+{
+ /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+#if defined(TARGET_RISCV64)
+ tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
+#else
+ tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
+#endif
+
+ tcg_temp_free(t0);
+
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 944836dd7c..933ca9fb69 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1514,6 +1514,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
#include "insn_trans/trans_rva.inc.c"
+#include "insn_trans/trans_rvf.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32-64.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 54 +++++++++++++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 0bee95c984..6319f872ac 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index b101593ac4..b667c576d4 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -332,3 +332,57 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
return true;
}
+
+#ifdef TARGET_RISCV64
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+ return true;
+}
+#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32-64.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 54 +++++++++++++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 0bee95c984..6319f872ac 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index b101593ac4..b667c576d4 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -332,3 +332,57 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
return true;
}
+
+#ifdef TARGET_RISCV64
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+ return true;
+}
+#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 28 +++
target/riscv/insn_trans/trans_rvd.inc.c | 315 ++++++++++++++++++++++++
target/riscv/translate.c | 1 +
3 files changed, 344 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e40836bf03..e64b2b5e34 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -154,3 +154,31 @@ fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
+
+# *** RV32D Standard Extension ***
+fld ............ ..... 011 ..... 0000111 @i
+fsd ....... ..... ..... 011 ..... 0100111 @s
+fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
+fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
+fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
+fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
+fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
+fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
+fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
+fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
+fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
+fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
+fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
+fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
+fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
+fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
+fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
+fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
+feq_d 1010001 ..... ..... 010 ..... 1010011 @r
+flt_d 1010001 ..... ..... 001 ..... 1010011 @r
+fle_d 1010001 ..... ..... 000 ..... 1010011 @r
+fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
+fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
+fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
new file mode 100644
index 0000000000..a7e2335ffa
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -0,0 +1,315 @@
+/*
+ * RISC-V translation routines for the RV64D Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_fld(DisasContext *ctx, arg_fld *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ return true;
+}
+
+static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
+{
+ if (a->rs1 == a->rs2) { /* FMOV */
+ tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ } else {
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2],
+ cpu_fpr[a->rs1], 0, 63);
+ }
+ return true;
+}
+
+static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FNEG */
+ tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FABS */
+ tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN);
+ tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ return true;
+}
+
+static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ return true;
+}
+
+static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 933ca9fb69..7f3443db20 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1515,6 +1515,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rvm.inc.c"
#include "insn_trans/trans_rva.inc.c"
#include "insn_trans/trans_rvf.inc.c"
+#include "insn_trans/trans_rvd.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 28 +++
target/riscv/insn_trans/trans_rvd.inc.c | 315 ++++++++++++++++++++++++
target/riscv/translate.c | 1 +
3 files changed, 344 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e40836bf03..e64b2b5e34 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -154,3 +154,31 @@ fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
+
+# *** RV32D Standard Extension ***
+fld ............ ..... 011 ..... 0000111 @i
+fsd ....... ..... ..... 011 ..... 0100111 @s
+fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
+fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
+fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
+fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
+fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
+fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
+fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
+fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
+fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
+fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
+fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
+fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
+fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
+fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
+fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
+fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
+feq_d 1010001 ..... ..... 010 ..... 1010011 @r
+flt_d 1010001 ..... ..... 001 ..... 1010011 @r
+fle_d 1010001 ..... ..... 000 ..... 1010011 @r
+fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
+fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
+fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
new file mode 100644
index 0000000000..a7e2335ffa
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -0,0 +1,315 @@
+/*
+ * RISC-V translation routines for the RV64D Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_fld(DisasContext *ctx, arg_fld *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
+{
+ REQUIRE_FPU;
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ return true;
+}
+
+static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ return true;
+}
+
+static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
+{
+ if (a->rs1 == a->rs2) { /* FMOV */
+ tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ } else {
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2],
+ cpu_fpr[a->rs1], 0, 63);
+ }
+ return true;
+}
+
+static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FNEG */
+ tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
+{
+ REQUIRE_FPU;
+ if (a->rs1 == a->rs2) { /* FABS */
+ tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN);
+ tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
+ tcg_temp_free_i64(t0);
+ }
+ return true;
+}
+
+static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ return true;
+}
+
+static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ return true;
+}
+
+static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ return true;
+}
+
+static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 933ca9fb69..7f3443db20 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1515,6 +1515,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rvm.inc.c"
#include "insn_trans/trans_rva.inc.c"
#include "insn_trans/trans_rvf.inc.c"
+#include "insn_trans/trans_rvd.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32-64.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 73 ++++
target/riscv/translate.c | 487 +-----------------------
3 files changed, 82 insertions(+), 486 deletions(-)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 6319f872ac..380bf791bc 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -62,3 +62,11 @@ fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** RV64D Standard Extension (in addition to RV32D) ***
+fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
+fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
index a7e2335ffa..2e45c8ed7e 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -313,3 +313,76 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
return true;
}
+
+#ifdef TARGET_RISCV64
+
+static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
+ return true;
+}
+
+static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
+ tcg_temp_free(t0);
+ return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7f3443db20..4dda78d7c1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -180,44 +180,6 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(rh);
}
-static void gen_fsgnj(DisasContext *ctx, uint32_t rd, uint32_t rs1,
- uint32_t rs2, int rm, uint64_t min)
-{
- switch (rm) {
- case 0: /* fsgnj */
- if (rs1 == rs2) { /* FMOV */
- tcg_gen_mov_i64(cpu_fpr[rd], cpu_fpr[rs1]);
- } else {
- tcg_gen_deposit_i64(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1],
- 0, min == INT32_MIN ? 31 : 63);
- }
- break;
- case 1: /* fsgnjn */
- if (rs1 == rs2) { /* FNEG */
- tcg_gen_xori_i64(cpu_fpr[rd], cpu_fpr[rs1], min);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_not_i64(t0, cpu_fpr[rs2]);
- tcg_gen_deposit_i64(cpu_fpr[rd], t0, cpu_fpr[rs1],
- 0, min == INT32_MIN ? 31 : 63);
- tcg_temp_free_i64(t0);
- }
- break;
- case 2: /* fsgnjx */
- if (rs1 == rs2) { /* FABS */
- tcg_gen_andi_i64(cpu_fpr[rd], cpu_fpr[rs1], ~min);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_andi_i64(t0, cpu_fpr[rs2], min);
- tcg_gen_xor_i64(cpu_fpr[rd], cpu_fpr[rs1], t0);
- tcg_temp_free_i64(t0);
- }
- break;
- default:
- gen_exception_illegal(ctx);
- }
-}
-
static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
int rs2)
{
@@ -724,421 +686,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FMADD_S:
- gen_set_rm(ctx, rm);
- gen_helper_fmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FMADD_D:
- gen_set_rm(ctx, rm);
- gen_helper_fmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FMSUB_S:
- gen_set_rm(ctx, rm);
- gen_helper_fmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FMSUB_D:
- gen_set_rm(ctx, rm);
- gen_helper_fmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FNMSUB_S:
- gen_set_rm(ctx, rm);
- gen_helper_fnmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FNMSUB_D:
- gen_set_rm(ctx, rm);
- gen_helper_fnmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FNMADD_S:
- gen_set_rm(ctx, rm);
- gen_helper_fnmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FNMADD_D:
- gen_set_rm(ctx, rm);
- gen_helper_fnmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rm)
-{
- TCGv t0 = NULL;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- goto do_illegal;
- }
-
- switch (opc) {
- case OPC_RISC_FADD_S:
- gen_set_rm(ctx, rm);
- gen_helper_fadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSUB_S:
- gen_set_rm(ctx, rm);
- gen_helper_fsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FMUL_S:
- gen_set_rm(ctx, rm);
- gen_helper_fmul_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FDIV_S:
- gen_set_rm(ctx, rm);
- gen_helper_fdiv_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSQRT_S:
- gen_set_rm(ctx, rm);
- gen_helper_fsqrt_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- case OPC_RISC_FSGNJ_S:
- gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN);
- break;
-
- case OPC_RISC_FMIN_S:
- /* also handles: OPC_RISC_FMAX_S */
- switch (rm) {
- case 0x0:
- gen_helper_fmin_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x1:
- gen_helper_fmax_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FEQ_S:
- /* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */
- t0 = tcg_temp_new();
- switch (rm) {
- case 0x0:
- gen_helper_fle_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x1:
- gen_helper_flt_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x2:
- gen_helper_feq_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_W_S:
- /* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S */
- t0 = tcg_temp_new();
- switch (rs2) {
- case 0: /* FCVT_W_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 1: /* FCVT_WU_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#if defined(TARGET_RISCV64)
- case 2: /* FCVT_L_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 3: /* FCVT_LU_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#endif
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_S_W:
- /* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU */
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- switch (rs2) {
- case 0: /* FCVT_S_W */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_w(cpu_fpr[rd], cpu_env, t0);
- break;
- case 1: /* FCVT_S_WU */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_wu(cpu_fpr[rd], cpu_env, t0);
- break;
-#if defined(TARGET_RISCV64)
- case 2: /* FCVT_S_L */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_l(cpu_fpr[rd], cpu_env, t0);
- break;
- case 3: /* FCVT_S_LU */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_lu(cpu_fpr[rd], cpu_env, t0);
- break;
-#endif
- default:
- goto do_illegal;
- }
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_X_S:
- /* also OPC_RISC_FCLASS_S */
- t0 = tcg_temp_new();
- switch (rm) {
- case 0: /* FMV */
-#if defined(TARGET_RISCV64)
- tcg_gen_ext32s_tl(t0, cpu_fpr[rs1]);
-#else
- tcg_gen_extrl_i64_i32(t0, cpu_fpr[rs1]);
-#endif
- break;
- case 1:
- gen_helper_fclass_s(t0, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_S_X:
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
-#if defined(TARGET_RISCV64)
- tcg_gen_mov_i64(cpu_fpr[rd], t0);
-#else
- tcg_gen_extu_i32_i64(cpu_fpr[rd], t0);
-#endif
- tcg_temp_free(t0);
- break;
-
- /* double */
- case OPC_RISC_FADD_D:
- gen_set_rm(ctx, rm);
- gen_helper_fadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSUB_D:
- gen_set_rm(ctx, rm);
- gen_helper_fsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FMUL_D:
- gen_set_rm(ctx, rm);
- gen_helper_fmul_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FDIV_D:
- gen_set_rm(ctx, rm);
- gen_helper_fdiv_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSQRT_D:
- gen_set_rm(ctx, rm);
- gen_helper_fsqrt_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- case OPC_RISC_FSGNJ_D:
- gen_fsgnj(ctx, rd, rs1, rs2, rm, INT64_MIN);
- break;
-
- case OPC_RISC_FMIN_D:
- /* also OPC_RISC_FMAX_D */
- switch (rm) {
- case 0:
- gen_helper_fmin_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 1:
- gen_helper_fmax_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FCVT_S_D:
- switch (rs2) {
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FCVT_D_S:
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FEQ_D:
- /* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */
- t0 = tcg_temp_new();
- switch (rm) {
- case 0:
- gen_helper_fle_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 1:
- gen_helper_flt_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 2:
- gen_helper_feq_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_W_D:
- /* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D */
- t0 = tcg_temp_new();
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#if defined(TARGET_RISCV64)
- case 2:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 3:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#endif
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_D_W:
- /* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU */
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_w(cpu_fpr[rd], cpu_env, t0);
- break;
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_wu(cpu_fpr[rd], cpu_env, t0);
- break;
-#if defined(TARGET_RISCV64)
- case 2:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_l(cpu_fpr[rd], cpu_env, t0);
- break;
- case 3:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_lu(cpu_fpr[rd], cpu_env, t0);
- break;
-#endif
- default:
- goto do_illegal;
- }
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_X_D:
- /* also OPC_RISC_FCLASS_D */
- switch (rm) {
-#if defined(TARGET_RISCV64)
- case 0: /* FMV */
- gen_set_gpr(rd, cpu_fpr[rs1]);
- break;
-#endif
- case 1:
- t0 = tcg_temp_new();
- gen_helper_fclass_d(t0, cpu_fpr[rs1]);
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
- default:
- goto do_illegal;
- }
- break;
-
-#if defined(TARGET_RISCV64)
- case OPC_RISC_FMV_D_X:
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_mov_tl(cpu_fpr[rd], t0);
- tcg_temp_free(t0);
- break;
-#endif
-
- default:
- do_illegal:
- if (t0) {
- tcg_temp_free(t0);
- }
- gen_exception_illegal(ctx);
- break;
- }
-}
-
static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs1, int csr)
{
@@ -1519,11 +1066,8 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
- int rs1;
- int rs2;
- int rd;
+ int rs1, rd;
uint32_t op;
- target_long imm;
/* We do not do misaligned address check here: the address should never be
* misaligned at this point. Instructions that set PC must do the check,
@@ -1532,38 +1076,9 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
op = MASK_OP_MAJOR(ctx->opcode);
rs1 = GET_RS1(ctx->opcode);
- rs2 = GET_RS2(ctx->opcode);
rd = GET_RD(ctx->opcode);
- imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_FP_LOAD:
- gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_FP_STORE:
- gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2,
- GET_STORE_IMM(ctx->opcode));
- break;
- case OPC_RISC_FMADD:
- gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FMSUB:
- gen_fp_fmsub(ctx, MASK_OP_FP_FMSUB(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FNMSUB:
- gen_fp_fnmsub(ctx, MASK_OP_FP_FNMSUB(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FNMADD:
- gen_fp_fnmadd(ctx, MASK_OP_FP_FNMADD(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FP_ARITH:
- gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
- GET_RM(ctx->opcode));
- break;
case OPC_RISC_SYSTEM:
gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 15/35] target/riscv: Convert RV64D insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32-64.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 73 ++++
target/riscv/translate.c | 487 +-----------------------
3 files changed, 82 insertions(+), 486 deletions(-)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 6319f872ac..380bf791bc 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -62,3 +62,11 @@ fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** RV64D Standard Extension (in addition to RV32D) ***
+fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
+fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
index a7e2335ffa..2e45c8ed7e 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -313,3 +313,76 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
return true;
}
+
+#ifdef TARGET_RISCV64
+
+static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
+{
+ REQUIRE_FPU;
+
+ gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
+ return true;
+}
+
+static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
+{
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
+ tcg_temp_free(t0);
+ return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7f3443db20..4dda78d7c1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -180,44 +180,6 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(rh);
}
-static void gen_fsgnj(DisasContext *ctx, uint32_t rd, uint32_t rs1,
- uint32_t rs2, int rm, uint64_t min)
-{
- switch (rm) {
- case 0: /* fsgnj */
- if (rs1 == rs2) { /* FMOV */
- tcg_gen_mov_i64(cpu_fpr[rd], cpu_fpr[rs1]);
- } else {
- tcg_gen_deposit_i64(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1],
- 0, min == INT32_MIN ? 31 : 63);
- }
- break;
- case 1: /* fsgnjn */
- if (rs1 == rs2) { /* FNEG */
- tcg_gen_xori_i64(cpu_fpr[rd], cpu_fpr[rs1], min);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_not_i64(t0, cpu_fpr[rs2]);
- tcg_gen_deposit_i64(cpu_fpr[rd], t0, cpu_fpr[rs1],
- 0, min == INT32_MIN ? 31 : 63);
- tcg_temp_free_i64(t0);
- }
- break;
- case 2: /* fsgnjx */
- if (rs1 == rs2) { /* FABS */
- tcg_gen_andi_i64(cpu_fpr[rd], cpu_fpr[rs1], ~min);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_andi_i64(t0, cpu_fpr[rs2], min);
- tcg_gen_xor_i64(cpu_fpr[rd], cpu_fpr[rs1], t0);
- tcg_temp_free_i64(t0);
- }
- break;
- default:
- gen_exception_illegal(ctx);
- }
-}
-
static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
int rs2)
{
@@ -724,421 +686,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FMADD_S:
- gen_set_rm(ctx, rm);
- gen_helper_fmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FMADD_D:
- gen_set_rm(ctx, rm);
- gen_helper_fmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FMSUB_S:
- gen_set_rm(ctx, rm);
- gen_helper_fmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FMSUB_D:
- gen_set_rm(ctx, rm);
- gen_helper_fmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FNMSUB_S:
- gen_set_rm(ctx, rm);
- gen_helper_fnmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FNMSUB_D:
- gen_set_rm(ctx, rm);
- gen_helper_fnmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FNMADD_S:
- gen_set_rm(ctx, rm);
- gen_helper_fnmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FNMADD_D:
- gen_set_rm(ctx, rm);
- gen_helper_fnmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rm)
-{
- TCGv t0 = NULL;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- goto do_illegal;
- }
-
- switch (opc) {
- case OPC_RISC_FADD_S:
- gen_set_rm(ctx, rm);
- gen_helper_fadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSUB_S:
- gen_set_rm(ctx, rm);
- gen_helper_fsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FMUL_S:
- gen_set_rm(ctx, rm);
- gen_helper_fmul_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FDIV_S:
- gen_set_rm(ctx, rm);
- gen_helper_fdiv_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSQRT_S:
- gen_set_rm(ctx, rm);
- gen_helper_fsqrt_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- case OPC_RISC_FSGNJ_S:
- gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN);
- break;
-
- case OPC_RISC_FMIN_S:
- /* also handles: OPC_RISC_FMAX_S */
- switch (rm) {
- case 0x0:
- gen_helper_fmin_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x1:
- gen_helper_fmax_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FEQ_S:
- /* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */
- t0 = tcg_temp_new();
- switch (rm) {
- case 0x0:
- gen_helper_fle_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x1:
- gen_helper_flt_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x2:
- gen_helper_feq_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_W_S:
- /* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S */
- t0 = tcg_temp_new();
- switch (rs2) {
- case 0: /* FCVT_W_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 1: /* FCVT_WU_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#if defined(TARGET_RISCV64)
- case 2: /* FCVT_L_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 3: /* FCVT_LU_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#endif
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_S_W:
- /* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU */
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- switch (rs2) {
- case 0: /* FCVT_S_W */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_w(cpu_fpr[rd], cpu_env, t0);
- break;
- case 1: /* FCVT_S_WU */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_wu(cpu_fpr[rd], cpu_env, t0);
- break;
-#if defined(TARGET_RISCV64)
- case 2: /* FCVT_S_L */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_l(cpu_fpr[rd], cpu_env, t0);
- break;
- case 3: /* FCVT_S_LU */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_lu(cpu_fpr[rd], cpu_env, t0);
- break;
-#endif
- default:
- goto do_illegal;
- }
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_X_S:
- /* also OPC_RISC_FCLASS_S */
- t0 = tcg_temp_new();
- switch (rm) {
- case 0: /* FMV */
-#if defined(TARGET_RISCV64)
- tcg_gen_ext32s_tl(t0, cpu_fpr[rs1]);
-#else
- tcg_gen_extrl_i64_i32(t0, cpu_fpr[rs1]);
-#endif
- break;
- case 1:
- gen_helper_fclass_s(t0, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_S_X:
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
-#if defined(TARGET_RISCV64)
- tcg_gen_mov_i64(cpu_fpr[rd], t0);
-#else
- tcg_gen_extu_i32_i64(cpu_fpr[rd], t0);
-#endif
- tcg_temp_free(t0);
- break;
-
- /* double */
- case OPC_RISC_FADD_D:
- gen_set_rm(ctx, rm);
- gen_helper_fadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSUB_D:
- gen_set_rm(ctx, rm);
- gen_helper_fsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FMUL_D:
- gen_set_rm(ctx, rm);
- gen_helper_fmul_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FDIV_D:
- gen_set_rm(ctx, rm);
- gen_helper_fdiv_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSQRT_D:
- gen_set_rm(ctx, rm);
- gen_helper_fsqrt_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- case OPC_RISC_FSGNJ_D:
- gen_fsgnj(ctx, rd, rs1, rs2, rm, INT64_MIN);
- break;
-
- case OPC_RISC_FMIN_D:
- /* also OPC_RISC_FMAX_D */
- switch (rm) {
- case 0:
- gen_helper_fmin_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 1:
- gen_helper_fmax_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FCVT_S_D:
- switch (rs2) {
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FCVT_D_S:
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FEQ_D:
- /* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */
- t0 = tcg_temp_new();
- switch (rm) {
- case 0:
- gen_helper_fle_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 1:
- gen_helper_flt_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 2:
- gen_helper_feq_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_W_D:
- /* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D */
- t0 = tcg_temp_new();
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#if defined(TARGET_RISCV64)
- case 2:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 3:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#endif
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FCVT_D_W:
- /* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU */
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_w(cpu_fpr[rd], cpu_env, t0);
- break;
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_wu(cpu_fpr[rd], cpu_env, t0);
- break;
-#if defined(TARGET_RISCV64)
- case 2:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_l(cpu_fpr[rd], cpu_env, t0);
- break;
- case 3:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_lu(cpu_fpr[rd], cpu_env, t0);
- break;
-#endif
- default:
- goto do_illegal;
- }
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_X_D:
- /* also OPC_RISC_FCLASS_D */
- switch (rm) {
-#if defined(TARGET_RISCV64)
- case 0: /* FMV */
- gen_set_gpr(rd, cpu_fpr[rs1]);
- break;
-#endif
- case 1:
- t0 = tcg_temp_new();
- gen_helper_fclass_d(t0, cpu_fpr[rs1]);
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
- default:
- goto do_illegal;
- }
- break;
-
-#if defined(TARGET_RISCV64)
- case OPC_RISC_FMV_D_X:
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_mov_tl(cpu_fpr[rd], t0);
- tcg_temp_free(t0);
- break;
-#endif
-
- default:
- do_illegal:
- if (t0) {
- tcg_temp_free(t0);
- }
- gen_exception_illegal(ctx);
- break;
- }
-}
-
static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs1, int csr)
{
@@ -1519,11 +1066,8 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
- int rs1;
- int rs2;
- int rd;
+ int rs1, rd;
uint32_t op;
- target_long imm;
/* We do not do misaligned address check here: the address should never be
* misaligned at this point. Instructions that set PC must do the check,
@@ -1532,38 +1076,9 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
op = MASK_OP_MAJOR(ctx->opcode);
rs1 = GET_RS1(ctx->opcode);
- rs2 = GET_RS2(ctx->opcode);
rd = GET_RD(ctx->opcode);
- imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_FP_LOAD:
- gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_FP_STORE:
- gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2,
- GET_STORE_IMM(ctx->opcode));
- break;
- case OPC_RISC_FMADD:
- gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FMSUB:
- gen_fp_fmsub(ctx, MASK_OP_FP_FMSUB(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FNMSUB:
- gen_fp_fnmsub(ctx, MASK_OP_FP_FNMSUB(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FNMADD:
- gen_fp_fnmadd(ctx, MASK_OP_FP_FNMADD(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FP_ARITH:
- gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
- GET_RM(ctx->opcode));
- break;
case OPC_RISC_SYSTEM:
gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 15 +++
.../riscv/insn_trans/trans_privileged.inc.c | 110 ++++++++++++++++++
target/riscv/translate.c | 57 +--------
3 files changed, 126 insertions(+), 56 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e64b2b5e34..ecc46a50cc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -57,6 +57,21 @@
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
+@sfence_vm ....... ..... ..... ... ..... ....... %rs1
+
+
+# *** Privileged Instructions ***
+ecall 000000000000 00000 000 00000 1110011
+ebreak 000000000001 00000 000 00000 1110011
+uret 0000000 00010 00000 000 00000 1110011
+sret 0001000 00010 00000 000 00000 1110011
+hret 0010000 00010 00000 000 00000 1110011
+mret 0011000 00010 00000 000 00000 1110011
+wfi 0001000 00101 00000 000 00000 1110011
+sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
new file mode 100644
index 0000000000..fb2da8f5f0
--- /dev/null
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -0,0 +1,110 @@
+/*
+ * RISC-V translation routines for the RISC-V privileged instructions.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
+{
+ /* always generates U-level ECALL, fixed in do_interrupt handler */
+ generate_exception(ctx, RISCV_EXCP_U_ECALL);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+{
+ generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_uret(DisasContext *ctx, arg_uret *a)
+{
+ return false;
+}
+
+static bool trans_sret(DisasContext *ctx, arg_sret *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+
+ if (riscv_has_ext(ctx->env, RVS)) {
+ gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ } else {
+ return false;
+ }
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hret(DisasContext *ctx, arg_hret *a)
+{
+ return false;
+}
+
+static bool trans_mret(DisasContext *ctx, arg_mret *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ gen_helper_wfi(cpu_env);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->env->priv_ver == PRIV_VERSION_1_10_0) {
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ }
+#endif
+ return false;
+}
+
+static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->env->priv_ver <= PRIV_VERSION_1_09_1) {
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ }
+#endif
+ return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4dda78d7c1..ff15e0f7ed 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -689,26 +689,8 @@ static void gen_set_rm(DisasContext *ctx, int rm)
static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs1, int csr)
{
- TCGv source1, dest;
- source1 = tcg_temp_new();
- dest = tcg_temp_new();
- gen_get_gpr(source1, rs1);
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-#ifndef CONFIG_USER_ONLY
- /* Extract funct7 value and check whether it matches SFENCE.VMA */
- if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
- if (env->priv_ver == PRIV_VERSION_1_10_0) {
- /* sfence.vma */
- /* TODO: handle ASID specific fences */
- gen_helper_tlb_flush(cpu_env);
- return;
- } else {
- gen_exception_illegal(ctx);
- }
- }
-#endif
-
switch (opc) {
case OPC_RISC_ECALL:
switch (csr) {
@@ -723,50 +705,12 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
break;
-#ifndef CONFIG_USER_ONLY
- case 0x002: /* URET */
- gen_exception_illegal(ctx);
- break;
- case 0x102: /* SRET */
- if (riscv_has_ext(env, RVS)) {
- gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- } else {
- gen_exception_illegal(ctx);
- }
- break;
- case 0x202: /* HRET */
- gen_exception_illegal(ctx);
- break;
- case 0x302: /* MRET */
- gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x7b2: /* DRET */
- gen_exception_illegal(ctx);
- break;
- case 0x105: /* WFI */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- gen_helper_wfi(cpu_env);
- break;
- case 0x104: /* SFENCE.VM */
- if (env->priv_ver <= PRIV_VERSION_1_09_1) {
- gen_helper_tlb_flush(cpu_env);
- } else {
- gen_exception_illegal(ctx);
- }
- break;
-#endif
default:
gen_exception_illegal(ctx);
break;
}
break;
}
- tcg_temp_free(source1);
- tcg_temp_free(dest);
}
static void decode_RV32_64C0(DisasContext *ctx)
@@ -1063,6 +1007,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rva.inc.c"
#include "insn_trans/trans_rvf.inc.c"
#include "insn_trans/trans_rvd.inc.c"
+#include "insn_trans/trans_privileged.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 16/35] target/riscv: Convert RV priv insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 15 +++
.../riscv/insn_trans/trans_privileged.inc.c | 110 ++++++++++++++++++
target/riscv/translate.c | 57 +--------
3 files changed, 126 insertions(+), 56 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e64b2b5e34..ecc46a50cc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -57,6 +57,21 @@
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
+@sfence_vm ....... ..... ..... ... ..... ....... %rs1
+
+
+# *** Privileged Instructions ***
+ecall 000000000000 00000 000 00000 1110011
+ebreak 000000000001 00000 000 00000 1110011
+uret 0000000 00010 00000 000 00000 1110011
+sret 0001000 00010 00000 000 00000 1110011
+hret 0010000 00010 00000 000 00000 1110011
+mret 0011000 00010 00000 000 00000 1110011
+wfi 0001000 00101 00000 000 00000 1110011
+sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
+
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
new file mode 100644
index 0000000000..fb2da8f5f0
--- /dev/null
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -0,0 +1,110 @@
+/*
+ * RISC-V translation routines for the RISC-V privileged instructions.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
+{
+ /* always generates U-level ECALL, fixed in do_interrupt handler */
+ generate_exception(ctx, RISCV_EXCP_U_ECALL);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+{
+ generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_uret(DisasContext *ctx, arg_uret *a)
+{
+ return false;
+}
+
+static bool trans_sret(DisasContext *ctx, arg_sret *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+
+ if (riscv_has_ext(ctx->env, RVS)) {
+ gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ } else {
+ return false;
+ }
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hret(DisasContext *ctx, arg_hret *a)
+{
+ return false;
+}
+
+static bool trans_mret(DisasContext *ctx, arg_mret *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ gen_helper_wfi(cpu_env);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->env->priv_ver == PRIV_VERSION_1_10_0) {
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ }
+#endif
+ return false;
+}
+
+static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->env->priv_ver <= PRIV_VERSION_1_09_1) {
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ }
+#endif
+ return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4dda78d7c1..ff15e0f7ed 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -689,26 +689,8 @@ static void gen_set_rm(DisasContext *ctx, int rm)
static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs1, int csr)
{
- TCGv source1, dest;
- source1 = tcg_temp_new();
- dest = tcg_temp_new();
- gen_get_gpr(source1, rs1);
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-#ifndef CONFIG_USER_ONLY
- /* Extract funct7 value and check whether it matches SFENCE.VMA */
- if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
- if (env->priv_ver == PRIV_VERSION_1_10_0) {
- /* sfence.vma */
- /* TODO: handle ASID specific fences */
- gen_helper_tlb_flush(cpu_env);
- return;
- } else {
- gen_exception_illegal(ctx);
- }
- }
-#endif
-
switch (opc) {
case OPC_RISC_ECALL:
switch (csr) {
@@ -723,50 +705,12 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
break;
-#ifndef CONFIG_USER_ONLY
- case 0x002: /* URET */
- gen_exception_illegal(ctx);
- break;
- case 0x102: /* SRET */
- if (riscv_has_ext(env, RVS)) {
- gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- } else {
- gen_exception_illegal(ctx);
- }
- break;
- case 0x202: /* HRET */
- gen_exception_illegal(ctx);
- break;
- case 0x302: /* MRET */
- gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x7b2: /* DRET */
- gen_exception_illegal(ctx);
- break;
- case 0x105: /* WFI */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- gen_helper_wfi(cpu_env);
- break;
- case 0x104: /* SFENCE.VM */
- if (env->priv_ver <= PRIV_VERSION_1_09_1) {
- gen_helper_tlb_flush(cpu_env);
- } else {
- gen_exception_illegal(ctx);
- }
- break;
-#endif
default:
gen_exception_illegal(ctx);
break;
}
break;
}
- tcg_temp_free(source1);
- tcg_temp_free(dest);
}
static void decode_RV32_64C0(DisasContext *ctx)
@@ -1063,6 +1007,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rva.inc.c"
#include "insn_trans/trans_rvf.inc.c"
#include "insn_trans/trans_rvd.inc.c"
+#include "insn_trans/trans_privileged.inc.c"
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode | 55 ++++++++++++++++++
target/riscv/insn_trans/trans_rvc.inc.c | 75 +++++++++++++++++++++++++
target/riscv/translate.c | 53 ++++++-----------
4 files changed, 154 insertions(+), 38 deletions(-)
create mode 100644 target/riscv/insn16.decode
create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 05087a91bb..9c6c109327 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -10,4 +10,11 @@ target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
"GEN", $(TARGET_DIR)$@)
-target/riscv/translate.o: target/riscv/decode_insn32.inc.c
+target/riscv/decode_insn16.inc.c: \
+ $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+ $(call quiet-command, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
+ "GEN", $(TARGET_DIR)$@)
+
+target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
+ target/riscv/decode_insn16.inc.c
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
new file mode 100644
index 0000000000..558c0c41f0
--- /dev/null
+++ b/target/riscv/insn16.decode
@@ -0,0 +1,55 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Fields:
+%rd 7:5
+%rs1_3 7:3 !function=ex_rvc_register
+%rs2_3 2:3 !function=ex_rvc_register
+
+# Immediates:
+%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2
+%uimm_cl_d 5:2 10:3 !function=ex_shift_3
+%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
+
+
+# Argument sets:
+&cl rs1 rd
+&cl_dw uimm rs1 rd
+&ciw nzuimm rd
+&cs rs1 rs2
+&cs_dw uimm rs1 rs2
+
+
+# Formats 16:
+@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
+@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
+@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
+@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
+@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
+@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
+@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
+
+
+# *** RV64C Standard Extension (Quadrant 0) ***
+c_addi4spn 000 ........ ... 00 @ciw
+c_fld 001 ... ... .. ... 00 @cl_d
+c_lw 010 ... ... .. ... 00 @cl_w
+c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
+c_fsd 101 ... ... .. ... 00 @cs_d
+c_sw 110 ... ... .. ... 00 @cs_w
+c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
new file mode 100644
index 0000000000..93ec8aa30b
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -0,0 +1,75 @@
+/*
+ * RISC-V translation routines for the RVC Compressed Instruction Set.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
+{
+ if (a->nzuimm == 0) {
+ /* Reserved in ISA */
+ return false;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm };
+ return trans_addi(ctx, &arg);
+}
+
+static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
+{
+ arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
+ return trans_fld(ctx, &arg);
+}
+
+static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
+{
+ arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
+ return trans_lw(ctx, &arg);
+}
+
+static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FLW ( RV32FC-only ) */
+ return false;
+#else
+ /* C.LD ( RV64C/RV128C-only ) */
+ return false;
+#endif
+}
+
+static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
+{
+ arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_fsd(ctx, &arg);
+}
+
+static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
+{
+ arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_sw(ctx, &arg);
+}
+
+static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FSW ( RV32FC-only ) */
+ return false;
+#else
+ /* C.SD ( RV64C/RV128C-only ) */
+ return false;
+#endif
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ff15e0f7ed..1ee13c1907 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -720,27 +720,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
uint8_t rs1s = GET_C_RS1S(ctx->opcode);
switch (funct3) {
- case 0:
- /* illegal */
- if (ctx->opcode == 0) {
- gen_exception_illegal(ctx);
- } else {
- /* C.ADDI4SPN -> addi rd', x2, zimm[9:2]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs2, 2,
- GET_C_ADDI4SPN_IMM(ctx->opcode));
- }
- break;
- case 1:
- /* C.FLD -> fld rd', offset[7:3](rs1')*/
- gen_fp_load(ctx, OPC_RISC_FLD, rd_rs2, rs1s,
- GET_C_LD_IMM(ctx->opcode));
- /* C.LQ(RV128) */
- break;
- case 2:
- /* C.LW -> lw rd', offset[6:2](rs1') */
- gen_load(ctx, OPC_RISC_LW, rd_rs2, rs1s,
- GET_C_LW_IMM(ctx->opcode));
- break;
case 3:
#if defined(TARGET_RISCV64)
/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
@@ -752,21 +731,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
GET_C_LW_IMM(ctx->opcode));
#endif
break;
- case 4:
- /* reserved */
- gen_exception_illegal(ctx);
- break;
- case 5:
- /* C.FSD(RV32/64) -> fsd rs2', offset[7:3](rs1') */
- gen_fp_store(ctx, OPC_RISC_FSD, rs1s, rd_rs2,
- GET_C_LD_IMM(ctx->opcode));
- /* C.SQ (RV128) */
- break;
- case 6:
- /* C.SW -> sw rs2', offset[6:2](rs1')*/
- gen_store(ctx, OPC_RISC_SW, rs1s, rd_rs2,
- GET_C_LW_IMM(ctx->opcode));
- break;
case 7:
#if defined(TARGET_RISCV64)
/* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
@@ -996,8 +960,15 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
return imm << amount; \
}
EX_SH(1)
+EX_SH(2)
+EX_SH(3)
EX_SH(12)
+static int ex_rvc_register(int reg)
+{
+ return 8 + reg;
+}
+
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
@@ -1009,6 +980,11 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rvd.inc.c"
#include "insn_trans/trans_privileged.inc.c"
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
+/* auto-generated decoder*/
+#include "decode_insn16.inc.c"
+#include "insn_trans/trans_rvc.inc.c"
+
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
int rs1, rd;
@@ -1042,7 +1018,10 @@ static void decode_opc(DisasContext *ctx)
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- decode_RV32_64C(ctx->env, ctx);
+ if (!decode_insn16(ctx, ctx->opcode)) {
+ /* fall back to old decoder */
+ decode_RV32_64C(ctx->env, ctx);
+ }
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode | 55 ++++++++++++++++++
target/riscv/insn_trans/trans_rvc.inc.c | 75 +++++++++++++++++++++++++
target/riscv/translate.c | 53 ++++++-----------
4 files changed, 154 insertions(+), 38 deletions(-)
create mode 100644 target/riscv/insn16.decode
create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 05087a91bb..9c6c109327 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -10,4 +10,11 @@ target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
"GEN", $(TARGET_DIR)$@)
-target/riscv/translate.o: target/riscv/decode_insn32.inc.c
+target/riscv/decode_insn16.inc.c: \
+ $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+ $(call quiet-command, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
+ "GEN", $(TARGET_DIR)$@)
+
+target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
+ target/riscv/decode_insn16.inc.c
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
new file mode 100644
index 0000000000..558c0c41f0
--- /dev/null
+++ b/target/riscv/insn16.decode
@@ -0,0 +1,55 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Fields:
+%rd 7:5
+%rs1_3 7:3 !function=ex_rvc_register
+%rs2_3 2:3 !function=ex_rvc_register
+
+# Immediates:
+%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2
+%uimm_cl_d 5:2 10:3 !function=ex_shift_3
+%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
+
+
+# Argument sets:
+&cl rs1 rd
+&cl_dw uimm rs1 rd
+&ciw nzuimm rd
+&cs rs1 rs2
+&cs_dw uimm rs1 rs2
+
+
+# Formats 16:
+@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
+@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
+@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
+@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
+@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
+@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
+@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
+
+
+# *** RV64C Standard Extension (Quadrant 0) ***
+c_addi4spn 000 ........ ... 00 @ciw
+c_fld 001 ... ... .. ... 00 @cl_d
+c_lw 010 ... ... .. ... 00 @cl_w
+c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
+c_fsd 101 ... ... .. ... 00 @cs_d
+c_sw 110 ... ... .. ... 00 @cs_w
+c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
new file mode 100644
index 0000000000..93ec8aa30b
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -0,0 +1,75 @@
+/*
+ * RISC-V translation routines for the RVC Compressed Instruction Set.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
+{
+ if (a->nzuimm == 0) {
+ /* Reserved in ISA */
+ return false;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm };
+ return trans_addi(ctx, &arg);
+}
+
+static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
+{
+ arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
+ return trans_fld(ctx, &arg);
+}
+
+static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
+{
+ arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
+ return trans_lw(ctx, &arg);
+}
+
+static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FLW ( RV32FC-only ) */
+ return false;
+#else
+ /* C.LD ( RV64C/RV128C-only ) */
+ return false;
+#endif
+}
+
+static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
+{
+ arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_fsd(ctx, &arg);
+}
+
+static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
+{
+ arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_sw(ctx, &arg);
+}
+
+static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FSW ( RV32FC-only ) */
+ return false;
+#else
+ /* C.SD ( RV64C/RV128C-only ) */
+ return false;
+#endif
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ff15e0f7ed..1ee13c1907 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -720,27 +720,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
uint8_t rs1s = GET_C_RS1S(ctx->opcode);
switch (funct3) {
- case 0:
- /* illegal */
- if (ctx->opcode == 0) {
- gen_exception_illegal(ctx);
- } else {
- /* C.ADDI4SPN -> addi rd', x2, zimm[9:2]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs2, 2,
- GET_C_ADDI4SPN_IMM(ctx->opcode));
- }
- break;
- case 1:
- /* C.FLD -> fld rd', offset[7:3](rs1')*/
- gen_fp_load(ctx, OPC_RISC_FLD, rd_rs2, rs1s,
- GET_C_LD_IMM(ctx->opcode));
- /* C.LQ(RV128) */
- break;
- case 2:
- /* C.LW -> lw rd', offset[6:2](rs1') */
- gen_load(ctx, OPC_RISC_LW, rd_rs2, rs1s,
- GET_C_LW_IMM(ctx->opcode));
- break;
case 3:
#if defined(TARGET_RISCV64)
/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
@@ -752,21 +731,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
GET_C_LW_IMM(ctx->opcode));
#endif
break;
- case 4:
- /* reserved */
- gen_exception_illegal(ctx);
- break;
- case 5:
- /* C.FSD(RV32/64) -> fsd rs2', offset[7:3](rs1') */
- gen_fp_store(ctx, OPC_RISC_FSD, rs1s, rd_rs2,
- GET_C_LD_IMM(ctx->opcode));
- /* C.SQ (RV128) */
- break;
- case 6:
- /* C.SW -> sw rs2', offset[6:2](rs1')*/
- gen_store(ctx, OPC_RISC_SW, rs1s, rd_rs2,
- GET_C_LW_IMM(ctx->opcode));
- break;
case 7:
#if defined(TARGET_RISCV64)
/* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
@@ -996,8 +960,15 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
return imm << amount; \
}
EX_SH(1)
+EX_SH(2)
+EX_SH(3)
EX_SH(12)
+static int ex_rvc_register(int reg)
+{
+ return 8 + reg;
+}
+
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
@@ -1009,6 +980,11 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rvd.inc.c"
#include "insn_trans/trans_privileged.inc.c"
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
+/* auto-generated decoder*/
+#include "decode_insn16.inc.c"
+#include "insn_trans/trans_rvc.inc.c"
+
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
int rs1, rd;
@@ -1042,7 +1018,10 @@ static void decode_opc(DisasContext *ctx)
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- decode_RV32_64C(ctx->env, ctx);
+ if (!decode_insn16(ctx, ctx->opcode)) {
+ /* fall back to old decoder */
+ decode_RV32_64C(ctx->env, ctx);
+ }
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn16.decode | 43 +++++++
target/riscv/insn_trans/trans_rvc.inc.c | 151 ++++++++++++++++++++++++
target/riscv/translate.c | 118 +-----------------
3 files changed, 195 insertions(+), 117 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 558c0c41f0..29dade0fa1 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -22,28 +22,53 @@
%rs2_3 2:3 !function=ex_rvc_register
# Immediates:
+%imm_ci 12:s1 2:5
%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2
%uimm_cl_d 5:2 10:3 !function=ex_shift_3
%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
+%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
+%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
+
+%nzuimm_6bit 12:1 2:5
+
+%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
+%imm_lui 12:s1 2:5 !function=ex_shift_12
+
# Argument sets:
&cl rs1 rd
&cl_dw uimm rs1 rd
+&ci imm rd
&ciw nzuimm rd
&cs rs1 rs2
&cs_dw uimm rs1 rs2
+&cb imm rs1
+&cr rd rs2
+&c_j imm
+&c_shift shamt rd
+
+&c_addi16sp_lui imm_lui imm_addi16sp rd
# Formats 16:
+@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
+@cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
+@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
+@cj ... ........... .. &c_j imm=%imm_cj
+@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp %rd
+
+@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
+
+@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
# *** RV64C Standard Extension (Quadrant 0) ***
c_addi4spn 000 ........ ... 00 @ciw
@@ -53,3 +78,21 @@ c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
c_fsd 101 ... ... .. ... 00 @cs_d
c_sw 110 ... ... .. ... 00 @cs_w
c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
+
+# *** RV64C Standard Extension (Quadrant 1) ***
+c_addi 000 . ..... ..... 01 @ci
+c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually
+c_li 010 . ..... ..... 01 @ci
+c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
+c_srli 100 . 00 ... ..... 01 @c_shift
+c_srai 100 . 01 ... ..... 01 @c_shift
+c_andi 100 . 10 ... ..... 01 @c_andi
+c_sub 100 0 11 ... 00 ... 01 @cs_2
+c_xor 100 0 11 ... 01 ... 01 @cs_2
+c_or 100 0 11 ... 10 ... 01 @cs_2
+c_and 100 0 11 ... 11 ... 01 @cs_2
+c_subw 100 1 11 ... 00 ... 01 @cs_2
+c_addw 100 1 11 ... 01 ... 01 @cs_2
+c_j 101 ........... 01 @cj
+c_beqz 110 ... ... ..... 01 @cb
+c_bnez 111 ... ... ..... 01 @cb
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index 93ec8aa30b..b06c435c98 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -73,3 +73,154 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
return false;
#endif
}
+
+static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
+{
+ if (a->imm == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_addi(ctx, &arg);
+}
+
+static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.JAL */
+ arg_jal arg = { .rd = 1, .imm = a->imm };
+ return trans_jal(ctx, &arg);
+#else
+ /* C.ADDIW */
+ arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_addiw(ctx, &arg);
+#endif
+}
+
+static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
+{
+ if (a->rd == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm };
+ return trans_addi(ctx, &arg);
+}
+
+static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
+{
+ if (a->rd == 2) {
+ /* C.ADDI16SP */
+ arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp };
+ return trans_addi(ctx, &arg);
+ } else if (a->imm_lui != 0) {
+ /* C.LUI */
+ if (a->rd == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_lui arg = { .rd = a->rd, .imm = a->imm_lui };
+ return trans_lui(ctx, &arg);
+ }
+ return false;
+}
+
+static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a)
+{
+ int shamt = a->shamt;
+ if (shamt == 0) {
+ /* For RV128 a shamt of 0 means a shift by 64 */
+ shamt = 64;
+ }
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_srli(ctx, &arg);
+}
+
+static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
+{
+ int shamt = a->shamt;
+ if (shamt == 0) {
+ /* For RV128 a shamt of 0 means a shift by 64 */
+ shamt = 64;
+ }
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_srai(ctx, &arg);
+}
+
+static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
+{
+ arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_andi(ctx, &arg);
+}
+
+static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
+{
+ arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_sub(ctx, &arg);
+}
+
+static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
+{
+ arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_xor(ctx, &arg);
+}
+
+static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
+{
+ arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_or(ctx, &arg);
+}
+
+static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
+{
+ arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_and(ctx, &arg);
+}
+
+static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
+{
+#ifdef TARGET_RISCV64
+ arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_subw(ctx, &arg);
+#else
+ return false;
+#endif
+}
+
+static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
+{
+#ifdef TARGET_RISCV64
+ arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_addw(ctx, &arg);
+#else
+ return false;
+#endif
+}
+
+static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
+{
+ arg_jal arg = { .rd = 0, .imm = a->imm };
+ return trans_jal(ctx, &arg);
+}
+
+static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
+{
+ arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
+ return trans_beq(ctx, &arg);
+}
+
+static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
+{
+ arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
+ return trans_bne(ctx, &arg);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1ee13c1907..498fbc20ef 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -745,120 +745,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
}
}
-static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
-{
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
- uint8_t rd_rs1 = GET_C_RS1(ctx->opcode);
- uint8_t rs1s, rs2s;
- uint8_t funct2;
-
- switch (funct3) {
- case 0:
- /* C.ADDI -> addi rd, rd, nzimm[5:0] */
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, rd_rs1,
- GET_C_IMM(ctx->opcode));
- break;
- case 1:
-#if defined(TARGET_RISCV64)
- /* C.ADDIW (RV64/128) -> addiw rd, rd, imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ADDIW, rd_rs1, rd_rs1,
- GET_C_IMM(ctx->opcode));
-#else
- /* C.JAL(RV32) -> jal x1, offset[11:1] */
- gen_jal(env, ctx, 1, GET_C_J_IMM(ctx->opcode));
-#endif
- break;
- case 2:
- /* C.LI -> addi rd, x0, imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, 0, GET_C_IMM(ctx->opcode));
- break;
- case 3:
- if (rd_rs1 == 2) {
- /* C.ADDI16SP -> addi x2, x2, nzimm[9:4]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, 2, 2,
- GET_C_ADDI16SP_IMM(ctx->opcode));
- } else if (rd_rs1 != 0) {
- /* C.LUI (rs1/rd =/= {0,2}) -> lui rd, nzimm[17:12]*/
- tcg_gen_movi_tl(cpu_gpr[rd_rs1],
- GET_C_IMM(ctx->opcode) << 12);
- }
- break;
- case 4:
- funct2 = extract32(ctx->opcode, 10, 2);
- rs1s = GET_C_RS1S(ctx->opcode);
- switch (funct2) {
- case 0: /* C.SRLI(RV32) -> srli rd', rd', shamt[5:0] */
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s,
- GET_C_ZIMM(ctx->opcode));
- /* C.SRLI64(RV128) */
- break;
- case 1:
- /* C.SRAI -> srai rd', rd', shamt[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s,
- GET_C_ZIMM(ctx->opcode) | 0x400);
- /* C.SRAI64(RV128) */
- break;
- case 2:
- /* C.ANDI -> andi rd', rd', imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ANDI, rs1s, rs1s,
- GET_C_IMM(ctx->opcode));
- break;
- case 3:
- funct2 = extract32(ctx->opcode, 5, 2);
- rs2s = GET_C_RS2S(ctx->opcode);
- switch (funct2) {
- case 0:
- /* C.SUB -> sub rd', rd', rs2' */
- if (extract32(ctx->opcode, 12, 1) == 0) {
- gen_arith(ctx, OPC_RISC_SUB, rs1s, rs1s, rs2s);
- }
-#if defined(TARGET_RISCV64)
- else {
- gen_arith(ctx, OPC_RISC_SUBW, rs1s, rs1s, rs2s);
- }
-#endif
- break;
- case 1:
- /* C.XOR -> xor rs1', rs1', rs2' */
- if (extract32(ctx->opcode, 12, 1) == 0) {
- gen_arith(ctx, OPC_RISC_XOR, rs1s, rs1s, rs2s);
- }
-#if defined(TARGET_RISCV64)
- else {
- /* C.ADDW (RV64/128) */
- gen_arith(ctx, OPC_RISC_ADDW, rs1s, rs1s, rs2s);
- }
-#endif
- break;
- case 2:
- /* C.OR -> or rs1', rs1', rs2' */
- gen_arith(ctx, OPC_RISC_OR, rs1s, rs1s, rs2s);
- break;
- case 3:
- /* C.AND -> and rs1', rs1', rs2' */
- gen_arith(ctx, OPC_RISC_AND, rs1s, rs1s, rs2s);
- break;
- }
- break;
- }
- break;
- case 5:
- /* C.J -> jal x0, offset[11:1]*/
- gen_jal(env, ctx, 0, GET_C_J_IMM(ctx->opcode));
- break;
- case 6:
- /* C.BEQZ -> beq rs1', x0, offset[8:1]*/
- rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(env, ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode));
- break;
- case 7:
- /* C.BNEZ -> bne rs1', x0, offset[8:1]*/
- rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(env, ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode));
- break;
- }
-}
-
static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
{
uint8_t rd, rs2;
@@ -945,9 +831,6 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
case 0:
decode_RV32_64C0(ctx);
break;
- case 1:
- decode_RV32_64C1(env, ctx);
- break;
case 2:
decode_RV32_64C2(env, ctx);
break;
@@ -962,6 +845,7 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
EX_SH(1)
EX_SH(2)
EX_SH(3)
+EX_SH(4)
EX_SH(12)
static int ex_rvc_register(int reg)
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn16.decode | 43 +++++++
target/riscv/insn_trans/trans_rvc.inc.c | 151 ++++++++++++++++++++++++
target/riscv/translate.c | 118 +-----------------
3 files changed, 195 insertions(+), 117 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 558c0c41f0..29dade0fa1 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -22,28 +22,53 @@
%rs2_3 2:3 !function=ex_rvc_register
# Immediates:
+%imm_ci 12:s1 2:5
%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2
%uimm_cl_d 5:2 10:3 !function=ex_shift_3
%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
+%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
+%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
+
+%nzuimm_6bit 12:1 2:5
+
+%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
+%imm_lui 12:s1 2:5 !function=ex_shift_12
+
# Argument sets:
&cl rs1 rd
&cl_dw uimm rs1 rd
+&ci imm rd
&ciw nzuimm rd
&cs rs1 rs2
&cs_dw uimm rs1 rs2
+&cb imm rs1
+&cr rd rs2
+&c_j imm
+&c_shift shamt rd
+
+&c_addi16sp_lui imm_lui imm_addi16sp rd
# Formats 16:
+@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
+@cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
+@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
+@cj ... ........... .. &c_j imm=%imm_cj
+@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp %rd
+
+@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
+
+@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
# *** RV64C Standard Extension (Quadrant 0) ***
c_addi4spn 000 ........ ... 00 @ciw
@@ -53,3 +78,21 @@ c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
c_fsd 101 ... ... .. ... 00 @cs_d
c_sw 110 ... ... .. ... 00 @cs_w
c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
+
+# *** RV64C Standard Extension (Quadrant 1) ***
+c_addi 000 . ..... ..... 01 @ci
+c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually
+c_li 010 . ..... ..... 01 @ci
+c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
+c_srli 100 . 00 ... ..... 01 @c_shift
+c_srai 100 . 01 ... ..... 01 @c_shift
+c_andi 100 . 10 ... ..... 01 @c_andi
+c_sub 100 0 11 ... 00 ... 01 @cs_2
+c_xor 100 0 11 ... 01 ... 01 @cs_2
+c_or 100 0 11 ... 10 ... 01 @cs_2
+c_and 100 0 11 ... 11 ... 01 @cs_2
+c_subw 100 1 11 ... 00 ... 01 @cs_2
+c_addw 100 1 11 ... 01 ... 01 @cs_2
+c_j 101 ........... 01 @cj
+c_beqz 110 ... ... ..... 01 @cb
+c_bnez 111 ... ... ..... 01 @cb
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index 93ec8aa30b..b06c435c98 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -73,3 +73,154 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
return false;
#endif
}
+
+static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
+{
+ if (a->imm == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_addi(ctx, &arg);
+}
+
+static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.JAL */
+ arg_jal arg = { .rd = 1, .imm = a->imm };
+ return trans_jal(ctx, &arg);
+#else
+ /* C.ADDIW */
+ arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_addiw(ctx, &arg);
+#endif
+}
+
+static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
+{
+ if (a->rd == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm };
+ return trans_addi(ctx, &arg);
+}
+
+static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
+{
+ if (a->rd == 2) {
+ /* C.ADDI16SP */
+ arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp };
+ return trans_addi(ctx, &arg);
+ } else if (a->imm_lui != 0) {
+ /* C.LUI */
+ if (a->rd == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_lui arg = { .rd = a->rd, .imm = a->imm_lui };
+ return trans_lui(ctx, &arg);
+ }
+ return false;
+}
+
+static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a)
+{
+ int shamt = a->shamt;
+ if (shamt == 0) {
+ /* For RV128 a shamt of 0 means a shift by 64 */
+ shamt = 64;
+ }
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_srli(ctx, &arg);
+}
+
+static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
+{
+ int shamt = a->shamt;
+ if (shamt == 0) {
+ /* For RV128 a shamt of 0 means a shift by 64 */
+ shamt = 64;
+ }
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_srai(ctx, &arg);
+}
+
+static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
+{
+ arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_andi(ctx, &arg);
+}
+
+static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
+{
+ arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_sub(ctx, &arg);
+}
+
+static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
+{
+ arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_xor(ctx, &arg);
+}
+
+static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
+{
+ arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_or(ctx, &arg);
+}
+
+static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
+{
+ arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_and(ctx, &arg);
+}
+
+static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
+{
+#ifdef TARGET_RISCV64
+ arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_subw(ctx, &arg);
+#else
+ return false;
+#endif
+}
+
+static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
+{
+#ifdef TARGET_RISCV64
+ arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_addw(ctx, &arg);
+#else
+ return false;
+#endif
+}
+
+static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
+{
+ arg_jal arg = { .rd = 0, .imm = a->imm };
+ return trans_jal(ctx, &arg);
+}
+
+static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
+{
+ arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
+ return trans_beq(ctx, &arg);
+}
+
+static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
+{
+ arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
+ return trans_bne(ctx, &arg);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1ee13c1907..498fbc20ef 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -745,120 +745,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
}
}
-static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
-{
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
- uint8_t rd_rs1 = GET_C_RS1(ctx->opcode);
- uint8_t rs1s, rs2s;
- uint8_t funct2;
-
- switch (funct3) {
- case 0:
- /* C.ADDI -> addi rd, rd, nzimm[5:0] */
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, rd_rs1,
- GET_C_IMM(ctx->opcode));
- break;
- case 1:
-#if defined(TARGET_RISCV64)
- /* C.ADDIW (RV64/128) -> addiw rd, rd, imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ADDIW, rd_rs1, rd_rs1,
- GET_C_IMM(ctx->opcode));
-#else
- /* C.JAL(RV32) -> jal x1, offset[11:1] */
- gen_jal(env, ctx, 1, GET_C_J_IMM(ctx->opcode));
-#endif
- break;
- case 2:
- /* C.LI -> addi rd, x0, imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, 0, GET_C_IMM(ctx->opcode));
- break;
- case 3:
- if (rd_rs1 == 2) {
- /* C.ADDI16SP -> addi x2, x2, nzimm[9:4]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, 2, 2,
- GET_C_ADDI16SP_IMM(ctx->opcode));
- } else if (rd_rs1 != 0) {
- /* C.LUI (rs1/rd =/= {0,2}) -> lui rd, nzimm[17:12]*/
- tcg_gen_movi_tl(cpu_gpr[rd_rs1],
- GET_C_IMM(ctx->opcode) << 12);
- }
- break;
- case 4:
- funct2 = extract32(ctx->opcode, 10, 2);
- rs1s = GET_C_RS1S(ctx->opcode);
- switch (funct2) {
- case 0: /* C.SRLI(RV32) -> srli rd', rd', shamt[5:0] */
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s,
- GET_C_ZIMM(ctx->opcode));
- /* C.SRLI64(RV128) */
- break;
- case 1:
- /* C.SRAI -> srai rd', rd', shamt[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s,
- GET_C_ZIMM(ctx->opcode) | 0x400);
- /* C.SRAI64(RV128) */
- break;
- case 2:
- /* C.ANDI -> andi rd', rd', imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ANDI, rs1s, rs1s,
- GET_C_IMM(ctx->opcode));
- break;
- case 3:
- funct2 = extract32(ctx->opcode, 5, 2);
- rs2s = GET_C_RS2S(ctx->opcode);
- switch (funct2) {
- case 0:
- /* C.SUB -> sub rd', rd', rs2' */
- if (extract32(ctx->opcode, 12, 1) == 0) {
- gen_arith(ctx, OPC_RISC_SUB, rs1s, rs1s, rs2s);
- }
-#if defined(TARGET_RISCV64)
- else {
- gen_arith(ctx, OPC_RISC_SUBW, rs1s, rs1s, rs2s);
- }
-#endif
- break;
- case 1:
- /* C.XOR -> xor rs1', rs1', rs2' */
- if (extract32(ctx->opcode, 12, 1) == 0) {
- gen_arith(ctx, OPC_RISC_XOR, rs1s, rs1s, rs2s);
- }
-#if defined(TARGET_RISCV64)
- else {
- /* C.ADDW (RV64/128) */
- gen_arith(ctx, OPC_RISC_ADDW, rs1s, rs1s, rs2s);
- }
-#endif
- break;
- case 2:
- /* C.OR -> or rs1', rs1', rs2' */
- gen_arith(ctx, OPC_RISC_OR, rs1s, rs1s, rs2s);
- break;
- case 3:
- /* C.AND -> and rs1', rs1', rs2' */
- gen_arith(ctx, OPC_RISC_AND, rs1s, rs1s, rs2s);
- break;
- }
- break;
- }
- break;
- case 5:
- /* C.J -> jal x0, offset[11:1]*/
- gen_jal(env, ctx, 0, GET_C_J_IMM(ctx->opcode));
- break;
- case 6:
- /* C.BEQZ -> beq rs1', x0, offset[8:1]*/
- rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(env, ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode));
- break;
- case 7:
- /* C.BNEZ -> bne rs1', x0, offset[8:1]*/
- rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(env, ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode));
- break;
- }
-}
-
static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
{
uint8_t rd, rs2;
@@ -945,9 +831,6 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
case 0:
decode_RV32_64C0(ctx);
break;
- case 1:
- decode_RV32_64C1(env, ctx);
- break;
case 2:
decode_RV32_64C2(env, ctx);
break;
@@ -962,6 +845,7 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
EX_SH(1)
EX_SH(2)
EX_SH(3)
+EX_SH(4)
EX_SH(12)
static int ex_rvc_register(int reg)
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn16.decode | 31 ++++++++
target/riscv/insn_trans/trans_rvc.inc.c | 101 ++++++++++++++++++++++++
target/riscv/translate.c | 83 +------------------
3 files changed, 134 insertions(+), 81 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 29dade0fa1..0829e3bc59 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -20,6 +20,7 @@
%rd 7:5
%rs1_3 7:3 !function=ex_rvc_register
%rs2_3 2:3 !function=ex_rvc_register
+%rs2_5 2:5
# Immediates:
%imm_ci 12:s1 2:5
@@ -30,6 +31,10 @@
%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
%nzuimm_6bit 12:1 2:5
+%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
+%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
+%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3
+%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2
%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
%imm_lui 12:s1 2:5 !function=ex_shift_12
@@ -48,10 +53,15 @@
&c_j imm
&c_shift shamt rd
+&c_ld uimm rd
+&c_sd uimm rs2
&c_addi16sp_lui imm_lui imm_addi16sp rd
+&c_flwsp_ldsp uimm_flwsp uimm_ldsp rd
+&c_fswsp_sdsp uimm_fswsp uimm_sdsp rs2
# Formats 16:
+@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd
@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@@ -64,9 +74,19 @@
@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
@cj ... ........... .. &c_j imm=%imm_cj
+@c_ld ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd
+@c_lw ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd
+@c_sd ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd rs2=%rs2_5
+@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5
+
@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp %rd
+@c_flwsp_ldsp ... . ..... ..... .. &c_flwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
+ uimm_ldsp=%uimm_6bit_ld %rd
+@c_fswsp_sdsp ... . ..... ..... .. &c_fswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
+ uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
+@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
@@ -96,3 +116,14 @@ c_addw 100 1 11 ... 01 ... 01 @cs_2
c_j 101 ........... 01 @cj
c_beqz 110 ... ... ..... 01 @cb
c_bnez 111 ... ... ..... 01 @cb
+
+# *** RV64C Standard Extension (Quadrant 2) ***
+c_slli 000 . ..... ..... 10 @c_shift2
+c_fldsp 001 . ..... ..... 10 @c_ld
+c_lwsp 010 . ..... ..... 10 @c_lw
+c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
+c_jr_mv 100 0 ..... ..... 10 @cr
+c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
+c_fsdsp 101 ...... ..... 10 @c_sd
+c_swsp 110 . ..... ..... 10 @c_sw
+c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index b06c435c98..bcdf64d3b7 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -224,3 +224,104 @@ static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
return trans_bne(ctx, &arg);
}
+
+static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
+{
+ int shamt = a->shamt;
+ if (shamt == 0) {
+ /* For RV128 a shamt of 0 means a shift by 64 */
+ shamt = 64;
+ }
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_slli(ctx, &arg);
+}
+
+static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
+{
+ arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
+ return trans_fld(ctx, &arg);
+}
+
+static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
+{
+ arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
+ return trans_lw(ctx, &arg);
+}
+
+static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FLWSP */
+ arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
+ return trans_flw(ctx, &arg_flw);
+#else
+ /* C.LDSP */
+ arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
+ return trans_ld(ctx, &arg_ld);
+#endif
+ return false;
+}
+
+static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
+{
+ if (a->rd != 0 && a->rs2 == 0) {
+ /* C.JR */
+ arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 };
+ return trans_jalr(ctx, &arg);
+ } else if (a->rd != 0 && a->rs2 != 0) {
+ /* C.MV */
+ arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 };
+ return trans_add(ctx, &arg);
+ }
+ return false;
+}
+
+static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
+{
+ if (a->rd == 0 && a->rs2 == 0) {
+ /* C.EBREAK */
+ arg_ebreak arg = { };
+ return trans_ebreak(ctx, &arg);
+ } else if (a->rd != 0) {
+ if (a->rs2 == 0) {
+ /* C.JALR */
+ arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 };
+ return trans_jalr(ctx, &arg);
+ } else {
+ /* C.ADD */
+ arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_add(ctx, &arg);
+ }
+ }
+ return false;
+}
+
+static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
+{
+ arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_fsd(ctx, &arg);
+}
+
+static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
+{
+ arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_sw(ctx, &arg);
+}
+
+static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FSWSP */
+ arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp };
+ return trans_fsw(ctx, &a_fsw);
+#else
+ /* C.SDSP */
+ arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
+ return trans_sd(ctx, &a_sd);
+#endif
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 498fbc20ef..53febc60b0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -614,6 +614,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
tcg_temp_free(dat);
}
+#ifdef TARGET_RISCV32
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
{
@@ -672,6 +673,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
tcg_temp_free(t0);
}
+#endif
static void gen_set_rm(DisasContext *ctx, int rm)
{
@@ -745,84 +747,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
}
}
-static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
-{
- uint8_t rd, rs2;
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
-
-
- rd = GET_RD(ctx->opcode);
-
- switch (funct3) {
- case 0: /* C.SLLI -> slli rd, rd, shamt[5:0]
- C.SLLI64 -> */
- gen_arith_imm(ctx, OPC_RISC_SLLI, rd, rd, GET_C_ZIMM(ctx->opcode));
- break;
- case 1: /* C.FLDSP(RV32/64DC) -> fld rd, offset[8:3](x2) */
- gen_fp_load(ctx, OPC_RISC_FLD, rd, 2, GET_C_LDSP_IMM(ctx->opcode));
- break;
- case 2: /* C.LWSP -> lw rd, offset[7:2](x2) */
- gen_load(ctx, OPC_RISC_LW, rd, 2, GET_C_LWSP_IMM(ctx->opcode));
- break;
- case 3:
-#if defined(TARGET_RISCV64)
- /* C.LDSP(RVC64) -> ld rd, offset[8:3](x2) */
- gen_load(ctx, OPC_RISC_LD, rd, 2, GET_C_LDSP_IMM(ctx->opcode));
-#else
- /* C.FLWSP(RV32FC) -> flw rd, offset[7:2](x2) */
- gen_fp_load(ctx, OPC_RISC_FLW, rd, 2, GET_C_LWSP_IMM(ctx->opcode));
-#endif
- break;
- case 4:
- rs2 = GET_C_RS2(ctx->opcode);
-
- if (extract32(ctx->opcode, 12, 1) == 0) {
- if (rs2 == 0) {
- /* C.JR -> jalr x0, rs1, 0*/
- gen_jalr(env, ctx, OPC_RISC_JALR, 0, rd, 0);
- } else {
- /* C.MV -> add rd, x0, rs2 */
- gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2);
- }
- } else {
- if (rd == 0) {
- /* C.EBREAK -> ebreak*/
- gen_system(env, ctx, OPC_RISC_ECALL, 0, 0, 0x1);
- } else {
- if (rs2 == 0) {
- /* C.JALR -> jalr x1, rs1, 0*/
- gen_jalr(env, ctx, OPC_RISC_JALR, 1, rd, 0);
- } else {
- /* C.ADD -> add rd, rd, rs2 */
- gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2);
- }
- }
- }
- break;
- case 5:
- /* C.FSDSP -> fsd rs2, offset[8:3](x2)*/
- gen_fp_store(ctx, OPC_RISC_FSD, 2, GET_C_RS2(ctx->opcode),
- GET_C_SDSP_IMM(ctx->opcode));
- /* C.SQSP */
- break;
- case 6: /* C.SWSP -> sw rs2, offset[7:2](x2)*/
- gen_store(ctx, OPC_RISC_SW, 2, GET_C_RS2(ctx->opcode),
- GET_C_SWSP_IMM(ctx->opcode));
- break;
- case 7:
-#if defined(TARGET_RISCV64)
- /* C.SDSP(Rv64/128) -> sd rs2, offset[8:3](x2)*/
- gen_store(ctx, OPC_RISC_SD, 2, GET_C_RS2(ctx->opcode),
- GET_C_SDSP_IMM(ctx->opcode));
-#else
- /* C.FSWSP(RV32) -> fsw rs2, offset[7:2](x2) */
- gen_fp_store(ctx, OPC_RISC_FSW, 2, GET_C_RS2(ctx->opcode),
- GET_C_SWSP_IMM(ctx->opcode));
-#endif
- break;
- }
-}
-
static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
{
uint8_t op = extract32(ctx->opcode, 0, 2);
@@ -831,9 +755,6 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
case 0:
decode_RV32_64C0(ctx);
break;
- case 2:
- decode_RV32_64C2(env, ctx);
- break;
}
}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn16.decode | 31 ++++++++
target/riscv/insn_trans/trans_rvc.inc.c | 101 ++++++++++++++++++++++++
target/riscv/translate.c | 83 +------------------
3 files changed, 134 insertions(+), 81 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 29dade0fa1..0829e3bc59 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -20,6 +20,7 @@
%rd 7:5
%rs1_3 7:3 !function=ex_rvc_register
%rs2_3 2:3 !function=ex_rvc_register
+%rs2_5 2:5
# Immediates:
%imm_ci 12:s1 2:5
@@ -30,6 +31,10 @@
%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
%nzuimm_6bit 12:1 2:5
+%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
+%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
+%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3
+%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2
%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
%imm_lui 12:s1 2:5 !function=ex_shift_12
@@ -48,10 +53,15 @@
&c_j imm
&c_shift shamt rd
+&c_ld uimm rd
+&c_sd uimm rs2
&c_addi16sp_lui imm_lui imm_addi16sp rd
+&c_flwsp_ldsp uimm_flwsp uimm_ldsp rd
+&c_fswsp_sdsp uimm_fswsp uimm_sdsp rs2
# Formats 16:
+@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd
@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@@ -64,9 +74,19 @@
@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
@cj ... ........... .. &c_j imm=%imm_cj
+@c_ld ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd
+@c_lw ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd
+@c_sd ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd rs2=%rs2_5
+@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5
+
@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp %rd
+@c_flwsp_ldsp ... . ..... ..... .. &c_flwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
+ uimm_ldsp=%uimm_6bit_ld %rd
+@c_fswsp_sdsp ... . ..... ..... .. &c_fswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
+ uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
+@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
@@ -96,3 +116,14 @@ c_addw 100 1 11 ... 01 ... 01 @cs_2
c_j 101 ........... 01 @cj
c_beqz 110 ... ... ..... 01 @cb
c_bnez 111 ... ... ..... 01 @cb
+
+# *** RV64C Standard Extension (Quadrant 2) ***
+c_slli 000 . ..... ..... 10 @c_shift2
+c_fldsp 001 . ..... ..... 10 @c_ld
+c_lwsp 010 . ..... ..... 10 @c_lw
+c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
+c_jr_mv 100 0 ..... ..... 10 @cr
+c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
+c_fsdsp 101 ...... ..... 10 @c_sd
+c_swsp 110 . ..... ..... 10 @c_sw
+c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index b06c435c98..bcdf64d3b7 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -224,3 +224,104 @@ static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
return trans_bne(ctx, &arg);
}
+
+static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
+{
+ int shamt = a->shamt;
+ if (shamt == 0) {
+ /* For RV128 a shamt of 0 means a shift by 64 */
+ shamt = 64;
+ }
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_slli(ctx, &arg);
+}
+
+static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
+{
+ arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
+ return trans_fld(ctx, &arg);
+}
+
+static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
+{
+ arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
+ return trans_lw(ctx, &arg);
+}
+
+static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FLWSP */
+ arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
+ return trans_flw(ctx, &arg_flw);
+#else
+ /* C.LDSP */
+ arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
+ return trans_ld(ctx, &arg_ld);
+#endif
+ return false;
+}
+
+static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
+{
+ if (a->rd != 0 && a->rs2 == 0) {
+ /* C.JR */
+ arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 };
+ return trans_jalr(ctx, &arg);
+ } else if (a->rd != 0 && a->rs2 != 0) {
+ /* C.MV */
+ arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 };
+ return trans_add(ctx, &arg);
+ }
+ return false;
+}
+
+static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
+{
+ if (a->rd == 0 && a->rs2 == 0) {
+ /* C.EBREAK */
+ arg_ebreak arg = { };
+ return trans_ebreak(ctx, &arg);
+ } else if (a->rd != 0) {
+ if (a->rs2 == 0) {
+ /* C.JALR */
+ arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 };
+ return trans_jalr(ctx, &arg);
+ } else {
+ /* C.ADD */
+ arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_add(ctx, &arg);
+ }
+ }
+ return false;
+}
+
+static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
+{
+ arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_fsd(ctx, &arg);
+}
+
+static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
+{
+ arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_sw(ctx, &arg);
+}
+
+static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FSWSP */
+ arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp };
+ return trans_fsw(ctx, &a_fsw);
+#else
+ /* C.SDSP */
+ arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
+ return trans_sd(ctx, &a_sd);
+#endif
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 498fbc20ef..53febc60b0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -614,6 +614,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
tcg_temp_free(dat);
}
+#ifdef TARGET_RISCV32
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
{
@@ -672,6 +673,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
tcg_temp_free(t0);
}
+#endif
static void gen_set_rm(DisasContext *ctx, int rm)
{
@@ -745,84 +747,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
}
}
-static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
-{
- uint8_t rd, rs2;
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
-
-
- rd = GET_RD(ctx->opcode);
-
- switch (funct3) {
- case 0: /* C.SLLI -> slli rd, rd, shamt[5:0]
- C.SLLI64 -> */
- gen_arith_imm(ctx, OPC_RISC_SLLI, rd, rd, GET_C_ZIMM(ctx->opcode));
- break;
- case 1: /* C.FLDSP(RV32/64DC) -> fld rd, offset[8:3](x2) */
- gen_fp_load(ctx, OPC_RISC_FLD, rd, 2, GET_C_LDSP_IMM(ctx->opcode));
- break;
- case 2: /* C.LWSP -> lw rd, offset[7:2](x2) */
- gen_load(ctx, OPC_RISC_LW, rd, 2, GET_C_LWSP_IMM(ctx->opcode));
- break;
- case 3:
-#if defined(TARGET_RISCV64)
- /* C.LDSP(RVC64) -> ld rd, offset[8:3](x2) */
- gen_load(ctx, OPC_RISC_LD, rd, 2, GET_C_LDSP_IMM(ctx->opcode));
-#else
- /* C.FLWSP(RV32FC) -> flw rd, offset[7:2](x2) */
- gen_fp_load(ctx, OPC_RISC_FLW, rd, 2, GET_C_LWSP_IMM(ctx->opcode));
-#endif
- break;
- case 4:
- rs2 = GET_C_RS2(ctx->opcode);
-
- if (extract32(ctx->opcode, 12, 1) == 0) {
- if (rs2 == 0) {
- /* C.JR -> jalr x0, rs1, 0*/
- gen_jalr(env, ctx, OPC_RISC_JALR, 0, rd, 0);
- } else {
- /* C.MV -> add rd, x0, rs2 */
- gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2);
- }
- } else {
- if (rd == 0) {
- /* C.EBREAK -> ebreak*/
- gen_system(env, ctx, OPC_RISC_ECALL, 0, 0, 0x1);
- } else {
- if (rs2 == 0) {
- /* C.JALR -> jalr x1, rs1, 0*/
- gen_jalr(env, ctx, OPC_RISC_JALR, 1, rd, 0);
- } else {
- /* C.ADD -> add rd, rd, rs2 */
- gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2);
- }
- }
- }
- break;
- case 5:
- /* C.FSDSP -> fsd rs2, offset[8:3](x2)*/
- gen_fp_store(ctx, OPC_RISC_FSD, 2, GET_C_RS2(ctx->opcode),
- GET_C_SDSP_IMM(ctx->opcode));
- /* C.SQSP */
- break;
- case 6: /* C.SWSP -> sw rs2, offset[7:2](x2)*/
- gen_store(ctx, OPC_RISC_SW, 2, GET_C_RS2(ctx->opcode),
- GET_C_SWSP_IMM(ctx->opcode));
- break;
- case 7:
-#if defined(TARGET_RISCV64)
- /* C.SDSP(Rv64/128) -> sd rs2, offset[8:3](x2)*/
- gen_store(ctx, OPC_RISC_SD, 2, GET_C_RS2(ctx->opcode),
- GET_C_SDSP_IMM(ctx->opcode));
-#else
- /* C.FSWSP(RV32) -> fsw rs2, offset[7:2](x2) */
- gen_fp_store(ctx, OPC_RISC_FSW, 2, GET_C_RS2(ctx->opcode),
- GET_C_SWSP_IMM(ctx->opcode));
-#endif
- break;
- }
-}
-
static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
{
uint8_t op = extract32(ctx->opcode, 0, 2);
@@ -831,9 +755,6 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
case 0:
decode_RV32_64C0(ctx);
break;
- case 2:
- decode_RV32_64C2(env, ctx);
- break;
}
}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr()
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +++++++++++++++++-
target/riscv/translate.c | 38 -------------------------
2 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index b0f35cef14..3b3aff4803 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -42,7 +42,33 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{
- gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+ /* no chaining with JALR */
+ TCGLabel *misaligned = NULL;
+ TCGv t0 = tcg_temp_new();
+
+
+ gen_get_gpr(cpu_pc, a->rs1);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+ tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+ if (!riscv_has_ext(ctx->env, RVC)) {
+ misaligned = gen_new_label();
+ tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+ }
+
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+ }
+ tcg_gen_lookup_and_goto_ptr();
+
+ if (misaligned) {
+ gen_set_label(misaligned);
+ gen_exception_inst_addr_mis(ctx);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(t0);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 53febc60b0..1f59b02c84 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,44 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, target_long imm)
-{
- /* no chaining with JALR */
- TCGLabel *misaligned = NULL;
- TCGv t0 = tcg_temp_new();
-
- switch (opc) {
- case OPC_RISC_JALR:
- gen_get_gpr(cpu_pc, rs1);
- tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
- tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
- if (!riscv_has_ext(env, RVC)) {
- misaligned = gen_new_label();
- tcg_gen_andi_tl(t0, cpu_pc, 0x2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
- }
-
- if (rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
- }
- tcg_gen_lookup_and_goto_ptr();
-
- if (misaligned) {
- gen_set_label(misaligned);
- gen_exception_inst_addr_mis(ctx);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rs1, int rs2, target_long bimm)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 20/35] target/riscv: Remove gen_jalr()
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, Alistair Francis
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +++++++++++++++++-
target/riscv/translate.c | 38 -------------------------
2 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index b0f35cef14..3b3aff4803 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -42,7 +42,33 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{
- gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+ /* no chaining with JALR */
+ TCGLabel *misaligned = NULL;
+ TCGv t0 = tcg_temp_new();
+
+
+ gen_get_gpr(cpu_pc, a->rs1);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+ tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+ if (!riscv_has_ext(ctx->env, RVC)) {
+ misaligned = gen_new_label();
+ tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+ }
+
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+ }
+ tcg_gen_lookup_and_goto_ptr();
+
+ if (misaligned) {
+ gen_set_label(misaligned);
+ gen_exception_inst_addr_mis(ctx);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(t0);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 53febc60b0..1f59b02c84 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,44 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, target_long imm)
-{
- /* no chaining with JALR */
- TCGLabel *misaligned = NULL;
- TCGv t0 = tcg_temp_new();
-
- switch (opc) {
- case OPC_RISC_JALR:
- gen_get_gpr(cpu_pc, rs1);
- tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
- tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
- if (!riscv_has_ext(env, RVC)) {
- misaligned = gen_new_label();
- tcg_gen_andi_tl(t0, cpu_pc, 0x2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
- }
-
- if (rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
- }
- tcg_gen_lookup_and_goto_ptr();
-
- if (misaligned) {
- gen_set_label(misaligned);
- gen_exception_inst_addr_mis(ctx);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rs1, int rs2, target_long bimm)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch()
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 46 +++++++++++++++++-------
target/riscv/translate.c | 47 -------------------------
2 files changed, 33 insertions(+), 60 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 3b3aff4803..0db1f79d20 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -72,41 +72,61 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
return true;
}
-static bool trans_beq(DisasContext *ctx, arg_beq *a)
+static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
+ TCGLabel *l = gen_new_label();
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_brcond_tl(cond, source1, source2, l);
+ gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+ gen_set_label(l); /* branch taken */
+
+ if (!riscv_has_ext(ctx->env, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+ /* misaligned */
+ gen_exception_inst_addr_mis(ctx);
+ } else {
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+
return true;
}
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+ return gen_branch(ctx, a, TCG_COND_EQ);
+}
+
static bool trans_bne(DisasContext *ctx, arg_bne *a)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_NE);
}
static bool trans_blt(DisasContext *ctx, arg_blt *a)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_LT);
}
static bool trans_bge(DisasContext *ctx, arg_bge *a)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_GE);
}
static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_LTU);
}
static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
{
-
- gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_GEU);
}
static bool trans_lb(DisasContext *ctx, arg_lb *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1f59b02c84..a0e96b94a9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,53 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rs1, int rs2, target_long bimm)
-{
- TCGLabel *l = gen_new_label();
- TCGv source1, source2;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
- gen_get_gpr(source1, rs1);
- gen_get_gpr(source2, rs2);
-
- switch (opc) {
- case OPC_RISC_BEQ:
- tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l);
- break;
- case OPC_RISC_BNE:
- tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l);
- break;
- case OPC_RISC_BLT:
- tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l);
- break;
- case OPC_RISC_BGE:
- tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l);
- break;
- case OPC_RISC_BLTU:
- tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l);
- break;
- case OPC_RISC_BGEU:
- tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
- tcg_temp_free(source1);
- tcg_temp_free(source2);
-
- gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
- gen_set_label(l); /* branch taken */
- if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
- /* misaligned */
- gen_exception_inst_addr_mis(ctx);
- } else {
- gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
-}
-
static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch()
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 46 +++++++++++++++++-------
target/riscv/translate.c | 47 -------------------------
2 files changed, 33 insertions(+), 60 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 3b3aff4803..0db1f79d20 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -72,41 +72,61 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
return true;
}
-static bool trans_beq(DisasContext *ctx, arg_beq *a)
+static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
+ TCGLabel *l = gen_new_label();
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_brcond_tl(cond, source1, source2, l);
+ gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+ gen_set_label(l); /* branch taken */
+
+ if (!riscv_has_ext(ctx->env, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+ /* misaligned */
+ gen_exception_inst_addr_mis(ctx);
+ } else {
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+
return true;
}
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+ return gen_branch(ctx, a, TCG_COND_EQ);
+}
+
static bool trans_bne(DisasContext *ctx, arg_bne *a)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_NE);
}
static bool trans_blt(DisasContext *ctx, arg_blt *a)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_LT);
}
static bool trans_bge(DisasContext *ctx, arg_bge *a)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_GE);
}
static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
{
- gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_LTU);
}
static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
{
-
- gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_GEU);
}
static bool trans_lb(DisasContext *ctx, arg_lb *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1f59b02c84..a0e96b94a9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,53 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rs1, int rs2, target_long bimm)
-{
- TCGLabel *l = gen_new_label();
- TCGv source1, source2;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
- gen_get_gpr(source1, rs1);
- gen_get_gpr(source2, rs2);
-
- switch (opc) {
- case OPC_RISC_BEQ:
- tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l);
- break;
- case OPC_RISC_BNE:
- tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l);
- break;
- case OPC_RISC_BLT:
- tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l);
- break;
- case OPC_RISC_BGE:
- tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l);
- break;
- case OPC_RISC_BLTU:
- tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l);
- break;
- case OPC_RISC_BGEU:
- tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
- tcg_temp_free(source1);
- tcg_temp_free(source2);
-
- gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
- gen_set_label(l); /* branch taken */
- if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
- /* misaligned */
- gen_exception_inst_addr_mis(ctx);
- } else {
- gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
-}
-
static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load()
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++----------
target/riscv/translate.c | 6 +++--
2 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 0db1f79d20..1ad00bd776 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -129,34 +129,43 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
return gen_branch(ctx, a, TCG_COND_GEU);
}
-static bool trans_lb(DisasContext *ctx, arg_lb *a)
+static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop)
{
- gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
return true;
}
+static bool trans_lb(DisasContext *ctx, arg_lb *a)
+{
+ return gen_load(ctx, a, MO_SB);
+}
+
static bool trans_lh(DisasContext *ctx, arg_lh *a)
{
- gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TESW);
}
static bool trans_lw(DisasContext *ctx, arg_lw *a)
{
- gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TESL);
}
static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
{
- gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_UB);
}
static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
{
- gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEUW);
}
static bool trans_sb(DisasContext *ctx, arg_sb *a)
@@ -180,14 +189,12 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
#ifdef TARGET_RISCV64
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
{
- gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEUL);
}
static bool trans_ld(DisasContext *ctx, arg_ld *a)
{
- gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEQ);
}
static bool trans_sd(DisasContext *ctx, arg_sd *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a0e96b94a9..d0fefa8fb9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,7 +489,8 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+#ifdef TARGET_RISCV64
+static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
TCGv t0 = tcg_temp_new();
@@ -508,6 +509,7 @@ static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(t0);
tcg_temp_free(t1);
}
+#endif
static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
@@ -640,7 +642,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
case 3:
#if defined(TARGET_RISCV64)
/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
- gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s,
+ gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load()
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++----------
target/riscv/translate.c | 6 +++--
2 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 0db1f79d20..1ad00bd776 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -129,34 +129,43 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
return gen_branch(ctx, a, TCG_COND_GEU);
}
-static bool trans_lb(DisasContext *ctx, arg_lb *a)
+static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop)
{
- gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
return true;
}
+static bool trans_lb(DisasContext *ctx, arg_lb *a)
+{
+ return gen_load(ctx, a, MO_SB);
+}
+
static bool trans_lh(DisasContext *ctx, arg_lh *a)
{
- gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TESW);
}
static bool trans_lw(DisasContext *ctx, arg_lw *a)
{
- gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TESL);
}
static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
{
- gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_UB);
}
static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
{
- gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEUW);
}
static bool trans_sb(DisasContext *ctx, arg_sb *a)
@@ -180,14 +189,12 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
#ifdef TARGET_RISCV64
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
{
- gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEUL);
}
static bool trans_ld(DisasContext *ctx, arg_ld *a)
{
- gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
- return true;
+ return gen_load(ctx, a, MO_TEQ);
}
static bool trans_sd(DisasContext *ctx, arg_sd *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a0e96b94a9..d0fefa8fb9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,7 +489,8 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+#ifdef TARGET_RISCV64
+static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
TCGv t0 = tcg_temp_new();
@@ -508,6 +509,7 @@ static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(t0);
tcg_temp_free(t1);
}
+#endif
static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
@@ -640,7 +642,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
case 3:
#if defined(TARGET_RISCV64)
/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
- gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s,
+ gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store()
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 27 +++++++++++++++++--------
target/riscv/translate.c | 8 +++++---
2 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 1ad00bd776..da843b4e99 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -168,22 +168,34 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
return gen_load(ctx, a, MO_TEUW);
}
-static bool trans_sb(DisasContext *ctx, arg_sb *a)
+static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop)
{
- gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_get_gpr(dat, a->rs2);
+
+ tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
return true;
}
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a)
+{
+ return gen_store(ctx, a, MO_SB);
+}
+
static bool trans_sh(DisasContext *ctx, arg_sh *a)
{
- gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TESW);
}
static bool trans_sw(DisasContext *ctx, arg_sw *a)
{
- gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TESL);
}
#ifdef TARGET_RISCV64
@@ -199,8 +211,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a)
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
- gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TEQ);
}
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d0fefa8fb9..59452be191 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -55,6 +55,7 @@ typedef struct DisasContext {
CPURISCVState *env;
} DisasContext;
+#ifdef TARGET_RISCV64
/* convert riscv funct3 to qemu memop for load/store */
static const int tcg_memop_lookup[8] = {
[0 ... 7] = -1,
@@ -68,6 +69,7 @@ static const int tcg_memop_lookup[8] = {
[6] = MO_TEUL,
#endif
};
+#endif
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
@@ -509,9 +511,8 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(t0);
tcg_temp_free(t1);
}
-#endif
-static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
{
TCGv t0 = tcg_temp_new();
@@ -530,6 +531,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
tcg_temp_free(t0);
tcg_temp_free(dat);
}
+#endif
#ifdef TARGET_RISCV32
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
@@ -653,7 +655,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
case 7:
#if defined(TARGET_RISCV64)
/* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
- gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2,
+ gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store()
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 27 +++++++++++++++++--------
target/riscv/translate.c | 8 +++++---
2 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 1ad00bd776..da843b4e99 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -168,22 +168,34 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
return gen_load(ctx, a, MO_TEUW);
}
-static bool trans_sb(DisasContext *ctx, arg_sb *a)
+static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop)
{
- gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_get_gpr(dat, a->rs2);
+
+ tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
return true;
}
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a)
+{
+ return gen_store(ctx, a, MO_SB);
+}
+
static bool trans_sh(DisasContext *ctx, arg_sh *a)
{
- gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TESW);
}
static bool trans_sw(DisasContext *ctx, arg_sw *a)
{
- gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TESL);
}
#ifdef TARGET_RISCV64
@@ -199,8 +211,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a)
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
- gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TEQ);
}
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d0fefa8fb9..59452be191 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -55,6 +55,7 @@ typedef struct DisasContext {
CPURISCVState *env;
} DisasContext;
+#ifdef TARGET_RISCV64
/* convert riscv funct3 to qemu memop for load/store */
static const int tcg_memop_lookup[8] = {
[0 ... 7] = -1,
@@ -68,6 +69,7 @@ static const int tcg_memop_lookup[8] = {
[6] = MO_TEUL,
#endif
};
+#endif
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
@@ -509,9 +511,8 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(t0);
tcg_temp_free(t1);
}
-#endif
-static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
{
TCGv t0 = tcg_temp_new();
@@ -530,6 +531,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
tcg_temp_free(t0);
tcg_temp_free(dat);
}
+#endif
#ifdef TARGET_RISCV32
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
@@ -653,7 +655,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
case 7:
#if defined(TARGET_RISCV64)
/* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
- gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2,
+ gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v4 -> v5:
- moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
- removed extra sign extension of sraiw
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvi.inc.c | 98 +++++++++++++++++-----
target/riscv/translate.c | 107 ++++++------------------
3 files changed, 108 insertions(+), 100 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ecc46a50cc..d6b4197841 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -35,12 +35,13 @@
# Argument sets:
&b imm rs2 rs1
+&i imm rs1 rd
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
# Formats 32:
@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
-@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
+@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index da843b4e99..dc6e395863 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -217,52 +217,96 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
- gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
}
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
return true;
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
return true;
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
{
- gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_ori(DisasContext *ctx, arg_ori *a)
{
- gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
}
static bool trans_andi(DisasContext *ctx, arg_andi *a)
{
- gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_shli_tl(t, t, a->shamt);
+
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt);
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_shri_tl(t, t, a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0x400);
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_sari_tl(t, t, a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
@@ -329,26 +373,42 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
#ifdef TARGET_RISCV64
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
- gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &gen_addw);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_shli_tl(source1, source1, a->shamt);
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+
+ tcg_temp_free(source1);
return true;
}
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW, a->rd, a->rs1, a->shamt);
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
+ /* sign-extend for W instructions */
+ tcg_gen_ext32s_tl(t, t);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
return true;
}
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1,
- a->shamt | 0x400);
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 59452be191..55b10fdd64 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -390,86 +390,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(source2);
}
-static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, target_long imm)
-{
- TCGv source1 = tcg_temp_new();
- int shift_len = TARGET_LONG_BITS;
- int shift_a;
-
- gen_get_gpr(source1, rs1);
-
- switch (opc) {
- case OPC_RISC_ADDI:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ADDIW:
-#endif
- tcg_gen_addi_tl(source1, source1, imm);
- break;
- case OPC_RISC_SLTI:
- tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, imm);
- break;
- case OPC_RISC_SLTIU:
- tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, imm);
- break;
- case OPC_RISC_XORI:
- tcg_gen_xori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ORI:
- tcg_gen_ori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ANDI:
- tcg_gen_andi_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SLLIW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SLLI:
- if (imm >= shift_len) {
- goto do_illegal;
- }
- tcg_gen_shli_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SHIFT_RIGHT_IW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SHIFT_RIGHT_I:
- /* differentiate on IMM */
- shift_a = imm & 0x400;
- imm &= 0x3ff;
- if (imm >= shift_len) {
- goto do_illegal;
- }
- if (imm != 0) {
- if (shift_a) {
- /* SRAI[W] */
- tcg_gen_sextract_tl(source1, source1, imm, shift_len - imm);
- } else {
- /* SRLI[W] */
- tcg_gen_extract_tl(source1, source1, imm, shift_len - imm);
- }
- /* No further sign-extension needed for W instructions. */
- opc &= ~0x8;
- }
- break;
- default:
- do_illegal:
- gen_exception_illegal(ctx);
- return;
- }
-
- if (opc & 0x8) { /* sign-extend for W instructions */
- tcg_gen_ext32s_tl(source1, source1);
- }
-
- gen_set_gpr(rd, source1);
- tcg_temp_free(source1);
-}
-
static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
target_ulong imm)
{
@@ -696,6 +616,33 @@ static int ex_rvc_register(int reg)
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
+
+static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->imm);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_add_tl(ret, arg1, arg2);
+ tcg_gen_ext32s_tl(ret, ret);
+}
+#endif
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v4 -> v5:
- moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
- removed extra sign extension of sraiw
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvi.inc.c | 98 +++++++++++++++++-----
target/riscv/translate.c | 107 ++++++------------------
3 files changed, 108 insertions(+), 100 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ecc46a50cc..d6b4197841 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -35,12 +35,13 @@
# Argument sets:
&b imm rs2 rs1
+&i imm rs1 rd
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
# Formats 32:
@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
-@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
+@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index da843b4e99..dc6e395863 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -217,52 +217,96 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
- gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
}
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
return true;
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
return true;
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
{
- gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_ori(DisasContext *ctx, arg_ori *a)
{
- gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
}
static bool trans_andi(DisasContext *ctx, arg_andi *a)
{
- gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_shli_tl(t, t, a->shamt);
+
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt);
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_shri_tl(t, t, a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0x400);
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_sari_tl(t, t, a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
@@ -329,26 +373,42 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
#ifdef TARGET_RISCV64
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
- gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &gen_addw);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_shli_tl(source1, source1, a->shamt);
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+
+ tcg_temp_free(source1);
return true;
}
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW, a->rd, a->rs1, a->shamt);
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
+ /* sign-extend for W instructions */
+ tcg_gen_ext32s_tl(t, t);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
return true;
}
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1,
- a->shamt | 0x400);
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 59452be191..55b10fdd64 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -390,86 +390,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(source2);
}
-static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, target_long imm)
-{
- TCGv source1 = tcg_temp_new();
- int shift_len = TARGET_LONG_BITS;
- int shift_a;
-
- gen_get_gpr(source1, rs1);
-
- switch (opc) {
- case OPC_RISC_ADDI:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ADDIW:
-#endif
- tcg_gen_addi_tl(source1, source1, imm);
- break;
- case OPC_RISC_SLTI:
- tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, imm);
- break;
- case OPC_RISC_SLTIU:
- tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, imm);
- break;
- case OPC_RISC_XORI:
- tcg_gen_xori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ORI:
- tcg_gen_ori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ANDI:
- tcg_gen_andi_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SLLIW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SLLI:
- if (imm >= shift_len) {
- goto do_illegal;
- }
- tcg_gen_shli_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SHIFT_RIGHT_IW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SHIFT_RIGHT_I:
- /* differentiate on IMM */
- shift_a = imm & 0x400;
- imm &= 0x3ff;
- if (imm >= shift_len) {
- goto do_illegal;
- }
- if (imm != 0) {
- if (shift_a) {
- /* SRAI[W] */
- tcg_gen_sextract_tl(source1, source1, imm, shift_len - imm);
- } else {
- /* SRLI[W] */
- tcg_gen_extract_tl(source1, source1, imm, shift_len - imm);
- }
- /* No further sign-extension needed for W instructions. */
- opc &= ~0x8;
- }
- break;
- default:
- do_illegal:
- gen_exception_illegal(ctx);
- return;
- }
-
- if (opc & 0x8) { /* sign-extend for W instructions */
- tcg_gen_ext32s_tl(source1, source1);
- }
-
- gen_set_gpr(rd, source1);
- tcg_temp_free(source1);
-}
-
static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
target_ulong imm)
{
@@ -696,6 +616,33 @@ static int ex_rvc_register(int reg)
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
+
+static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->imm);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_add_tl(ret, arg1, arg2);
+ tcg_gen_ext32s_tl(ret, ret);
+}
+#endif
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:28 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvi.inc.c | 21 +++++--------
target/riscv/translate.c | 40 +++++++++++++++----------
3 files changed, 34 insertions(+), 30 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d6b4197841..6f3ab7aa52 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -36,11 +36,12 @@
# Argument sets:
&b imm rs2 rs1
&i imm rs1 rd
+&r rd rs1 rs2
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
# Formats 32:
-@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
+@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index dc6e395863..f52182e9f4 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -312,14 +312,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
- gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
- gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -342,8 +340,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
- gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -360,14 +357,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
- gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
- gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
@@ -414,14 +409,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
- gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
- gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 55b10fdd64..f691cbcd80 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -192,12 +192,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
- CASE_OP_32_64(OPC_RISC_ADD):
- tcg_gen_add_tl(source1, source1, source2);
- break;
- CASE_OP_32_64(OPC_RISC_SUB):
- tcg_gen_sub_tl(source1, source1, source2);
- break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SLLW:
tcg_gen_andi_tl(source2, source2, 0x1F);
@@ -214,9 +208,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
case OPC_RISC_SLTU:
tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
break;
- case OPC_RISC_XOR:
- tcg_gen_xor_tl(source1, source1, source2);
- break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SRLW:
/* clear upper 32 */
@@ -242,12 +233,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
tcg_gen_sar_tl(source1, source1, source2);
break;
- case OPC_RISC_OR:
- tcg_gen_or_tl(source1, source1, source2);
- break;
- case OPC_RISC_AND:
- tcg_gen_and_tl(source1, source1, source2);
- break;
CASE_OP_32_64(OPC_RISC_MUL):
tcg_gen_mul_tl(source1, source1, source2);
break;
@@ -641,8 +626,33 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_add_tl(ret, arg1, arg2);
tcg_gen_ext32s_tl(ret, ret);
}
+
+static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_sub_tl(ret, arg1, arg2);
+ tcg_gen_ext32s_tl(ret, ret);
+}
+
#endif
+static bool trans_arith(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
@ 2019-01-22 9:28 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:28 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvi.inc.c | 21 +++++--------
target/riscv/translate.c | 40 +++++++++++++++----------
3 files changed, 34 insertions(+), 30 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d6b4197841..6f3ab7aa52 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -36,11 +36,12 @@
# Argument sets:
&b imm rs2 rs1
&i imm rs1 rd
+&r rd rs1 rs2
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
# Formats 32:
-@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
+@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index dc6e395863..f52182e9f4 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -312,14 +312,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
- gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
- gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -342,8 +340,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
- gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -360,14 +357,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
- gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
- gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
@@ -414,14 +409,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
- gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
- gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 55b10fdd64..f691cbcd80 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -192,12 +192,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
- CASE_OP_32_64(OPC_RISC_ADD):
- tcg_gen_add_tl(source1, source1, source2);
- break;
- CASE_OP_32_64(OPC_RISC_SUB):
- tcg_gen_sub_tl(source1, source1, source2);
- break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SLLW:
tcg_gen_andi_tl(source2, source2, 0x1F);
@@ -214,9 +208,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
case OPC_RISC_SLTU:
tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
break;
- case OPC_RISC_XOR:
- tcg_gen_xor_tl(source1, source1, source2);
- break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SRLW:
/* clear upper 32 */
@@ -242,12 +233,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
tcg_gen_sar_tl(source1, source1, source2);
break;
- case OPC_RISC_OR:
- tcg_gen_or_tl(source1, source1, source2);
- break;
- case OPC_RISC_AND:
- tcg_gen_and_tl(source1, source1, source2);
- break;
CASE_OP_32_64(OPC_RISC_MUL):
tcg_gen_mul_tl(source1, source1, source2);
break;
@@ -641,8 +626,33 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_add_tl(ret, arg1, arg2);
tcg_gen_ext32s_tl(ret, ret);
}
+
+static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_sub_tl(ret, arg1, arg2);
+ tcg_gen_ext32s_tl(ret, ret);
+}
+
#endif
+static bool trans_arith(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:29 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v4 -> v5:
- removed rs2 == 0 special cases in sraw/srlw
target/riscv/insn_trans/trans_rvi.inc.c | 93 +++++++++++++++++--------
target/riscv/translate.c | 59 +++++-----------
2 files changed, 81 insertions(+), 71 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index f52182e9f4..3badb70b1d 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -220,30 +220,25 @@ static bool trans_addi(DisasContext *ctx, arg_addi *a)
return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
}
-static bool trans_slti(DisasContext *ctx, arg_slti *a)
+static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
{
- TCGv source1;
- source1 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
+ tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
+}
+
+static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
+{
+ tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
+}
- tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
- return true;
+static bool trans_slti(DisasContext *ctx, arg_slti *a)
+{
+ return gen_arith_imm(ctx, a, &gen_slt);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
- TCGv source1;
- source1 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
-
- tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
-
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
- return true;
+ return gen_arith_imm(ctx, a, &gen_sltu);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
@@ -322,20 +317,17 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
static bool trans_sll(DisasContext *ctx, arg_sll *a)
{
- gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_shift(ctx, a, &tcg_gen_shl_tl);
}
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_slt);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_sltu);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
@@ -345,14 +337,12 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a)
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
- gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_shift(ctx, a, &tcg_gen_shr_tl);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
- gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_shift(ctx, a, &tcg_gen_sar_tl);
}
static bool trans_or(DisasContext *ctx, arg_or *a)
@@ -419,19 +409,62 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a)
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
- gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shl_tl(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
- gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /* clear upper 32 */
+ tcg_gen_ext32u_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shr_tl(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
- gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /*
+ * first, trick to get it to act like working on 32 bits (get rid of
+ * upper 32, sign extend to fill space)
+ */
+ tcg_gen_ext32s_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_sar_tl(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+
return true;
}
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f691cbcd80..442c7d26a3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -192,47 +192,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SLLW:
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shl_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SLL:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_shl_tl(source1, source1, source2);
- break;
- case OPC_RISC_SLT:
- tcg_gen_setcond_tl(TCG_COND_LT, source1, source1, source2);
- break;
- case OPC_RISC_SLTU:
- tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SRLW:
- /* clear upper 32 */
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shr_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SRL:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_shr_tl(source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SRAW:
- /* first, trick to get it to act like working on 32 bits (get rid of
- upper 32, sign extend to fill space) */
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_sar_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SRA:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_sar_tl(source1, source1, source2);
- break;
CASE_OP_32_64(OPC_RISC_MUL):
tcg_gen_mul_tl(source1, source1, source2);
break;
@@ -653,6 +612,24 @@ static bool trans_arith(DisasContext *ctx, arg_r *a,
return true;
}
+static bool gen_shift(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding
@ 2019-01-22 9:29 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v4 -> v5:
- removed rs2 == 0 special cases in sraw/srlw
target/riscv/insn_trans/trans_rvi.inc.c | 93 +++++++++++++++++--------
target/riscv/translate.c | 59 +++++-----------
2 files changed, 81 insertions(+), 71 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index f52182e9f4..3badb70b1d 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -220,30 +220,25 @@ static bool trans_addi(DisasContext *ctx, arg_addi *a)
return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
}
-static bool trans_slti(DisasContext *ctx, arg_slti *a)
+static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
{
- TCGv source1;
- source1 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
+ tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
+}
+
+static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
+{
+ tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
+}
- tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
- return true;
+static bool trans_slti(DisasContext *ctx, arg_slti *a)
+{
+ return gen_arith_imm(ctx, a, &gen_slt);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
- TCGv source1;
- source1 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
-
- tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
-
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
- return true;
+ return gen_arith_imm(ctx, a, &gen_sltu);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
@@ -322,20 +317,17 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
static bool trans_sll(DisasContext *ctx, arg_sll *a)
{
- gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_shift(ctx, a, &tcg_gen_shl_tl);
}
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_slt);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_sltu);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
@@ -345,14 +337,12 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a)
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
- gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_shift(ctx, a, &tcg_gen_shr_tl);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
- gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_shift(ctx, a, &tcg_gen_sar_tl);
}
static bool trans_or(DisasContext *ctx, arg_or *a)
@@ -419,19 +409,62 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a)
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
- gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shl_tl(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
- gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /* clear upper 32 */
+ tcg_gen_ext32u_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shr_tl(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
- gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /*
+ * first, trick to get it to act like working on 32 bits (get rid of
+ * upper 32, sign extend to fill space)
+ */
+ tcg_gen_ext32s_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_sar_tl(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+
return true;
}
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f691cbcd80..442c7d26a3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -192,47 +192,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SLLW:
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shl_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SLL:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_shl_tl(source1, source1, source2);
- break;
- case OPC_RISC_SLT:
- tcg_gen_setcond_tl(TCG_COND_LT, source1, source1, source2);
- break;
- case OPC_RISC_SLTU:
- tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SRLW:
- /* clear upper 32 */
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shr_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SRL:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_shr_tl(source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SRAW:
- /* first, trick to get it to act like working on 32 bits (get rid of
- upper 32, sign extend to fill space) */
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_sar_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SRA:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_sar_tl(source1, source1, source2);
- break;
CASE_OP_32_64(OPC_RISC_MUL):
tcg_gen_mul_tl(source1, source1, source2);
break;
@@ -653,6 +612,24 @@ static bool trans_arith(DisasContext *ctx, arg_r *a,
return true;
}
+static bool gen_shift(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:29 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvm.inc.c | 55 +++--
target/riscv/translate.c | 283 +++++++++++-------------
2 files changed, 164 insertions(+), 174 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c
index ec3197ede8..949f59ddb2 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -21,80 +21,87 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
- gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_mul_tl);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
{
- gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_muls2_tl(source2, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
- gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_mulhsu);
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
{
- gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_mulu2_tl(source2, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_div(DisasContext *ctx, arg_div *a)
{
- gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_div);
}
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
- gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_divu);
}
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
- gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_rem);
}
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
- gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_remu);
}
#ifdef TARGET_RISCV64
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
- gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_mulw);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
- gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_arith_div_w(ctx, a, &gen_div);
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
{
- gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_arith_div_w(ctx, a, &gen_divu);
}
static bool trans_remw(DisasContext *ctx, arg_remw *a)
{
- gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_arith_div_w(ctx, a, &gen_rem);
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
{
- gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_arith_div_w(ctx, a, &gen_remu);
}
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 442c7d26a3..6a722a0045 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -182,156 +182,112 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(rh);
}
-static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- int rs2)
-{
- TCGv source1, source2, cond1, cond2, zeroreg, resultopt1;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
- gen_get_gpr(source1, rs1);
- gen_get_gpr(source2, rs2);
-
- switch (opc) {
- CASE_OP_32_64(OPC_RISC_MUL):
- tcg_gen_mul_tl(source1, source1, source2);
- break;
- case OPC_RISC_MULH:
- tcg_gen_muls2_tl(source2, source1, source1, source2);
- break;
- case OPC_RISC_MULHSU:
- gen_mulhsu(source1, source1, source2);
- break;
- case OPC_RISC_MULHU:
- tcg_gen_mulu2_tl(source2, source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_DIVW:
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_ext32s_tl(source2, source2);
- /* fall through to DIV */
-#endif
- case OPC_RISC_DIV:
- /* Handle by altering args to tcg_gen_div to produce req'd results:
- * For overflow: want source1 in source1 and 1 in source2
- * For div by zero: want -1 in source1 and 1 in source2 -> -1 result */
- cond1 = tcg_temp_new();
- cond2 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
- ((target_ulong)1) << (TARGET_LONG_BITS - 1));
- tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
- /* if div by zero, set source1 to -1, otherwise don't change */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
- resultopt1);
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_or_tl(cond1, cond1, cond2);
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_div_tl(source1, source1, source2);
-
- tcg_temp_free(cond1);
- tcg_temp_free(cond2);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_DIVUW:
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_ext32u_tl(source2, source2);
- /* fall through to DIVU */
-#endif
- case OPC_RISC_DIVU:
- cond1 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
- tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
- resultopt1);
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_divu_tl(source1, source1, source2);
-
- tcg_temp_free(cond1);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_REMW:
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_ext32s_tl(source2, source2);
- /* fall through to REM */
-#endif
- case OPC_RISC_REM:
- cond1 = tcg_temp_new();
- cond2 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, 1L);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
- (target_ulong)1 << (TARGET_LONG_BITS - 1));
- tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_or_tl(cond2, cond1, cond2);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
- resultopt1);
- tcg_gen_rem_tl(resultopt1, source1, source2);
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt1,
- source1);
-
- tcg_temp_free(cond1);
- tcg_temp_free(cond2);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_REMUW:
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_ext32u_tl(source2, source2);
- /* fall through to REMU */
-#endif
- case OPC_RISC_REMU:
- cond1 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_remu_tl(resultopt1, source1, source2);
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt1,
- source1);
-
- tcg_temp_free(cond1);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
-
- if (opc & 0x8) { /* sign extend for W instructions */
- tcg_gen_ext32s_tl(source1, source1);
- }
-
- gen_set_gpr(rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
+static void gen_div(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, cond2, zeroreg, resultopt1;
+ /*
+ * Handle by altering args to tcg_gen_div to produce req'd results:
+ * For overflow: want source1 in source1 and 1 in source2
+ * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
+ */
+ cond1 = tcg_temp_new();
+ cond2 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
+ ((target_ulong)1) << (TARGET_LONG_BITS - 1));
+ tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
+ /* if div by zero, set source1 to -1, otherwise don't change */
+ tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
+ resultopt1);
+ /* if overflow or div by zero, set source2 to 1, else don't change */
+ tcg_gen_or_tl(cond1, cond1, cond2);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_div_tl(ret, source1, source2);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(cond2);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
+}
+
+static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, zeroreg, resultopt1;
+ cond1 = tcg_temp_new();
+
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
+ resultopt1);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_divu_tl(ret, source1, source2);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
+}
+
+static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, cond2, zeroreg, resultopt1;
+
+ cond1 = tcg_temp_new();
+ cond2 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_movi_tl(resultopt1, 1L);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
+ (target_ulong)1 << (TARGET_LONG_BITS - 1));
+ tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
+ /* if overflow or div by zero, set source2 to 1, else don't change */
+ tcg_gen_or_tl(cond2, cond1, cond2);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
+ resultopt1);
+ tcg_gen_rem_tl(resultopt1, source1, source2);
+ /* if div by zero, just return the original dividend */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
+ source1);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(cond2);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
+}
+
+static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, zeroreg, resultopt1;
+ cond1 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_remu_tl(resultopt1, source1, source2);
+ /* if div by zero, just return the original dividend */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
+ source1);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
}
static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
@@ -592,6 +548,33 @@ static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_ext32s_tl(ret, ret);
}
+static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_mul_tl(ret, arg1, arg2);
+ tcg_gen_ext32s_tl(ret, ret);
+}
+
+static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+ tcg_gen_ext32s_tl(source1, source1);
+ tcg_gen_ext32s_tl(source2, source2);
+
+ (*func)(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
#endif
static bool trans_arith(DisasContext *ctx, arg_r *a,
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn
@ 2019-01-22 9:29 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvm.inc.c | 55 +++--
target/riscv/translate.c | 283 +++++++++++-------------
2 files changed, 164 insertions(+), 174 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c
index ec3197ede8..949f59ddb2 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -21,80 +21,87 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
- gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_mul_tl);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
{
- gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_muls2_tl(source2, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
- gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_mulhsu);
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
{
- gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_mulu2_tl(source2, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_div(DisasContext *ctx, arg_div *a)
{
- gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_div);
}
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
- gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_divu);
}
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
- gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_rem);
}
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
- gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_remu);
}
#ifdef TARGET_RISCV64
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
- gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_mulw);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
- gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_arith_div_w(ctx, a, &gen_div);
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
{
- gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_arith_div_w(ctx, a, &gen_divu);
}
static bool trans_remw(DisasContext *ctx, arg_remw *a)
{
- gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_arith_div_w(ctx, a, &gen_rem);
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
{
- gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_arith_div_w(ctx, a, &gen_remu);
}
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 442c7d26a3..6a722a0045 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -182,156 +182,112 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(rh);
}
-static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- int rs2)
-{
- TCGv source1, source2, cond1, cond2, zeroreg, resultopt1;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
- gen_get_gpr(source1, rs1);
- gen_get_gpr(source2, rs2);
-
- switch (opc) {
- CASE_OP_32_64(OPC_RISC_MUL):
- tcg_gen_mul_tl(source1, source1, source2);
- break;
- case OPC_RISC_MULH:
- tcg_gen_muls2_tl(source2, source1, source1, source2);
- break;
- case OPC_RISC_MULHSU:
- gen_mulhsu(source1, source1, source2);
- break;
- case OPC_RISC_MULHU:
- tcg_gen_mulu2_tl(source2, source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_DIVW:
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_ext32s_tl(source2, source2);
- /* fall through to DIV */
-#endif
- case OPC_RISC_DIV:
- /* Handle by altering args to tcg_gen_div to produce req'd results:
- * For overflow: want source1 in source1 and 1 in source2
- * For div by zero: want -1 in source1 and 1 in source2 -> -1 result */
- cond1 = tcg_temp_new();
- cond2 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
- ((target_ulong)1) << (TARGET_LONG_BITS - 1));
- tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
- /* if div by zero, set source1 to -1, otherwise don't change */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
- resultopt1);
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_or_tl(cond1, cond1, cond2);
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_div_tl(source1, source1, source2);
-
- tcg_temp_free(cond1);
- tcg_temp_free(cond2);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_DIVUW:
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_ext32u_tl(source2, source2);
- /* fall through to DIVU */
-#endif
- case OPC_RISC_DIVU:
- cond1 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
- tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
- resultopt1);
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_divu_tl(source1, source1, source2);
-
- tcg_temp_free(cond1);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_REMW:
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_ext32s_tl(source2, source2);
- /* fall through to REM */
-#endif
- case OPC_RISC_REM:
- cond1 = tcg_temp_new();
- cond2 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, 1L);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
- (target_ulong)1 << (TARGET_LONG_BITS - 1));
- tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_or_tl(cond2, cond1, cond2);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
- resultopt1);
- tcg_gen_rem_tl(resultopt1, source1, source2);
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt1,
- source1);
-
- tcg_temp_free(cond1);
- tcg_temp_free(cond2);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_REMUW:
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_ext32u_tl(source2, source2);
- /* fall through to REMU */
-#endif
- case OPC_RISC_REMU:
- cond1 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_remu_tl(resultopt1, source1, source2);
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt1,
- source1);
-
- tcg_temp_free(cond1);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
-
- if (opc & 0x8) { /* sign extend for W instructions */
- tcg_gen_ext32s_tl(source1, source1);
- }
-
- gen_set_gpr(rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
+static void gen_div(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, cond2, zeroreg, resultopt1;
+ /*
+ * Handle by altering args to tcg_gen_div to produce req'd results:
+ * For overflow: want source1 in source1 and 1 in source2
+ * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
+ */
+ cond1 = tcg_temp_new();
+ cond2 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
+ ((target_ulong)1) << (TARGET_LONG_BITS - 1));
+ tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
+ /* if div by zero, set source1 to -1, otherwise don't change */
+ tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
+ resultopt1);
+ /* if overflow or div by zero, set source2 to 1, else don't change */
+ tcg_gen_or_tl(cond1, cond1, cond2);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_div_tl(ret, source1, source2);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(cond2);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
+}
+
+static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, zeroreg, resultopt1;
+ cond1 = tcg_temp_new();
+
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
+ resultopt1);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_divu_tl(ret, source1, source2);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
+}
+
+static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, cond2, zeroreg, resultopt1;
+
+ cond1 = tcg_temp_new();
+ cond2 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_movi_tl(resultopt1, 1L);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
+ (target_ulong)1 << (TARGET_LONG_BITS - 1));
+ tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
+ /* if overflow or div by zero, set source2 to 1, else don't change */
+ tcg_gen_or_tl(cond2, cond1, cond2);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
+ resultopt1);
+ tcg_gen_rem_tl(resultopt1, source1, source2);
+ /* if div by zero, just return the original dividend */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
+ source1);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(cond2);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
+}
+
+static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, zeroreg, resultopt1;
+ cond1 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_remu_tl(resultopt1, source1, source2);
+ /* if div by zero, just return the original dividend */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
+ source1);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
}
static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
@@ -592,6 +548,33 @@ static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_ext32s_tl(ret, ret);
}
+static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_mul_tl(ret, arg1, arg2);
+ tcg_gen_ext32s_tl(ret, ret);
+}
+
+static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+ tcg_gen_ext32s_tl(source1, source1);
+ tcg_gen_ext32s_tl(source2, source2);
+
+ (*func)(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
#endif
static bool trans_arith(DisasContext *ctx, arg_r *a,
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:29 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 18 +++++++++---------
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++++++-------
target/riscv/translate.c | 4 ++--
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 3badb70b1d..5a09ee556f 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -307,12 +307,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
- return trans_arith(ctx, a, &tcg_gen_add_tl);
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
- return trans_arith(ctx, a, &tcg_gen_sub_tl);
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -322,17 +322,17 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- return trans_arith(ctx, a, &gen_slt);
+ return gen_arith(ctx, a, &gen_slt);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- return trans_arith(ctx, a, &gen_sltu);
+ return gen_arith(ctx, a, &gen_sltu);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
- return trans_arith(ctx, a, &tcg_gen_xor_tl);
+ return gen_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -347,12 +347,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
- return trans_arith(ctx, a, &tcg_gen_or_tl);
+ return gen_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
- return trans_arith(ctx, a, &tcg_gen_and_tl);
+ return gen_arith(ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
@@ -399,12 +399,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
- return trans_arith(ctx, a, &gen_addw);
+ return gen_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
- return trans_arith(ctx, a, &gen_subw);
+ return gen_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c
index 949f59ddb2..5844d6f5be 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -21,7 +21,7 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
- return trans_arith(ctx, a, &tcg_gen_mul_tl);
+ return gen_arith(ctx, a, &tcg_gen_mul_tl);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
@@ -41,7 +41,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
- return trans_arith(ctx, a, &gen_mulhsu);
+ return gen_arith(ctx, a, &gen_mulhsu);
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
@@ -61,28 +61,28 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
static bool trans_div(DisasContext *ctx, arg_div *a)
{
- return trans_arith(ctx, a, &gen_div);
+ return gen_arith(ctx, a, &gen_div);
}
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
- return trans_arith(ctx, a, &gen_divu);
+ return gen_arith(ctx, a, &gen_divu);
}
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
- return trans_arith(ctx, a, &gen_rem);
+ return gen_arith(ctx, a, &gen_rem);
}
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
- return trans_arith(ctx, a, &gen_remu);
+ return gen_arith(ctx, a, &gen_remu);
}
#ifdef TARGET_RISCV64
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
- return trans_arith(ctx, a, &gen_mulw);
+ return gen_arith(ctx, a, &gen_mulw);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6a722a0045..d0b0fca12b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -577,8 +577,8 @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
#endif
-static bool trans_arith(DisasContext *ctx, arg_r *a,
- void(*func)(TCGv, TCGv, TCGv))
+static bool gen_arith(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith
@ 2019-01-22 9:29 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 18 +++++++++---------
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++++++-------
target/riscv/translate.c | 4 ++--
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 3badb70b1d..5a09ee556f 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -307,12 +307,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
- return trans_arith(ctx, a, &tcg_gen_add_tl);
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
- return trans_arith(ctx, a, &tcg_gen_sub_tl);
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -322,17 +322,17 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- return trans_arith(ctx, a, &gen_slt);
+ return gen_arith(ctx, a, &gen_slt);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- return trans_arith(ctx, a, &gen_sltu);
+ return gen_arith(ctx, a, &gen_sltu);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
- return trans_arith(ctx, a, &tcg_gen_xor_tl);
+ return gen_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -347,12 +347,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
- return trans_arith(ctx, a, &tcg_gen_or_tl);
+ return gen_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
- return trans_arith(ctx, a, &tcg_gen_and_tl);
+ return gen_arith(ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
@@ -399,12 +399,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
- return trans_arith(ctx, a, &gen_addw);
+ return gen_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
- return trans_arith(ctx, a, &gen_subw);
+ return gen_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c
index 949f59ddb2..5844d6f5be 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -21,7 +21,7 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
- return trans_arith(ctx, a, &tcg_gen_mul_tl);
+ return gen_arith(ctx, a, &tcg_gen_mul_tl);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
@@ -41,7 +41,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
- return trans_arith(ctx, a, &gen_mulhsu);
+ return gen_arith(ctx, a, &gen_mulhsu);
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
@@ -61,28 +61,28 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
static bool trans_div(DisasContext *ctx, arg_div *a)
{
- return trans_arith(ctx, a, &gen_div);
+ return gen_arith(ctx, a, &gen_div);
}
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
- return trans_arith(ctx, a, &gen_divu);
+ return gen_arith(ctx, a, &gen_divu);
}
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
- return trans_arith(ctx, a, &gen_rem);
+ return gen_arith(ctx, a, &gen_rem);
}
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
- return trans_arith(ctx, a, &gen_remu);
+ return gen_arith(ctx, a, &gen_remu);
}
#ifdef TARGET_RISCV64
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
- return trans_arith(ctx, a, &gen_mulw);
+ return gen_arith(ctx, a, &gen_mulw);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6a722a0045..d0b0fca12b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -577,8 +577,8 @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
#endif
-static bool trans_arith(DisasContext *ctx, arg_r *a,
- void(*func)(TCGv, TCGv, TCGv))
+static bool gen_arith(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system()
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:29 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/translate.c | 31 -------------------------------
1 file changed, 31 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d0b0fca12b..0e37beb68e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -427,32 +427,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int csr)
-{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
- switch (opc) {
- case OPC_RISC_ECALL:
- switch (csr) {
- case 0x0: /* ECALL */
- /* always generates U-level ECALL, fixed in do_interrupt handler */
- generate_exception(ctx, RISCV_EXCP_U_ECALL);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x1: /* EBREAK */
- generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- break;
- }
-}
static void decode_RV32_64C0(DisasContext *ctx)
{
@@ -628,7 +602,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
- int rs1, rd;
uint32_t op;
/* We do not do misaligned address check here: the address should never be
@@ -637,13 +610,9 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
* perform the misaligned instruction fetch */
op = MASK_OP_MAJOR(ctx->opcode);
- rs1 = GET_RS1(ctx->opcode);
- rd = GET_RD(ctx->opcode);
switch (op) {
case OPC_RISC_SYSTEM:
- gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
- (ctx->opcode & 0xFFF00000) >> 20);
break;
default:
gen_exception_illegal(ctx);
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 29/35] target/riscv: Remove gen_system()
@ 2019-01-22 9:29 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/translate.c | 31 -------------------------------
1 file changed, 31 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d0b0fca12b..0e37beb68e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -427,32 +427,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int csr)
-{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
- switch (opc) {
- case OPC_RISC_ECALL:
- switch (csr) {
- case 0x0: /* ECALL */
- /* always generates U-level ECALL, fixed in do_interrupt handler */
- generate_exception(ctx, RISCV_EXCP_U_ECALL);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x1: /* EBREAK */
- generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- break;
- }
-}
static void decode_RV32_64C0(DisasContext *ctx)
{
@@ -628,7 +602,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
- int rs1, rd;
uint32_t op;
/* We do not do misaligned address check here: the address should never be
@@ -637,13 +610,9 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
* perform the misaligned instruction fetch */
op = MASK_OP_MAJOR(ctx->opcode);
- rs1 = GET_RS1(ctx->opcode);
- rd = GET_RD(ctx->opcode);
switch (op) {
case OPC_RISC_SYSTEM:
- gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
- (ctx->opcode & 0xFFF00000) >> 20);
break;
default:
gen_exception_illegal(ctx);
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G()
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:29 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/translate.c | 23 +----------------------
1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0e37beb68e..b0251b3518 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -600,26 +600,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
-static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
-{
- uint32_t op;
-
- /* We do not do misaligned address check here: the address should never be
- * misaligned at this point. Instructions that set PC must do the check,
- * since epc must be the address of the instruction that caused us to
- * perform the misaligned instruction fetch */
-
- op = MASK_OP_MAJOR(ctx->opcode);
-
- switch (op) {
- case OPC_RISC_SYSTEM:
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
@@ -636,8 +616,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, ctx->opcode)) {
- /* fallback to old decoder */
- decode_RV32_64G(ctx->env, ctx);
+ gen_exception_illegal(ctx);
}
}
}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G()
@ 2019-01-22 9:29 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/translate.c | 23 +----------------------
1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0e37beb68e..b0251b3518 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -600,26 +600,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
-static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
-{
- uint32_t op;
-
- /* We do not do misaligned address check here: the address should never be
- * misaligned at this point. Instructions that set PC must do the check,
- * since epc must be the address of the instruction that caused us to
- * perform the misaligned instruction fetch */
-
- op = MASK_OP_MAJOR(ctx->opcode);
-
- switch (op) {
- case OPC_RISC_SYSTEM:
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
@@ -636,8 +616,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, ctx->opcode)) {
- /* fallback to old decoder */
- decode_RV32_64G(ctx->env, ctx);
+ gen_exception_illegal(ctx);
}
}
}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:29 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
These all expand simply to R format instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/Makefile.objs | 10 +++---
target/riscv/insn16-64.decode | 24 ++++++++++++++
target/riscv/insn16.decode | 15 +++++----
target/riscv/insn_trans/trans_rvc.inc.c | 44 -------------------------
target/riscv/translate.c | 20 ++++++++---
5 files changed, 54 insertions(+), 59 deletions(-)
create mode 100644 target/riscv/insn16-64.decode
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 9c6c109327..990bd89016 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -5,16 +5,18 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
+decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
+decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
+
target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(call quiet-command, \
$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
"GEN", $(TARGET_DIR)$@)
-target/riscv/decode_insn16.inc.c: \
- $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
$(call quiet-command, \
- $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
- "GEN", $(TARGET_DIR)$@)
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 \
+ $(decode16-y), "GEN", $(TARGET_DIR)$@)
target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
target/riscv/decode_insn16.inc.c
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
new file mode 100644
index 0000000000..5af2e2b072
--- /dev/null
+++ b/target/riscv/insn16-64.decode
@@ -0,0 +1,24 @@
+#
+# RISC-V translation routines for the RVC Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This is concatenated with insn16.decode for risc64 targets.
+# All of the fields and formats are there.
+
+# *** RV64C Standard Extension (Quadrant 1) ***
+subw 100 1 11 ... 00 ... 01 @cs_2
+addw 100 1 11 ... 01 ... 01 @cs_2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 0829e3bc59..c7a58d80e5 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -41,6 +41,9 @@
+# Argument sets imported from insn32.decode:
+&r rd rs1 rs2 !extern
+
# Argument sets:
&cl rs1 rd
&cl_dw uimm rs1 rd
@@ -68,7 +71,7 @@
@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
-@cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3
+@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
@@ -107,12 +110,10 @@ c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
c_srli 100 . 00 ... ..... 01 @c_shift
c_srai 100 . 01 ... ..... 01 @c_shift
c_andi 100 . 10 ... ..... 01 @c_andi
-c_sub 100 0 11 ... 00 ... 01 @cs_2
-c_xor 100 0 11 ... 01 ... 01 @cs_2
-c_or 100 0 11 ... 10 ... 01 @cs_2
-c_and 100 0 11 ... 11 ... 01 @cs_2
-c_subw 100 1 11 ... 00 ... 01 @cs_2
-c_addw 100 1 11 ... 01 ... 01 @cs_2
+sub 100 0 11 ... 00 ... 01 @cs_2
+xor 100 0 11 ... 01 ... 01 @cs_2
+or 100 0 11 ... 10 ... 01 @cs_2
+and 100 0 11 ... 11 ... 01 @cs_2
c_j 101 ........... 01 @cj
c_beqz 110 ... ... ..... 01 @cb
c_bnez 111 ... ... ..... 01 @cb
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index bcdf64d3b7..639c381edf 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -163,50 +163,6 @@ static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
return trans_andi(ctx, &arg);
}
-static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
-{
- arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_sub(ctx, &arg);
-}
-
-static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
-{
- arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_xor(ctx, &arg);
-}
-
-static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
-{
- arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_or(ctx, &arg);
-}
-
-static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
-{
- arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_and(ctx, &arg);
-}
-
-static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
-{
-#ifdef TARGET_RISCV64
- arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_subw(ctx, &arg);
-#else
- return false;
-#endif
-}
-
-static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
-{
-#ifdef TARGET_RISCV64
- arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_addw(ctx, &arg);
-#else
- return false;
-#endif
-}
-
static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
{
arg_jal arg = { .rd = 0, .imm = a->imm };
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b0251b3518..5079c68b18 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -487,10 +487,25 @@ static int ex_rvc_register(int reg)
return 8 + reg;
}
+/*
+ * Include the auto-generated decoders.
+ * Note that the 16-bit decoder reuses some of the trans_* functions
+ * from the 32-bit decoder, which results in duplicate declarations
+ * of the relevant helpers. Suppress the warning.
+ */
bool decode_insn32(DisasContext *ctx, uint32_t insn);
-/* Include the auto-generated decoder for 32 bit insn */
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
+
#include "decode_insn32.inc.c"
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+
+#include "decode_insn16.inc.c"
+
+#pragma GCC diagnostic pop
+
+
static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
void(*func)(TCGv, TCGv, TCGv))
{
@@ -595,9 +610,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
#include "insn_trans/trans_rvd.inc.c"
#include "insn_trans/trans_privileged.inc.c"
-bool decode_insn16(DisasContext *ctx, uint16_t insn);
-/* auto-generated decoder*/
-#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
static void decode_opc(DisasContext *ctx)
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions
@ 2019-01-22 9:29 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
These all expand simply to R format instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/Makefile.objs | 10 +++---
target/riscv/insn16-64.decode | 24 ++++++++++++++
target/riscv/insn16.decode | 15 +++++----
target/riscv/insn_trans/trans_rvc.inc.c | 44 -------------------------
target/riscv/translate.c | 20 ++++++++---
5 files changed, 54 insertions(+), 59 deletions(-)
create mode 100644 target/riscv/insn16-64.decode
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 9c6c109327..990bd89016 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -5,16 +5,18 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
+decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
+decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
+
target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(call quiet-command, \
$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
"GEN", $(TARGET_DIR)$@)
-target/riscv/decode_insn16.inc.c: \
- $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
$(call quiet-command, \
- $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
- "GEN", $(TARGET_DIR)$@)
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 \
+ $(decode16-y), "GEN", $(TARGET_DIR)$@)
target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
target/riscv/decode_insn16.inc.c
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
new file mode 100644
index 0000000000..5af2e2b072
--- /dev/null
+++ b/target/riscv/insn16-64.decode
@@ -0,0 +1,24 @@
+#
+# RISC-V translation routines for the RVC Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This is concatenated with insn16.decode for risc64 targets.
+# All of the fields and formats are there.
+
+# *** RV64C Standard Extension (Quadrant 1) ***
+subw 100 1 11 ... 00 ... 01 @cs_2
+addw 100 1 11 ... 01 ... 01 @cs_2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 0829e3bc59..c7a58d80e5 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -41,6 +41,9 @@
+# Argument sets imported from insn32.decode:
+&r rd rs1 rs2 !extern
+
# Argument sets:
&cl rs1 rd
&cl_dw uimm rs1 rd
@@ -68,7 +71,7 @@
@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
-@cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3
+@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
@@ -107,12 +110,10 @@ c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
c_srli 100 . 00 ... ..... 01 @c_shift
c_srai 100 . 01 ... ..... 01 @c_shift
c_andi 100 . 10 ... ..... 01 @c_andi
-c_sub 100 0 11 ... 00 ... 01 @cs_2
-c_xor 100 0 11 ... 01 ... 01 @cs_2
-c_or 100 0 11 ... 10 ... 01 @cs_2
-c_and 100 0 11 ... 11 ... 01 @cs_2
-c_subw 100 1 11 ... 00 ... 01 @cs_2
-c_addw 100 1 11 ... 01 ... 01 @cs_2
+sub 100 0 11 ... 00 ... 01 @cs_2
+xor 100 0 11 ... 01 ... 01 @cs_2
+or 100 0 11 ... 10 ... 01 @cs_2
+and 100 0 11 ... 11 ... 01 @cs_2
c_j 101 ........... 01 @cj
c_beqz 110 ... ... ..... 01 @cb
c_bnez 111 ... ... ..... 01 @cb
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index bcdf64d3b7..639c381edf 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -163,50 +163,6 @@ static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
return trans_andi(ctx, &arg);
}
-static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
-{
- arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_sub(ctx, &arg);
-}
-
-static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
-{
- arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_xor(ctx, &arg);
-}
-
-static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
-{
- arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_or(ctx, &arg);
-}
-
-static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
-{
- arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_and(ctx, &arg);
-}
-
-static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
-{
-#ifdef TARGET_RISCV64
- arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_subw(ctx, &arg);
-#else
- return false;
-#endif
-}
-
-static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
-{
-#ifdef TARGET_RISCV64
- arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_addw(ctx, &arg);
-#else
- return false;
-#endif
-}
-
static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
{
arg_jal arg = { .rd = 0, .imm = a->imm };
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b0251b3518..5079c68b18 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -487,10 +487,25 @@ static int ex_rvc_register(int reg)
return 8 + reg;
}
+/*
+ * Include the auto-generated decoders.
+ * Note that the 16-bit decoder reuses some of the trans_* functions
+ * from the 32-bit decoder, which results in duplicate declarations
+ * of the relevant helpers. Suppress the warning.
+ */
bool decode_insn32(DisasContext *ctx, uint32_t insn);
-/* Include the auto-generated decoder for 32 bit insn */
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
+
#include "decode_insn32.inc.c"
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+
+#include "decode_insn16.inc.c"
+
+#pragma GCC diagnostic pop
+
+
static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
void(*func)(TCGv, TCGv, TCGv))
{
@@ -595,9 +610,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
#include "insn_trans/trans_rvd.inc.c"
#include "insn_trans/trans_privileged.inc.c"
-bool decode_insn16(DisasContext *ctx, uint16_t insn);
-/* auto-generated decoder*/
-#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
static void decode_opc(DisasContext *ctx)
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:29 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/insn16.decode | 20 ++++++++++----------
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvc.inc.c | 24 ------------------------
3 files changed, 12 insertions(+), 35 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index c7a58d80e5..c215867ff9 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -43,14 +43,14 @@
# Argument sets imported from insn32.decode:
&r rd rs1 rs2 !extern
+&i imm rs1 rd !extern
+&s imm rs1 rs2 !extern
# Argument sets:
&cl rs1 rd
-&cl_dw uimm rs1 rd
&ci imm rd
&ciw nzuimm rd
&cs rs1 rs2
-&cs_dw uimm rs1 rs2
&cb imm rs1
&cr rd rs2
&c_j imm
@@ -67,13 +67,13 @@
@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd
@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
-@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
-@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
+@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
+@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
-@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
-@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
+@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
+@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
@cj ... ........... .. &c_j imm=%imm_cj
@@ -95,11 +95,11 @@
# *** RV64C Standard Extension (Quadrant 0) ***
c_addi4spn 000 ........ ... 00 @ciw
-c_fld 001 ... ... .. ... 00 @cl_d
-c_lw 010 ... ... .. ... 00 @cl_w
+fld 001 ... ... .. ... 00 @cl_d
+lw 010 ... ... .. ... 00 @cl_w
c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
-c_fsd 101 ... ... .. ... 00 @cs_d
-c_sw 110 ... ... .. ... 00 @cs_w
+fsd 101 ... ... .. ... 00 @cs_d
+sw 110 ... ... .. ... 00 @cs_w
c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
# *** RV64C Standard Extension (Quadrant 1) ***
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6f3ab7aa52..b59a00cc42 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -37,6 +37,7 @@
&b imm rs2 rs1
&i imm rs1 rd
&r rd rs1 rs2
+&s imm rs2 rs1
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
@@ -44,7 +45,7 @@
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
-@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
+@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
@j .................... ..... ....... imm=%imm_j %rd
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index 639c381edf..d932bfd3e0 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
return trans_addi(ctx, &arg);
}
-static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
-{
- arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
- return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
-{
- arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
- return trans_lw(ctx, &arg);
-}
-
static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
{
#ifdef TARGET_RISCV32
@@ -51,18 +39,6 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
#endif
}
-static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
-{
- arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
- return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
-{
- arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
- return trans_sw(ctx, &arg);
-}
-
static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
{
#ifdef TARGET_RISCV32
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
@ 2019-01-22 9:29 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/insn16.decode | 20 ++++++++++----------
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvc.inc.c | 24 ------------------------
3 files changed, 12 insertions(+), 35 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index c7a58d80e5..c215867ff9 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -43,14 +43,14 @@
# Argument sets imported from insn32.decode:
&r rd rs1 rs2 !extern
+&i imm rs1 rd !extern
+&s imm rs1 rs2 !extern
# Argument sets:
&cl rs1 rd
-&cl_dw uimm rs1 rd
&ci imm rd
&ciw nzuimm rd
&cs rs1 rs2
-&cs_dw uimm rs1 rs2
&cb imm rs1
&cr rd rs2
&c_j imm
@@ -67,13 +67,13 @@
@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd
@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
-@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
-@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
+@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
+@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
-@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
-@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
+@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
+@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
@cj ... ........... .. &c_j imm=%imm_cj
@@ -95,11 +95,11 @@
# *** RV64C Standard Extension (Quadrant 0) ***
c_addi4spn 000 ........ ... 00 @ciw
-c_fld 001 ... ... .. ... 00 @cl_d
-c_lw 010 ... ... .. ... 00 @cl_w
+fld 001 ... ... .. ... 00 @cl_d
+lw 010 ... ... .. ... 00 @cl_w
c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
-c_fsd 101 ... ... .. ... 00 @cs_d
-c_sw 110 ... ... .. ... 00 @cs_w
+fsd 101 ... ... .. ... 00 @cs_d
+sw 110 ... ... .. ... 00 @cs_w
c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
# *** RV64C Standard Extension (Quadrant 1) ***
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6f3ab7aa52..b59a00cc42 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -37,6 +37,7 @@
&b imm rs2 rs1
&i imm rs1 rd
&r rd rs1 rs2
+&s imm rs2 rs1
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
@@ -44,7 +45,7 @@
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
-@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
+@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
@j .................... ..... ....... imm=%imm_j %rd
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index 639c381edf..d932bfd3e0 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
return trans_addi(ctx, &arg);
}
-static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
-{
- arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
- return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
-{
- arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
- return trans_lw(ctx, &arg);
-}
-
static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
{
#ifdef TARGET_RISCV32
@@ -51,18 +39,6 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
#endif
}
-static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
-{
- arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
- return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
-{
- arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
- return trans_sw(ctx, &arg);
-}
-
static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
{
#ifdef TARGET_RISCV32
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:29 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
this finally removes the old decoder functions that we carried along
with it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/Makefile.objs | 1 +
target/riscv/insn16-32.decode | 24 ++++
target/riscv/insn16-64.decode | 4 +
target/riscv/insn16.decode | 7 +-
target/riscv/insn_trans/trans_rvc.inc.c | 22 ----
target/riscv/translate.c | 165 +-----------------------
6 files changed, 31 insertions(+), 192 deletions(-)
create mode 100644 target/riscv/insn16-32.decode
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 990bd89016..a31a9ea061 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -6,6 +6,7 @@ decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
+decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
new file mode 100644
index 0000000000..e21a701056
--- /dev/null
+++ b/target/riscv/insn16-32.decode
@@ -0,0 +1,24 @@
+#
+# RISC-V translation routines for the RVC Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This is concatenated with insn16.decode for risc32 targets.
+# All of the fields and formats are there.
+
+# *** RV32C Standard Extension (Quadrant 0) ***
+flw 011 ... ... .. ... 00 @cl_w
+fsw 111 ... ... .. ... 00 @cs_w
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
index 5af2e2b072..de97a45acf 100644
--- a/target/riscv/insn16-64.decode
+++ b/target/riscv/insn16-64.decode
@@ -19,6 +19,10 @@
# This is concatenated with insn16.decode for risc64 targets.
# All of the fields and formats are there.
+# *** RV64C Standard Extension (Quadrant 0) ***
+ld 011 ... ... .. ... 00 @cl_d
+sd 111 ... ... .. ... 00 @cs_d
+
# *** RV64C Standard Extension (Quadrant 1) ***
subw 100 1 11 ... 00 ... 01 @cs_2
addw 100 1 11 ... 01 ... 01 @cs_2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index c215867ff9..b075336062 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -47,10 +47,9 @@
&s imm rs1 rs2 !extern
# Argument sets:
-&cl rs1 rd
&ci imm rd
&ciw nzuimm rd
-&cs rs1 rs2
+&cs_dw uimm rs1 rs2
&cb imm rs1
&cr rd rs2
&c_j imm
@@ -69,8 +68,6 @@
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
-@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
-@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@@ -97,10 +94,8 @@
c_addi4spn 000 ........ ... 00 @ciw
fld 001 ... ... .. ... 00 @cl_d
lw 010 ... ... .. ... 00 @cl_w
-c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
fsd 101 ... ... .. ... 00 @cs_d
sw 110 ... ... .. ... 00 @cs_w
-c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
# *** RV64C Standard Extension (Quadrant 1) ***
c_addi 000 . ..... ..... 01 @ci
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index d932bfd3e0..f521daf32e 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -28,28 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
return trans_addi(ctx, &arg);
}
-static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FLW ( RV32FC-only ) */
- return false;
-#else
- /* C.LD ( RV64C/RV128C-only ) */
- return false;
-#endif
-}
-
-static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FSW ( RV32FC-only ) */
- return false;
-#else
- /* C.SD ( RV64C/RV128C-only ) */
- return false;
-#endif
-}
-
static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
{
if (a->imm == 0) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5079c68b18..9b8b53a9db 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -55,22 +55,6 @@ typedef struct DisasContext {
CPURISCVState *env;
} DisasContext;
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
- [0 ... 7] = -1,
- [0] = MO_SB,
- [1] = MO_TESW,
- [2] = MO_TESL,
- [4] = MO_UB,
- [5] = MO_TEUW,
-#ifdef TARGET_RISCV64
- [3] = MO_TEQ,
- [6] = MO_TEUL,
-#endif
-};
-#endif
-
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
#else
@@ -311,109 +295,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
- gen_set_gpr(rd, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- gen_get_gpr(dat, rs2);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
- tcg_temp_free(t0);
- tcg_temp_free(dat);
-}
-#endif
-
-#ifdef TARGET_RISCV32
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, target_long imm)
-{
- TCGv t0;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- gen_exception_illegal(ctx);
- return;
- }
-
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
-
- switch (opc) {
- case OPC_RISC_FLW:
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
- /* RISC-V requires NaN-boxing of narrower width floating point values */
- tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
- break;
- case OPC_RISC_FLD:
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
- int rs2, target_long imm)
-{
- TCGv t0;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- gen_exception_illegal(ctx);
- return;
- }
-
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
-
- switch (opc) {
- case OPC_RISC_FSW:
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
- break;
- case OPC_RISC_FSD:
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-
- tcg_temp_free(t0);
-}
-#endif
-
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
@@ -428,49 +309,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
}
-static void decode_RV32_64C0(DisasContext *ctx)
-{
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
- uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode);
- uint8_t rs1s = GET_C_RS1S(ctx->opcode);
-
- switch (funct3) {
- case 3:
-#if defined(TARGET_RISCV64)
- /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
- gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
- GET_C_LD_IMM(ctx->opcode));
-#else
- /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
- gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
- GET_C_LW_IMM(ctx->opcode));
-#endif
- break;
- case 7:
-#if defined(TARGET_RISCV64)
- /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
- gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
- GET_C_LD_IMM(ctx->opcode));
-#else
- /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
- gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
- GET_C_LW_IMM(ctx->opcode));
-#endif
- break;
- }
-}
-
-static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
-{
- uint8_t op = extract32(ctx->opcode, 0, 2);
-
- switch (op) {
- case 0:
- decode_RV32_64C0(ctx);
- break;
- }
-}
-
#define EX_SH(amount) \
static int ex_shift_##amount(int imm) \
{ \
@@ -621,8 +459,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (!decode_insn16(ctx, ctx->opcode)) {
- /* fall back to old decoder */
- decode_RV32_64C(ctx->env, ctx);
+ gen_exception_illegal(ctx);
}
}
} else {
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
@ 2019-01-22 9:29 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
this finally removes the old decoder functions that we carried along
with it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/Makefile.objs | 1 +
target/riscv/insn16-32.decode | 24 ++++
target/riscv/insn16-64.decode | 4 +
target/riscv/insn16.decode | 7 +-
target/riscv/insn_trans/trans_rvc.inc.c | 22 ----
target/riscv/translate.c | 165 +-----------------------
6 files changed, 31 insertions(+), 192 deletions(-)
create mode 100644 target/riscv/insn16-32.decode
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 990bd89016..a31a9ea061 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -6,6 +6,7 @@ decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
+decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
new file mode 100644
index 0000000000..e21a701056
--- /dev/null
+++ b/target/riscv/insn16-32.decode
@@ -0,0 +1,24 @@
+#
+# RISC-V translation routines for the RVC Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This is concatenated with insn16.decode for risc32 targets.
+# All of the fields and formats are there.
+
+# *** RV32C Standard Extension (Quadrant 0) ***
+flw 011 ... ... .. ... 00 @cl_w
+fsw 111 ... ... .. ... 00 @cs_w
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
index 5af2e2b072..de97a45acf 100644
--- a/target/riscv/insn16-64.decode
+++ b/target/riscv/insn16-64.decode
@@ -19,6 +19,10 @@
# This is concatenated with insn16.decode for risc64 targets.
# All of the fields and formats are there.
+# *** RV64C Standard Extension (Quadrant 0) ***
+ld 011 ... ... .. ... 00 @cl_d
+sd 111 ... ... .. ... 00 @cs_d
+
# *** RV64C Standard Extension (Quadrant 1) ***
subw 100 1 11 ... 00 ... 01 @cs_2
addw 100 1 11 ... 01 ... 01 @cs_2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index c215867ff9..b075336062 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -47,10 +47,9 @@
&s imm rs1 rs2 !extern
# Argument sets:
-&cl rs1 rd
&ci imm rd
&ciw nzuimm rd
-&cs rs1 rs2
+&cs_dw uimm rs1 rs2
&cb imm rs1
&cr rd rs2
&c_j imm
@@ -69,8 +68,6 @@
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
-@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
-@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@@ -97,10 +94,8 @@
c_addi4spn 000 ........ ... 00 @ciw
fld 001 ... ... .. ... 00 @cl_d
lw 010 ... ... .. ... 00 @cl_w
-c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
fsd 101 ... ... .. ... 00 @cs_d
sw 110 ... ... .. ... 00 @cs_w
-c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
# *** RV64C Standard Extension (Quadrant 1) ***
c_addi 000 . ..... ..... 01 @ci
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index d932bfd3e0..f521daf32e 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -28,28 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
return trans_addi(ctx, &arg);
}
-static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FLW ( RV32FC-only ) */
- return false;
-#else
- /* C.LD ( RV64C/RV128C-only ) */
- return false;
-#endif
-}
-
-static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FSW ( RV32FC-only ) */
- return false;
-#else
- /* C.SD ( RV64C/RV128C-only ) */
- return false;
-#endif
-}
-
static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
{
if (a->imm == 0) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5079c68b18..9b8b53a9db 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -55,22 +55,6 @@ typedef struct DisasContext {
CPURISCVState *env;
} DisasContext;
-#ifdef TARGET_RISCV64
-/* convert riscv funct3 to qemu memop for load/store */
-static const int tcg_memop_lookup[8] = {
- [0 ... 7] = -1,
- [0] = MO_SB,
- [1] = MO_TESW,
- [2] = MO_TESL,
- [4] = MO_UB,
- [5] = MO_TEUW,
-#ifdef TARGET_RISCV64
- [3] = MO_TEQ,
- [6] = MO_TEUL,
-#endif
-};
-#endif
-
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
#else
@@ -311,109 +295,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-#ifdef TARGET_RISCV64
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
- gen_set_gpr(rd, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- gen_get_gpr(dat, rs2);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
- tcg_temp_free(t0);
- tcg_temp_free(dat);
-}
-#endif
-
-#ifdef TARGET_RISCV32
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, target_long imm)
-{
- TCGv t0;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- gen_exception_illegal(ctx);
- return;
- }
-
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
-
- switch (opc) {
- case OPC_RISC_FLW:
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
- /* RISC-V requires NaN-boxing of narrower width floating point values */
- tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
- break;
- case OPC_RISC_FLD:
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
- int rs2, target_long imm)
-{
- TCGv t0;
-
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
- gen_exception_illegal(ctx);
- return;
- }
-
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
-
- switch (opc) {
- case OPC_RISC_FSW:
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
- break;
- case OPC_RISC_FSD:
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
-
- tcg_temp_free(t0);
-}
-#endif
-
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
@@ -428,49 +309,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
}
-static void decode_RV32_64C0(DisasContext *ctx)
-{
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
- uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode);
- uint8_t rs1s = GET_C_RS1S(ctx->opcode);
-
- switch (funct3) {
- case 3:
-#if defined(TARGET_RISCV64)
- /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
- gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
- GET_C_LD_IMM(ctx->opcode));
-#else
- /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
- gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
- GET_C_LW_IMM(ctx->opcode));
-#endif
- break;
- case 7:
-#if defined(TARGET_RISCV64)
- /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
- gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
- GET_C_LD_IMM(ctx->opcode));
-#else
- /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
- gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
- GET_C_LW_IMM(ctx->opcode));
-#endif
- break;
- }
-}
-
-static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
-{
- uint8_t op = extract32(ctx->opcode, 0, 2);
-
- switch (op) {
- case 0:
- decode_RV32_64C0(ctx);
- break;
- }
-}
-
#define EX_SH(amount) \
static int ex_shift_##amount(int imm) \
{ \
@@ -621,8 +459,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (!decode_insn16(ctx, ctx->opcode)) {
- /* fall back to old decoder */
- decode_RV32_64C(ctx->env, ctx);
+ gen_exception_illegal(ctx);
}
}
} else {
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:29 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
it splices flwsp_ldsp, fswsp_sdsp, and jal_addiw and makes each of them
reuse the code generator used for the non compressed insns.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/insn16-32.decode | 7 +++++
target/riscv/insn16-64.decode | 5 ++++
target/riscv/insn16.decode | 12 ++------
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvc.inc.c | 40 -------------------------
5 files changed, 16 insertions(+), 51 deletions(-)
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
index e21a701056..978b8d5834 100644
--- a/target/riscv/insn16-32.decode
+++ b/target/riscv/insn16-32.decode
@@ -22,3 +22,10 @@
# *** RV32C Standard Extension (Quadrant 0) ***
flw 011 ... ... .. ... 00 @cl_w
fsw 111 ... ... .. ... 00 @cs_w
+
+# *** RV32C Standard Extension (Quadrant 1) ***
+jal 001 ...... ..... 01 &j imm=%imm_cj rd=1
+
+# *** RV32C Standard Extension (Quadrant 2) ***
+flw 011 . ..... ..... 10 &i imm=%uimm_6bit_lw %rd rs1=2
+fsw 111 ...... ..... 10 &s imm=%uimm_6bit_sw rs2=2 rs1=%rs2_5
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
index de97a45acf..d43055837a 100644
--- a/target/riscv/insn16-64.decode
+++ b/target/riscv/insn16-64.decode
@@ -24,5 +24,10 @@ ld 011 ... ... .. ... 00 @cl_d
sd 111 ... ... .. ... 00 @cs_d
# *** RV64C Standard Extension (Quadrant 1) ***
+addiw 001 . ..... ..... 01 @ci
subw 100 1 11 ... 00 ... 01 @cs_2
addw 100 1 11 ... 01 ... 01 @cs_2
+
+# *** RV64C Standard Extension (Quadrant 2) ***
+ld 011 . ..... ..... 10 &i imm=%uimm_6bit_ld %rd rs1=2
+sd 111 ...... ..... 10 &s imm=%uimm_6bit_sd rs2=%rs2_5 rs1=2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index b075336062..98dd672c7f 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -45,6 +45,7 @@
&r rd rs1 rs2 !extern
&i imm rs1 rd !extern
&s imm rs1 rs2 !extern
+&j imm rd !extern
# Argument sets:
&ci imm rd
@@ -59,12 +60,10 @@
&c_sd uimm rs2
&c_addi16sp_lui imm_lui imm_addi16sp rd
-&c_flwsp_ldsp uimm_flwsp uimm_ldsp rd
-&c_fswsp_sdsp uimm_fswsp uimm_sdsp rs2
# Formats 16:
@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd
-@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
+@ci ... . ..... ..... .. &i imm=%imm_ci %rd rs1=%rd
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@@ -80,10 +79,6 @@
@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5
@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp %rd
-@c_flwsp_ldsp ... . ..... ..... .. &c_flwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
- uimm_ldsp=%uimm_6bit_ld %rd
-@c_fswsp_sdsp ... . ..... ..... .. &c_fswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
- uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
@@ -99,7 +94,6 @@ sw 110 ... ... .. ... 00 @cs_w
# *** RV64C Standard Extension (Quadrant 1) ***
c_addi 000 . ..... ..... 01 @ci
-c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually
c_li 010 . ..... ..... 01 @ci
c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
c_srli 100 . 00 ... ..... 01 @c_shift
@@ -117,9 +111,7 @@ c_bnez 111 ... ... ..... 01 @cb
c_slli 000 . ..... ..... 10 @c_shift2
c_fldsp 001 . ..... ..... 10 @c_ld
c_lwsp 010 . ..... ..... 10 @c_lw
-c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
c_jr_mv 100 0 ..... ..... 10 @cr
c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
c_fsdsp 101 ...... ..... 10 @c_sd
c_swsp 110 . ..... ..... 10 @c_sw
-c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b59a00cc42..0e098e05fe 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -38,6 +38,7 @@
&i imm rs1 rd
&r rd rs1 rs2
&s imm rs2 rs1
+&j imm rd
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
@@ -47,7 +48,7 @@
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
-@j .................... ..... ....... imm=%imm_j %rd
+@j .................... ..... ....... &j imm=%imm_j %rd
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index f521daf32e..db9119ec9b 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -38,19 +38,6 @@ static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
return trans_addi(ctx, &arg);
}
-static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
-{
-#ifdef TARGET_RISCV32
- /* C.JAL */
- arg_jal arg = { .rd = 1, .imm = a->imm };
- return trans_jal(ctx, &arg);
-#else
- /* C.ADDIW */
- arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
- return trans_addiw(ctx, &arg);
-#endif
-}
-
static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
{
if (a->rd == 0) {
@@ -163,20 +150,6 @@ static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
return trans_lw(ctx, &arg);
}
-static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FLWSP */
- arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
- return trans_flw(ctx, &arg_flw);
-#else
- /* C.LDSP */
- arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
- return trans_ld(ctx, &arg_ld);
-#endif
- return false;
-}
-
static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
{
if (a->rd != 0 && a->rs2 == 0) {
@@ -222,16 +195,3 @@ static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
return trans_sw(ctx, &arg);
}
-
-static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FSWSP */
- arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp };
- return trans_fsw(ctx, &a_fsw);
-#else
- /* C.SDSP */
- arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
- return trans_sd(ctx, &a_sd);
-#endif
-}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
@ 2019-01-22 9:29 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
it splices flwsp_ldsp, fswsp_sdsp, and jal_addiw and makes each of them
reuse the code generator used for the non compressed insns.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/insn16-32.decode | 7 +++++
target/riscv/insn16-64.decode | 5 ++++
target/riscv/insn16.decode | 12 ++------
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvc.inc.c | 40 -------------------------
5 files changed, 16 insertions(+), 51 deletions(-)
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
index e21a701056..978b8d5834 100644
--- a/target/riscv/insn16-32.decode
+++ b/target/riscv/insn16-32.decode
@@ -22,3 +22,10 @@
# *** RV32C Standard Extension (Quadrant 0) ***
flw 011 ... ... .. ... 00 @cl_w
fsw 111 ... ... .. ... 00 @cs_w
+
+# *** RV32C Standard Extension (Quadrant 1) ***
+jal 001 ...... ..... 01 &j imm=%imm_cj rd=1
+
+# *** RV32C Standard Extension (Quadrant 2) ***
+flw 011 . ..... ..... 10 &i imm=%uimm_6bit_lw %rd rs1=2
+fsw 111 ...... ..... 10 &s imm=%uimm_6bit_sw rs2=2 rs1=%rs2_5
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
index de97a45acf..d43055837a 100644
--- a/target/riscv/insn16-64.decode
+++ b/target/riscv/insn16-64.decode
@@ -24,5 +24,10 @@ ld 011 ... ... .. ... 00 @cl_d
sd 111 ... ... .. ... 00 @cs_d
# *** RV64C Standard Extension (Quadrant 1) ***
+addiw 001 . ..... ..... 01 @ci
subw 100 1 11 ... 00 ... 01 @cs_2
addw 100 1 11 ... 01 ... 01 @cs_2
+
+# *** RV64C Standard Extension (Quadrant 2) ***
+ld 011 . ..... ..... 10 &i imm=%uimm_6bit_ld %rd rs1=2
+sd 111 ...... ..... 10 &s imm=%uimm_6bit_sd rs2=%rs2_5 rs1=2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index b075336062..98dd672c7f 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -45,6 +45,7 @@
&r rd rs1 rs2 !extern
&i imm rs1 rd !extern
&s imm rs1 rs2 !extern
+&j imm rd !extern
# Argument sets:
&ci imm rd
@@ -59,12 +60,10 @@
&c_sd uimm rs2
&c_addi16sp_lui imm_lui imm_addi16sp rd
-&c_flwsp_ldsp uimm_flwsp uimm_ldsp rd
-&c_fswsp_sdsp uimm_fswsp uimm_sdsp rs2
# Formats 16:
@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd
-@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
+@ci ... . ..... ..... .. &i imm=%imm_ci %rd rs1=%rd
@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@@ -80,10 +79,6 @@
@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5
@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp %rd
-@c_flwsp_ldsp ... . ..... ..... .. &c_flwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
- uimm_ldsp=%uimm_6bit_ld %rd
-@c_fswsp_sdsp ... . ..... ..... .. &c_fswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
- uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
@@ -99,7 +94,6 @@ sw 110 ... ... .. ... 00 @cs_w
# *** RV64C Standard Extension (Quadrant 1) ***
c_addi 000 . ..... ..... 01 @ci
-c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually
c_li 010 . ..... ..... 01 @ci
c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
c_srli 100 . 00 ... ..... 01 @c_shift
@@ -117,9 +111,7 @@ c_bnez 111 ... ... ..... 01 @cb
c_slli 000 . ..... ..... 10 @c_shift2
c_fldsp 001 . ..... ..... 10 @c_ld
c_lwsp 010 . ..... ..... 10 @c_lw
-c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
c_jr_mv 100 0 ..... ..... 10 @cr
c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
c_fsdsp 101 ...... ..... 10 @c_sd
c_swsp 110 . ..... ..... 10 @c_sw
-c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b59a00cc42..0e098e05fe 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -38,6 +38,7 @@
&i imm rs1 rd
&r rd rs1 rs2
&s imm rs2 rs1
+&j imm rd
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
@@ -47,7 +48,7 @@
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
-@j .................... ..... ....... imm=%imm_j %rd
+@j .................... ..... ....... &j imm=%imm_j %rd
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index f521daf32e..db9119ec9b 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -38,19 +38,6 @@ static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
return trans_addi(ctx, &arg);
}
-static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
-{
-#ifdef TARGET_RISCV32
- /* C.JAL */
- arg_jal arg = { .rd = 1, .imm = a->imm };
- return trans_jal(ctx, &arg);
-#else
- /* C.ADDIW */
- arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
- return trans_addiw(ctx, &arg);
-#endif
-}
-
static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
{
if (a->rd == 0) {
@@ -163,20 +150,6 @@ static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
return trans_lw(ctx, &arg);
}
-static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FLWSP */
- arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
- return trans_flw(ctx, &arg_flw);
-#else
- /* C.LDSP */
- arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
- return trans_ld(ctx, &arg_ld);
-#endif
- return false;
-}
-
static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
{
if (a->rd != 0 && a->rs2 == 0) {
@@ -222,16 +195,3 @@ static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
return trans_sw(ctx, &arg);
}
-
-static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FSWSP */
- arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp };
- return trans_fsw(ctx, &a_fsw);
-#else
- /* C.SDSP */
- arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
- return trans_sd(ctx, &a_sd);
-#endif
-}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-devel] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 9:29 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
only one translate functions of rvc needs to handle special cases. For
the other rvc insns we can remove the extra layer of indirection.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/insn16.decode | 37 +++++++++----------
target/riscv/insn_trans/trans_rvc.inc.c | 48 -------------------------
2 files changed, 17 insertions(+), 68 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 98dd672c7f..d88a0c78ab 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -46,19 +46,15 @@
&i imm rs1 rd !extern
&s imm rs1 rs2 !extern
&j imm rd !extern
+&b imm rs2 rs1 !extern
# Argument sets:
&ci imm rd
&ciw nzuimm rd
&cs_dw uimm rs1 rs2
-&cb imm rs1
&cr rd rs2
-&c_j imm
&c_shift shamt rd
-&c_ld uimm rd
-&c_sd uimm rs2
-
&c_addi16sp_lui imm_lui imm_addi16sp rd
# Formats 16:
@@ -70,20 +66,21 @@
@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
-@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
-@cj ... ........... .. &c_j imm=%imm_cj
+@cb ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0
+@cj ... ........... .. &j imm=%imm_cj rd=0
-@c_ld ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd
-@c_lw ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd
-@c_sd ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd rs2=%rs2_5
-@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5
+@c_ld ... . ..... ..... .. &i imm=%uimm_6bit_ld %rd rs1=2
+@c_lw ... . ..... ..... .. &i imm=%uimm_6bit_lw %rd rs1=2
+@c_sd ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
+@c_sw ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp %rd
@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
-@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
+@c_andi ... . .. ... ..... .. &i imm=%imm_ci rd=%rs1_3 rs1=%rs1_3
+
# *** RV64C Standard Extension (Quadrant 0) ***
c_addi4spn 000 ........ ... 00 @ciw
@@ -98,20 +95,20 @@ c_li 010 . ..... ..... 01 @ci
c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
c_srli 100 . 00 ... ..... 01 @c_shift
c_srai 100 . 01 ... ..... 01 @c_shift
-c_andi 100 . 10 ... ..... 01 @c_andi
+andi 100 . 10 ... ..... 01 @c_andi
sub 100 0 11 ... 00 ... 01 @cs_2
xor 100 0 11 ... 01 ... 01 @cs_2
or 100 0 11 ... 10 ... 01 @cs_2
and 100 0 11 ... 11 ... 01 @cs_2
-c_j 101 ........... 01 @cj
-c_beqz 110 ... ... ..... 01 @cb
-c_bnez 111 ... ... ..... 01 @cb
+jal 101 ........... 01 @cj # c_j
+beq 110 ... ... ..... 01 @cb # c_beqz
+bne 111 ... ... ..... 01 @cb # c_bnez
# *** RV64C Standard Extension (Quadrant 2) ***
c_slli 000 . ..... ..... 10 @c_shift2
-c_fldsp 001 . ..... ..... 10 @c_ld
-c_lwsp 010 . ..... ..... 10 @c_lw
+fld 001 . ..... ..... 10 @c_ld # fldsp
+lw 010 . ..... ..... 10 @c_lw # lwsp
c_jr_mv 100 0 ..... ..... 10 @cr
c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
-c_fsdsp 101 ...... ..... 10 @c_sd
-c_swsp 110 . ..... ..... 10 @c_sw
+fsd 101 ...... ..... 10 @c_sd # fsdsp
+sw 110 . ..... ..... 10 @c_sw # swsp
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index db9119ec9b..631e72c8b5 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -98,30 +98,6 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
return trans_srai(ctx, &arg);
}
-static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
-{
- arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
- return trans_andi(ctx, &arg);
-}
-
-static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
-{
- arg_jal arg = { .rd = 0, .imm = a->imm };
- return trans_jal(ctx, &arg);
-}
-
-static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
-{
- arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
- return trans_beq(ctx, &arg);
-}
-
-static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
-{
- arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
- return trans_bne(ctx, &arg);
-}
-
static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
{
int shamt = a->shamt;
@@ -138,18 +114,6 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
return trans_slli(ctx, &arg);
}
-static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
-{
- arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
- return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
-{
- arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
- return trans_lw(ctx, &arg);
-}
-
static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
{
if (a->rd != 0 && a->rs2 == 0) {
@@ -183,15 +147,3 @@ static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
}
return false;
}
-
-static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
-{
- arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
- return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
-{
- arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
- return trans_sw(ctx, &arg);
-}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* [Qemu-riscv] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators
@ 2019-01-22 9:29 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-22 9:29 UTC (permalink / raw)
To: sagark, palmer, kbastian
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel
only one translate functions of rvc needs to handle special cases. For
the other rvc insns we can remove the extra layer of indirection.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/insn16.decode | 37 +++++++++----------
target/riscv/insn_trans/trans_rvc.inc.c | 48 -------------------------
2 files changed, 17 insertions(+), 68 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 98dd672c7f..d88a0c78ab 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -46,19 +46,15 @@
&i imm rs1 rd !extern
&s imm rs1 rs2 !extern
&j imm rd !extern
+&b imm rs2 rs1 !extern
# Argument sets:
&ci imm rd
&ciw nzuimm rd
&cs_dw uimm rs1 rs2
-&cb imm rs1
&cr rd rs2
-&c_j imm
&c_shift shamt rd
-&c_ld uimm rd
-&c_sd uimm rs2
-
&c_addi16sp_lui imm_lui imm_addi16sp rd
# Formats 16:
@@ -70,20 +66,21 @@
@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
-@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
-@cj ... ........... .. &c_j imm=%imm_cj
+@cb ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0
+@cj ... ........... .. &j imm=%imm_cj rd=0
-@c_ld ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd
-@c_lw ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd
-@c_sd ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd rs2=%rs2_5
-@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5
+@c_ld ... . ..... ..... .. &i imm=%uimm_6bit_ld %rd rs1=2
+@c_lw ... . ..... ..... .. &i imm=%uimm_6bit_lw %rd rs1=2
+@c_sd ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
+@c_sw ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp %rd
@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
-@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
+@c_andi ... . .. ... ..... .. &i imm=%imm_ci rd=%rs1_3 rs1=%rs1_3
+
# *** RV64C Standard Extension (Quadrant 0) ***
c_addi4spn 000 ........ ... 00 @ciw
@@ -98,20 +95,20 @@ c_li 010 . ..... ..... 01 @ci
c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
c_srli 100 . 00 ... ..... 01 @c_shift
c_srai 100 . 01 ... ..... 01 @c_shift
-c_andi 100 . 10 ... ..... 01 @c_andi
+andi 100 . 10 ... ..... 01 @c_andi
sub 100 0 11 ... 00 ... 01 @cs_2
xor 100 0 11 ... 01 ... 01 @cs_2
or 100 0 11 ... 10 ... 01 @cs_2
and 100 0 11 ... 11 ... 01 @cs_2
-c_j 101 ........... 01 @cj
-c_beqz 110 ... ... ..... 01 @cb
-c_bnez 111 ... ... ..... 01 @cb
+jal 101 ........... 01 @cj # c_j
+beq 110 ... ... ..... 01 @cb # c_beqz
+bne 111 ... ... ..... 01 @cb # c_bnez
# *** RV64C Standard Extension (Quadrant 2) ***
c_slli 000 . ..... ..... 10 @c_shift2
-c_fldsp 001 . ..... ..... 10 @c_ld
-c_lwsp 010 . ..... ..... 10 @c_lw
+fld 001 . ..... ..... 10 @c_ld # fldsp
+lw 010 . ..... ..... 10 @c_lw # lwsp
c_jr_mv 100 0 ..... ..... 10 @cr
c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
-c_fsdsp 101 ...... ..... 10 @c_sd
-c_swsp 110 . ..... ..... 10 @c_sw
+fsd 101 ...... ..... 10 @c_sd # fsdsp
+sw 110 . ..... ..... 10 @c_sw # swsp
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index db9119ec9b..631e72c8b5 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -98,30 +98,6 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
return trans_srai(ctx, &arg);
}
-static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
-{
- arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
- return trans_andi(ctx, &arg);
-}
-
-static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
-{
- arg_jal arg = { .rd = 0, .imm = a->imm };
- return trans_jal(ctx, &arg);
-}
-
-static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
-{
- arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
- return trans_beq(ctx, &arg);
-}
-
-static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
-{
- arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
- return trans_bne(ctx, &arg);
-}
-
static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
{
int shamt = a->shamt;
@@ -138,18 +114,6 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
return trans_slli(ctx, &arg);
}
-static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
-{
- arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
- return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
-{
- arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
- return trans_lw(ctx, &arg);
-}
-
static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
{
if (a->rd != 0 && a->rs2 == 0) {
@@ -183,15 +147,3 @@ static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
}
return false;
}
-
-static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
-{
- arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
- return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
-{
- arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
- return trans_sw(ctx, &arg);
-}
--
2.20.1
^ permalink raw reply related [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 21:32 ` Richard Henderson
-1 siblings, 0 replies; 164+ messages in thread
From: Richard Henderson @ 2019-01-22 21:32 UTC (permalink / raw)
To: Bastian Koppelmann, sagark, palmer; +Cc: peer.adelt, qemu-riscv, qemu-devel
On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
> ---
> target/riscv/insn16.decode | 31 ++++++++
> target/riscv/insn_trans/trans_rvc.inc.c | 101 ++++++++++++++++++++++++
> target/riscv/translate.c | 83 +------------------
> 3 files changed, 134 insertions(+), 81 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [PATCH v5 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
@ 2019-01-22 21:32 ` Richard Henderson
0 siblings, 0 replies; 164+ messages in thread
From: Richard Henderson @ 2019-01-22 21:32 UTC (permalink / raw)
To: Bastian Koppelmann, sagark, palmer; +Cc: peer.adelt, qemu-riscv, qemu-devel
On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
> ---
> target/riscv/insn16.decode | 31 ++++++++
> target/riscv/insn_trans/trans_rvc.inc.c | 101 ++++++++++++++++++++++++
> target/riscv/translate.c | 83 +------------------
> 3 files changed, 134 insertions(+), 81 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 21:36 ` Richard Henderson
-1 siblings, 0 replies; 164+ messages in thread
From: Richard Henderson @ 2019-01-22 21:36 UTC (permalink / raw)
To: Bastian Koppelmann, sagark, palmer; +Cc: peer.adelt, qemu-riscv, qemu-devel
On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> gen_arith_imm() does a lot of decoding manually, which was hard to read
> in case of the shift instructions and is not necessary anymore with
> decodetree.
>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
Watch the funky indentation.
> + if (a->rd != 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> +
> + tcg_gen_sari_tl(t, t, a->shamt);
> + gen_set_gpr(a->rd, t);
Likewise.
r~
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
@ 2019-01-22 21:36 ` Richard Henderson
0 siblings, 0 replies; 164+ messages in thread
From: Richard Henderson @ 2019-01-22 21:36 UTC (permalink / raw)
To: Bastian Koppelmann, sagark, palmer; +Cc: peer.adelt, qemu-riscv, qemu-devel
On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> gen_arith_imm() does a lot of decoding manually, which was hard to read
> in case of the shift instructions and is not necessary anymore with
> decodetree.
>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
Watch the funky indentation.
> + if (a->rd != 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> +
> + tcg_gen_sari_tl(t, t, a->shamt);
> + gen_set_gpr(a->rd, t);
Likewise.
r~
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 21:38 ` Richard Henderson
-1 siblings, 0 replies; 164+ messages in thread
From: Richard Henderson @ 2019-01-22 21:38 UTC (permalink / raw)
To: Bastian Koppelmann, sagark, palmer; +Cc: peer.adelt, qemu-riscv, qemu-devel
On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> Hi,
>
> this patchset converts the RISC-V decoder to decodetree in four major steps:
>
> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> Many of the gen_* functions are called by the decode functions for 16-bit
> and 32-bit functions. If we move translation code from the gen_*
> functions to the generated trans_* functions of decode-tree, we get a lot of
> duplication. Therefore, we mostly generate calls to the old gen_* function
> which are properly replaced after step 2).
>
> Each of the trans_ functions are grouped into files corresponding to their
> ISA extension, e.g. addi which is in RV32I is translated in the file
> 'trans_rvi.inc.c'.
>
> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
> we convert the arguments in the 16 bit trans_ function to the arguments of
> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>
> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
> this move all manual translation code into the trans_* instructions of
> decode tree, such that we can remove the old decode_* functions.
>
> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
> by Richard. [Patch 31-35]
>
> full tree available at
> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>
> Cheers,
> Bastian
>
> v4 -> v5:
> - fixed rebase error
> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
> - removed extra sign extension of sraiw
> - removed rs2 == 0 special cases in sraw/srlw
All looks good to me now. Thanks for persevering.
r~
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-22 21:38 ` Richard Henderson
0 siblings, 0 replies; 164+ messages in thread
From: Richard Henderson @ 2019-01-22 21:38 UTC (permalink / raw)
To: Bastian Koppelmann, sagark, palmer; +Cc: peer.adelt, qemu-riscv, qemu-devel
On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> Hi,
>
> this patchset converts the RISC-V decoder to decodetree in four major steps:
>
> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> Many of the gen_* functions are called by the decode functions for 16-bit
> and 32-bit functions. If we move translation code from the gen_*
> functions to the generated trans_* functions of decode-tree, we get a lot of
> duplication. Therefore, we mostly generate calls to the old gen_* function
> which are properly replaced after step 2).
>
> Each of the trans_ functions are grouped into files corresponding to their
> ISA extension, e.g. addi which is in RV32I is translated in the file
> 'trans_rvi.inc.c'.
>
> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
> we convert the arguments in the 16 bit trans_ function to the arguments of
> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>
> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
> this move all manual translation code into the trans_* instructions of
> decode tree, such that we can remove the old decode_* functions.
>
> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
> by Richard. [Patch 31-35]
>
> full tree available at
> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>
> Cheers,
> Bastian
>
> v4 -> v5:
> - fixed rebase error
> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
> - removed extra sign extension of sraiw
> - removed rs2 == 0 special cases in sraw/srlw
All looks good to me now. Thanks for persevering.
r~
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 23:03 ` Alistair Francis
-1 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-22 23:03 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 2:12 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 19 ++++++++++
> target/riscv/insn_trans/trans_rvi.inc.c | 49 +++++++++++++++++++++++++
> target/riscv/translate.c | 12 +-----
> 3 files changed, 69 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 44d4e922b6..81f56c16b4 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -17,14 +17,33 @@
> # this program. If not, see <http://www.gnu.org/licenses/>.
>
> # Fields:
> +%rs2 20:5
> +%rs1 15:5
> %rd 7:5
>
> # immediates:
> +%imm_i 20:s12
> +%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
> +%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
> %imm_u 12:s20 !function=ex_shift_12
>
> +# Argument sets:
> +&b imm rs2 rs1
> +
> # Formats 32:
> +@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
> +@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
> @u .................... ..... ....... imm=%imm_u %rd
> +@j .................... ..... ....... imm=%imm_j %rd
>
> # *** RV32I Base Instruction Set ***
> lui .................... ..... 0110111 @u
> auipc .................... ..... 0010111 @u
> +jal .................... ..... 1101111 @j
> +jalr ............ ..... 000 ..... 1100111 @i
> +beq ....... ..... ..... 000 ..... 1100011 @b
> +bne ....... ..... ..... 001 ..... 1100011 @b
> +blt ....... ..... ..... 100 ..... 1100011 @b
> +bge ....... ..... ..... 101 ..... 1100011 @b
> +bltu ....... ..... ..... 110 ..... 1100011 @b
> +bgeu ....... ..... ..... 111 ..... 1100011 @b
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index 9885a8d275..0347461ee6 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -33,3 +33,52 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
> }
> return true;
> }
> +
> +static bool trans_jal(DisasContext *ctx, arg_jal *a)
> +{
> + gen_jal(ctx->env, ctx, a->rd, a->imm);
> + return true;
> +}
> +
> +static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
> +{
> + gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_beq(DisasContext *ctx, arg_beq *a)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bne(DisasContext *ctx, arg_bne *a)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_blt(DisasContext *ctx, arg_blt *a)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bge(DisasContext *ctx, arg_bge *a)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
> +{
> +
> + gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 99829a600d..b81297f23e 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1682,6 +1682,7 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
> { \
> return imm << amount; \
> }
> +EX_SH(1)
> EX_SH(12)
>
> bool decode_insn32(DisasContext *ctx, uint32_t insn);
> @@ -1710,17 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> imm = GET_IMM(ctx->opcode);
>
> switch (op) {
> - case OPC_RISC_JAL:
> - imm = GET_JAL_IMM(ctx->opcode);
> - gen_jal(env, ctx, rd, imm);
> - break;
> - case OPC_RISC_JALR:
> - gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
> - break;
> - case OPC_RISC_BRANCH:
> - gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
> - GET_B_IMM(ctx->opcode));
> - break;
> case OPC_RISC_LOAD:
> gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
> break;
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree
@ 2019-01-22 23:03 ` Alistair Francis
0 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-22 23:03 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 2:12 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 19 ++++++++++
> target/riscv/insn_trans/trans_rvi.inc.c | 49 +++++++++++++++++++++++++
> target/riscv/translate.c | 12 +-----
> 3 files changed, 69 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 44d4e922b6..81f56c16b4 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -17,14 +17,33 @@
> # this program. If not, see <http://www.gnu.org/licenses/>.
>
> # Fields:
> +%rs2 20:5
> +%rs1 15:5
> %rd 7:5
>
> # immediates:
> +%imm_i 20:s12
> +%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
> +%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
> %imm_u 12:s20 !function=ex_shift_12
>
> +# Argument sets:
> +&b imm rs2 rs1
> +
> # Formats 32:
> +@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
> +@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
> @u .................... ..... ....... imm=%imm_u %rd
> +@j .................... ..... ....... imm=%imm_j %rd
>
> # *** RV32I Base Instruction Set ***
> lui .................... ..... 0110111 @u
> auipc .................... ..... 0010111 @u
> +jal .................... ..... 1101111 @j
> +jalr ............ ..... 000 ..... 1100111 @i
> +beq ....... ..... ..... 000 ..... 1100011 @b
> +bne ....... ..... ..... 001 ..... 1100011 @b
> +blt ....... ..... ..... 100 ..... 1100011 @b
> +bge ....... ..... ..... 101 ..... 1100011 @b
> +bltu ....... ..... ..... 110 ..... 1100011 @b
> +bgeu ....... ..... ..... 111 ..... 1100011 @b
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index 9885a8d275..0347461ee6 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -33,3 +33,52 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
> }
> return true;
> }
> +
> +static bool trans_jal(DisasContext *ctx, arg_jal *a)
> +{
> + gen_jal(ctx->env, ctx, a->rd, a->imm);
> + return true;
> +}
> +
> +static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
> +{
> + gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_beq(DisasContext *ctx, arg_beq *a)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bne(DisasContext *ctx, arg_bne *a)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_blt(DisasContext *ctx, arg_blt *a)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bge(DisasContext *ctx, arg_bge *a)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
> +{
> + gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
> +{
> +
> + gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 99829a600d..b81297f23e 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1682,6 +1682,7 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
> { \
> return imm << amount; \
> }
> +EX_SH(1)
> EX_SH(12)
>
> bool decode_insn32(DisasContext *ctx, uint32_t insn);
> @@ -1710,17 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> imm = GET_IMM(ctx->opcode);
>
> switch (op) {
> - case OPC_RISC_JAL:
> - imm = GET_JAL_IMM(ctx->opcode);
> - gen_jal(env, ctx, rd, imm);
> - break;
> - case OPC_RISC_JALR:
> - gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
> - break;
> - case OPC_RISC_BRANCH:
> - gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
> - GET_B_IMM(ctx->opcode));
> - break;
> case OPC_RISC_LOAD:
> gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
> break;
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 23:38 ` Alistair Francis
-1 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-22 23:38 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 2:07 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 10 ++++++
> target/riscv/insn_trans/trans_rvi.inc.c | 48 +++++++++++++++++++++++++
> 2 files changed, 58 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 81f56c16b4..076de873c4 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -23,6 +23,7 @@
>
> # immediates:
> %imm_i 20:s12
> +%imm_s 25:s7 7:5
> %imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
> %imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
> %imm_u 12:s20 !function=ex_shift_12
> @@ -33,6 +34,7 @@
> # Formats 32:
> @i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
> @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
> +@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
> @u .................... ..... ....... imm=%imm_u %rd
> @j .................... ..... ....... imm=%imm_j %rd
>
> @@ -47,3 +49,11 @@ blt ....... ..... ..... 100 ..... 1100011 @b
> bge ....... ..... ..... 101 ..... 1100011 @b
> bltu ....... ..... ..... 110 ..... 1100011 @b
> bgeu ....... ..... ..... 111 ..... 1100011 @b
> +lb ............ ..... 000 ..... 0000011 @i
> +lh ............ ..... 001 ..... 0000011 @i
> +lw ............ ..... 010 ..... 0000011 @i
> +lbu ............ ..... 100 ..... 0000011 @i
> +lhu ............ ..... 101 ..... 0000011 @i
> +sb ....... ..... ..... 000 ..... 0100011 @s
> +sh ....... ..... ..... 001 ..... 0100011 @s
> +sw ....... ..... ..... 010 ..... 0100011 @s
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index 0347461ee6..f3b88ebb69 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -82,3 +82,51 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
> gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
> return true;
> }
> +
> +static bool trans_lb(DisasContext *ctx, arg_lb *a)
> +{
> + gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_lh(DisasContext *ctx, arg_lh *a)
> +{
> + gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_lw(DisasContext *ctx, arg_lw *a)
> +{
> + gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
> +{
> + gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
> +{
> + gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_sb(DisasContext *ctx, arg_sb *a)
> +{
> + gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_sh(DisasContext *ctx, arg_sh *a)
> +{
> + gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_sw(DisasContext *ctx, arg_sw *a)
> +{
> + gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store insns to decodetree
@ 2019-01-22 23:38 ` Alistair Francis
0 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-22 23:38 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 2:07 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 10 ++++++
> target/riscv/insn_trans/trans_rvi.inc.c | 48 +++++++++++++++++++++++++
> 2 files changed, 58 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 81f56c16b4..076de873c4 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -23,6 +23,7 @@
>
> # immediates:
> %imm_i 20:s12
> +%imm_s 25:s7 7:5
> %imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
> %imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
> %imm_u 12:s20 !function=ex_shift_12
> @@ -33,6 +34,7 @@
> # Formats 32:
> @i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
> @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
> +@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
> @u .................... ..... ....... imm=%imm_u %rd
> @j .................... ..... ....... imm=%imm_j %rd
>
> @@ -47,3 +49,11 @@ blt ....... ..... ..... 100 ..... 1100011 @b
> bge ....... ..... ..... 101 ..... 1100011 @b
> bltu ....... ..... ..... 110 ..... 1100011 @b
> bgeu ....... ..... ..... 111 ..... 1100011 @b
> +lb ............ ..... 000 ..... 0000011 @i
> +lh ............ ..... 001 ..... 0000011 @i
> +lw ............ ..... 010 ..... 0000011 @i
> +lbu ............ ..... 100 ..... 0000011 @i
> +lhu ............ ..... 101 ..... 0000011 @i
> +sb ....... ..... ..... 000 ..... 0100011 @s
> +sh ....... ..... ..... 001 ..... 0100011 @s
> +sw ....... ..... ..... 010 ..... 0100011 @s
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index 0347461ee6..f3b88ebb69 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -82,3 +82,51 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
> gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
> return true;
> }
> +
> +static bool trans_lb(DisasContext *ctx, arg_lb *a)
> +{
> + gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_lh(DisasContext *ctx, arg_lh *a)
> +{
> + gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_lw(DisasContext *ctx, arg_lw *a)
> +{
> + gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
> +{
> + gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
> +{
> + gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +
> +static bool trans_sb(DisasContext *ctx, arg_sb *a)
> +{
> + gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_sh(DisasContext *ctx, arg_sh *a)
> +{
> + gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> +
> +static bool trans_sw(DisasContext *ctx, arg_sw *a)
> +{
> + gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
> + return true;
> +}
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-22 23:43 ` Alistair Francis
-1 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-22 23:43 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 2:03 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 17 +++
> target/riscv/insn_trans/trans_rva.inc.c | 149 ++++++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 3 files changed, 167 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index e53944bf0e..00b9e2d9a5 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -34,6 +34,7 @@
> # Argument sets:
> &b imm rs2 rs1
> &shift shamt rs1 rd
> +&atomic aq rl rs2 rs1 rd
>
> # Formats 32:
> @r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
> @@ -46,6 +47,9 @@
> @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
> @csr ............ ..... ... ..... ....... %csr %rs1 %rd
>
> +@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
> +@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
> +
> # *** RV32I Base Instruction Set ***
> lui .................... ..... 0110111 @u
> auipc .................... ..... 0010111 @u
> @@ -102,3 +106,16 @@ div 0000001 ..... ..... 100 ..... 0110011 @r
> divu 0000001 ..... ..... 101 ..... 0110011 @r
> rem 0000001 ..... ..... 110 ..... 0110011 @r
> remu 0000001 ..... ..... 111 ..... 0110011 @r
> +
> +# *** RV32A Standard Extension ***
> +lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
> +sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
> +amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
> +amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
> +amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
> +amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
> +amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
> +amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
> +amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
> +amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
> +amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
> diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c
> new file mode 100644
> index 0000000000..ab6ccf0e90
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rva.inc.c
> @@ -0,0 +1,149 @@
> +/*
> + * RISC-V translation routines for the RV64A Standard Extension.
> + *
> + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
> +{
> + TCGv src1 = tcg_temp_new();
> + /* Put addr in load_res, data in load_val. */
> + gen_get_gpr(src1, a->rs1);
> + if (a->rl) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
> + }
> + tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
> + if (a->aq) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
> + }
> + tcg_gen_mov_tl(load_res, src1);
> + gen_set_gpr(a->rd, load_val);
> +
> + tcg_temp_free(src1);
> + return true;
> +}
> +
> +static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
> +{
> + TCGv src1 = tcg_temp_new();
> + TCGv src2 = tcg_temp_new();
> + TCGv dat = tcg_temp_new();
> + TCGLabel *l1 = gen_new_label();
> + TCGLabel *l2 = gen_new_label();
> +
> + gen_get_gpr(src1, a->rs1);
> + tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
> +
> + gen_get_gpr(src2, a->rs2);
> + /*
> + * Note that the TCG atomic primitives are SC,
> + * so we can ignore AQ/RL along this path.
> + */
> + tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
> + ctx->mem_idx, mop);
> + tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
> + gen_set_gpr(a->rd, dat);
> + tcg_gen_br(l2);
> +
> + gen_set_label(l1);
> + /*
> + * Address comparion failure. However, we still need to
> + * provide the memory barrier implied by AQ/RL.
> + */
> + tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
> + tcg_gen_movi_tl(dat, 1);
> + gen_set_gpr(a->rd, dat);
> +
> + gen_set_label(l2);
> + tcg_temp_free(dat);
> + tcg_temp_free(src1);
> + tcg_temp_free(src2);
> + return true;
> +}
> +
> +static bool gen_amo(DisasContext *ctx, arg_atomic *a,
> + void(*func)(TCGv, TCGv, TCGv, TCGArg, TCGMemOp),
> + TCGMemOp mop)
> +{
> + TCGv src1 = tcg_temp_new();
> + TCGv src2 = tcg_temp_new();
> +
> + gen_get_gpr(src1, a->rs1);
> + gen_get_gpr(src2, a->rs2);
> +
> + (*func)(src2, src1, src2, ctx->mem_idx, mop);
> +
> + gen_set_gpr(a->rd, src2);
> + tcg_temp_free(src1);
> + tcg_temp_free(src2);
> + return true;
> +}
> +
> +static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
> +{
> + return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
> +{
> + return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 666c039662..98180002ef 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1650,6 +1650,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
> /* Include insn module translation function */
> #include "insn_trans/trans_rvi.inc.c"
> #include "insn_trans/trans_rvm.inc.c"
> +#include "insn_trans/trans_rva.inc.c"
>
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A insns to decodetree
@ 2019-01-22 23:43 ` Alistair Francis
0 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-22 23:43 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 2:03 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 17 +++
> target/riscv/insn_trans/trans_rva.inc.c | 149 ++++++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 3 files changed, 167 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index e53944bf0e..00b9e2d9a5 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -34,6 +34,7 @@
> # Argument sets:
> &b imm rs2 rs1
> &shift shamt rs1 rd
> +&atomic aq rl rs2 rs1 rd
>
> # Formats 32:
> @r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
> @@ -46,6 +47,9 @@
> @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
> @csr ............ ..... ... ..... ....... %csr %rs1 %rd
>
> +@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
> +@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
> +
> # *** RV32I Base Instruction Set ***
> lui .................... ..... 0110111 @u
> auipc .................... ..... 0010111 @u
> @@ -102,3 +106,16 @@ div 0000001 ..... ..... 100 ..... 0110011 @r
> divu 0000001 ..... ..... 101 ..... 0110011 @r
> rem 0000001 ..... ..... 110 ..... 0110011 @r
> remu 0000001 ..... ..... 111 ..... 0110011 @r
> +
> +# *** RV32A Standard Extension ***
> +lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
> +sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
> +amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
> +amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
> +amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
> +amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
> +amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
> +amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
> +amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
> +amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
> +amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
> diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c
> new file mode 100644
> index 0000000000..ab6ccf0e90
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rva.inc.c
> @@ -0,0 +1,149 @@
> +/*
> + * RISC-V translation routines for the RV64A Standard Extension.
> + *
> + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
> +{
> + TCGv src1 = tcg_temp_new();
> + /* Put addr in load_res, data in load_val. */
> + gen_get_gpr(src1, a->rs1);
> + if (a->rl) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
> + }
> + tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
> + if (a->aq) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
> + }
> + tcg_gen_mov_tl(load_res, src1);
> + gen_set_gpr(a->rd, load_val);
> +
> + tcg_temp_free(src1);
> + return true;
> +}
> +
> +static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
> +{
> + TCGv src1 = tcg_temp_new();
> + TCGv src2 = tcg_temp_new();
> + TCGv dat = tcg_temp_new();
> + TCGLabel *l1 = gen_new_label();
> + TCGLabel *l2 = gen_new_label();
> +
> + gen_get_gpr(src1, a->rs1);
> + tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
> +
> + gen_get_gpr(src2, a->rs2);
> + /*
> + * Note that the TCG atomic primitives are SC,
> + * so we can ignore AQ/RL along this path.
> + */
> + tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
> + ctx->mem_idx, mop);
> + tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
> + gen_set_gpr(a->rd, dat);
> + tcg_gen_br(l2);
> +
> + gen_set_label(l1);
> + /*
> + * Address comparion failure. However, we still need to
> + * provide the memory barrier implied by AQ/RL.
> + */
> + tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
> + tcg_gen_movi_tl(dat, 1);
> + gen_set_gpr(a->rd, dat);
> +
> + gen_set_label(l2);
> + tcg_temp_free(dat);
> + tcg_temp_free(src1);
> + tcg_temp_free(src2);
> + return true;
> +}
> +
> +static bool gen_amo(DisasContext *ctx, arg_atomic *a,
> + void(*func)(TCGv, TCGv, TCGv, TCGArg, TCGMemOp),
> + TCGMemOp mop)
> +{
> + TCGv src1 = tcg_temp_new();
> + TCGv src2 = tcg_temp_new();
> +
> + gen_get_gpr(src1, a->rs1);
> + gen_get_gpr(src2, a->rs2);
> +
> + (*func)(src2, src1, src2, ctx->mem_idx, mop);
> +
> + gen_set_gpr(a->rd, src2);
> + tcg_temp_free(src1);
> + tcg_temp_free(src2);
> + return true;
> +}
> +
> +static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
> +{
> + return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
> +{
> + return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
> +{
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 666c039662..98180002ef 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1650,6 +1650,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
> /* Include insn module translation function */
> #include "insn_trans/trans_rvi.inc.c"
> #include "insn_trans/trans_rvm.inc.c"
> +#include "insn_trans/trans_rva.inc.c"
>
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-23 0:00 ` Alistair Francis
-1 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 0:00 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:52 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 35 +++
> target/riscv/insn_trans/trans_rvf.inc.c | 334 ++++++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 3 files changed, 370 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 00b9e2d9a5..e40836bf03 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -17,12 +17,14 @@
> # this program. If not, see <http://www.gnu.org/licenses/>.
>
> # Fields:
> +%rs3 27:5
> %rs2 20:5
> %rs1 15:5
> %rd 7:5
>
> %sh10 20:10
> %csr 20:12
> +%rm 12:3
>
> # immediates:
> %imm_i 20:s12
> @@ -50,6 +52,11 @@
> @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
> @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
>
> +@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
> +@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
> +@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
> +@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
> +
> # *** RV32I Base Instruction Set ***
> lui .................... ..... 0110111 @u
> auipc .................... ..... 0010111 @u
> @@ -119,3 +126,31 @@ amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
> amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
> amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
> amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
> +
> +# *** RV32F Standard Extension ***
> +flw ............ ..... 010 ..... 0000111 @i
> +fsw ....... ..... ..... 010 ..... 0100111 @s
> +fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
> +fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
> +fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
> +fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
> +fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
> +fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
> +fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
> +fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
> +fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
> +fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
> +fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
> +fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
> +fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
> +fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
> +fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
> +fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
> +fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
> +feq_s 1010000 ..... ..... 010 ..... 1010011 @r
> +flt_s 1010000 ..... ..... 001 ..... 1010011 @r
> +fle_s 1010000 ..... ..... 000 ..... 1010011 @r
> +fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
> +fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
> +fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
> +fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
> diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
> new file mode 100644
> index 0000000000..b101593ac4
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvf.inc.c
> @@ -0,0 +1,334 @@
> +/*
> + * RISC-V translation routines for the RV64F Standard Extension.
> + *
> + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_FPU do {\
> + if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) \
> + return false; \
> +} while (0)
> +
> +static bool trans_flw(DisasContext *ctx, arg_flw *a)
> +{
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> + REQUIRE_FPU;
> + tcg_gen_addi_tl(t0, t0, a->imm);
> +
> + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
> + /* RISC-V requires NaN-boxing of narrower width floating point values */
> + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
> +{
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + REQUIRE_FPU;
> + tcg_gen_addi_tl(t0, t0, a->imm);
> +
> + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
> + return true;
> +}
> +
> +static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FMOV */
> + tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
> + } else { /* FSGNJ */
> + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
> + 0, 31);
> + }
> + return true;
> +}
> +
> +static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FNEG */
> + tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
> + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
> + tcg_temp_free_i64(t0);
> + }
> + return true;
> +}
> +
> +static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FABS */
> + tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN);
> + tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
> + tcg_temp_free_i64(t0);
> + }
> + return true;
> +}
> +
> +static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
> +{
> + /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> +
> +#if defined(TARGET_RISCV64)
> + tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
> +#else
> + tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
> +#endif
> +
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
> +{
> + REQUIRE_FPU;
> + TCGv t0 = tcg_temp_new();
> + gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
> +{
> + REQUIRE_FPU;
> + TCGv t0 = tcg_temp_new();
> + gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
> +{
> + REQUIRE_FPU;
> + TCGv t0 = tcg_temp_new();
> + gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> +
> + gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
> +
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
> +
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
> +
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
> +{
> + /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> +#if defined(TARGET_RISCV64)
> + tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
> +#else
> + tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
> +#endif
> +
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 944836dd7c..933ca9fb69 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1514,6 +1514,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
> #include "insn_trans/trans_rvi.inc.c"
> #include "insn_trans/trans_rvm.inc.c"
> #include "insn_trans/trans_rva.inc.c"
> +#include "insn_trans/trans_rvf.inc.c"
>
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F insns to decodetree
@ 2019-01-23 0:00 ` Alistair Francis
0 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 0:00 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:52 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 35 +++
> target/riscv/insn_trans/trans_rvf.inc.c | 334 ++++++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 3 files changed, 370 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 00b9e2d9a5..e40836bf03 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -17,12 +17,14 @@
> # this program. If not, see <http://www.gnu.org/licenses/>.
>
> # Fields:
> +%rs3 27:5
> %rs2 20:5
> %rs1 15:5
> %rd 7:5
>
> %sh10 20:10
> %csr 20:12
> +%rm 12:3
>
> # immediates:
> %imm_i 20:s12
> @@ -50,6 +52,11 @@
> @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
> @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
>
> +@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
> +@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
> +@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
> +@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
> +
> # *** RV32I Base Instruction Set ***
> lui .................... ..... 0110111 @u
> auipc .................... ..... 0010111 @u
> @@ -119,3 +126,31 @@ amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
> amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
> amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
> amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
> +
> +# *** RV32F Standard Extension ***
> +flw ............ ..... 010 ..... 0000111 @i
> +fsw ....... ..... ..... 010 ..... 0100111 @s
> +fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
> +fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
> +fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
> +fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
> +fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
> +fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
> +fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
> +fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
> +fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
> +fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
> +fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
> +fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
> +fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
> +fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
> +fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
> +fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
> +fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
> +feq_s 1010000 ..... ..... 010 ..... 1010011 @r
> +flt_s 1010000 ..... ..... 001 ..... 1010011 @r
> +fle_s 1010000 ..... ..... 000 ..... 1010011 @r
> +fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
> +fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
> +fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
> +fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
> diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
> new file mode 100644
> index 0000000000..b101593ac4
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvf.inc.c
> @@ -0,0 +1,334 @@
> +/*
> + * RISC-V translation routines for the RV64F Standard Extension.
> + *
> + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_FPU do {\
> + if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) \
> + return false; \
> +} while (0)
> +
> +static bool trans_flw(DisasContext *ctx, arg_flw *a)
> +{
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> + REQUIRE_FPU;
> + tcg_gen_addi_tl(t0, t0, a->imm);
> +
> + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
> + /* RISC-V requires NaN-boxing of narrower width floating point values */
> + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
> +{
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + REQUIRE_FPU;
> + tcg_gen_addi_tl(t0, t0, a->imm);
> +
> + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
> + return true;
> +}
> +
> +static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FMOV */
> + tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
> + } else { /* FSGNJ */
> + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
> + 0, 31);
> + }
> + return true;
> +}
> +
> +static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FNEG */
> + tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
> + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
> + tcg_temp_free_i64(t0);
> + }
> + return true;
> +}
> +
> +static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FABS */
> + tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN);
> + tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
> + tcg_temp_free_i64(t0);
> + }
> + return true;
> +}
> +
> +static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2]);
> + return true;
> +}
> +
> +static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
> +{
> + /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> +
> +#if defined(TARGET_RISCV64)
> + tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
> +#else
> + tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
> +#endif
> +
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
> +{
> + REQUIRE_FPU;
> + TCGv t0 = tcg_temp_new();
> + gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
> +{
> + REQUIRE_FPU;
> + TCGv t0 = tcg_temp_new();
> + gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
> +{
> + REQUIRE_FPU;
> + TCGv t0 = tcg_temp_new();
> + gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> +
> + gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
> +
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
> +
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
> +
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
> +{
> + /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> +#if defined(TARGET_RISCV64)
> + tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
> +#else
> + tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
> +#endif
> +
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 944836dd7c..933ca9fb69 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1514,6 +1514,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
> #include "insn_trans/trans_rvi.inc.c"
> #include "insn_trans/trans_rvm.inc.c"
> #include "insn_trans/trans_rva.inc.c"
> +#include "insn_trans/trans_rvf.inc.c"
>
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-23 0:08 ` Alistair Francis
-1 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 0:08 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:49 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32-64.decode | 6 +++
> target/riscv/insn_trans/trans_rvf.inc.c | 54 +++++++++++++++++++++++++
> 2 files changed, 60 insertions(+)
>
> diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
> index 0bee95c984..6319f872ac 100644
> --- a/target/riscv/insn32-64.decode
> +++ b/target/riscv/insn32-64.decode
> @@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
> amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
> amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
> amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
> +
> +# *** RV64F Standard Extension (in addition to RV32F) ***
> +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
> +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
> +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
> +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
> diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
> index b101593ac4..b667c576d4 100644
> --- a/target/riscv/insn_trans/trans_rvf.inc.c
> +++ b/target/riscv/insn_trans/trans_rvf.inc.c
> @@ -332,3 +332,57 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
>
> return true;
> }
> +
> +#ifdef TARGET_RISCV64
> +static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +#endif
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree
@ 2019-01-23 0:08 ` Alistair Francis
0 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 0:08 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:49 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32-64.decode | 6 +++
> target/riscv/insn_trans/trans_rvf.inc.c | 54 +++++++++++++++++++++++++
> 2 files changed, 60 insertions(+)
>
> diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
> index 0bee95c984..6319f872ac 100644
> --- a/target/riscv/insn32-64.decode
> +++ b/target/riscv/insn32-64.decode
> @@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
> amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
> amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
> amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
> +
> +# *** RV64F Standard Extension (in addition to RV32F) ***
> +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
> +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
> +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
> +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
> diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
> index b101593ac4..b667c576d4 100644
> --- a/target/riscv/insn_trans/trans_rvf.inc.c
> +++ b/target/riscv/insn_trans/trans_rvf.inc.c
> @@ -332,3 +332,57 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
>
> return true;
> }
> +
> +#ifdef TARGET_RISCV64
> +static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +#endif
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-23 0:08 ` Alistair Francis
-1 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 0:08 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:57 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 28 +++
> target/riscv/insn_trans/trans_rvd.inc.c | 315 ++++++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 3 files changed, 344 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index e40836bf03..e64b2b5e34 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -154,3 +154,31 @@ fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
> fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
> fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
> fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
> +
> +# *** RV32D Standard Extension ***
> +fld ............ ..... 011 ..... 0000111 @i
> +fsd ....... ..... ..... 011 ..... 0100111 @s
> +fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
> +fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
> +fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
> +fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
> +fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
> +fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
> +fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
> +fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
> +fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
> +fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
> +fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
> +fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
> +fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
> +fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
> +fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
> +fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
> +feq_d 1010001 ..... ..... 010 ..... 1010011 @r
> +flt_d 1010001 ..... ..... 001 ..... 1010011 @r
> +fle_d 1010001 ..... ..... 000 ..... 1010011 @r
> +fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
> +fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
> +fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
> +fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
> +fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
> diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
> new file mode 100644
> index 0000000000..a7e2335ffa
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvd.inc.c
> @@ -0,0 +1,315 @@
> +/*
> + * RISC-V translation routines for the RV64D Standard Extension.
> + *
> + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static bool trans_fld(DisasContext *ctx, arg_fld *a)
> +{
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> + REQUIRE_FPU;
> + tcg_gen_addi_tl(t0, t0, a->imm);
> +
> + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
> +{
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> + REQUIRE_FPU;
> + tcg_gen_addi_tl(t0, t0, a->imm);
> +
> + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
> +
> + return true;
> +}
> +
> +static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
> +{
> + if (a->rs1 == a->rs2) { /* FMOV */
> + tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
> + } else {
> + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2],
> + cpu_fpr[a->rs1], 0, 63);
> + }
> + return true;
> +}
> +
> +static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FNEG */
> + tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
> + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63);
> + tcg_temp_free_i64(t0);
> + }
> + return true;
> +}
> +
> +static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FABS */
> + tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN);
> + tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
> + tcg_temp_free_i64(t0);
> + }
> + return true;
> +}
> +
> +static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
> +
> + return true;
> +}
> +
> +static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 933ca9fb69..7f3443db20 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1515,6 +1515,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
> #include "insn_trans/trans_rvm.inc.c"
> #include "insn_trans/trans_rva.inc.c"
> #include "insn_trans/trans_rvf.inc.c"
> +#include "insn_trans/trans_rvd.inc.c"
>
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree
@ 2019-01-23 0:08 ` Alistair Francis
0 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 0:08 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:57 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 28 +++
> target/riscv/insn_trans/trans_rvd.inc.c | 315 ++++++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 3 files changed, 344 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index e40836bf03..e64b2b5e34 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -154,3 +154,31 @@ fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
> fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
> fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
> fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
> +
> +# *** RV32D Standard Extension ***
> +fld ............ ..... 011 ..... 0000111 @i
> +fsd ....... ..... ..... 011 ..... 0100111 @s
> +fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
> +fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
> +fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
> +fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
> +fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
> +fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
> +fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
> +fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
> +fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
> +fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
> +fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
> +fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
> +fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
> +fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
> +fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
> +fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
> +feq_d 1010001 ..... ..... 010 ..... 1010011 @r
> +flt_d 1010001 ..... ..... 001 ..... 1010011 @r
> +fle_d 1010001 ..... ..... 000 ..... 1010011 @r
> +fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
> +fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
> +fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
> +fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
> +fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
> diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
> new file mode 100644
> index 0000000000..a7e2335ffa
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvd.inc.c
> @@ -0,0 +1,315 @@
> +/*
> + * RISC-V translation routines for the RV64D Standard Extension.
> + *
> + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static bool trans_fld(DisasContext *ctx, arg_fld *a)
> +{
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> + REQUIRE_FPU;
> + tcg_gen_addi_tl(t0, t0, a->imm);
> +
> + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
> +{
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> + REQUIRE_FPU;
> + tcg_gen_addi_tl(t0, t0, a->imm);
> +
> + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
> +
> + return true;
> +}
> +
> +static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
> +{
> + if (a->rs1 == a->rs2) { /* FMOV */
> + tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
> + } else {
> + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2],
> + cpu_fpr[a->rs1], 0, 63);
> + }
> + return true;
> +}
> +
> +static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FNEG */
> + tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
> + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63);
> + tcg_temp_free_i64(t0);
> + }
> + return true;
> +}
> +
> +static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FABS */
> + tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN);
> + tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
> + tcg_temp_free_i64(t0);
> + }
> + return true;
> +}
> +
> +static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
> +
> + return true;
> +}
> +
> +static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 933ca9fb69..7f3443db20 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1515,6 +1515,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
> #include "insn_trans/trans_rvm.inc.c"
> #include "insn_trans/trans_rva.inc.c"
> #include "insn_trans/trans_rvf.inc.c"
> +#include "insn_trans/trans_rvd.inc.c"
>
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-23 0:10 ` Alistair Francis
-1 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 0:10 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:45 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32-64.decode | 8 +
> target/riscv/insn_trans/trans_rvd.inc.c | 73 ++++
> target/riscv/translate.c | 487 +-----------------------
> 3 files changed, 82 insertions(+), 486 deletions(-)
>
> diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
> index 6319f872ac..380bf791bc 100644
> --- a/target/riscv/insn32-64.decode
> +++ b/target/riscv/insn32-64.decode
> @@ -62,3 +62,11 @@ fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
> fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
> fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
> fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
> +
> +# *** RV64D Standard Extension (in addition to RV32D) ***
> +fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
> +fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
> +fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
> +fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
> +fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
> +fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
> diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
> index a7e2335ffa..2e45c8ed7e 100644
> --- a/target/riscv/insn_trans/trans_rvd.inc.c
> +++ b/target/riscv/insn_trans/trans_rvd.inc.c
> @@ -313,3 +313,76 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
>
> return true;
> }
> +
> +#ifdef TARGET_RISCV64
> +
> +static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
> + return true;
> +}
> +
> +static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +#endif
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 7f3443db20..4dda78d7c1 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -180,44 +180,6 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
> tcg_temp_free(rh);
> }
>
> -static void gen_fsgnj(DisasContext *ctx, uint32_t rd, uint32_t rs1,
> - uint32_t rs2, int rm, uint64_t min)
> -{
> - switch (rm) {
> - case 0: /* fsgnj */
> - if (rs1 == rs2) { /* FMOV */
> - tcg_gen_mov_i64(cpu_fpr[rd], cpu_fpr[rs1]);
> - } else {
> - tcg_gen_deposit_i64(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1],
> - 0, min == INT32_MIN ? 31 : 63);
> - }
> - break;
> - case 1: /* fsgnjn */
> - if (rs1 == rs2) { /* FNEG */
> - tcg_gen_xori_i64(cpu_fpr[rd], cpu_fpr[rs1], min);
> - } else {
> - TCGv_i64 t0 = tcg_temp_new_i64();
> - tcg_gen_not_i64(t0, cpu_fpr[rs2]);
> - tcg_gen_deposit_i64(cpu_fpr[rd], t0, cpu_fpr[rs1],
> - 0, min == INT32_MIN ? 31 : 63);
> - tcg_temp_free_i64(t0);
> - }
> - break;
> - case 2: /* fsgnjx */
> - if (rs1 == rs2) { /* FABS */
> - tcg_gen_andi_i64(cpu_fpr[rd], cpu_fpr[rs1], ~min);
> - } else {
> - TCGv_i64 t0 = tcg_temp_new_i64();
> - tcg_gen_andi_i64(t0, cpu_fpr[rs2], min);
> - tcg_gen_xor_i64(cpu_fpr[rd], cpu_fpr[rs1], t0);
> - tcg_temp_free_i64(t0);
> - }
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - }
> -}
> -
> static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
> int rs2)
> {
> @@ -724,421 +686,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
> tcg_temp_free_i32(t0);
> }
>
> -static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd,
> - int rs1, int rs2, int rs3, int rm)
> -{
> - switch (opc) {
> - case OPC_RISC_FMADD_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - case OPC_RISC_FMADD_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> -static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd,
> - int rs1, int rs2, int rs3, int rm)
> -{
> - switch (opc) {
> - case OPC_RISC_FMSUB_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - case OPC_RISC_FMSUB_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> -static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd,
> - int rs1, int rs2, int rs3, int rm)
> -{
> - switch (opc) {
> - case OPC_RISC_FNMSUB_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fnmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - case OPC_RISC_FNMSUB_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fnmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> -static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd,
> - int rs1, int rs2, int rs3, int rm)
> -{
> - switch (opc) {
> - case OPC_RISC_FNMADD_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fnmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - case OPC_RISC_FNMADD_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fnmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> -static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
> - int rs1, int rs2, int rm)
> -{
> - TCGv t0 = NULL;
> -
> - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
> - goto do_illegal;
> - }
> -
> - switch (opc) {
> - case OPC_RISC_FADD_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FSUB_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FMUL_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmul_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FDIV_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fdiv_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FSQRT_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fsqrt_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
> - break;
> - case OPC_RISC_FSGNJ_S:
> - gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN);
> - break;
> -
> - case OPC_RISC_FMIN_S:
> - /* also handles: OPC_RISC_FMAX_S */
> - switch (rm) {
> - case 0x0:
> - gen_helper_fmin_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 0x1:
> - gen_helper_fmax_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - break;
> -
> - case OPC_RISC_FEQ_S:
> - /* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */
> - t0 = tcg_temp_new();
> - switch (rm) {
> - case 0x0:
> - gen_helper_fle_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 0x1:
> - gen_helper_flt_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 0x2:
> - gen_helper_feq_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FCVT_W_S:
> - /* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S */
> - t0 = tcg_temp_new();
> - switch (rs2) {
> - case 0: /* FCVT_W_S */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> - case 1: /* FCVT_WU_S */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> -#if defined(TARGET_RISCV64)
> - case 2: /* FCVT_L_S */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> - case 3: /* FCVT_LU_S */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> -#endif
> - default:
> - goto do_illegal;
> - }
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FCVT_S_W:
> - /* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU */
> - t0 = tcg_temp_new();
> - gen_get_gpr(t0, rs1);
> - switch (rs2) {
> - case 0: /* FCVT_S_W */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_s_w(cpu_fpr[rd], cpu_env, t0);
> - break;
> - case 1: /* FCVT_S_WU */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_s_wu(cpu_fpr[rd], cpu_env, t0);
> - break;
> -#if defined(TARGET_RISCV64)
> - case 2: /* FCVT_S_L */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_s_l(cpu_fpr[rd], cpu_env, t0);
> - break;
> - case 3: /* FCVT_S_LU */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_s_lu(cpu_fpr[rd], cpu_env, t0);
> - break;
> -#endif
> - default:
> - goto do_illegal;
> - }
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FMV_X_S:
> - /* also OPC_RISC_FCLASS_S */
> - t0 = tcg_temp_new();
> - switch (rm) {
> - case 0: /* FMV */
> -#if defined(TARGET_RISCV64)
> - tcg_gen_ext32s_tl(t0, cpu_fpr[rs1]);
> -#else
> - tcg_gen_extrl_i64_i32(t0, cpu_fpr[rs1]);
> -#endif
> - break;
> - case 1:
> - gen_helper_fclass_s(t0, cpu_fpr[rs1]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FMV_S_X:
> - t0 = tcg_temp_new();
> - gen_get_gpr(t0, rs1);
> -#if defined(TARGET_RISCV64)
> - tcg_gen_mov_i64(cpu_fpr[rd], t0);
> -#else
> - tcg_gen_extu_i32_i64(cpu_fpr[rd], t0);
> -#endif
> - tcg_temp_free(t0);
> - break;
> -
> - /* double */
> - case OPC_RISC_FADD_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FSUB_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FMUL_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmul_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FDIV_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fdiv_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FSQRT_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fsqrt_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
> - break;
> - case OPC_RISC_FSGNJ_D:
> - gen_fsgnj(ctx, rd, rs1, rs2, rm, INT64_MIN);
> - break;
> -
> - case OPC_RISC_FMIN_D:
> - /* also OPC_RISC_FMAX_D */
> - switch (rm) {
> - case 0:
> - gen_helper_fmin_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 1:
> - gen_helper_fmax_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - break;
> -
> - case OPC_RISC_FCVT_S_D:
> - switch (rs2) {
> - case 1:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_s_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - break;
> -
> - case OPC_RISC_FCVT_D_S:
> - switch (rs2) {
> - case 0:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_d_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - break;
> -
> - case OPC_RISC_FEQ_D:
> - /* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */
> - t0 = tcg_temp_new();
> - switch (rm) {
> - case 0:
> - gen_helper_fle_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 1:
> - gen_helper_flt_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 2:
> - gen_helper_feq_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FCVT_W_D:
> - /* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D */
> - t0 = tcg_temp_new();
> - switch (rs2) {
> - case 0:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> - case 1:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> -#if defined(TARGET_RISCV64)
> - case 2:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> - case 3:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> -#endif
> - default:
> - goto do_illegal;
> - }
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FCVT_D_W:
> - /* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU */
> - t0 = tcg_temp_new();
> - gen_get_gpr(t0, rs1);
> - switch (rs2) {
> - case 0:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_d_w(cpu_fpr[rd], cpu_env, t0);
> - break;
> - case 1:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_d_wu(cpu_fpr[rd], cpu_env, t0);
> - break;
> -#if defined(TARGET_RISCV64)
> - case 2:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_d_l(cpu_fpr[rd], cpu_env, t0);
> - break;
> - case 3:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_d_lu(cpu_fpr[rd], cpu_env, t0);
> - break;
> -#endif
> - default:
> - goto do_illegal;
> - }
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FMV_X_D:
> - /* also OPC_RISC_FCLASS_D */
> - switch (rm) {
> -#if defined(TARGET_RISCV64)
> - case 0: /* FMV */
> - gen_set_gpr(rd, cpu_fpr[rs1]);
> - break;
> -#endif
> - case 1:
> - t0 = tcg_temp_new();
> - gen_helper_fclass_d(t0, cpu_fpr[rs1]);
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> - default:
> - goto do_illegal;
> - }
> - break;
> -
> -#if defined(TARGET_RISCV64)
> - case OPC_RISC_FMV_D_X:
> - t0 = tcg_temp_new();
> - gen_get_gpr(t0, rs1);
> - tcg_gen_mov_tl(cpu_fpr[rd], t0);
> - tcg_temp_free(t0);
> - break;
> -#endif
> -
> - default:
> - do_illegal:
> - if (t0) {
> - tcg_temp_free(t0);
> - }
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> int rd, int rs1, int csr)
> {
> @@ -1519,11 +1066,8 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
>
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> - int rs1;
> - int rs2;
> - int rd;
> + int rs1, rd;
> uint32_t op;
> - target_long imm;
>
> /* We do not do misaligned address check here: the address should never be
> * misaligned at this point. Instructions that set PC must do the check,
> @@ -1532,38 +1076,9 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
>
> op = MASK_OP_MAJOR(ctx->opcode);
> rs1 = GET_RS1(ctx->opcode);
> - rs2 = GET_RS2(ctx->opcode);
> rd = GET_RD(ctx->opcode);
> - imm = GET_IMM(ctx->opcode);
>
> switch (op) {
> - case OPC_RISC_FP_LOAD:
> - gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
> - break;
> - case OPC_RISC_FP_STORE:
> - gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2,
> - GET_STORE_IMM(ctx->opcode));
> - break;
> - case OPC_RISC_FMADD:
> - gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2,
> - GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
> - break;
> - case OPC_RISC_FMSUB:
> - gen_fp_fmsub(ctx, MASK_OP_FP_FMSUB(ctx->opcode), rd, rs1, rs2,
> - GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
> - break;
> - case OPC_RISC_FNMSUB:
> - gen_fp_fnmsub(ctx, MASK_OP_FP_FNMSUB(ctx->opcode), rd, rs1, rs2,
> - GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
> - break;
> - case OPC_RISC_FNMADD:
> - gen_fp_fnmadd(ctx, MASK_OP_FP_FNMADD(ctx->opcode), rd, rs1, rs2,
> - GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
> - break;
> - case OPC_RISC_FP_ARITH:
> - gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
> - GET_RM(ctx->opcode));
> - break;
> case OPC_RISC_SYSTEM:
> gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
> (ctx->opcode & 0xFFF00000) >> 20);
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D insns to decodetree
@ 2019-01-23 0:10 ` Alistair Francis
0 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 0:10 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:45 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32-64.decode | 8 +
> target/riscv/insn_trans/trans_rvd.inc.c | 73 ++++
> target/riscv/translate.c | 487 +-----------------------
> 3 files changed, 82 insertions(+), 486 deletions(-)
>
> diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
> index 6319f872ac..380bf791bc 100644
> --- a/target/riscv/insn32-64.decode
> +++ b/target/riscv/insn32-64.decode
> @@ -62,3 +62,11 @@ fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
> fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
> fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
> fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
> +
> +# *** RV64D Standard Extension (in addition to RV32D) ***
> +fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
> +fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
> +fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
> +fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
> +fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
> +fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
> diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
> index a7e2335ffa..2e45c8ed7e 100644
> --- a/target/riscv/insn_trans/trans_rvd.inc.c
> +++ b/target/riscv/insn_trans/trans_rvd.inc.c
> @@ -313,3 +313,76 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
>
> return true;
> }
> +
> +#ifdef TARGET_RISCV64
> +
> +static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
> + return true;
> +}
> +
> +static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +#endif
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 7f3443db20..4dda78d7c1 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -180,44 +180,6 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
> tcg_temp_free(rh);
> }
>
> -static void gen_fsgnj(DisasContext *ctx, uint32_t rd, uint32_t rs1,
> - uint32_t rs2, int rm, uint64_t min)
> -{
> - switch (rm) {
> - case 0: /* fsgnj */
> - if (rs1 == rs2) { /* FMOV */
> - tcg_gen_mov_i64(cpu_fpr[rd], cpu_fpr[rs1]);
> - } else {
> - tcg_gen_deposit_i64(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1],
> - 0, min == INT32_MIN ? 31 : 63);
> - }
> - break;
> - case 1: /* fsgnjn */
> - if (rs1 == rs2) { /* FNEG */
> - tcg_gen_xori_i64(cpu_fpr[rd], cpu_fpr[rs1], min);
> - } else {
> - TCGv_i64 t0 = tcg_temp_new_i64();
> - tcg_gen_not_i64(t0, cpu_fpr[rs2]);
> - tcg_gen_deposit_i64(cpu_fpr[rd], t0, cpu_fpr[rs1],
> - 0, min == INT32_MIN ? 31 : 63);
> - tcg_temp_free_i64(t0);
> - }
> - break;
> - case 2: /* fsgnjx */
> - if (rs1 == rs2) { /* FABS */
> - tcg_gen_andi_i64(cpu_fpr[rd], cpu_fpr[rs1], ~min);
> - } else {
> - TCGv_i64 t0 = tcg_temp_new_i64();
> - tcg_gen_andi_i64(t0, cpu_fpr[rs2], min);
> - tcg_gen_xor_i64(cpu_fpr[rd], cpu_fpr[rs1], t0);
> - tcg_temp_free_i64(t0);
> - }
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - }
> -}
> -
> static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
> int rs2)
> {
> @@ -724,421 +686,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
> tcg_temp_free_i32(t0);
> }
>
> -static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd,
> - int rs1, int rs2, int rs3, int rm)
> -{
> - switch (opc) {
> - case OPC_RISC_FMADD_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - case OPC_RISC_FMADD_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> -static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd,
> - int rs1, int rs2, int rs3, int rm)
> -{
> - switch (opc) {
> - case OPC_RISC_FMSUB_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - case OPC_RISC_FMSUB_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> -static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd,
> - int rs1, int rs2, int rs3, int rm)
> -{
> - switch (opc) {
> - case OPC_RISC_FNMSUB_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fnmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - case OPC_RISC_FNMSUB_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fnmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> -static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd,
> - int rs1, int rs2, int rs3, int rm)
> -{
> - switch (opc) {
> - case OPC_RISC_FNMADD_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fnmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - case OPC_RISC_FNMADD_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fnmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> - cpu_fpr[rs2], cpu_fpr[rs3]);
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> -static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
> - int rs1, int rs2, int rm)
> -{
> - TCGv t0 = NULL;
> -
> - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
> - goto do_illegal;
> - }
> -
> - switch (opc) {
> - case OPC_RISC_FADD_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FSUB_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FMUL_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmul_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FDIV_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fdiv_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FSQRT_S:
> - gen_set_rm(ctx, rm);
> - gen_helper_fsqrt_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
> - break;
> - case OPC_RISC_FSGNJ_S:
> - gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN);
> - break;
> -
> - case OPC_RISC_FMIN_S:
> - /* also handles: OPC_RISC_FMAX_S */
> - switch (rm) {
> - case 0x0:
> - gen_helper_fmin_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 0x1:
> - gen_helper_fmax_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - break;
> -
> - case OPC_RISC_FEQ_S:
> - /* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */
> - t0 = tcg_temp_new();
> - switch (rm) {
> - case 0x0:
> - gen_helper_fle_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 0x1:
> - gen_helper_flt_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 0x2:
> - gen_helper_feq_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FCVT_W_S:
> - /* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S */
> - t0 = tcg_temp_new();
> - switch (rs2) {
> - case 0: /* FCVT_W_S */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> - case 1: /* FCVT_WU_S */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> -#if defined(TARGET_RISCV64)
> - case 2: /* FCVT_L_S */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> - case 3: /* FCVT_LU_S */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> -#endif
> - default:
> - goto do_illegal;
> - }
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FCVT_S_W:
> - /* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU */
> - t0 = tcg_temp_new();
> - gen_get_gpr(t0, rs1);
> - switch (rs2) {
> - case 0: /* FCVT_S_W */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_s_w(cpu_fpr[rd], cpu_env, t0);
> - break;
> - case 1: /* FCVT_S_WU */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_s_wu(cpu_fpr[rd], cpu_env, t0);
> - break;
> -#if defined(TARGET_RISCV64)
> - case 2: /* FCVT_S_L */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_s_l(cpu_fpr[rd], cpu_env, t0);
> - break;
> - case 3: /* FCVT_S_LU */
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_s_lu(cpu_fpr[rd], cpu_env, t0);
> - break;
> -#endif
> - default:
> - goto do_illegal;
> - }
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FMV_X_S:
> - /* also OPC_RISC_FCLASS_S */
> - t0 = tcg_temp_new();
> - switch (rm) {
> - case 0: /* FMV */
> -#if defined(TARGET_RISCV64)
> - tcg_gen_ext32s_tl(t0, cpu_fpr[rs1]);
> -#else
> - tcg_gen_extrl_i64_i32(t0, cpu_fpr[rs1]);
> -#endif
> - break;
> - case 1:
> - gen_helper_fclass_s(t0, cpu_fpr[rs1]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FMV_S_X:
> - t0 = tcg_temp_new();
> - gen_get_gpr(t0, rs1);
> -#if defined(TARGET_RISCV64)
> - tcg_gen_mov_i64(cpu_fpr[rd], t0);
> -#else
> - tcg_gen_extu_i32_i64(cpu_fpr[rd], t0);
> -#endif
> - tcg_temp_free(t0);
> - break;
> -
> - /* double */
> - case OPC_RISC_FADD_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FSUB_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FMUL_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fmul_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FDIV_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fdiv_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case OPC_RISC_FSQRT_D:
> - gen_set_rm(ctx, rm);
> - gen_helper_fsqrt_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
> - break;
> - case OPC_RISC_FSGNJ_D:
> - gen_fsgnj(ctx, rd, rs1, rs2, rm, INT64_MIN);
> - break;
> -
> - case OPC_RISC_FMIN_D:
> - /* also OPC_RISC_FMAX_D */
> - switch (rm) {
> - case 0:
> - gen_helper_fmin_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 1:
> - gen_helper_fmax_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - break;
> -
> - case OPC_RISC_FCVT_S_D:
> - switch (rs2) {
> - case 1:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_s_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - break;
> -
> - case OPC_RISC_FCVT_D_S:
> - switch (rs2) {
> - case 0:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_d_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - break;
> -
> - case OPC_RISC_FEQ_D:
> - /* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */
> - t0 = tcg_temp_new();
> - switch (rm) {
> - case 0:
> - gen_helper_fle_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 1:
> - gen_helper_flt_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - case 2:
> - gen_helper_feq_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
> - break;
> - default:
> - goto do_illegal;
> - }
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FCVT_W_D:
> - /* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D */
> - t0 = tcg_temp_new();
> - switch (rs2) {
> - case 0:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> - case 1:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> -#if defined(TARGET_RISCV64)
> - case 2:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> - case 3:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[rs1]);
> - break;
> -#endif
> - default:
> - goto do_illegal;
> - }
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FCVT_D_W:
> - /* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU */
> - t0 = tcg_temp_new();
> - gen_get_gpr(t0, rs1);
> - switch (rs2) {
> - case 0:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_d_w(cpu_fpr[rd], cpu_env, t0);
> - break;
> - case 1:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_d_wu(cpu_fpr[rd], cpu_env, t0);
> - break;
> -#if defined(TARGET_RISCV64)
> - case 2:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_d_l(cpu_fpr[rd], cpu_env, t0);
> - break;
> - case 3:
> - gen_set_rm(ctx, rm);
> - gen_helper_fcvt_d_lu(cpu_fpr[rd], cpu_env, t0);
> - break;
> -#endif
> - default:
> - goto do_illegal;
> - }
> - tcg_temp_free(t0);
> - break;
> -
> - case OPC_RISC_FMV_X_D:
> - /* also OPC_RISC_FCLASS_D */
> - switch (rm) {
> -#if defined(TARGET_RISCV64)
> - case 0: /* FMV */
> - gen_set_gpr(rd, cpu_fpr[rs1]);
> - break;
> -#endif
> - case 1:
> - t0 = tcg_temp_new();
> - gen_helper_fclass_d(t0, cpu_fpr[rs1]);
> - gen_set_gpr(rd, t0);
> - tcg_temp_free(t0);
> - break;
> - default:
> - goto do_illegal;
> - }
> - break;
> -
> -#if defined(TARGET_RISCV64)
> - case OPC_RISC_FMV_D_X:
> - t0 = tcg_temp_new();
> - gen_get_gpr(t0, rs1);
> - tcg_gen_mov_tl(cpu_fpr[rd], t0);
> - tcg_temp_free(t0);
> - break;
> -#endif
> -
> - default:
> - do_illegal:
> - if (t0) {
> - tcg_temp_free(t0);
> - }
> - gen_exception_illegal(ctx);
> - break;
> - }
> -}
> -
> static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> int rd, int rs1, int csr)
> {
> @@ -1519,11 +1066,8 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
>
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> - int rs1;
> - int rs2;
> - int rd;
> + int rs1, rd;
> uint32_t op;
> - target_long imm;
>
> /* We do not do misaligned address check here: the address should never be
> * misaligned at this point. Instructions that set PC must do the check,
> @@ -1532,38 +1076,9 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
>
> op = MASK_OP_MAJOR(ctx->opcode);
> rs1 = GET_RS1(ctx->opcode);
> - rs2 = GET_RS2(ctx->opcode);
> rd = GET_RD(ctx->opcode);
> - imm = GET_IMM(ctx->opcode);
>
> switch (op) {
> - case OPC_RISC_FP_LOAD:
> - gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
> - break;
> - case OPC_RISC_FP_STORE:
> - gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2,
> - GET_STORE_IMM(ctx->opcode));
> - break;
> - case OPC_RISC_FMADD:
> - gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2,
> - GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
> - break;
> - case OPC_RISC_FMSUB:
> - gen_fp_fmsub(ctx, MASK_OP_FP_FMSUB(ctx->opcode), rd, rs1, rs2,
> - GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
> - break;
> - case OPC_RISC_FNMSUB:
> - gen_fp_fnmsub(ctx, MASK_OP_FP_FNMSUB(ctx->opcode), rd, rs1, rs2,
> - GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
> - break;
> - case OPC_RISC_FNMADD:
> - gen_fp_fnmadd(ctx, MASK_OP_FP_FNMADD(ctx->opcode), rd, rs1, rs2,
> - GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
> - break;
> - case OPC_RISC_FP_ARITH:
> - gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
> - GET_RM(ctx->opcode));
> - break;
> case OPC_RISC_SYSTEM:
> gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
> (ctx->opcode & 0xFFF00000) >> 20);
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv insns to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-23 1:00 ` Alistair Francis
-1 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 1:00 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:55 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 15 +++
> .../riscv/insn_trans/trans_privileged.inc.c | 110 ++++++++++++++++++
> target/riscv/translate.c | 57 +--------
> 3 files changed, 126 insertions(+), 56 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index e64b2b5e34..ecc46a50cc 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -57,6 +57,21 @@
> @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
> @r2 ....... ..... ..... ... ..... ....... %rs1 %rd
>
> +@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
> +@sfence_vm ....... ..... ..... ... ..... ....... %rs1
> +
> +
> +# *** Privileged Instructions ***
> +ecall 000000000000 00000 000 00000 1110011
> +ebreak 000000000001 00000 000 00000 1110011
> +uret 0000000 00010 00000 000 00000 1110011
> +sret 0001000 00010 00000 000 00000 1110011
> +hret 0010000 00010 00000 000 00000 1110011
> +mret 0011000 00010 00000 000 00000 1110011
> +wfi 0001000 00101 00000 000 00000 1110011
> +sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
> +sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
> +
> # *** RV32I Base Instruction Set ***
> lui .................... ..... 0110111 @u
> auipc .................... ..... 0010111 @u
> diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
> new file mode 100644
> index 0000000000..fb2da8f5f0
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_privileged.inc.c
> @@ -0,0 +1,110 @@
> +/*
> + * RISC-V translation routines for the RISC-V privileged instructions.
> + *
> + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
> +{
> + /* always generates U-level ECALL, fixed in do_interrupt handler */
> + generate_exception(ctx, RISCV_EXCP_U_ECALL);
> + tcg_gen_exit_tb(NULL, 0); /* no chaining */
> + ctx->base.is_jmp = DISAS_NORETURN;
> + return true;
> +}
> +
> +static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
> +{
> + generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
> + tcg_gen_exit_tb(NULL, 0); /* no chaining */
> + ctx->base.is_jmp = DISAS_NORETURN;
> + return true;
> +}
> +
> +static bool trans_uret(DisasContext *ctx, arg_uret *a)
> +{
> + return false;
> +}
> +
> +static bool trans_sret(DisasContext *ctx, arg_sret *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> +
> + if (riscv_has_ext(ctx->env, RVS)) {
> + gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
> + tcg_gen_exit_tb(NULL, 0); /* no chaining */
> + ctx->base.is_jmp = DISAS_NORETURN;
> + } else {
> + return false;
> + }
> + return true;
> +#else
> + return false;
> +#endif
> +}
> +
> +static bool trans_hret(DisasContext *ctx, arg_hret *a)
> +{
> + return false;
> +}
> +
> +static bool trans_mret(DisasContext *ctx, arg_mret *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> + gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
> + tcg_gen_exit_tb(NULL, 0); /* no chaining */
> + ctx->base.is_jmp = DISAS_NORETURN;
> + return true;
> +#else
> + return false;
> +#endif
> +}
> +
> +static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> + gen_helper_wfi(cpu_env);
> + return true;
> +#else
> + return false;
> +#endif
> +}
> +
> +static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + if (ctx->env->priv_ver == PRIV_VERSION_1_10_0) {
> + gen_helper_tlb_flush(cpu_env);
> + return true;
> + }
> +#endif
> + return false;
> +}
> +
> +static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + if (ctx->env->priv_ver <= PRIV_VERSION_1_09_1) {
> + gen_helper_tlb_flush(cpu_env);
> + return true;
> + }
> +#endif
> + return false;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 4dda78d7c1..ff15e0f7ed 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -689,26 +689,8 @@ static void gen_set_rm(DisasContext *ctx, int rm)
> static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> int rd, int rs1, int csr)
> {
> - TCGv source1, dest;
> - source1 = tcg_temp_new();
> - dest = tcg_temp_new();
> - gen_get_gpr(source1, rs1);
> tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
>
> -#ifndef CONFIG_USER_ONLY
> - /* Extract funct7 value and check whether it matches SFENCE.VMA */
> - if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
> - if (env->priv_ver == PRIV_VERSION_1_10_0) {
> - /* sfence.vma */
> - /* TODO: handle ASID specific fences */
> - gen_helper_tlb_flush(cpu_env);
> - return;
> - } else {
> - gen_exception_illegal(ctx);
> - }
> - }
> -#endif
> -
> switch (opc) {
> case OPC_RISC_ECALL:
> switch (csr) {
> @@ -723,50 +705,12 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> tcg_gen_exit_tb(NULL, 0); /* no chaining */
> ctx->base.is_jmp = DISAS_NORETURN;
> break;
> -#ifndef CONFIG_USER_ONLY
> - case 0x002: /* URET */
> - gen_exception_illegal(ctx);
> - break;
> - case 0x102: /* SRET */
> - if (riscv_has_ext(env, RVS)) {
> - gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
> - tcg_gen_exit_tb(NULL, 0); /* no chaining */
> - ctx->base.is_jmp = DISAS_NORETURN;
> - } else {
> - gen_exception_illegal(ctx);
> - }
> - break;
> - case 0x202: /* HRET */
> - gen_exception_illegal(ctx);
> - break;
> - case 0x302: /* MRET */
> - gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
> - tcg_gen_exit_tb(NULL, 0); /* no chaining */
> - ctx->base.is_jmp = DISAS_NORETURN;
> - break;
> - case 0x7b2: /* DRET */
> - gen_exception_illegal(ctx);
> - break;
> - case 0x105: /* WFI */
> - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> - gen_helper_wfi(cpu_env);
> - break;
> - case 0x104: /* SFENCE.VM */
> - if (env->priv_ver <= PRIV_VERSION_1_09_1) {
> - gen_helper_tlb_flush(cpu_env);
> - } else {
> - gen_exception_illegal(ctx);
> - }
> - break;
> -#endif
> default:
> gen_exception_illegal(ctx);
> break;
> }
> break;
> }
> - tcg_temp_free(source1);
> - tcg_temp_free(dest);
> }
>
> static void decode_RV32_64C0(DisasContext *ctx)
> @@ -1063,6 +1007,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
> #include "insn_trans/trans_rva.inc.c"
> #include "insn_trans/trans_rvf.inc.c"
> #include "insn_trans/trans_rvd.inc.c"
> +#include "insn_trans/trans_privileged.inc.c"
>
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv insns to decodetree
@ 2019-01-23 1:00 ` Alistair Francis
0 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 1:00 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Sagar Karandikar, Palmer Dabbelt, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:55 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 15 +++
> .../riscv/insn_trans/trans_privileged.inc.c | 110 ++++++++++++++++++
> target/riscv/translate.c | 57 +--------
> 3 files changed, 126 insertions(+), 56 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index e64b2b5e34..ecc46a50cc 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -57,6 +57,21 @@
> @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
> @r2 ....... ..... ..... ... ..... ....... %rs1 %rd
>
> +@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
> +@sfence_vm ....... ..... ..... ... ..... ....... %rs1
> +
> +
> +# *** Privileged Instructions ***
> +ecall 000000000000 00000 000 00000 1110011
> +ebreak 000000000001 00000 000 00000 1110011
> +uret 0000000 00010 00000 000 00000 1110011
> +sret 0001000 00010 00000 000 00000 1110011
> +hret 0010000 00010 00000 000 00000 1110011
> +mret 0011000 00010 00000 000 00000 1110011
> +wfi 0001000 00101 00000 000 00000 1110011
> +sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
> +sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
> +
> # *** RV32I Base Instruction Set ***
> lui .................... ..... 0110111 @u
> auipc .................... ..... 0010111 @u
> diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
> new file mode 100644
> index 0000000000..fb2da8f5f0
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_privileged.inc.c
> @@ -0,0 +1,110 @@
> +/*
> + * RISC-V translation routines for the RISC-V privileged instructions.
> + *
> + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
> +{
> + /* always generates U-level ECALL, fixed in do_interrupt handler */
> + generate_exception(ctx, RISCV_EXCP_U_ECALL);
> + tcg_gen_exit_tb(NULL, 0); /* no chaining */
> + ctx->base.is_jmp = DISAS_NORETURN;
> + return true;
> +}
> +
> +static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
> +{
> + generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
> + tcg_gen_exit_tb(NULL, 0); /* no chaining */
> + ctx->base.is_jmp = DISAS_NORETURN;
> + return true;
> +}
> +
> +static bool trans_uret(DisasContext *ctx, arg_uret *a)
> +{
> + return false;
> +}
> +
> +static bool trans_sret(DisasContext *ctx, arg_sret *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> +
> + if (riscv_has_ext(ctx->env, RVS)) {
> + gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
> + tcg_gen_exit_tb(NULL, 0); /* no chaining */
> + ctx->base.is_jmp = DISAS_NORETURN;
> + } else {
> + return false;
> + }
> + return true;
> +#else
> + return false;
> +#endif
> +}
> +
> +static bool trans_hret(DisasContext *ctx, arg_hret *a)
> +{
> + return false;
> +}
> +
> +static bool trans_mret(DisasContext *ctx, arg_mret *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> + gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
> + tcg_gen_exit_tb(NULL, 0); /* no chaining */
> + ctx->base.is_jmp = DISAS_NORETURN;
> + return true;
> +#else
> + return false;
> +#endif
> +}
> +
> +static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> + gen_helper_wfi(cpu_env);
> + return true;
> +#else
> + return false;
> +#endif
> +}
> +
> +static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + if (ctx->env->priv_ver == PRIV_VERSION_1_10_0) {
> + gen_helper_tlb_flush(cpu_env);
> + return true;
> + }
> +#endif
> + return false;
> +}
> +
> +static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> + if (ctx->env->priv_ver <= PRIV_VERSION_1_09_1) {
> + gen_helper_tlb_flush(cpu_env);
> + return true;
> + }
> +#endif
> + return false;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 4dda78d7c1..ff15e0f7ed 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -689,26 +689,8 @@ static void gen_set_rm(DisasContext *ctx, int rm)
> static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> int rd, int rs1, int csr)
> {
> - TCGv source1, dest;
> - source1 = tcg_temp_new();
> - dest = tcg_temp_new();
> - gen_get_gpr(source1, rs1);
> tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
>
> -#ifndef CONFIG_USER_ONLY
> - /* Extract funct7 value and check whether it matches SFENCE.VMA */
> - if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
> - if (env->priv_ver == PRIV_VERSION_1_10_0) {
> - /* sfence.vma */
> - /* TODO: handle ASID specific fences */
> - gen_helper_tlb_flush(cpu_env);
> - return;
> - } else {
> - gen_exception_illegal(ctx);
> - }
> - }
> -#endif
> -
> switch (opc) {
> case OPC_RISC_ECALL:
> switch (csr) {
> @@ -723,50 +705,12 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> tcg_gen_exit_tb(NULL, 0); /* no chaining */
> ctx->base.is_jmp = DISAS_NORETURN;
> break;
> -#ifndef CONFIG_USER_ONLY
> - case 0x002: /* URET */
> - gen_exception_illegal(ctx);
> - break;
> - case 0x102: /* SRET */
> - if (riscv_has_ext(env, RVS)) {
> - gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
> - tcg_gen_exit_tb(NULL, 0); /* no chaining */
> - ctx->base.is_jmp = DISAS_NORETURN;
> - } else {
> - gen_exception_illegal(ctx);
> - }
> - break;
> - case 0x202: /* HRET */
> - gen_exception_illegal(ctx);
> - break;
> - case 0x302: /* MRET */
> - gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
> - tcg_gen_exit_tb(NULL, 0); /* no chaining */
> - ctx->base.is_jmp = DISAS_NORETURN;
> - break;
> - case 0x7b2: /* DRET */
> - gen_exception_illegal(ctx);
> - break;
> - case 0x105: /* WFI */
> - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> - gen_helper_wfi(cpu_env);
> - break;
> - case 0x104: /* SFENCE.VM */
> - if (env->priv_ver <= PRIV_VERSION_1_09_1) {
> - gen_helper_tlb_flush(cpu_env);
> - } else {
> - gen_exception_illegal(ctx);
> - }
> - break;
> -#endif
> default:
> gen_exception_illegal(ctx);
> break;
> }
> break;
> }
> - tcg_temp_free(source1);
> - tcg_temp_free(dest);
> }
>
> static void decode_RV32_64C0(DisasContext *ctx)
> @@ -1063,6 +1007,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
> #include "insn_trans/trans_rva.inc.c"
> #include "insn_trans/trans_rvf.inc.c"
> #include "insn_trans/trans_rvd.inc.c"
> +#include "insn_trans/trans_privileged.inc.c"
>
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 21:38 ` [Qemu-riscv] " Richard Henderson
@ 2019-01-23 9:15 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-23 9:15 UTC (permalink / raw)
To: Richard Henderson, sagark, palmer; +Cc: peer.adelt, qemu-riscv, qemu-devel
On 1/22/19 10:38 PM, Richard Henderson wrote:
> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
>> Hi,
>>
>> this patchset converts the RISC-V decoder to decodetree in four major steps:
>>
>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>> Many of the gen_* functions are called by the decode functions for 16-bit
>> and 32-bit functions. If we move translation code from the gen_*
>> functions to the generated trans_* functions of decode-tree, we get a lot of
>> duplication. Therefore, we mostly generate calls to the old gen_* function
>> which are properly replaced after step 2).
>>
>> Each of the trans_ functions are grouped into files corresponding to their
>> ISA extension, e.g. addi which is in RV32I is translated in the file
>> 'trans_rvi.inc.c'.
>>
>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
>> we convert the arguments in the 16 bit trans_ function to the arguments of
>> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>>
>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
>> this move all manual translation code into the trans_* instructions of
>> decode tree, such that we can remove the old decode_* functions.
>>
>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
>> by Richard. [Patch 31-35]
>>
>> full tree available at
>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>>
>> Cheers,
>> Bastian
>>
>> v4 -> v5:
>> - fixed rebase error
>> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
>> - removed extra sign extension of sraiw
>> - removed rs2 == 0 special cases in sraw/srlw
> All looks good to me now. Thanks for persevering.
Thanks for your great reviews. I'll do a final respin to fix the funky
indentations. Alistair do you want to pick up the series?
Cheers,
Bastian
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-23 9:15 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-23 9:15 UTC (permalink / raw)
To: Richard Henderson, sagark, palmer; +Cc: peer.adelt, qemu-riscv, qemu-devel
On 1/22/19 10:38 PM, Richard Henderson wrote:
> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
>> Hi,
>>
>> this patchset converts the RISC-V decoder to decodetree in four major steps:
>>
>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>> Many of the gen_* functions are called by the decode functions for 16-bit
>> and 32-bit functions. If we move translation code from the gen_*
>> functions to the generated trans_* functions of decode-tree, we get a lot of
>> duplication. Therefore, we mostly generate calls to the old gen_* function
>> which are properly replaced after step 2).
>>
>> Each of the trans_ functions are grouped into files corresponding to their
>> ISA extension, e.g. addi which is in RV32I is translated in the file
>> 'trans_rvi.inc.c'.
>>
>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
>> we convert the arguments in the 16 bit trans_ function to the arguments of
>> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>>
>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
>> this move all manual translation code into the trans_* instructions of
>> decode tree, such that we can remove the old decode_* functions.
>>
>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
>> by Richard. [Patch 31-35]
>>
>> full tree available at
>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>>
>> Cheers,
>> Bastian
>>
>> v4 -> v5:
>> - fixed rebase error
>> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
>> - removed extra sign extension of sraiw
>> - removed rs2 == 0 special cases in sraw/srlw
> All looks good to me now. Thanks for persevering.
Thanks for your great reviews. I'll do a final respin to fix the funky
indentations. Alistair do you want to pick up the series?
Cheers,
Bastian
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-23 9:15 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-23 21:22 ` Alistair Francis
-1 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 21:22 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Richard Henderson, Sagar Karandikar, Palmer Dabbelt, peer.adelt,
qemu-riscv, qemu-devel@nongnu.org Developers
On Wed, Jan 23, 2019 at 1:15 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
>
> On 1/22/19 10:38 PM, Richard Henderson wrote:
> > On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> >> Hi,
> >>
> >> this patchset converts the RISC-V decoder to decodetree in four major steps:
> >>
> >> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> >> Many of the gen_* functions are called by the decode functions for 16-bit
> >> and 32-bit functions. If we move translation code from the gen_*
> >> functions to the generated trans_* functions of decode-tree, we get a lot of
> >> duplication. Therefore, we mostly generate calls to the old gen_* function
> >> which are properly replaced after step 2).
> >>
> >> Each of the trans_ functions are grouped into files corresponding to their
> >> ISA extension, e.g. addi which is in RV32I is translated in the file
> >> 'trans_rvi.inc.c'.
> >>
> >> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
> >> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
> >> we convert the arguments in the 16 bit trans_ function to the arguments of
> >> the corresponding 32 bit instruction and call the 32 bit trans_ function.
> >>
> >> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
> >> this move all manual translation code into the trans_* instructions of
> >> decode tree, such that we can remove the old decode_* functions.
> >>
> >> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
> >> by Richard. [Patch 31-35]
> >>
> >> full tree available at
> >> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
> >>
> >> Cheers,
> >> Bastian
> >>
> >> v4 -> v5:
> >> - fixed rebase error
> >> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
> >> - removed extra sign extension of sraiw
> >> - removed rs2 == 0 special cases in sraw/srlw
> > All looks good to me now. Thanks for persevering.
>
>
> Thanks for your great reviews. I'll do a final respin to fix the funky
> indentations. Alistair do you want to pick up the series?
Thanks, the series looks good :)
Palmer is in charge of pull requests for RISC-V QEMU. So it will have
to go through him.
Alistair
>
> Cheers,
>
> Bastian
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-23 21:22 ` Alistair Francis
0 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-23 21:22 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Richard Henderson, Sagar Karandikar, Palmer Dabbelt, peer.adelt,
qemu-riscv, qemu-devel@nongnu.org Developers
On Wed, Jan 23, 2019 at 1:15 AM Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
>
> On 1/22/19 10:38 PM, Richard Henderson wrote:
> > On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> >> Hi,
> >>
> >> this patchset converts the RISC-V decoder to decodetree in four major steps:
> >>
> >> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> >> Many of the gen_* functions are called by the decode functions for 16-bit
> >> and 32-bit functions. If we move translation code from the gen_*
> >> functions to the generated trans_* functions of decode-tree, we get a lot of
> >> duplication. Therefore, we mostly generate calls to the old gen_* function
> >> which are properly replaced after step 2).
> >>
> >> Each of the trans_ functions are grouped into files corresponding to their
> >> ISA extension, e.g. addi which is in RV32I is translated in the file
> >> 'trans_rvi.inc.c'.
> >>
> >> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
> >> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
> >> we convert the arguments in the 16 bit trans_ function to the arguments of
> >> the corresponding 32 bit instruction and call the 32 bit trans_ function.
> >>
> >> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
> >> this move all manual translation code into the trans_* instructions of
> >> decode tree, such that we can remove the old decode_* functions.
> >>
> >> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
> >> by Richard. [Patch 31-35]
> >>
> >> full tree available at
> >> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
> >>
> >> Cheers,
> >> Bastian
> >>
> >> v4 -> v5:
> >> - fixed rebase error
> >> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
> >> - removed extra sign extension of sraiw
> >> - removed rs2 == 0 special cases in sraw/srlw
> > All looks good to me now. Thanks for persevering.
>
>
> Thanks for your great reviews. I'll do a final respin to fix the funky
> indentations. Alistair do you want to pick up the series?
Thanks, the series looks good :)
Palmer is in charge of pull requests for RISC-V QEMU. So it will have
to go through him.
Alistair
>
> Cheers,
>
> Bastian
>
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 21:38 ` [Qemu-riscv] " Richard Henderson
@ 2019-01-25 23:54 ` Palmer Dabbelt
-1 siblings, 0 replies; 164+ messages in thread
From: Palmer Dabbelt @ 2019-01-25 23:54 UTC (permalink / raw)
To: richard.henderson
Cc: Bastian Koppelmann, sagark, peer.adelt, qemu-riscv, qemu-devel
On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.henderson@linaro.org wrote:
> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
>> Hi,
>>
>> this patchset converts the RISC-V decoder to decodetree in four major steps:
>>
>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>> Many of the gen_* functions are called by the decode functions for 16-bit
>> and 32-bit functions. If we move translation code from the gen_*
>> functions to the generated trans_* functions of decode-tree, we get a lot of
>> duplication. Therefore, we mostly generate calls to the old gen_* function
>> which are properly replaced after step 2).
>>
>> Each of the trans_ functions are grouped into files corresponding to their
>> ISA extension, e.g. addi which is in RV32I is translated in the file
>> 'trans_rvi.inc.c'.
>>
>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
>> we convert the arguments in the 16 bit trans_ function to the arguments of
>> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>>
>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
>> this move all manual translation code into the trans_* instructions of
>> decode tree, such that we can remove the old decode_* functions.
>>
>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
>> by Richard. [Patch 31-35]
>>
>> full tree available at
>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>>
>> Cheers,
>> Bastian
>>
>> v4 -> v5:
>> - fixed rebase error
>> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
>> - removed extra sign extension of sraiw
>> - removed rs2 == 0 special cases in sraw/srlw
>
> All looks good to me now. Thanks for persevering.
Thanks for reviewing this.
Bastian: what sort of testing have you done here? This is a pretty big change,
and while it's been fairly extensively reviewed I'm just generally paranoid.
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-25 23:54 ` Palmer Dabbelt
0 siblings, 0 replies; 164+ messages in thread
From: Palmer Dabbelt @ 2019-01-25 23:54 UTC (permalink / raw)
To: richard.henderson
Cc: Bastian Koppelmann, sagark, peer.adelt, qemu-riscv, qemu-devel
On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.henderson@linaro.org wrote:
> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
>> Hi,
>>
>> this patchset converts the RISC-V decoder to decodetree in four major steps:
>>
>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>> Many of the gen_* functions are called by the decode functions for 16-bit
>> and 32-bit functions. If we move translation code from the gen_*
>> functions to the generated trans_* functions of decode-tree, we get a lot of
>> duplication. Therefore, we mostly generate calls to the old gen_* function
>> which are properly replaced after step 2).
>>
>> Each of the trans_ functions are grouped into files corresponding to their
>> ISA extension, e.g. addi which is in RV32I is translated in the file
>> 'trans_rvi.inc.c'.
>>
>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
>> we convert the arguments in the 16 bit trans_ function to the arguments of
>> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>>
>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
>> this move all manual translation code into the trans_* instructions of
>> decode tree, such that we can remove the old decode_* functions.
>>
>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
>> by Richard. [Patch 31-35]
>>
>> full tree available at
>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>>
>> Cheers,
>> Bastian
>>
>> v4 -> v5:
>> - fixed rebase error
>> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
>> - removed extra sign extension of sraiw
>> - removed rs2 == 0 special cases in sraw/srlw
>
> All looks good to me now. Thanks for persevering.
Thanks for reviewing this.
Bastian: what sort of testing have you done here? This is a pretty big change,
and while it's been fairly extensively reviewed I'm just generally paranoid.
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-25 23:54 ` [Qemu-riscv] " Palmer Dabbelt
@ 2019-01-26 8:51 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-26 8:51 UTC (permalink / raw)
To: Palmer Dabbelt, richard.henderson
Cc: peer.adelt, qemu-riscv, qemu-devel, sagark
On 1/26/19 12:54 AM, Palmer Dabbelt wrote:
> On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.henderson@linaro.org wrote:
>> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
>>> Hi,
>>>
>>> this patchset converts the RISC-V decoder to decodetree in four major steps:
>>>
>>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>>> Many of the gen_* functions are called by the decode functions for 16-bit
>>> and 32-bit functions. If we move translation code from the gen_*
>>> functions to the generated trans_* functions of decode-tree, we get a lot of
>>> duplication. Therefore, we mostly generate calls to the old gen_* function
>>> which are properly replaced after step 2).
>>>
>>> Each of the trans_ functions are grouped into files corresponding to their
>>> ISA extension, e.g. addi which is in RV32I is translated in the file
>>> 'trans_rvi.inc.c'.
>>>
>>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>>> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
>>> we convert the arguments in the 16 bit trans_ function to the arguments of
>>> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>>>
>>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
>>> this move all manual translation code into the trans_* instructions of
>>> decode tree, such that we can remove the old decode_* functions.
>>>
>>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
>>> by Richard. [Patch 31-35]
>>>
>>> full tree available at
>>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>>>
>>> Cheers,
>>> Bastian
>>>
>>> v4 -> v5:
>>> - fixed rebase error
>>> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
>>> - removed extra sign extension of sraiw
>>> - removed rs2 == 0 special cases in sraw/srlw
>>
>> All looks good to me now. Thanks for persevering.
>
> Thanks for reviewing this.
>
> Bastian: what sort of testing have you done here? This is a pretty big change,
> and while it's been fairly extensively reviewed I'm just generally paranoid.
>
I ran riscv-test as well as booting the newest fedora.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-26 8:51 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-26 8:51 UTC (permalink / raw)
To: Palmer Dabbelt, richard.henderson
Cc: peer.adelt, qemu-riscv, qemu-devel, sagark
On 1/26/19 12:54 AM, Palmer Dabbelt wrote:
> On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.henderson@linaro.org wrote:
>> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
>>> Hi,
>>>
>>> this patchset converts the RISC-V decoder to decodetree in four major steps:
>>>
>>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>>> Many of the gen_* functions are called by the decode functions for 16-bit
>>> and 32-bit functions. If we move translation code from the gen_*
>>> functions to the generated trans_* functions of decode-tree, we get a lot of
>>> duplication. Therefore, we mostly generate calls to the old gen_* function
>>> which are properly replaced after step 2).
>>>
>>> Each of the trans_ functions are grouped into files corresponding to their
>>> ISA extension, e.g. addi which is in RV32I is translated in the file
>>> 'trans_rvi.inc.c'.
>>>
>>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>>> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
>>> we convert the arguments in the 16 bit trans_ function to the arguments of
>>> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>>>
>>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
>>> this move all manual translation code into the trans_* instructions of
>>> decode tree, such that we can remove the old decode_* functions.
>>>
>>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
>>> by Richard. [Patch 31-35]
>>>
>>> full tree available at
>>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>>>
>>> Cheers,
>>> Bastian
>>>
>>> v4 -> v5:
>>> - fixed rebase error
>>> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
>>> - removed extra sign extension of sraiw
>>> - removed rs2 == 0 special cases in sraw/srlw
>>
>> All looks good to me now. Thanks for persevering.
>
> Thanks for reviewing this.
>
> Bastian: what sort of testing have you done here? This is a pretty big change,
> and while it's been fairly extensively reviewed I'm just generally paranoid.
>
I ran riscv-test as well as booting the newest fedora.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-26 8:51 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-29 19:22 ` Palmer Dabbelt
-1 siblings, 0 replies; 164+ messages in thread
From: Palmer Dabbelt @ 2019-01-29 19:22 UTC (permalink / raw)
To: Bastian Koppelmann, Alistair Francis
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, sagark
On Sat, 26 Jan 2019 00:51:23 PST (-0800), Bastian Koppelmann wrote:
> On 1/26/19 12:54 AM, Palmer Dabbelt wrote:
>> On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.henderson@linaro.org wrote:
>>> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
>>>> Hi,
>>>>
>>>> this patchset converts the RISC-V decoder to decodetree in four major steps:
>>>>
>>>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>>>> Many of the gen_* functions are called by the decode functions for 16-bit
>>>> and 32-bit functions. If we move translation code from the gen_*
>>>> functions to the generated trans_* functions of decode-tree, we get a lot of
>>>> duplication. Therefore, we mostly generate calls to the old gen_* function
>>>> which are properly replaced after step 2).
>>>>
>>>> Each of the trans_ functions are grouped into files corresponding to their
>>>> ISA extension, e.g. addi which is in RV32I is translated in the file
>>>> 'trans_rvi.inc.c'.
>>>>
>>>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>>>> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
>>>> we convert the arguments in the 16 bit trans_ function to the arguments of
>>>> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>>>>
>>>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
>>>> this move all manual translation code into the trans_* instructions of
>>>> decode tree, such that we can remove the old decode_* functions.
>>>>
>>>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
>>>> by Richard. [Patch 31-35]
>>>>
>>>> full tree available at
>>>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>>>>
>>>> Cheers,
>>>> Bastian
>>>>
>>>> v4 -> v5:
>>>> - fixed rebase error
>>>> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
>>>> - removed extra sign extension of sraiw
>>>> - removed rs2 == 0 special cases in sraw/srlw
>>>
>>> All looks good to me now. Thanks for persevering.
>>
>> Thanks for reviewing this.
>>
>> Bastian: what sort of testing have you done here? This is a pretty big change,
>> and while it's been fairly extensively reviewed I'm just generally paranoid.
>>
>
> I ran riscv-test as well as booting the newest fedora.
Well, that pretty much exhausts my testing scheme :). I think Alistair might
have a setup for booting a 32-bit Yocto-based distro in QEMU. Assuming he has
the flow set up and it boots then I don't see any reason not to merge it.
Thanks for pulling this all together, it's really great to have a cleaner
decoder!
Alistair: if that's true, can you give this a shot?
Bastian: do you mind collecting the relevant tags (Reviwed-by, etc) and putting
them in a v6?
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-29 19:22 ` Palmer Dabbelt
0 siblings, 0 replies; 164+ messages in thread
From: Palmer Dabbelt @ 2019-01-29 19:22 UTC (permalink / raw)
To: Bastian Koppelmann, Alistair Francis
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, sagark
On Sat, 26 Jan 2019 00:51:23 PST (-0800), Bastian Koppelmann wrote:
> On 1/26/19 12:54 AM, Palmer Dabbelt wrote:
>> On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.henderson@linaro.org wrote:
>>> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
>>>> Hi,
>>>>
>>>> this patchset converts the RISC-V decoder to decodetree in four major steps:
>>>>
>>>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>>>> Many of the gen_* functions are called by the decode functions for 16-bit
>>>> and 32-bit functions. If we move translation code from the gen_*
>>>> functions to the generated trans_* functions of decode-tree, we get a lot of
>>>> duplication. Therefore, we mostly generate calls to the old gen_* function
>>>> which are properly replaced after step 2).
>>>>
>>>> Each of the trans_ functions are grouped into files corresponding to their
>>>> ISA extension, e.g. addi which is in RV32I is translated in the file
>>>> 'trans_rvi.inc.c'.
>>>>
>>>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>>>> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
>>>> we convert the arguments in the 16 bit trans_ function to the arguments of
>>>> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>>>>
>>>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
>>>> this move all manual translation code into the trans_* instructions of
>>>> decode tree, such that we can remove the old decode_* functions.
>>>>
>>>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
>>>> by Richard. [Patch 31-35]
>>>>
>>>> full tree available at
>>>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>>>>
>>>> Cheers,
>>>> Bastian
>>>>
>>>> v4 -> v5:
>>>> - fixed rebase error
>>>> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
>>>> - removed extra sign extension of sraiw
>>>> - removed rs2 == 0 special cases in sraw/srlw
>>>
>>> All looks good to me now. Thanks for persevering.
>>
>> Thanks for reviewing this.
>>
>> Bastian: what sort of testing have you done here? This is a pretty big change,
>> and while it's been fairly extensively reviewed I'm just generally paranoid.
>>
>
> I ran riscv-test as well as booting the newest fedora.
Well, that pretty much exhausts my testing scheme :). I think Alistair might
have a setup for booting a 32-bit Yocto-based distro in QEMU. Assuming he has
the flow set up and it boots then I don't see any reason not to merge it.
Thanks for pulling this all together, it's really great to have a cleaner
decoder!
Alistair: if that's true, can you give this a shot?
Bastian: do you mind collecting the relevant tags (Reviwed-by, etc) and putting
them in a v6?
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-29 19:22 ` [Qemu-riscv] " Palmer Dabbelt
@ 2019-01-29 21:13 ` Alistair Francis
-1 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-29 21:13 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Bastian Koppelmann, Alistair Francis, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers,
Sagar Karandikar
On Tue, Jan 29, 2019 at 11:31 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Sat, 26 Jan 2019 00:51:23 PST (-0800), Bastian Koppelmann wrote:
> > On 1/26/19 12:54 AM, Palmer Dabbelt wrote:
> >> On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.henderson@linaro.org wrote:
> >>> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> >>>> Hi,
> >>>>
> >>>> this patchset converts the RISC-V decoder to decodetree in four major steps:
> >>>>
> >>>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> >>>> Many of the gen_* functions are called by the decode functions for 16-bit
> >>>> and 32-bit functions. If we move translation code from the gen_*
> >>>> functions to the generated trans_* functions of decode-tree, we get a lot of
> >>>> duplication. Therefore, we mostly generate calls to the old gen_* function
> >>>> which are properly replaced after step 2).
> >>>>
> >>>> Each of the trans_ functions are grouped into files corresponding to their
> >>>> ISA extension, e.g. addi which is in RV32I is translated in the file
> >>>> 'trans_rvi.inc.c'.
> >>>>
> >>>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
> >>>> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
> >>>> we convert the arguments in the 16 bit trans_ function to the arguments of
> >>>> the corresponding 32 bit instruction and call the 32 bit trans_ function.
> >>>>
> >>>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
> >>>> this move all manual translation code into the trans_* instructions of
> >>>> decode tree, such that we can remove the old decode_* functions.
> >>>>
> >>>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
> >>>> by Richard. [Patch 31-35]
> >>>>
> >>>> full tree available at
> >>>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
> >>>>
> >>>> Cheers,
> >>>> Bastian
> >>>>
> >>>> v4 -> v5:
> >>>> - fixed rebase error
> >>>> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
> >>>> - removed extra sign extension of sraiw
> >>>> - removed rs2 == 0 special cases in sraw/srlw
> >>>
> >>> All looks good to me now. Thanks for persevering.
> >>
> >> Thanks for reviewing this.
> >>
> >> Bastian: what sort of testing have you done here? This is a pretty big change,
> >> and while it's been fairly extensively reviewed I'm just generally paranoid.
> >>
> >
> > I ran riscv-test as well as booting the newest fedora.
>
> Well, that pretty much exhausts my testing scheme :). I think Alistair might
> have a setup for booting a 32-bit Yocto-based distro in QEMU. Assuming he has
> the flow set up and it boots then I don't see any reason not to merge it.
I just tested it and 32-bit images boot the same before and after this
patchset. So the 4.19 (with patches ontop) kernel boots, but the 5.0
(with patches ontop) crashes at init.
>
> Thanks for pulling this all together, it's really great to have a cleaner
> decoder!
>
> Alistair: if that's true, can you give this a shot?
Yep, I have been using this in my daily use and haven't seen any
problems. That isn't exhaustive testing but should cover a bit.
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> Bastian: do you mind collecting the relevant tags (Reviwed-by, etc) and putting
> them in a v6?
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-29 21:13 ` Alistair Francis
0 siblings, 0 replies; 164+ messages in thread
From: Alistair Francis @ 2019-01-29 21:13 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Bastian Koppelmann, Alistair Francis, qemu-riscv, peer.adelt,
Richard Henderson, qemu-devel@nongnu.org Developers,
Sagar Karandikar
On Tue, Jan 29, 2019 at 11:31 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Sat, 26 Jan 2019 00:51:23 PST (-0800), Bastian Koppelmann wrote:
> > On 1/26/19 12:54 AM, Palmer Dabbelt wrote:
> >> On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.henderson@linaro.org wrote:
> >>> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> >>>> Hi,
> >>>>
> >>>> this patchset converts the RISC-V decoder to decodetree in four major steps:
> >>>>
> >>>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> >>>> Many of the gen_* functions are called by the decode functions for 16-bit
> >>>> and 32-bit functions. If we move translation code from the gen_*
> >>>> functions to the generated trans_* functions of decode-tree, we get a lot of
> >>>> duplication. Therefore, we mostly generate calls to the old gen_* function
> >>>> which are properly replaced after step 2).
> >>>>
> >>>> Each of the trans_ functions are grouped into files corresponding to their
> >>>> ISA extension, e.g. addi which is in RV32I is translated in the file
> >>>> 'trans_rvi.inc.c'.
> >>>>
> >>>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
> >>>> All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
> >>>> we convert the arguments in the 16 bit trans_ function to the arguments of
> >>>> the corresponding 32 bit instruction and call the 32 bit trans_ function.
> >>>>
> >>>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
> >>>> this move all manual translation code into the trans_* instructions of
> >>>> decode tree, such that we can remove the old decode_* functions.
> >>>>
> >>>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
> >>>> by Richard. [Patch 31-35]
> >>>>
> >>>> full tree available at
> >>>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
> >>>>
> >>>> Cheers,
> >>>> Bastian
> >>>>
> >>>> v4 -> v5:
> >>>> - fixed rebase error
> >>>> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
> >>>> - removed extra sign extension of sraiw
> >>>> - removed rs2 == 0 special cases in sraw/srlw
> >>>
> >>> All looks good to me now. Thanks for persevering.
> >>
> >> Thanks for reviewing this.
> >>
> >> Bastian: what sort of testing have you done here? This is a pretty big change,
> >> and while it's been fairly extensively reviewed I'm just generally paranoid.
> >>
> >
> > I ran riscv-test as well as booting the newest fedora.
>
> Well, that pretty much exhausts my testing scheme :). I think Alistair might
> have a setup for booting a 32-bit Yocto-based distro in QEMU. Assuming he has
> the flow set up and it boots then I don't see any reason not to merge it.
I just tested it and 32-bit images boot the same before and after this
patchset. So the 4.19 (with patches ontop) kernel boots, but the 5.0
(with patches ontop) crashes at init.
>
> Thanks for pulling this all together, it's really great to have a cleaner
> decoder!
>
> Alistair: if that's true, can you give this a shot?
Yep, I have been using this in my daily use and haven't seen any
problems. That isn't exhaustive testing but should cover a bit.
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> Bastian: do you mind collecting the relevant tags (Reviwed-by, etc) and putting
> them in a v6?
>
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-29 19:22 ` [Qemu-riscv] " Palmer Dabbelt
@ 2019-01-30 9:08 ` Bastian Koppelmann
-1 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-30 9:08 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, sagark
Hi Palmer,
On 1/29/19 8:22 PM, Palmer Dabbelt wrote:
> [..]
> Well, that pretty much exhausts my testing scheme :). I think
> Alistair might have a setup for booting a 32-bit Yocto-based distro in
> QEMU. Assuming he has the flow set up and it boots then I don't see
> any reason not to merge it.
>
> Thanks for pulling this all together, it's really great to have a
> cleaner decoder!
>
> Alistair: if that's true, can you give this a shot?
>
> Bastian: do you mind collecting the relevant tags (Reviwed-by, etc)
> and putting them in a v6?
I already did (see
http://lists.gnu.org/archive/html/qemu-riscv/2019-01/msg00147.html) :)
Cheers,
Bastian
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-30 9:08 ` Bastian Koppelmann
0 siblings, 0 replies; 164+ messages in thread
From: Bastian Koppelmann @ 2019-01-30 9:08 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis
Cc: richard.henderson, peer.adelt, qemu-riscv, qemu-devel, sagark
Hi Palmer,
On 1/29/19 8:22 PM, Palmer Dabbelt wrote:
> [..]
> Well, that pretty much exhausts my testing scheme :). I think
> Alistair might have a setup for booting a 32-bit Yocto-based distro in
> QEMU. Assuming he has the flow set up and it boots then I don't see
> any reason not to merge it.
>
> Thanks for pulling this all together, it's really great to have a
> cleaner decoder!
>
> Alistair: if that's true, can you give this a shot?
>
> Bastian: do you mind collecting the relevant tags (Reviwed-by, etc)
> and putting them in a v6?
I already did (see
http://lists.gnu.org/archive/html/qemu-riscv/2019-01/msg00147.html) :)
Cheers,
Bastian
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-30 9:08 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-30 18:47 ` Palmer Dabbelt
-1 siblings, 0 replies; 164+ messages in thread
From: Palmer Dabbelt @ 2019-01-30 18:47 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Alistair Francis, richard.henderson, peer.adelt, qemu-riscv,
qemu-devel, sagark
On Wed, 30 Jan 2019 01:08:33 PST (-0800), Bastian Koppelmann wrote:
> Hi Palmer,
>
> On 1/29/19 8:22 PM, Palmer Dabbelt wrote:
>> [..]
>> Well, that pretty much exhausts my testing scheme :). I think
>> Alistair might have a setup for booting a 32-bit Yocto-based distro in
>> QEMU. Assuming he has the flow set up and it boots then I don't see
>> any reason not to merge it.
>>
>> Thanks for pulling this all together, it's really great to have a
>> cleaner decoder!
>>
>> Alistair: if that's true, can you give this a shot?
>>
>> Bastian: do you mind collecting the relevant tags (Reviwed-by, etc)
>> and putting them in a v6?
>
>
> I already did (see
> http://lists.gnu.org/archive/html/qemu-riscv/2019-01/msg00147.html) :)
Sorry, my mail latency got a bit high. So I'm good here, just pending any
other testing we might have floating around. I just sent up a PR with a
handful of little things so we can avoid mixing too much stuff together, but I
don't see any reason not to include this in the next round.
Thanks!
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-30 18:47 ` Palmer Dabbelt
0 siblings, 0 replies; 164+ messages in thread
From: Palmer Dabbelt @ 2019-01-30 18:47 UTC (permalink / raw)
To: Bastian Koppelmann
Cc: Alistair Francis, richard.henderson, peer.adelt, qemu-riscv,
qemu-devel, sagark
On Wed, 30 Jan 2019 01:08:33 PST (-0800), Bastian Koppelmann wrote:
> Hi Palmer,
>
> On 1/29/19 8:22 PM, Palmer Dabbelt wrote:
>> [..]
>> Well, that pretty much exhausts my testing scheme :). I think
>> Alistair might have a setup for booting a 32-bit Yocto-based distro in
>> QEMU. Assuming he has the flow set up and it boots then I don't see
>> any reason not to merge it.
>>
>> Thanks for pulling this all together, it's really great to have a
>> cleaner decoder!
>>
>> Alistair: if that's true, can you give this a shot?
>>
>> Bastian: do you mind collecting the relevant tags (Reviwed-by, etc)
>> and putting them in a v6?
>
>
> I already did (see
> http://lists.gnu.org/archive/html/qemu-riscv/2019-01/msg00147.html) :)
Sorry, my mail latency got a bit high. So I'm good here, just pending any
other testing we might have floating around. I just sent up a PR with a
handful of little things so we can avoid mixing too much stuff together, but I
don't see any reason not to include this in the next round.
Thanks!
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 18:06 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 18:06 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
8fff3fc6a2 target/riscv: Remaining rvc insn reuse 32 bit translators
c563ab1ecb target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
e2d25e9d55 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
aa0f8ada63 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
c57a581714 target/riscv: Convert @cs_2 insns to share translation functions
0a0a43441c target/riscv: Remove decode_RV32_64G()
30f9d142a0 target/riscv: Remove gen_system()
5710f6d871 target/riscv: Rename trans_arith to gen_arith
3f07a91951 target/riscv: Remove manual decoding of RV32/64M insn
0fc287193b target/riscv: Remove shift and slt insn manual decoding
236a600baf target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
a4fde90aab target/riscv: Move gen_arith_imm() decoding into trans_* functions
efebe9125f target/riscv: Remove manual decoding from gen_store()
30bef8034b target/riscv: Remove manual decoding from gen_load()
ea82022814 target/riscv: Remove manual decoding from gen_branch()
047f3d2ee4 target/riscv: Remove gen_jalr()
7ea527626d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
27b3303efa target/riscv: Convert quadrant 1 of RVXC insns to decodetree
6a90487077 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2d8731dad1 target/riscv: Convert RV priv insns to decodetree
b78a5409c2 target/riscv: Convert RV64D insns to decodetree
7181a4f946 target/riscv: Convert RV32D insns to decodetree
dbb77cd4df target/riscv: Convert RV64F insns to decodetree
6ff19f1f62 target/riscv: Convert RV32F insns to decodetree
101b3708d7 target/riscv: Convert RV64A insns to decodetree
18db9d7cbe target/riscv: Convert RV32A insns to decodetree
c2032943b6 target/riscv: Convert RVXM insns to decodetree
80b7b0b6e0 target/riscv: Convert RVXI csr insns to decodetree
35ca21d90a target/riscv: Convert RVXI fence insns to decodetree
a974405bbb target/riscv: Convert RVXI arithmetic insns to decodetree
3ea0060942 target/riscv: Convert RV64I load/store insns to decodetree
c1b9e8b927 target/riscv: Convert RV32I load/store insns to decodetree
109a6de64b target/riscv: Convert RVXI branch insns to decodetree
492967f3a6 target/riscv: Activate decodetree and implemnt LUI & AUIPC
7f257b74de target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 7f257b74decd (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 492967f3a6ae (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 109a6de64b62 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit c1b9e8b927b1 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 3ea006094257 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit a974405bbbae (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 35ca21d90a96 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 80b7b0b6e041 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit c2032943b671 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 18db9d7cbe2a (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 101b3708d75e (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 6ff19f1f6274 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit dbb77cd4df54 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 7181a4f9463b (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit b78a5409c29d (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 2d8731dad167 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 6a9048707730 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 27b3303efa77 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 7ea527626d72 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 047f3d2ee462 (target/riscv: Remove gen_jalr())
21/35 Checking commit ea820228141b (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 30bef8034bd6 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit efebe9125f0c (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit a4fde90aab86 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 236a600baf26 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 0fc287193b96 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 3f07a91951e7 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 5710f6d87168 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 30f9d142a0d7 (target/riscv: Remove gen_system())
30/35 Checking commit 0a0a43441c43 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit c57a58171416 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit aa0f8ada6393 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit e2d25e9d5539 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit c563ab1ecbf8 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 8fff3fc6a21e (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 18:06 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 18:06 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
8fff3fc6a2 target/riscv: Remaining rvc insn reuse 32 bit translators
c563ab1ecb target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
e2d25e9d55 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
aa0f8ada63 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
c57a581714 target/riscv: Convert @cs_2 insns to share translation functions
0a0a43441c target/riscv: Remove decode_RV32_64G()
30f9d142a0 target/riscv: Remove gen_system()
5710f6d871 target/riscv: Rename trans_arith to gen_arith
3f07a91951 target/riscv: Remove manual decoding of RV32/64M insn
0fc287193b target/riscv: Remove shift and slt insn manual decoding
236a600baf target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
a4fde90aab target/riscv: Move gen_arith_imm() decoding into trans_* functions
efebe9125f target/riscv: Remove manual decoding from gen_store()
30bef8034b target/riscv: Remove manual decoding from gen_load()
ea82022814 target/riscv: Remove manual decoding from gen_branch()
047f3d2ee4 target/riscv: Remove gen_jalr()
7ea527626d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
27b3303efa target/riscv: Convert quadrant 1 of RVXC insns to decodetree
6a90487077 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2d8731dad1 target/riscv: Convert RV priv insns to decodetree
b78a5409c2 target/riscv: Convert RV64D insns to decodetree
7181a4f946 target/riscv: Convert RV32D insns to decodetree
dbb77cd4df target/riscv: Convert RV64F insns to decodetree
6ff19f1f62 target/riscv: Convert RV32F insns to decodetree
101b3708d7 target/riscv: Convert RV64A insns to decodetree
18db9d7cbe target/riscv: Convert RV32A insns to decodetree
c2032943b6 target/riscv: Convert RVXM insns to decodetree
80b7b0b6e0 target/riscv: Convert RVXI csr insns to decodetree
35ca21d90a target/riscv: Convert RVXI fence insns to decodetree
a974405bbb target/riscv: Convert RVXI arithmetic insns to decodetree
3ea0060942 target/riscv: Convert RV64I load/store insns to decodetree
c1b9e8b927 target/riscv: Convert RV32I load/store insns to decodetree
109a6de64b target/riscv: Convert RVXI branch insns to decodetree
492967f3a6 target/riscv: Activate decodetree and implemnt LUI & AUIPC
7f257b74de target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 7f257b74decd (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 492967f3a6ae (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 109a6de64b62 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit c1b9e8b927b1 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 3ea006094257 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit a974405bbbae (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 35ca21d90a96 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 80b7b0b6e041 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit c2032943b671 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 18db9d7cbe2a (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 101b3708d75e (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 6ff19f1f6274 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit dbb77cd4df54 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 7181a4f9463b (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit b78a5409c29d (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 2d8731dad167 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 6a9048707730 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 27b3303efa77 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 7ea527626d72 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 047f3d2ee462 (target/riscv: Remove gen_jalr())
21/35 Checking commit ea820228141b (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 30bef8034bd6 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit efebe9125f0c (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit a4fde90aab86 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 236a600baf26 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 0fc287193b96 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 3f07a91951e7 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 5710f6d87168 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 30f9d142a0d7 (target/riscv: Remove gen_system())
30/35 Checking commit 0a0a43441c43 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit c57a58171416 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit aa0f8ada6393 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit e2d25e9d5539 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit c563ab1ecbf8 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 8fff3fc6a21e (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 18:48 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 18:48 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
707ba25e6a target/riscv: Remaining rvc insn reuse 32 bit translators
e8e3fdd801 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
1271fb32d1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
e57717196e target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
9a48b3870f target/riscv: Convert @cs_2 insns to share translation functions
ae50456b4a target/riscv: Remove decode_RV32_64G()
689db535fa target/riscv: Remove gen_system()
ba19bbe72c target/riscv: Rename trans_arith to gen_arith
4821480397 target/riscv: Remove manual decoding of RV32/64M insn
bc78e8b198 target/riscv: Remove shift and slt insn manual decoding
b24202ed1b target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
c4655ea1af target/riscv: Move gen_arith_imm() decoding into trans_* functions
f4b51a8879 target/riscv: Remove manual decoding from gen_store()
271753698f target/riscv: Remove manual decoding from gen_load()
ce1206dbc3 target/riscv: Remove manual decoding from gen_branch()
35a81db796 target/riscv: Remove gen_jalr()
8d3033de1a target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7f04cc7343 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
6a1f9394fa target/riscv: Convert quadrant 0 of RVXC insns to decodetree
84311c64b5 target/riscv: Convert RV priv insns to decodetree
801dbbdb4c target/riscv: Convert RV64D insns to decodetree
566965419e target/riscv: Convert RV32D insns to decodetree
e2646f4afe target/riscv: Convert RV64F insns to decodetree
188a6e6678 target/riscv: Convert RV32F insns to decodetree
c39a5a597a target/riscv: Convert RV64A insns to decodetree
74169b8e38 target/riscv: Convert RV32A insns to decodetree
f0db8bcb9c target/riscv: Convert RVXM insns to decodetree
2db8b9a367 target/riscv: Convert RVXI csr insns to decodetree
abf36dbe82 target/riscv: Convert RVXI fence insns to decodetree
437709e78b target/riscv: Convert RVXI arithmetic insns to decodetree
201f108c71 target/riscv: Convert RV64I load/store insns to decodetree
7c6f47530c target/riscv: Convert RV32I load/store insns to decodetree
9e5332de20 target/riscv: Convert RVXI branch insns to decodetree
dc69d0a085 target/riscv: Activate decodetree and implemnt LUI & AUIPC
b4e49789dd target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit b4e49789dd4a (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit dc69d0a0852a (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 9e5332de20d5 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7c6f47530cd9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 201f108c71a8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 437709e78b8c (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit abf36dbe8296 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 2db8b9a36725 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f0db8bcb9cb8 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 74169b8e3825 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit c39a5a597a18 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 188a6e6678b6 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit e2646f4afea5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 566965419e20 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 801dbbdb4c1d (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 84311c64b54d (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 6a1f9394fa9b (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 7f04cc73436d (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 8d3033de1a18 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 35a81db7962a (target/riscv: Remove gen_jalr())
21/35 Checking commit ce1206dbc3c3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 271753698faf (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit f4b51a887927 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit c4655ea1af1a (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit b24202ed1b5e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit bc78e8b19846 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 4821480397dc (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ba19bbe72c20 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 689db535faaf (target/riscv: Remove gen_system())
30/35 Checking commit ae50456b4a24 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 9a48b3870f4c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit e57717196e63 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 1271fb32d170 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit e8e3fdd80100 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 707ba25e6ad9 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 18:48 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 18:48 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
707ba25e6a target/riscv: Remaining rvc insn reuse 32 bit translators
e8e3fdd801 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
1271fb32d1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
e57717196e target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
9a48b3870f target/riscv: Convert @cs_2 insns to share translation functions
ae50456b4a target/riscv: Remove decode_RV32_64G()
689db535fa target/riscv: Remove gen_system()
ba19bbe72c target/riscv: Rename trans_arith to gen_arith
4821480397 target/riscv: Remove manual decoding of RV32/64M insn
bc78e8b198 target/riscv: Remove shift and slt insn manual decoding
b24202ed1b target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
c4655ea1af target/riscv: Move gen_arith_imm() decoding into trans_* functions
f4b51a8879 target/riscv: Remove manual decoding from gen_store()
271753698f target/riscv: Remove manual decoding from gen_load()
ce1206dbc3 target/riscv: Remove manual decoding from gen_branch()
35a81db796 target/riscv: Remove gen_jalr()
8d3033de1a target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7f04cc7343 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
6a1f9394fa target/riscv: Convert quadrant 0 of RVXC insns to decodetree
84311c64b5 target/riscv: Convert RV priv insns to decodetree
801dbbdb4c target/riscv: Convert RV64D insns to decodetree
566965419e target/riscv: Convert RV32D insns to decodetree
e2646f4afe target/riscv: Convert RV64F insns to decodetree
188a6e6678 target/riscv: Convert RV32F insns to decodetree
c39a5a597a target/riscv: Convert RV64A insns to decodetree
74169b8e38 target/riscv: Convert RV32A insns to decodetree
f0db8bcb9c target/riscv: Convert RVXM insns to decodetree
2db8b9a367 target/riscv: Convert RVXI csr insns to decodetree
abf36dbe82 target/riscv: Convert RVXI fence insns to decodetree
437709e78b target/riscv: Convert RVXI arithmetic insns to decodetree
201f108c71 target/riscv: Convert RV64I load/store insns to decodetree
7c6f47530c target/riscv: Convert RV32I load/store insns to decodetree
9e5332de20 target/riscv: Convert RVXI branch insns to decodetree
dc69d0a085 target/riscv: Activate decodetree and implemnt LUI & AUIPC
b4e49789dd target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit b4e49789dd4a (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit dc69d0a0852a (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 9e5332de20d5 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7c6f47530cd9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 201f108c71a8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 437709e78b8c (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit abf36dbe8296 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 2db8b9a36725 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f0db8bcb9cb8 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 74169b8e3825 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit c39a5a597a18 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 188a6e6678b6 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit e2646f4afea5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 566965419e20 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 801dbbdb4c1d (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 84311c64b54d (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 6a1f9394fa9b (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 7f04cc73436d (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 8d3033de1a18 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 35a81db7962a (target/riscv: Remove gen_jalr())
21/35 Checking commit ce1206dbc3c3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 271753698faf (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit f4b51a887927 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit c4655ea1af1a (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit b24202ed1b5e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit bc78e8b19846 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 4821480397dc (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ba19bbe72c20 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 689db535faaf (target/riscv: Remove gen_system())
30/35 Checking commit ae50456b4a24 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 9a48b3870f4c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit e57717196e63 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 1271fb32d170 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit e8e3fdd80100 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 707ba25e6ad9 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 18:48 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 18:48 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
707ba25 target/riscv: Remaining rvc insn reuse 32 bit translators
e8e3fdd target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
1271fb3 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
e577171 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
9a48b38 target/riscv: Convert @cs_2 insns to share translation functions
ae50456 target/riscv: Remove decode_RV32_64G()
689db53 target/riscv: Remove gen_system()
ba19bbe target/riscv: Rename trans_arith to gen_arith
4821480 target/riscv: Remove manual decoding of RV32/64M insn
bc78e8b target/riscv: Remove shift and slt insn manual decoding
b24202e target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
c4655ea target/riscv: Move gen_arith_imm() decoding into trans_* functions
f4b51a8 target/riscv: Remove manual decoding from gen_store()
2717536 target/riscv: Remove manual decoding from gen_load()
ce1206d target/riscv: Remove manual decoding from gen_branch()
35a81db target/riscv: Remove gen_jalr()
8d3033d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7f04cc7 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
6a1f939 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
84311c6 target/riscv: Convert RV priv insns to decodetree
801dbbd target/riscv: Convert RV64D insns to decodetree
5669654 target/riscv: Convert RV32D insns to decodetree
e2646f4 target/riscv: Convert RV64F insns to decodetree
188a6e6 target/riscv: Convert RV32F insns to decodetree
c39a5a5 target/riscv: Convert RV64A insns to decodetree
74169b8 target/riscv: Convert RV32A insns to decodetree
f0db8bc target/riscv: Convert RVXM insns to decodetree
2db8b9a target/riscv: Convert RVXI csr insns to decodetree
abf36db target/riscv: Convert RVXI fence insns to decodetree
437709e target/riscv: Convert RVXI arithmetic insns to decodetree
201f108 target/riscv: Convert RV64I load/store insns to decodetree
7c6f475 target/riscv: Convert RV32I load/store insns to decodetree
9e5332d target/riscv: Convert RVXI branch insns to decodetree
dc69d0a target/riscv: Activate decodetree and implemnt LUI & AUIPC
b4e4978 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit b4e49789dd4a (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit dc69d0a0852a (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 9e5332de20d5 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7c6f47530cd9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 201f108c71a8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 437709e78b8c (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit abf36dbe8296 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 2db8b9a36725 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f0db8bcb9cb8 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 74169b8e3825 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit c39a5a597a18 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 188a6e6678b6 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit e2646f4afea5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 566965419e20 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 801dbbdb4c1d (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 84311c64b54d (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 6a1f9394fa9b (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 7f04cc73436d (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 8d3033de1a18 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 35a81db7962a (target/riscv: Remove gen_jalr())
21/35 Checking commit ce1206dbc3c3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 271753698faf (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit f4b51a887927 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit c4655ea1af1a (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit b24202ed1b5e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit bc78e8b19846 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 4821480397dc (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ba19bbe72c20 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 689db535faaf (target/riscv: Remove gen_system())
30/35 Checking commit ae50456b4a24 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 9a48b3870f4c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit e57717196e63 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 1271fb32d170 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit e8e3fdd80100 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 707ba25e6ad9 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 18:48 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 18:48 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
707ba25 target/riscv: Remaining rvc insn reuse 32 bit translators
e8e3fdd target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
1271fb3 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
e577171 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
9a48b38 target/riscv: Convert @cs_2 insns to share translation functions
ae50456 target/riscv: Remove decode_RV32_64G()
689db53 target/riscv: Remove gen_system()
ba19bbe target/riscv: Rename trans_arith to gen_arith
4821480 target/riscv: Remove manual decoding of RV32/64M insn
bc78e8b target/riscv: Remove shift and slt insn manual decoding
b24202e target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
c4655ea target/riscv: Move gen_arith_imm() decoding into trans_* functions
f4b51a8 target/riscv: Remove manual decoding from gen_store()
2717536 target/riscv: Remove manual decoding from gen_load()
ce1206d target/riscv: Remove manual decoding from gen_branch()
35a81db target/riscv: Remove gen_jalr()
8d3033d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7f04cc7 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
6a1f939 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
84311c6 target/riscv: Convert RV priv insns to decodetree
801dbbd target/riscv: Convert RV64D insns to decodetree
5669654 target/riscv: Convert RV32D insns to decodetree
e2646f4 target/riscv: Convert RV64F insns to decodetree
188a6e6 target/riscv: Convert RV32F insns to decodetree
c39a5a5 target/riscv: Convert RV64A insns to decodetree
74169b8 target/riscv: Convert RV32A insns to decodetree
f0db8bc target/riscv: Convert RVXM insns to decodetree
2db8b9a target/riscv: Convert RVXI csr insns to decodetree
abf36db target/riscv: Convert RVXI fence insns to decodetree
437709e target/riscv: Convert RVXI arithmetic insns to decodetree
201f108 target/riscv: Convert RV64I load/store insns to decodetree
7c6f475 target/riscv: Convert RV32I load/store insns to decodetree
9e5332d target/riscv: Convert RVXI branch insns to decodetree
dc69d0a target/riscv: Activate decodetree and implemnt LUI & AUIPC
b4e4978 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit b4e49789dd4a (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit dc69d0a0852a (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 9e5332de20d5 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7c6f47530cd9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 201f108c71a8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 437709e78b8c (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit abf36dbe8296 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 2db8b9a36725 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f0db8bcb9cb8 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 74169b8e3825 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit c39a5a597a18 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 188a6e6678b6 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit e2646f4afea5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 566965419e20 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 801dbbdb4c1d (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 84311c64b54d (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 6a1f9394fa9b (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 7f04cc73436d (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 8d3033de1a18 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 35a81db7962a (target/riscv: Remove gen_jalr())
21/35 Checking commit ce1206dbc3c3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 271753698faf (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit f4b51a887927 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit c4655ea1af1a (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit b24202ed1b5e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit bc78e8b19846 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 4821480397dc (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ba19bbe72c20 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 689db535faaf (target/riscv: Remove gen_system())
30/35 Checking commit ae50456b4a24 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 9a48b3870f4c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit e57717196e63 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 1271fb32d170 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit e8e3fdd80100 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 707ba25e6ad9 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 18:51 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 18:51 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
707ba25 target/riscv: Remaining rvc insn reuse 32 bit translators
e8e3fdd target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
1271fb3 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
e577171 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
9a48b38 target/riscv: Convert @cs_2 insns to share translation functions
ae50456 target/riscv: Remove decode_RV32_64G()
689db53 target/riscv: Remove gen_system()
ba19bbe target/riscv: Rename trans_arith to gen_arith
4821480 target/riscv: Remove manual decoding of RV32/64M insn
bc78e8b target/riscv: Remove shift and slt insn manual decoding
b24202e target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
c4655ea target/riscv: Move gen_arith_imm() decoding into trans_* functions
f4b51a8 target/riscv: Remove manual decoding from gen_store()
2717536 target/riscv: Remove manual decoding from gen_load()
ce1206d target/riscv: Remove manual decoding from gen_branch()
35a81db target/riscv: Remove gen_jalr()
8d3033d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7f04cc7 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
6a1f939 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
84311c6 target/riscv: Convert RV priv insns to decodetree
801dbbd target/riscv: Convert RV64D insns to decodetree
5669654 target/riscv: Convert RV32D insns to decodetree
e2646f4 target/riscv: Convert RV64F insns to decodetree
188a6e6 target/riscv: Convert RV32F insns to decodetree
c39a5a5 target/riscv: Convert RV64A insns to decodetree
74169b8 target/riscv: Convert RV32A insns to decodetree
f0db8bc target/riscv: Convert RVXM insns to decodetree
2db8b9a target/riscv: Convert RVXI csr insns to decodetree
abf36db target/riscv: Convert RVXI fence insns to decodetree
437709e target/riscv: Convert RVXI arithmetic insns to decodetree
201f108 target/riscv: Convert RV64I load/store insns to decodetree
7c6f475 target/riscv: Convert RV32I load/store insns to decodetree
9e5332d target/riscv: Convert RVXI branch insns to decodetree
dc69d0a target/riscv: Activate decodetree and implemnt LUI & AUIPC
b4e4978 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit b4e49789dd4a (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit dc69d0a0852a (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 9e5332de20d5 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7c6f47530cd9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 201f108c71a8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 437709e78b8c (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit abf36dbe8296 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 2db8b9a36725 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f0db8bcb9cb8 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 74169b8e3825 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit c39a5a597a18 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 188a6e6678b6 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit e2646f4afea5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 566965419e20 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 801dbbdb4c1d (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 84311c64b54d (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 6a1f9394fa9b (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 7f04cc73436d (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 8d3033de1a18 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 35a81db7962a (target/riscv: Remove gen_jalr())
21/35 Checking commit ce1206dbc3c3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 271753698faf (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit f4b51a887927 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit c4655ea1af1a (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit b24202ed1b5e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit bc78e8b19846 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 4821480397dc (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ba19bbe72c20 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 689db535faaf (target/riscv: Remove gen_system())
30/35 Checking commit ae50456b4a24 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 9a48b3870f4c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit e57717196e63 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 1271fb32d170 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit e8e3fdd80100 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 707ba25e6ad9 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 18:51 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 18:51 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
707ba25 target/riscv: Remaining rvc insn reuse 32 bit translators
e8e3fdd target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
1271fb3 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
e577171 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
9a48b38 target/riscv: Convert @cs_2 insns to share translation functions
ae50456 target/riscv: Remove decode_RV32_64G()
689db53 target/riscv: Remove gen_system()
ba19bbe target/riscv: Rename trans_arith to gen_arith
4821480 target/riscv: Remove manual decoding of RV32/64M insn
bc78e8b target/riscv: Remove shift and slt insn manual decoding
b24202e target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
c4655ea target/riscv: Move gen_arith_imm() decoding into trans_* functions
f4b51a8 target/riscv: Remove manual decoding from gen_store()
2717536 target/riscv: Remove manual decoding from gen_load()
ce1206d target/riscv: Remove manual decoding from gen_branch()
35a81db target/riscv: Remove gen_jalr()
8d3033d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7f04cc7 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
6a1f939 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
84311c6 target/riscv: Convert RV priv insns to decodetree
801dbbd target/riscv: Convert RV64D insns to decodetree
5669654 target/riscv: Convert RV32D insns to decodetree
e2646f4 target/riscv: Convert RV64F insns to decodetree
188a6e6 target/riscv: Convert RV32F insns to decodetree
c39a5a5 target/riscv: Convert RV64A insns to decodetree
74169b8 target/riscv: Convert RV32A insns to decodetree
f0db8bc target/riscv: Convert RVXM insns to decodetree
2db8b9a target/riscv: Convert RVXI csr insns to decodetree
abf36db target/riscv: Convert RVXI fence insns to decodetree
437709e target/riscv: Convert RVXI arithmetic insns to decodetree
201f108 target/riscv: Convert RV64I load/store insns to decodetree
7c6f475 target/riscv: Convert RV32I load/store insns to decodetree
9e5332d target/riscv: Convert RVXI branch insns to decodetree
dc69d0a target/riscv: Activate decodetree and implemnt LUI & AUIPC
b4e4978 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit b4e49789dd4a (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit dc69d0a0852a (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 9e5332de20d5 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7c6f47530cd9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 201f108c71a8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 437709e78b8c (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit abf36dbe8296 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 2db8b9a36725 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f0db8bcb9cb8 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 74169b8e3825 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit c39a5a597a18 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 188a6e6678b6 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit e2646f4afea5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 566965419e20 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 801dbbdb4c1d (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 84311c64b54d (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 6a1f9394fa9b (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 7f04cc73436d (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 8d3033de1a18 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 35a81db7962a (target/riscv: Remove gen_jalr())
21/35 Checking commit ce1206dbc3c3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 271753698faf (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit f4b51a887927 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit c4655ea1af1a (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit b24202ed1b5e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit bc78e8b19846 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 4821480397dc (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ba19bbe72c20 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 689db535faaf (target/riscv: Remove gen_system())
30/35 Checking commit ae50456b4a24 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 9a48b3870f4c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit e57717196e63 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 1271fb32d170 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit e8e3fdd80100 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 707ba25e6ad9 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 19:00 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 19:00 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
aefcd28366..e8977901b7 master -> master
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
84d9232271 target/riscv: Remaining rvc insn reuse 32 bit translators
d914ca8ad6 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
d91d36a5a5 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
96a7dd7cc4 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
4be75db113 target/riscv: Convert @cs_2 insns to share translation functions
5df6fa908b target/riscv: Remove decode_RV32_64G()
9e15d220cb target/riscv: Remove gen_system()
569b624066 target/riscv: Rename trans_arith to gen_arith
ab8fe35848 target/riscv: Remove manual decoding of RV32/64M insn
35c8b7cf65 target/riscv: Remove shift and slt insn manual decoding
aa1fcbc0b2 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
09af9d97eb target/riscv: Move gen_arith_imm() decoding into trans_* functions
2b6c72f3da target/riscv: Remove manual decoding from gen_store()
1d3a7b5cb7 target/riscv: Remove manual decoding from gen_load()
0551b57210 target/riscv: Remove manual decoding from gen_branch()
129eb0e041 target/riscv: Remove gen_jalr()
65a653d84d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
faca63ff69 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
0e9ac5bbcb target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8871e9f09a target/riscv: Convert RV priv insns to decodetree
4ffcac38e7 target/riscv: Convert RV64D insns to decodetree
8b13dafd4a target/riscv: Convert RV32D insns to decodetree
f59e9b8655 target/riscv: Convert RV64F insns to decodetree
8cd874a0eb target/riscv: Convert RV32F insns to decodetree
4f9f53aa9e target/riscv: Convert RV64A insns to decodetree
17aee59b02 target/riscv: Convert RV32A insns to decodetree
e93a947b94 target/riscv: Convert RVXM insns to decodetree
87454d7d1d target/riscv: Convert RVXI csr insns to decodetree
11f83510fd target/riscv: Convert RVXI fence insns to decodetree
40bf83abf8 target/riscv: Convert RVXI arithmetic insns to decodetree
6f109f635b target/riscv: Convert RV64I load/store insns to decodetree
1bdc022b7c target/riscv: Convert RV32I load/store insns to decodetree
ad3f70396f target/riscv: Convert RVXI branch insns to decodetree
693a52f261 target/riscv: Activate decodetree and implemnt LUI & AUIPC
b098fdaf40 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit b098fdaf40da (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 693a52f261fd (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit ad3f70396f2e (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 1bdc022b7ca3 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 6f109f635b03 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 40bf83abf814 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 11f83510fd16 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 87454d7d1d12 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit e93a947b945f (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 17aee59b02db (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 4f9f53aa9e45 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 8cd874a0eb9b (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit f59e9b865598 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 8b13dafd4acf (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 4ffcac38e78f (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8871e9f09a5f (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 0e9ac5bbcbe0 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit faca63ff6943 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 65a653d84db9 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 129eb0e041ee (target/riscv: Remove gen_jalr())
21/35 Checking commit 0551b5721024 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 1d3a7b5cb775 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 2b6c72f3dae3 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 09af9d97ebf5 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit aa1fcbc0b22f (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 35c8b7cf6516 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit ab8fe35848eb (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 569b6240661a (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 9e15d220cb1e (target/riscv: Remove gen_system())
30/35 Checking commit 5df6fa908b20 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 4be75db1131a (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 96a7dd7cc432 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit d91d36a5a5b1 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit d914ca8ad66d (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 84d923227191 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 19:00 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 19:00 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
aefcd28366..e8977901b7 master -> master
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
84d9232271 target/riscv: Remaining rvc insn reuse 32 bit translators
d914ca8ad6 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
d91d36a5a5 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
96a7dd7cc4 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
4be75db113 target/riscv: Convert @cs_2 insns to share translation functions
5df6fa908b target/riscv: Remove decode_RV32_64G()
9e15d220cb target/riscv: Remove gen_system()
569b624066 target/riscv: Rename trans_arith to gen_arith
ab8fe35848 target/riscv: Remove manual decoding of RV32/64M insn
35c8b7cf65 target/riscv: Remove shift and slt insn manual decoding
aa1fcbc0b2 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
09af9d97eb target/riscv: Move gen_arith_imm() decoding into trans_* functions
2b6c72f3da target/riscv: Remove manual decoding from gen_store()
1d3a7b5cb7 target/riscv: Remove manual decoding from gen_load()
0551b57210 target/riscv: Remove manual decoding from gen_branch()
129eb0e041 target/riscv: Remove gen_jalr()
65a653d84d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
faca63ff69 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
0e9ac5bbcb target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8871e9f09a target/riscv: Convert RV priv insns to decodetree
4ffcac38e7 target/riscv: Convert RV64D insns to decodetree
8b13dafd4a target/riscv: Convert RV32D insns to decodetree
f59e9b8655 target/riscv: Convert RV64F insns to decodetree
8cd874a0eb target/riscv: Convert RV32F insns to decodetree
4f9f53aa9e target/riscv: Convert RV64A insns to decodetree
17aee59b02 target/riscv: Convert RV32A insns to decodetree
e93a947b94 target/riscv: Convert RVXM insns to decodetree
87454d7d1d target/riscv: Convert RVXI csr insns to decodetree
11f83510fd target/riscv: Convert RVXI fence insns to decodetree
40bf83abf8 target/riscv: Convert RVXI arithmetic insns to decodetree
6f109f635b target/riscv: Convert RV64I load/store insns to decodetree
1bdc022b7c target/riscv: Convert RV32I load/store insns to decodetree
ad3f70396f target/riscv: Convert RVXI branch insns to decodetree
693a52f261 target/riscv: Activate decodetree and implemnt LUI & AUIPC
b098fdaf40 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit b098fdaf40da (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 693a52f261fd (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit ad3f70396f2e (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 1bdc022b7ca3 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 6f109f635b03 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 40bf83abf814 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 11f83510fd16 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 87454d7d1d12 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit e93a947b945f (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 17aee59b02db (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 4f9f53aa9e45 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 8cd874a0eb9b (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit f59e9b865598 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 8b13dafd4acf (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 4ffcac38e78f (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8871e9f09a5f (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 0e9ac5bbcbe0 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit faca63ff6943 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 65a653d84db9 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 129eb0e041ee (target/riscv: Remove gen_jalr())
21/35 Checking commit 0551b5721024 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 1d3a7b5cb775 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 2b6c72f3dae3 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 09af9d97ebf5 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit aa1fcbc0b22f (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 35c8b7cf6516 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit ab8fe35848eb (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 569b6240661a (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 9e15d220cb1e (target/riscv: Remove gen_system())
30/35 Checking commit 5df6fa908b20 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 4be75db1131a (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 96a7dd7cc432 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit d91d36a5a5b1 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit d914ca8ad66d (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 84d923227191 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 19:08 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 19:08 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
b7781a7 target/riscv: Remaining rvc insn reuse 32 bit translators
1ab9d8e target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
0fa8b2e target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
c244577 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
543f794 target/riscv: Convert @cs_2 insns to share translation functions
aa10284 target/riscv: Remove decode_RV32_64G()
722467d target/riscv: Remove gen_system()
7282e3f target/riscv: Rename trans_arith to gen_arith
740da2a target/riscv: Remove manual decoding of RV32/64M insn
82b3b82 target/riscv: Remove shift and slt insn manual decoding
888303c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f43fc38 target/riscv: Move gen_arith_imm() decoding into trans_* functions
675475d target/riscv: Remove manual decoding from gen_store()
18e9f9c target/riscv: Remove manual decoding from gen_load()
a4b5ccf target/riscv: Remove manual decoding from gen_branch()
2bcd11b target/riscv: Remove gen_jalr()
09af5a0 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f0cd394 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
7f0870a target/riscv: Convert quadrant 0 of RVXC insns to decodetree
0b9d6d2 target/riscv: Convert RV priv insns to decodetree
9c6e329 target/riscv: Convert RV64D insns to decodetree
e955fce target/riscv: Convert RV32D insns to decodetree
13e93c0 target/riscv: Convert RV64F insns to decodetree
12184ac target/riscv: Convert RV32F insns to decodetree
a3bcf32 target/riscv: Convert RV64A insns to decodetree
5c47e6b target/riscv: Convert RV32A insns to decodetree
b0f1dae target/riscv: Convert RVXM insns to decodetree
a58a706 target/riscv: Convert RVXI csr insns to decodetree
d47d9c8 target/riscv: Convert RVXI fence insns to decodetree
7a89aec target/riscv: Convert RVXI arithmetic insns to decodetree
a71f6e8 target/riscv: Convert RV64I load/store insns to decodetree
ca43510 target/riscv: Convert RV32I load/store insns to decodetree
e1f0ea1 target/riscv: Convert RVXI branch insns to decodetree
c7218af target/riscv: Activate decodetree and implemnt LUI & AUIPC
9c5a0c8 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 9c5a0c8e56d9 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit c7218af8df45 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit e1f0ea1e116d (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit ca43510d59be (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit a71f6e8504f8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 7a89aecc1174 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit d47d9c887001 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit a58a706b3359 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit b0f1dae534f9 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 5c47e6b13010 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit a3bcf32dcc89 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 12184aca41b0 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 13e93c0c2d8c (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit e955fcea2360 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 9c6e329affae (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 0b9d6d2b6712 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 7f0870aece04 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit f0cd3946bbd4 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 09af5a078201 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 2bcd11b0c280 (target/riscv: Remove gen_jalr())
21/35 Checking commit a4b5ccf08c55 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 18e9f9cb58b7 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 675475d8b0f7 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit f43fc3824068 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 888303cf5131 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 82b3b828f4a3 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 740da2a81db5 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7282e3f26c84 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 722467d01ef3 (target/riscv: Remove gen_system())
30/35 Checking commit aa10284d64ce (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 543f794cbe28 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit c24457729cb7 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 0fa8b2e28f93 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 1ab9d8e93ebe (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b7781a700d0d (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 19:08 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 19:08 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
b7781a7 target/riscv: Remaining rvc insn reuse 32 bit translators
1ab9d8e target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
0fa8b2e target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
c244577 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
543f794 target/riscv: Convert @cs_2 insns to share translation functions
aa10284 target/riscv: Remove decode_RV32_64G()
722467d target/riscv: Remove gen_system()
7282e3f target/riscv: Rename trans_arith to gen_arith
740da2a target/riscv: Remove manual decoding of RV32/64M insn
82b3b82 target/riscv: Remove shift and slt insn manual decoding
888303c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f43fc38 target/riscv: Move gen_arith_imm() decoding into trans_* functions
675475d target/riscv: Remove manual decoding from gen_store()
18e9f9c target/riscv: Remove manual decoding from gen_load()
a4b5ccf target/riscv: Remove manual decoding from gen_branch()
2bcd11b target/riscv: Remove gen_jalr()
09af5a0 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f0cd394 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
7f0870a target/riscv: Convert quadrant 0 of RVXC insns to decodetree
0b9d6d2 target/riscv: Convert RV priv insns to decodetree
9c6e329 target/riscv: Convert RV64D insns to decodetree
e955fce target/riscv: Convert RV32D insns to decodetree
13e93c0 target/riscv: Convert RV64F insns to decodetree
12184ac target/riscv: Convert RV32F insns to decodetree
a3bcf32 target/riscv: Convert RV64A insns to decodetree
5c47e6b target/riscv: Convert RV32A insns to decodetree
b0f1dae target/riscv: Convert RVXM insns to decodetree
a58a706 target/riscv: Convert RVXI csr insns to decodetree
d47d9c8 target/riscv: Convert RVXI fence insns to decodetree
7a89aec target/riscv: Convert RVXI arithmetic insns to decodetree
a71f6e8 target/riscv: Convert RV64I load/store insns to decodetree
ca43510 target/riscv: Convert RV32I load/store insns to decodetree
e1f0ea1 target/riscv: Convert RVXI branch insns to decodetree
c7218af target/riscv: Activate decodetree and implemnt LUI & AUIPC
9c5a0c8 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 9c5a0c8e56d9 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit c7218af8df45 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit e1f0ea1e116d (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit ca43510d59be (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit a71f6e8504f8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 7a89aecc1174 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit d47d9c887001 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit a58a706b3359 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit b0f1dae534f9 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 5c47e6b13010 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit a3bcf32dcc89 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 12184aca41b0 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 13e93c0c2d8c (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit e955fcea2360 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 9c6e329affae (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 0b9d6d2b6712 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 7f0870aece04 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit f0cd3946bbd4 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 09af5a078201 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 2bcd11b0c280 (target/riscv: Remove gen_jalr())
21/35 Checking commit a4b5ccf08c55 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 18e9f9cb58b7 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 675475d8b0f7 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit f43fc3824068 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 888303cf5131 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 82b3b828f4a3 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 740da2a81db5 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7282e3f26c84 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 722467d01ef3 (target/riscv: Remove gen_system())
30/35 Checking commit aa10284d64ce (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 543f794cbe28 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit c24457729cb7 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 0fa8b2e28f93 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 1ab9d8e93ebe (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b7781a700d0d (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 19:12 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 19:12 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
aefcd28..e897790 master -> master
- [tag update] patchew/20190121170731.2500692-1-stefanb@linux.ibm.com -> patchew/20190121170731.2500692-1-stefanb@linux.ibm.com
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
- [tag update] patchew/20190130132214.25493-1-laurent@vivier.eu -> patchew/20190130132214.25493-1-laurent@vivier.eu
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
b7781a7 target/riscv: Remaining rvc insn reuse 32 bit translators
1ab9d8e target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
0fa8b2e target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
c244577 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
543f794 target/riscv: Convert @cs_2 insns to share translation functions
aa10284 target/riscv: Remove decode_RV32_64G()
722467d target/riscv: Remove gen_system()
7282e3f target/riscv: Rename trans_arith to gen_arith
740da2a target/riscv: Remove manual decoding of RV32/64M insn
82b3b82 target/riscv: Remove shift and slt insn manual decoding
888303c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f43fc38 target/riscv: Move gen_arith_imm() decoding into trans_* functions
675475d target/riscv: Remove manual decoding from gen_store()
18e9f9c target/riscv: Remove manual decoding from gen_load()
a4b5ccf target/riscv: Remove manual decoding from gen_branch()
2bcd11b target/riscv: Remove gen_jalr()
09af5a0 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f0cd394 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
7f0870a target/riscv: Convert quadrant 0 of RVXC insns to decodetree
0b9d6d2 target/riscv: Convert RV priv insns to decodetree
9c6e329 target/riscv: Convert RV64D insns to decodetree
e955fce target/riscv: Convert RV32D insns to decodetree
13e93c0 target/riscv: Convert RV64F insns to decodetree
12184ac target/riscv: Convert RV32F insns to decodetree
a3bcf32 target/riscv: Convert RV64A insns to decodetree
5c47e6b target/riscv: Convert RV32A insns to decodetree
b0f1dae target/riscv: Convert RVXM insns to decodetree
a58a706 target/riscv: Convert RVXI csr insns to decodetree
d47d9c8 target/riscv: Convert RVXI fence insns to decodetree
7a89aec target/riscv: Convert RVXI arithmetic insns to decodetree
a71f6e8 target/riscv: Convert RV64I load/store insns to decodetree
ca43510 target/riscv: Convert RV32I load/store insns to decodetree
e1f0ea1 target/riscv: Convert RVXI branch insns to decodetree
c7218af target/riscv: Activate decodetree and implemnt LUI & AUIPC
9c5a0c8 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 9c5a0c8e56d9 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit c7218af8df45 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit e1f0ea1e116d (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit ca43510d59be (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit a71f6e8504f8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 7a89aecc1174 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit d47d9c887001 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit a58a706b3359 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit b0f1dae534f9 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 5c47e6b13010 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit a3bcf32dcc89 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 12184aca41b0 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 13e93c0c2d8c (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit e955fcea2360 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 9c6e329affae (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 0b9d6d2b6712 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 7f0870aece04 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit f0cd3946bbd4 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 09af5a078201 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 2bcd11b0c280 (target/riscv: Remove gen_jalr())
21/35 Checking commit a4b5ccf08c55 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 18e9f9cb58b7 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 675475d8b0f7 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit f43fc3824068 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 888303cf5131 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 82b3b828f4a3 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 740da2a81db5 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7282e3f26c84 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 722467d01ef3 (target/riscv: Remove gen_system())
30/35 Checking commit aa10284d64ce (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 543f794cbe28 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit c24457729cb7 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 0fa8b2e28f93 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 1ab9d8e93ebe (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b7781a700d0d (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 19:12 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 19:12 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
aefcd28..e897790 master -> master
- [tag update] patchew/20190121170731.2500692-1-stefanb@linux.ibm.com -> patchew/20190121170731.2500692-1-stefanb@linux.ibm.com
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
- [tag update] patchew/20190130132214.25493-1-laurent@vivier.eu -> patchew/20190130132214.25493-1-laurent@vivier.eu
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
b7781a7 target/riscv: Remaining rvc insn reuse 32 bit translators
1ab9d8e target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
0fa8b2e target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
c244577 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
543f794 target/riscv: Convert @cs_2 insns to share translation functions
aa10284 target/riscv: Remove decode_RV32_64G()
722467d target/riscv: Remove gen_system()
7282e3f target/riscv: Rename trans_arith to gen_arith
740da2a target/riscv: Remove manual decoding of RV32/64M insn
82b3b82 target/riscv: Remove shift and slt insn manual decoding
888303c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f43fc38 target/riscv: Move gen_arith_imm() decoding into trans_* functions
675475d target/riscv: Remove manual decoding from gen_store()
18e9f9c target/riscv: Remove manual decoding from gen_load()
a4b5ccf target/riscv: Remove manual decoding from gen_branch()
2bcd11b target/riscv: Remove gen_jalr()
09af5a0 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f0cd394 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
7f0870a target/riscv: Convert quadrant 0 of RVXC insns to decodetree
0b9d6d2 target/riscv: Convert RV priv insns to decodetree
9c6e329 target/riscv: Convert RV64D insns to decodetree
e955fce target/riscv: Convert RV32D insns to decodetree
13e93c0 target/riscv: Convert RV64F insns to decodetree
12184ac target/riscv: Convert RV32F insns to decodetree
a3bcf32 target/riscv: Convert RV64A insns to decodetree
5c47e6b target/riscv: Convert RV32A insns to decodetree
b0f1dae target/riscv: Convert RVXM insns to decodetree
a58a706 target/riscv: Convert RVXI csr insns to decodetree
d47d9c8 target/riscv: Convert RVXI fence insns to decodetree
7a89aec target/riscv: Convert RVXI arithmetic insns to decodetree
a71f6e8 target/riscv: Convert RV64I load/store insns to decodetree
ca43510 target/riscv: Convert RV32I load/store insns to decodetree
e1f0ea1 target/riscv: Convert RVXI branch insns to decodetree
c7218af target/riscv: Activate decodetree and implemnt LUI & AUIPC
9c5a0c8 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 9c5a0c8e56d9 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit c7218af8df45 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit e1f0ea1e116d (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit ca43510d59be (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit a71f6e8504f8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 7a89aecc1174 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit d47d9c887001 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit a58a706b3359 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit b0f1dae534f9 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 5c47e6b13010 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit a3bcf32dcc89 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 12184aca41b0 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 13e93c0c2d8c (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit e955fcea2360 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 9c6e329affae (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 0b9d6d2b6712 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 7f0870aece04 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit f0cd3946bbd4 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 09af5a078201 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 2bcd11b0c280 (target/riscv: Remove gen_jalr())
21/35 Checking commit a4b5ccf08c55 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 18e9f9cb58b7 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 675475d8b0f7 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit f43fc3824068 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 888303cf5131 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 82b3b828f4a3 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 740da2a81db5 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7282e3f26c84 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 722467d01ef3 (target/riscv: Remove gen_system())
30/35 Checking commit aa10284d64ce (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 543f794cbe28 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit c24457729cb7 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 0fa8b2e28f93 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 1ab9d8e93ebe (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b7781a700d0d (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:00 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:00 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
b0d91d5c95 target/riscv: Remaining rvc insn reuse 32 bit translators
7206dcc84c target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
b2503c4a5d target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8a29c8d73f target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
dfff5221bb target/riscv: Convert @cs_2 insns to share translation functions
6bd1806e46 target/riscv: Remove decode_RV32_64G()
5d8486984d target/riscv: Remove gen_system()
9398d224da target/riscv: Rename trans_arith to gen_arith
f46f9d3b7e target/riscv: Remove manual decoding of RV32/64M insn
4f99b16403 target/riscv: Remove shift and slt insn manual decoding
4b7a37bf50 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
d5dff5bb4f target/riscv: Move gen_arith_imm() decoding into trans_* functions
cdd18b5fd3 target/riscv: Remove manual decoding from gen_store()
02662360b2 target/riscv: Remove manual decoding from gen_load()
bd16560117 target/riscv: Remove manual decoding from gen_branch()
38dd04479d target/riscv: Remove gen_jalr()
f60b6e585d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
6696503c0b target/riscv: Convert quadrant 1 of RVXC insns to decodetree
798ef76c96 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
5a39fc2a0e target/riscv: Convert RV priv insns to decodetree
1f1f8c9bc3 target/riscv: Convert RV64D insns to decodetree
d1c0ab7fe1 target/riscv: Convert RV32D insns to decodetree
c6e274a4d5 target/riscv: Convert RV64F insns to decodetree
6c51feecdd target/riscv: Convert RV32F insns to decodetree
577e399bd4 target/riscv: Convert RV64A insns to decodetree
c4fef55a8d target/riscv: Convert RV32A insns to decodetree
fdbec6cffa target/riscv: Convert RVXM insns to decodetree
d9ed27a651 target/riscv: Convert RVXI csr insns to decodetree
591b4a364c target/riscv: Convert RVXI fence insns to decodetree
3fcba6a869 target/riscv: Convert RVXI arithmetic insns to decodetree
de26410380 target/riscv: Convert RV64I load/store insns to decodetree
15edfa7b53 target/riscv: Convert RV32I load/store insns to decodetree
aedd230ba2 target/riscv: Convert RVXI branch insns to decodetree
52f4c244c6 target/riscv: Activate decodetree and implemnt LUI & AUIPC
669f7c2086 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 669f7c2086d5 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 52f4c244c6bb (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit aedd230ba257 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 15edfa7b53d2 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit de26410380cd (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 3fcba6a869c8 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 591b4a364c72 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d9ed27a651b0 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit fdbec6cffaa5 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit c4fef55a8df1 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 577e399bd4e6 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 6c51feecddb7 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit c6e274a4d549 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit d1c0ab7fe104 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 1f1f8c9bc321 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 5a39fc2a0ed0 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 798ef76c9652 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 6696503c0b2b (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit f60b6e585df6 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 38dd04479d3a (target/riscv: Remove gen_jalr())
21/35 Checking commit bd16560117e3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 02662360b2a0 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit cdd18b5fd3f3 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit d5dff5bb4f95 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 4b7a37bf50cc (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 4f99b16403cd (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit f46f9d3b7e91 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 9398d224da90 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 5d8486984d26 (target/riscv: Remove gen_system())
30/35 Checking commit 6bd1806e46e5 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit dfff5221bb2c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8a29c8d73fba (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit b2503c4a5d2f (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 7206dcc84c13 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b0d91d5c9510 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:00 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:00 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
b0d91d5c95 target/riscv: Remaining rvc insn reuse 32 bit translators
7206dcc84c target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
b2503c4a5d target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8a29c8d73f target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
dfff5221bb target/riscv: Convert @cs_2 insns to share translation functions
6bd1806e46 target/riscv: Remove decode_RV32_64G()
5d8486984d target/riscv: Remove gen_system()
9398d224da target/riscv: Rename trans_arith to gen_arith
f46f9d3b7e target/riscv: Remove manual decoding of RV32/64M insn
4f99b16403 target/riscv: Remove shift and slt insn manual decoding
4b7a37bf50 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
d5dff5bb4f target/riscv: Move gen_arith_imm() decoding into trans_* functions
cdd18b5fd3 target/riscv: Remove manual decoding from gen_store()
02662360b2 target/riscv: Remove manual decoding from gen_load()
bd16560117 target/riscv: Remove manual decoding from gen_branch()
38dd04479d target/riscv: Remove gen_jalr()
f60b6e585d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
6696503c0b target/riscv: Convert quadrant 1 of RVXC insns to decodetree
798ef76c96 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
5a39fc2a0e target/riscv: Convert RV priv insns to decodetree
1f1f8c9bc3 target/riscv: Convert RV64D insns to decodetree
d1c0ab7fe1 target/riscv: Convert RV32D insns to decodetree
c6e274a4d5 target/riscv: Convert RV64F insns to decodetree
6c51feecdd target/riscv: Convert RV32F insns to decodetree
577e399bd4 target/riscv: Convert RV64A insns to decodetree
c4fef55a8d target/riscv: Convert RV32A insns to decodetree
fdbec6cffa target/riscv: Convert RVXM insns to decodetree
d9ed27a651 target/riscv: Convert RVXI csr insns to decodetree
591b4a364c target/riscv: Convert RVXI fence insns to decodetree
3fcba6a869 target/riscv: Convert RVXI arithmetic insns to decodetree
de26410380 target/riscv: Convert RV64I load/store insns to decodetree
15edfa7b53 target/riscv: Convert RV32I load/store insns to decodetree
aedd230ba2 target/riscv: Convert RVXI branch insns to decodetree
52f4c244c6 target/riscv: Activate decodetree and implemnt LUI & AUIPC
669f7c2086 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 669f7c2086d5 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 52f4c244c6bb (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit aedd230ba257 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 15edfa7b53d2 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit de26410380cd (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 3fcba6a869c8 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 591b4a364c72 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d9ed27a651b0 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit fdbec6cffaa5 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit c4fef55a8df1 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 577e399bd4e6 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 6c51feecddb7 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit c6e274a4d549 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit d1c0ab7fe104 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 1f1f8c9bc321 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 5a39fc2a0ed0 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 798ef76c9652 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 6696503c0b2b (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit f60b6e585df6 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 38dd04479d3a (target/riscv: Remove gen_jalr())
21/35 Checking commit bd16560117e3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 02662360b2a0 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit cdd18b5fd3f3 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit d5dff5bb4f95 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 4b7a37bf50cc (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 4f99b16403cd (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit f46f9d3b7e91 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 9398d224da90 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 5d8486984d26 (target/riscv: Remove gen_system())
30/35 Checking commit 6bd1806e46e5 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit dfff5221bb2c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8a29c8d73fba (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit b2503c4a5d2f (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 7206dcc84c13 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b0d91d5c9510 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:01 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:01 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
b0d91d5 target/riscv: Remaining rvc insn reuse 32 bit translators
7206dcc target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
b2503c4 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8a29c8d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
dfff522 target/riscv: Convert @cs_2 insns to share translation functions
6bd1806 target/riscv: Remove decode_RV32_64G()
5d84869 target/riscv: Remove gen_system()
9398d22 target/riscv: Rename trans_arith to gen_arith
f46f9d3 target/riscv: Remove manual decoding of RV32/64M insn
4f99b16 target/riscv: Remove shift and slt insn manual decoding
4b7a37b target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
d5dff5b target/riscv: Move gen_arith_imm() decoding into trans_* functions
cdd18b5 target/riscv: Remove manual decoding from gen_store()
0266236 target/riscv: Remove manual decoding from gen_load()
bd16560 target/riscv: Remove manual decoding from gen_branch()
38dd044 target/riscv: Remove gen_jalr()
f60b6e5 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
6696503 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
798ef76 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
5a39fc2 target/riscv: Convert RV priv insns to decodetree
1f1f8c9 target/riscv: Convert RV64D insns to decodetree
d1c0ab7 target/riscv: Convert RV32D insns to decodetree
c6e274a target/riscv: Convert RV64F insns to decodetree
6c51fee target/riscv: Convert RV32F insns to decodetree
577e399 target/riscv: Convert RV64A insns to decodetree
c4fef55 target/riscv: Convert RV32A insns to decodetree
fdbec6c target/riscv: Convert RVXM insns to decodetree
d9ed27a target/riscv: Convert RVXI csr insns to decodetree
591b4a3 target/riscv: Convert RVXI fence insns to decodetree
3fcba6a target/riscv: Convert RVXI arithmetic insns to decodetree
de26410 target/riscv: Convert RV64I load/store insns to decodetree
15edfa7 target/riscv: Convert RV32I load/store insns to decodetree
aedd230 target/riscv: Convert RVXI branch insns to decodetree
52f4c24 target/riscv: Activate decodetree and implemnt LUI & AUIPC
669f7c2 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 669f7c2086d5 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 52f4c244c6bb (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit aedd230ba257 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 15edfa7b53d2 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit de26410380cd (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 3fcba6a869c8 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 591b4a364c72 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d9ed27a651b0 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit fdbec6cffaa5 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit c4fef55a8df1 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 577e399bd4e6 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 6c51feecddb7 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit c6e274a4d549 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit d1c0ab7fe104 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 1f1f8c9bc321 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 5a39fc2a0ed0 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 798ef76c9652 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 6696503c0b2b (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit f60b6e585df6 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 38dd04479d3a (target/riscv: Remove gen_jalr())
21/35 Checking commit bd16560117e3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 02662360b2a0 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit cdd18b5fd3f3 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit d5dff5bb4f95 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 4b7a37bf50cc (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 4f99b16403cd (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit f46f9d3b7e91 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 9398d224da90 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 5d8486984d26 (target/riscv: Remove gen_system())
30/35 Checking commit 6bd1806e46e5 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit dfff5221bb2c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8a29c8d73fba (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit b2503c4a5d2f (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 7206dcc84c13 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b0d91d5c9510 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:01 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:01 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
b0d91d5 target/riscv: Remaining rvc insn reuse 32 bit translators
7206dcc target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
b2503c4 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8a29c8d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
dfff522 target/riscv: Convert @cs_2 insns to share translation functions
6bd1806 target/riscv: Remove decode_RV32_64G()
5d84869 target/riscv: Remove gen_system()
9398d22 target/riscv: Rename trans_arith to gen_arith
f46f9d3 target/riscv: Remove manual decoding of RV32/64M insn
4f99b16 target/riscv: Remove shift and slt insn manual decoding
4b7a37b target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
d5dff5b target/riscv: Move gen_arith_imm() decoding into trans_* functions
cdd18b5 target/riscv: Remove manual decoding from gen_store()
0266236 target/riscv: Remove manual decoding from gen_load()
bd16560 target/riscv: Remove manual decoding from gen_branch()
38dd044 target/riscv: Remove gen_jalr()
f60b6e5 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
6696503 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
798ef76 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
5a39fc2 target/riscv: Convert RV priv insns to decodetree
1f1f8c9 target/riscv: Convert RV64D insns to decodetree
d1c0ab7 target/riscv: Convert RV32D insns to decodetree
c6e274a target/riscv: Convert RV64F insns to decodetree
6c51fee target/riscv: Convert RV32F insns to decodetree
577e399 target/riscv: Convert RV64A insns to decodetree
c4fef55 target/riscv: Convert RV32A insns to decodetree
fdbec6c target/riscv: Convert RVXM insns to decodetree
d9ed27a target/riscv: Convert RVXI csr insns to decodetree
591b4a3 target/riscv: Convert RVXI fence insns to decodetree
3fcba6a target/riscv: Convert RVXI arithmetic insns to decodetree
de26410 target/riscv: Convert RV64I load/store insns to decodetree
15edfa7 target/riscv: Convert RV32I load/store insns to decodetree
aedd230 target/riscv: Convert RVXI branch insns to decodetree
52f4c24 target/riscv: Activate decodetree and implemnt LUI & AUIPC
669f7c2 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 669f7c2086d5 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 52f4c244c6bb (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit aedd230ba257 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 15edfa7b53d2 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit de26410380cd (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 3fcba6a869c8 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 591b4a364c72 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d9ed27a651b0 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit fdbec6cffaa5 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit c4fef55a8df1 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 577e399bd4e6 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 6c51feecddb7 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit c6e274a4d549 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit d1c0ab7fe104 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 1f1f8c9bc321 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 5a39fc2a0ed0 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 798ef76c9652 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 6696503c0b2b (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit f60b6e585df6 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 38dd04479d3a (target/riscv: Remove gen_jalr())
21/35 Checking commit bd16560117e3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 02662360b2a0 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit cdd18b5fd3f3 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit d5dff5bb4f95 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 4b7a37bf50cc (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 4f99b16403cd (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit f46f9d3b7e91 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 9398d224da90 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 5d8486984d26 (target/riscv: Remove gen_system())
30/35 Checking commit 6bd1806e46e5 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit dfff5221bb2c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8a29c8d73fba (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit b2503c4a5d2f (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 7206dcc84c13 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b0d91d5c9510 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:04 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:04 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
b0d91d5 target/riscv: Remaining rvc insn reuse 32 bit translators
7206dcc target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
b2503c4 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8a29c8d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
dfff522 target/riscv: Convert @cs_2 insns to share translation functions
6bd1806 target/riscv: Remove decode_RV32_64G()
5d84869 target/riscv: Remove gen_system()
9398d22 target/riscv: Rename trans_arith to gen_arith
f46f9d3 target/riscv: Remove manual decoding of RV32/64M insn
4f99b16 target/riscv: Remove shift and slt insn manual decoding
4b7a37b target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
d5dff5b target/riscv: Move gen_arith_imm() decoding into trans_* functions
cdd18b5 target/riscv: Remove manual decoding from gen_store()
0266236 target/riscv: Remove manual decoding from gen_load()
bd16560 target/riscv: Remove manual decoding from gen_branch()
38dd044 target/riscv: Remove gen_jalr()
f60b6e5 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
6696503 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
798ef76 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
5a39fc2 target/riscv: Convert RV priv insns to decodetree
1f1f8c9 target/riscv: Convert RV64D insns to decodetree
d1c0ab7 target/riscv: Convert RV32D insns to decodetree
c6e274a target/riscv: Convert RV64F insns to decodetree
6c51fee target/riscv: Convert RV32F insns to decodetree
577e399 target/riscv: Convert RV64A insns to decodetree
c4fef55 target/riscv: Convert RV32A insns to decodetree
fdbec6c target/riscv: Convert RVXM insns to decodetree
d9ed27a target/riscv: Convert RVXI csr insns to decodetree
591b4a3 target/riscv: Convert RVXI fence insns to decodetree
3fcba6a target/riscv: Convert RVXI arithmetic insns to decodetree
de26410 target/riscv: Convert RV64I load/store insns to decodetree
15edfa7 target/riscv: Convert RV32I load/store insns to decodetree
aedd230 target/riscv: Convert RVXI branch insns to decodetree
52f4c24 target/riscv: Activate decodetree and implemnt LUI & AUIPC
669f7c2 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 669f7c2086d5 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 52f4c244c6bb (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit aedd230ba257 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 15edfa7b53d2 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit de26410380cd (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 3fcba6a869c8 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 591b4a364c72 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d9ed27a651b0 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit fdbec6cffaa5 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit c4fef55a8df1 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 577e399bd4e6 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 6c51feecddb7 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit c6e274a4d549 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit d1c0ab7fe104 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 1f1f8c9bc321 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 5a39fc2a0ed0 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 798ef76c9652 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 6696503c0b2b (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit f60b6e585df6 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 38dd04479d3a (target/riscv: Remove gen_jalr())
21/35 Checking commit bd16560117e3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 02662360b2a0 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit cdd18b5fd3f3 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit d5dff5bb4f95 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 4b7a37bf50cc (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 4f99b16403cd (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit f46f9d3b7e91 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 9398d224da90 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 5d8486984d26 (target/riscv: Remove gen_system())
30/35 Checking commit 6bd1806e46e5 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit dfff5221bb2c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8a29c8d73fba (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit b2503c4a5d2f (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 7206dcc84c13 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b0d91d5c9510 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:04 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:04 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
b0d91d5 target/riscv: Remaining rvc insn reuse 32 bit translators
7206dcc target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
b2503c4 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8a29c8d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
dfff522 target/riscv: Convert @cs_2 insns to share translation functions
6bd1806 target/riscv: Remove decode_RV32_64G()
5d84869 target/riscv: Remove gen_system()
9398d22 target/riscv: Rename trans_arith to gen_arith
f46f9d3 target/riscv: Remove manual decoding of RV32/64M insn
4f99b16 target/riscv: Remove shift and slt insn manual decoding
4b7a37b target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
d5dff5b target/riscv: Move gen_arith_imm() decoding into trans_* functions
cdd18b5 target/riscv: Remove manual decoding from gen_store()
0266236 target/riscv: Remove manual decoding from gen_load()
bd16560 target/riscv: Remove manual decoding from gen_branch()
38dd044 target/riscv: Remove gen_jalr()
f60b6e5 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
6696503 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
798ef76 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
5a39fc2 target/riscv: Convert RV priv insns to decodetree
1f1f8c9 target/riscv: Convert RV64D insns to decodetree
d1c0ab7 target/riscv: Convert RV32D insns to decodetree
c6e274a target/riscv: Convert RV64F insns to decodetree
6c51fee target/riscv: Convert RV32F insns to decodetree
577e399 target/riscv: Convert RV64A insns to decodetree
c4fef55 target/riscv: Convert RV32A insns to decodetree
fdbec6c target/riscv: Convert RVXM insns to decodetree
d9ed27a target/riscv: Convert RVXI csr insns to decodetree
591b4a3 target/riscv: Convert RVXI fence insns to decodetree
3fcba6a target/riscv: Convert RVXI arithmetic insns to decodetree
de26410 target/riscv: Convert RV64I load/store insns to decodetree
15edfa7 target/riscv: Convert RV32I load/store insns to decodetree
aedd230 target/riscv: Convert RVXI branch insns to decodetree
52f4c24 target/riscv: Activate decodetree and implemnt LUI & AUIPC
669f7c2 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 669f7c2086d5 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 52f4c244c6bb (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit aedd230ba257 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 15edfa7b53d2 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit de26410380cd (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 3fcba6a869c8 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 591b4a364c72 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d9ed27a651b0 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit fdbec6cffaa5 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit c4fef55a8df1 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 577e399bd4e6 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 6c51feecddb7 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit c6e274a4d549 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit d1c0ab7fe104 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 1f1f8c9bc321 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 5a39fc2a0ed0 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 798ef76c9652 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 6696503c0b2b (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit f60b6e585df6 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 38dd04479d3a (target/riscv: Remove gen_jalr())
21/35 Checking commit bd16560117e3 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 02662360b2a0 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit cdd18b5fd3f3 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit d5dff5bb4f95 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 4b7a37bf50cc (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 4f99b16403cd (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit f46f9d3b7e91 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 9398d224da90 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 5d8486984d26 (target/riscv: Remove gen_system())
30/35 Checking commit 6bd1806e46e5 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit dfff5221bb2c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8a29c8d73fba (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit b2503c4a5d2f (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 7206dcc84c13 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b0d91d5c9510 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:09 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:09 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
a3cbe72 target/riscv: Remaining rvc insn reuse 32 bit translators
9afdd3e target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
b915423 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
4e79caa target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
0121b65 target/riscv: Convert @cs_2 insns to share translation functions
b7a4ef9 target/riscv: Remove decode_RV32_64G()
510bbe8 target/riscv: Remove gen_system()
f1331f5 target/riscv: Rename trans_arith to gen_arith
b276b8c target/riscv: Remove manual decoding of RV32/64M insn
d445e37 target/riscv: Remove shift and slt insn manual decoding
46bfc39 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
9db1077 target/riscv: Move gen_arith_imm() decoding into trans_* functions
72b35f4 target/riscv: Remove manual decoding from gen_store()
84c26d7 target/riscv: Remove manual decoding from gen_load()
4779d13 target/riscv: Remove manual decoding from gen_branch()
5870468 target/riscv: Remove gen_jalr()
fb02c0c target/riscv: Convert quadrant 2 of RVXC insns to decodetree
64793c9 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
5e210d0 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8d3d945 target/riscv: Convert RV priv insns to decodetree
d3a238f target/riscv: Convert RV64D insns to decodetree
982f175 target/riscv: Convert RV32D insns to decodetree
3fe1356 target/riscv: Convert RV64F insns to decodetree
d231c90 target/riscv: Convert RV32F insns to decodetree
82b118b target/riscv: Convert RV64A insns to decodetree
32b39a2 target/riscv: Convert RV32A insns to decodetree
d6f6f2b target/riscv: Convert RVXM insns to decodetree
34094a1 target/riscv: Convert RVXI csr insns to decodetree
6995f94 target/riscv: Convert RVXI fence insns to decodetree
0a445ed target/riscv: Convert RVXI arithmetic insns to decodetree
3566ff3 target/riscv: Convert RV64I load/store insns to decodetree
9f47cca target/riscv: Convert RV32I load/store insns to decodetree
b28fd8e target/riscv: Convert RVXI branch insns to decodetree
dde69a0 target/riscv: Activate decodetree and implemnt LUI & AUIPC
3e3b3d7 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 3e3b3d7bd110 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit dde69a04bec7 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit b28fd8eb6190 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 9f47cca20003 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 3566ff341f1c (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 0a445ed42134 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 6995f940028d (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 34094a1d0d03 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit d6f6f2bb7f86 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 32b39a20f7d1 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 82b118b87c5f (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit d231c90bc0fb (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 3fe1356adf7d (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 982f17583919 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit d3a238f2f0a7 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8d3d945cdcc3 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 5e210d0cb62b (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 64793c940e59 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit fb02c0c0753e (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 58704684980a (target/riscv: Remove gen_jalr())
21/35 Checking commit 4779d1354543 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 84c26d735452 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 72b35f4f5e56 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 9db10777af3b (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 46bfc390d4dd (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit d445e37b121e (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit b276b8c471be (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit f1331f538b13 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 510bbe84104f (target/riscv: Remove gen_system())
30/35 Checking commit b7a4ef9b8a01 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 0121b6527d37 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 4e79caa2c455 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit b915423a7d63 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 9afdd3ec498e (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit a3cbe726d4e4 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:09 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:09 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
a3cbe72 target/riscv: Remaining rvc insn reuse 32 bit translators
9afdd3e target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
b915423 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
4e79caa target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
0121b65 target/riscv: Convert @cs_2 insns to share translation functions
b7a4ef9 target/riscv: Remove decode_RV32_64G()
510bbe8 target/riscv: Remove gen_system()
f1331f5 target/riscv: Rename trans_arith to gen_arith
b276b8c target/riscv: Remove manual decoding of RV32/64M insn
d445e37 target/riscv: Remove shift and slt insn manual decoding
46bfc39 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
9db1077 target/riscv: Move gen_arith_imm() decoding into trans_* functions
72b35f4 target/riscv: Remove manual decoding from gen_store()
84c26d7 target/riscv: Remove manual decoding from gen_load()
4779d13 target/riscv: Remove manual decoding from gen_branch()
5870468 target/riscv: Remove gen_jalr()
fb02c0c target/riscv: Convert quadrant 2 of RVXC insns to decodetree
64793c9 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
5e210d0 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8d3d945 target/riscv: Convert RV priv insns to decodetree
d3a238f target/riscv: Convert RV64D insns to decodetree
982f175 target/riscv: Convert RV32D insns to decodetree
3fe1356 target/riscv: Convert RV64F insns to decodetree
d231c90 target/riscv: Convert RV32F insns to decodetree
82b118b target/riscv: Convert RV64A insns to decodetree
32b39a2 target/riscv: Convert RV32A insns to decodetree
d6f6f2b target/riscv: Convert RVXM insns to decodetree
34094a1 target/riscv: Convert RVXI csr insns to decodetree
6995f94 target/riscv: Convert RVXI fence insns to decodetree
0a445ed target/riscv: Convert RVXI arithmetic insns to decodetree
3566ff3 target/riscv: Convert RV64I load/store insns to decodetree
9f47cca target/riscv: Convert RV32I load/store insns to decodetree
b28fd8e target/riscv: Convert RVXI branch insns to decodetree
dde69a0 target/riscv: Activate decodetree and implemnt LUI & AUIPC
3e3b3d7 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 3e3b3d7bd110 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit dde69a04bec7 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit b28fd8eb6190 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 9f47cca20003 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 3566ff341f1c (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 0a445ed42134 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 6995f940028d (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 34094a1d0d03 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit d6f6f2bb7f86 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 32b39a20f7d1 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 82b118b87c5f (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit d231c90bc0fb (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 3fe1356adf7d (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 982f17583919 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit d3a238f2f0a7 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8d3d945cdcc3 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 5e210d0cb62b (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 64793c940e59 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit fb02c0c0753e (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 58704684980a (target/riscv: Remove gen_jalr())
21/35 Checking commit 4779d1354543 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 84c26d735452 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 72b35f4f5e56 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 9db10777af3b (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 46bfc390d4dd (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit d445e37b121e (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit b276b8c471be (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit f1331f538b13 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 510bbe84104f (target/riscv: Remove gen_system())
30/35 Checking commit b7a4ef9b8a01 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 0121b6527d37 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 4e79caa2c455 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit b915423a7d63 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 9afdd3ec498e (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit a3cbe726d4e4 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:10 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:10 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
b5d179aad0 target/riscv: Remaining rvc insn reuse 32 bit translators
89632ce033 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
2a407bf78c target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
82081bebf6 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
e17dd909d2 target/riscv: Convert @cs_2 insns to share translation functions
39402d7cf2 target/riscv: Remove decode_RV32_64G()
e168704ef0 target/riscv: Remove gen_system()
925f796a5d target/riscv: Rename trans_arith to gen_arith
ce11a2d977 target/riscv: Remove manual decoding of RV32/64M insn
819cbda0d1 target/riscv: Remove shift and slt insn manual decoding
6de3ea8220 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
ac209c8507 target/riscv: Move gen_arith_imm() decoding into trans_* functions
e6c57d70f0 target/riscv: Remove manual decoding from gen_store()
6e32a22cc2 target/riscv: Remove manual decoding from gen_load()
fc2febc2de target/riscv: Remove manual decoding from gen_branch()
24ffd31f26 target/riscv: Remove gen_jalr()
ecb0b58ef2 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7ce9e53aae target/riscv: Convert quadrant 1 of RVXC insns to decodetree
2cf65e25d0 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
ae6f285826 target/riscv: Convert RV priv insns to decodetree
9c31e4fb05 target/riscv: Convert RV64D insns to decodetree
5e73a245d4 target/riscv: Convert RV32D insns to decodetree
62b38c11f0 target/riscv: Convert RV64F insns to decodetree
4a7251e72d target/riscv: Convert RV32F insns to decodetree
cff510f04b target/riscv: Convert RV64A insns to decodetree
180d186fed target/riscv: Convert RV32A insns to decodetree
bf22444494 target/riscv: Convert RVXM insns to decodetree
a3244685ea target/riscv: Convert RVXI csr insns to decodetree
e4cb753f66 target/riscv: Convert RVXI fence insns to decodetree
851fff88fc target/riscv: Convert RVXI arithmetic insns to decodetree
b806b20de2 target/riscv: Convert RV64I load/store insns to decodetree
ca745cbfa1 target/riscv: Convert RV32I load/store insns to decodetree
850511d47c target/riscv: Convert RVXI branch insns to decodetree
812f4fb0e1 target/riscv: Activate decodetree and implemnt LUI & AUIPC
40371d802c target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 40371d802c19 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 812f4fb0e12e (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 850511d47ca4 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit ca745cbfa171 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit b806b20de230 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 851fff88fc5c (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit e4cb753f663e (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit a3244685ea17 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit bf2244449406 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 180d186fed80 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit cff510f04bf0 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 4a7251e72df0 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 62b38c11f073 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 5e73a245d405 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 9c31e4fb05a1 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit ae6f285826c0 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 2cf65e25d0a3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 7ce9e53aaeab (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit ecb0b58ef290 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 24ffd31f260b (target/riscv: Remove gen_jalr())
21/35 Checking commit fc2febc2de23 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 6e32a22cc246 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit e6c57d70f019 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit ac209c850750 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 6de3ea822041 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 819cbda0d1bf (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit ce11a2d977ab (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 925f796a5d0f (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit e168704ef0df (target/riscv: Remove gen_system())
30/35 Checking commit 39402d7cf28f (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit e17dd909d236 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 82081bebf6d0 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 2a407bf78c52 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 89632ce033c5 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b5d179aad0b5 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:10 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:10 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
b5d179aad0 target/riscv: Remaining rvc insn reuse 32 bit translators
89632ce033 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
2a407bf78c target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
82081bebf6 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
e17dd909d2 target/riscv: Convert @cs_2 insns to share translation functions
39402d7cf2 target/riscv: Remove decode_RV32_64G()
e168704ef0 target/riscv: Remove gen_system()
925f796a5d target/riscv: Rename trans_arith to gen_arith
ce11a2d977 target/riscv: Remove manual decoding of RV32/64M insn
819cbda0d1 target/riscv: Remove shift and slt insn manual decoding
6de3ea8220 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
ac209c8507 target/riscv: Move gen_arith_imm() decoding into trans_* functions
e6c57d70f0 target/riscv: Remove manual decoding from gen_store()
6e32a22cc2 target/riscv: Remove manual decoding from gen_load()
fc2febc2de target/riscv: Remove manual decoding from gen_branch()
24ffd31f26 target/riscv: Remove gen_jalr()
ecb0b58ef2 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7ce9e53aae target/riscv: Convert quadrant 1 of RVXC insns to decodetree
2cf65e25d0 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
ae6f285826 target/riscv: Convert RV priv insns to decodetree
9c31e4fb05 target/riscv: Convert RV64D insns to decodetree
5e73a245d4 target/riscv: Convert RV32D insns to decodetree
62b38c11f0 target/riscv: Convert RV64F insns to decodetree
4a7251e72d target/riscv: Convert RV32F insns to decodetree
cff510f04b target/riscv: Convert RV64A insns to decodetree
180d186fed target/riscv: Convert RV32A insns to decodetree
bf22444494 target/riscv: Convert RVXM insns to decodetree
a3244685ea target/riscv: Convert RVXI csr insns to decodetree
e4cb753f66 target/riscv: Convert RVXI fence insns to decodetree
851fff88fc target/riscv: Convert RVXI arithmetic insns to decodetree
b806b20de2 target/riscv: Convert RV64I load/store insns to decodetree
ca745cbfa1 target/riscv: Convert RV32I load/store insns to decodetree
850511d47c target/riscv: Convert RVXI branch insns to decodetree
812f4fb0e1 target/riscv: Activate decodetree and implemnt LUI & AUIPC
40371d802c target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 40371d802c19 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 812f4fb0e12e (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 850511d47ca4 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit ca745cbfa171 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit b806b20de230 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 851fff88fc5c (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit e4cb753f663e (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit a3244685ea17 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit bf2244449406 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 180d186fed80 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit cff510f04bf0 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 4a7251e72df0 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 62b38c11f073 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 5e73a245d405 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 9c31e4fb05a1 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit ae6f285826c0 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 2cf65e25d0a3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 7ce9e53aaeab (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit ecb0b58ef290 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 24ffd31f260b (target/riscv: Remove gen_jalr())
21/35 Checking commit fc2febc2de23 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 6e32a22cc246 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit e6c57d70f019 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit ac209c850750 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 6de3ea822041 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 819cbda0d1bf (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit ce11a2d977ab (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 925f796a5d0f (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit e168704ef0df (target/riscv: Remove gen_system())
30/35 Checking commit 39402d7cf28f (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit e17dd909d236 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 82081bebf6d0 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 2a407bf78c52 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 89632ce033c5 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b5d179aad0b5 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:11 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:11 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
b5d179a target/riscv: Remaining rvc insn reuse 32 bit translators
89632ce target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
2a407bf target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
82081be target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
e17dd90 target/riscv: Convert @cs_2 insns to share translation functions
39402d7 target/riscv: Remove decode_RV32_64G()
e168704 target/riscv: Remove gen_system()
925f796 target/riscv: Rename trans_arith to gen_arith
ce11a2d target/riscv: Remove manual decoding of RV32/64M insn
819cbda target/riscv: Remove shift and slt insn manual decoding
6de3ea8 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
ac209c8 target/riscv: Move gen_arith_imm() decoding into trans_* functions
e6c57d7 target/riscv: Remove manual decoding from gen_store()
6e32a22 target/riscv: Remove manual decoding from gen_load()
fc2febc target/riscv: Remove manual decoding from gen_branch()
24ffd31 target/riscv: Remove gen_jalr()
ecb0b58 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7ce9e53 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
2cf65e2 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
ae6f285 target/riscv: Convert RV priv insns to decodetree
9c31e4f target/riscv: Convert RV64D insns to decodetree
5e73a24 target/riscv: Convert RV32D insns to decodetree
62b38c1 target/riscv: Convert RV64F insns to decodetree
4a7251e target/riscv: Convert RV32F insns to decodetree
cff510f target/riscv: Convert RV64A insns to decodetree
180d186 target/riscv: Convert RV32A insns to decodetree
bf22444 target/riscv: Convert RVXM insns to decodetree
a324468 target/riscv: Convert RVXI csr insns to decodetree
e4cb753 target/riscv: Convert RVXI fence insns to decodetree
851fff8 target/riscv: Convert RVXI arithmetic insns to decodetree
b806b20 target/riscv: Convert RV64I load/store insns to decodetree
ca745cb target/riscv: Convert RV32I load/store insns to decodetree
850511d target/riscv: Convert RVXI branch insns to decodetree
812f4fb target/riscv: Activate decodetree and implemnt LUI & AUIPC
40371d8 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 40371d802c19 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 812f4fb0e12e (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 850511d47ca4 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit ca745cbfa171 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit b806b20de230 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 851fff88fc5c (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit e4cb753f663e (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit a3244685ea17 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit bf2244449406 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 180d186fed80 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit cff510f04bf0 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 4a7251e72df0 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 62b38c11f073 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 5e73a245d405 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 9c31e4fb05a1 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit ae6f285826c0 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 2cf65e25d0a3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 7ce9e53aaeab (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit ecb0b58ef290 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 24ffd31f260b (target/riscv: Remove gen_jalr())
21/35 Checking commit fc2febc2de23 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 6e32a22cc246 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit e6c57d70f019 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit ac209c850750 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 6de3ea822041 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 819cbda0d1bf (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit ce11a2d977ab (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 925f796a5d0f (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit e168704ef0df (target/riscv: Remove gen_system())
30/35 Checking commit 39402d7cf28f (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit e17dd909d236 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 82081bebf6d0 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 2a407bf78c52 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 89632ce033c5 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b5d179aad0b5 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:11 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:11 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
b5d179a target/riscv: Remaining rvc insn reuse 32 bit translators
89632ce target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
2a407bf target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
82081be target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
e17dd90 target/riscv: Convert @cs_2 insns to share translation functions
39402d7 target/riscv: Remove decode_RV32_64G()
e168704 target/riscv: Remove gen_system()
925f796 target/riscv: Rename trans_arith to gen_arith
ce11a2d target/riscv: Remove manual decoding of RV32/64M insn
819cbda target/riscv: Remove shift and slt insn manual decoding
6de3ea8 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
ac209c8 target/riscv: Move gen_arith_imm() decoding into trans_* functions
e6c57d7 target/riscv: Remove manual decoding from gen_store()
6e32a22 target/riscv: Remove manual decoding from gen_load()
fc2febc target/riscv: Remove manual decoding from gen_branch()
24ffd31 target/riscv: Remove gen_jalr()
ecb0b58 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7ce9e53 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
2cf65e2 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
ae6f285 target/riscv: Convert RV priv insns to decodetree
9c31e4f target/riscv: Convert RV64D insns to decodetree
5e73a24 target/riscv: Convert RV32D insns to decodetree
62b38c1 target/riscv: Convert RV64F insns to decodetree
4a7251e target/riscv: Convert RV32F insns to decodetree
cff510f target/riscv: Convert RV64A insns to decodetree
180d186 target/riscv: Convert RV32A insns to decodetree
bf22444 target/riscv: Convert RVXM insns to decodetree
a324468 target/riscv: Convert RVXI csr insns to decodetree
e4cb753 target/riscv: Convert RVXI fence insns to decodetree
851fff8 target/riscv: Convert RVXI arithmetic insns to decodetree
b806b20 target/riscv: Convert RV64I load/store insns to decodetree
ca745cb target/riscv: Convert RV32I load/store insns to decodetree
850511d target/riscv: Convert RVXI branch insns to decodetree
812f4fb target/riscv: Activate decodetree and implemnt LUI & AUIPC
40371d8 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 40371d802c19 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 812f4fb0e12e (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 850511d47ca4 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit ca745cbfa171 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit b806b20de230 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 851fff88fc5c (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit e4cb753f663e (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit a3244685ea17 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit bf2244449406 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 180d186fed80 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit cff510f04bf0 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 4a7251e72df0 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 62b38c11f073 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 5e73a245d405 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 9c31e4fb05a1 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit ae6f285826c0 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 2cf65e25d0a3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 7ce9e53aaeab (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit ecb0b58ef290 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 24ffd31f260b (target/riscv: Remove gen_jalr())
21/35 Checking commit fc2febc2de23 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 6e32a22cc246 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit e6c57d70f019 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit ac209c850750 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 6de3ea822041 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 819cbda0d1bf (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit ce11a2d977ab (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 925f796a5d0f (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit e168704ef0df (target/riscv: Remove gen_system())
30/35 Checking commit 39402d7cf28f (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit e17dd909d236 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 82081bebf6d0 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 2a407bf78c52 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 89632ce033c5 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit b5d179aad0b5 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:12 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:12 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
a3cbe72 target/riscv: Remaining rvc insn reuse 32 bit translators
9afdd3e target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
b915423 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
4e79caa target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
0121b65 target/riscv: Convert @cs_2 insns to share translation functions
b7a4ef9 target/riscv: Remove decode_RV32_64G()
510bbe8 target/riscv: Remove gen_system()
f1331f5 target/riscv: Rename trans_arith to gen_arith
b276b8c target/riscv: Remove manual decoding of RV32/64M insn
d445e37 target/riscv: Remove shift and slt insn manual decoding
46bfc39 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
9db1077 target/riscv: Move gen_arith_imm() decoding into trans_* functions
72b35f4 target/riscv: Remove manual decoding from gen_store()
84c26d7 target/riscv: Remove manual decoding from gen_load()
4779d13 target/riscv: Remove manual decoding from gen_branch()
5870468 target/riscv: Remove gen_jalr()
fb02c0c target/riscv: Convert quadrant 2 of RVXC insns to decodetree
64793c9 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
5e210d0 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8d3d945 target/riscv: Convert RV priv insns to decodetree
d3a238f target/riscv: Convert RV64D insns to decodetree
982f175 target/riscv: Convert RV32D insns to decodetree
3fe1356 target/riscv: Convert RV64F insns to decodetree
d231c90 target/riscv: Convert RV32F insns to decodetree
82b118b target/riscv: Convert RV64A insns to decodetree
32b39a2 target/riscv: Convert RV32A insns to decodetree
d6f6f2b target/riscv: Convert RVXM insns to decodetree
34094a1 target/riscv: Convert RVXI csr insns to decodetree
6995f94 target/riscv: Convert RVXI fence insns to decodetree
0a445ed target/riscv: Convert RVXI arithmetic insns to decodetree
3566ff3 target/riscv: Convert RV64I load/store insns to decodetree
9f47cca target/riscv: Convert RV32I load/store insns to decodetree
b28fd8e target/riscv: Convert RVXI branch insns to decodetree
dde69a0 target/riscv: Activate decodetree and implemnt LUI & AUIPC
3e3b3d7 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 3e3b3d7bd110 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit dde69a04bec7 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit b28fd8eb6190 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 9f47cca20003 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 3566ff341f1c (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 0a445ed42134 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 6995f940028d (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 34094a1d0d03 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit d6f6f2bb7f86 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 32b39a20f7d1 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 82b118b87c5f (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit d231c90bc0fb (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 3fe1356adf7d (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 982f17583919 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit d3a238f2f0a7 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8d3d945cdcc3 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 5e210d0cb62b (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 64793c940e59 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit fb02c0c0753e (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 58704684980a (target/riscv: Remove gen_jalr())
21/35 Checking commit 4779d1354543 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 84c26d735452 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 72b35f4f5e56 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 9db10777af3b (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 46bfc390d4dd (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit d445e37b121e (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit b276b8c471be (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit f1331f538b13 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 510bbe84104f (target/riscv: Remove gen_system())
30/35 Checking commit b7a4ef9b8a01 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 0121b6527d37 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 4e79caa2c455 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit b915423a7d63 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 9afdd3ec498e (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit a3cbe726d4e4 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:12 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:12 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
a3cbe72 target/riscv: Remaining rvc insn reuse 32 bit translators
9afdd3e target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
b915423 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
4e79caa target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
0121b65 target/riscv: Convert @cs_2 insns to share translation functions
b7a4ef9 target/riscv: Remove decode_RV32_64G()
510bbe8 target/riscv: Remove gen_system()
f1331f5 target/riscv: Rename trans_arith to gen_arith
b276b8c target/riscv: Remove manual decoding of RV32/64M insn
d445e37 target/riscv: Remove shift and slt insn manual decoding
46bfc39 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
9db1077 target/riscv: Move gen_arith_imm() decoding into trans_* functions
72b35f4 target/riscv: Remove manual decoding from gen_store()
84c26d7 target/riscv: Remove manual decoding from gen_load()
4779d13 target/riscv: Remove manual decoding from gen_branch()
5870468 target/riscv: Remove gen_jalr()
fb02c0c target/riscv: Convert quadrant 2 of RVXC insns to decodetree
64793c9 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
5e210d0 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8d3d945 target/riscv: Convert RV priv insns to decodetree
d3a238f target/riscv: Convert RV64D insns to decodetree
982f175 target/riscv: Convert RV32D insns to decodetree
3fe1356 target/riscv: Convert RV64F insns to decodetree
d231c90 target/riscv: Convert RV32F insns to decodetree
82b118b target/riscv: Convert RV64A insns to decodetree
32b39a2 target/riscv: Convert RV32A insns to decodetree
d6f6f2b target/riscv: Convert RVXM insns to decodetree
34094a1 target/riscv: Convert RVXI csr insns to decodetree
6995f94 target/riscv: Convert RVXI fence insns to decodetree
0a445ed target/riscv: Convert RVXI arithmetic insns to decodetree
3566ff3 target/riscv: Convert RV64I load/store insns to decodetree
9f47cca target/riscv: Convert RV32I load/store insns to decodetree
b28fd8e target/riscv: Convert RVXI branch insns to decodetree
dde69a0 target/riscv: Activate decodetree and implemnt LUI & AUIPC
3e3b3d7 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 3e3b3d7bd110 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit dde69a04bec7 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit b28fd8eb6190 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 9f47cca20003 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 3566ff341f1c (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 0a445ed42134 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 6995f940028d (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 34094a1d0d03 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit d6f6f2bb7f86 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 32b39a20f7d1 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 82b118b87c5f (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit d231c90bc0fb (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 3fe1356adf7d (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 982f17583919 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit d3a238f2f0a7 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8d3d945cdcc3 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 5e210d0cb62b (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 64793c940e59 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit fb02c0c0753e (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 58704684980a (target/riscv: Remove gen_jalr())
21/35 Checking commit 4779d1354543 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 84c26d735452 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 72b35f4f5e56 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 9db10777af3b (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 46bfc390d4dd (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit d445e37b121e (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit b276b8c471be (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit f1331f538b13 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 510bbe84104f (target/riscv: Remove gen_system())
30/35 Checking commit b7a4ef9b8a01 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 0121b6527d37 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 4e79caa2c455 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit b915423a7d63 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 9afdd3ec498e (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit a3cbe726d4e4 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:15 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:15 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
0b8b161ee9 target/riscv: Remaining rvc insn reuse 32 bit translators
c572ee3c49 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
4f6990dd63 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
978ba13fad target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
6950276f0b target/riscv: Convert @cs_2 insns to share translation functions
6800d2f774 target/riscv: Remove decode_RV32_64G()
52e9366cfe target/riscv: Remove gen_system()
ae15272edc target/riscv: Rename trans_arith to gen_arith
44cb4f52be target/riscv: Remove manual decoding of RV32/64M insn
061c8f4edb target/riscv: Remove shift and slt insn manual decoding
38903407bb target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
0e4b69edcc target/riscv: Move gen_arith_imm() decoding into trans_* functions
68786b751d target/riscv: Remove manual decoding from gen_store()
9724ef941d target/riscv: Remove manual decoding from gen_load()
8b7259ecd2 target/riscv: Remove manual decoding from gen_branch()
e1a89f8fa3 target/riscv: Remove gen_jalr()
3997202158 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
ef701a0633 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
ffedb662db target/riscv: Convert quadrant 0 of RVXC insns to decodetree
80efd9e0d7 target/riscv: Convert RV priv insns to decodetree
3936560c24 target/riscv: Convert RV64D insns to decodetree
b2cfe9c051 target/riscv: Convert RV32D insns to decodetree
ef187b9c6f target/riscv: Convert RV64F insns to decodetree
549ce3e937 target/riscv: Convert RV32F insns to decodetree
f12ae436a4 target/riscv: Convert RV64A insns to decodetree
d2d3a0129f target/riscv: Convert RV32A insns to decodetree
f2a1e72600 target/riscv: Convert RVXM insns to decodetree
123c4ce4d6 target/riscv: Convert RVXI csr insns to decodetree
0a7cb7b951 target/riscv: Convert RVXI fence insns to decodetree
23c598c7e8 target/riscv: Convert RVXI arithmetic insns to decodetree
251bd0658a target/riscv: Convert RV64I load/store insns to decodetree
b950690c00 target/riscv: Convert RV32I load/store insns to decodetree
c7c44352c5 target/riscv: Convert RVXI branch insns to decodetree
b9b322714c target/riscv: Activate decodetree and implemnt LUI & AUIPC
0b8dcc589a target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 0b8dcc589a0b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b9b322714c83 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit c7c44352c524 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit b950690c000c (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 251bd0658ab8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 23c598c7e86f (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 0a7cb7b951af (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 123c4ce4d6bc (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f2a1e72600c7 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit d2d3a0129f2c (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f12ae436a4b8 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 549ce3e93706 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit ef187b9c6fc5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit b2cfe9c05116 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 3936560c24a0 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 80efd9e0d72c (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit ffedb662dbd3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit ef701a063304 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 399720215811 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit e1a89f8fa301 (target/riscv: Remove gen_jalr())
21/35 Checking commit 8b7259ecd231 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 9724ef941d6a (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 68786b751df4 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 0e4b69edcca1 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 38903407bb7e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 061c8f4edbef (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 44cb4f52be9b (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ae15272edc4d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 52e9366cfe73 (target/riscv: Remove gen_system())
30/35 Checking commit 6800d2f774c2 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 6950276f0be8 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 978ba13fad9b (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 4f6990dd63a1 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit c572ee3c49bf (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 0b8b161ee93a (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:15 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:15 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
0b8b161ee9 target/riscv: Remaining rvc insn reuse 32 bit translators
c572ee3c49 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
4f6990dd63 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
978ba13fad target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
6950276f0b target/riscv: Convert @cs_2 insns to share translation functions
6800d2f774 target/riscv: Remove decode_RV32_64G()
52e9366cfe target/riscv: Remove gen_system()
ae15272edc target/riscv: Rename trans_arith to gen_arith
44cb4f52be target/riscv: Remove manual decoding of RV32/64M insn
061c8f4edb target/riscv: Remove shift and slt insn manual decoding
38903407bb target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
0e4b69edcc target/riscv: Move gen_arith_imm() decoding into trans_* functions
68786b751d target/riscv: Remove manual decoding from gen_store()
9724ef941d target/riscv: Remove manual decoding from gen_load()
8b7259ecd2 target/riscv: Remove manual decoding from gen_branch()
e1a89f8fa3 target/riscv: Remove gen_jalr()
3997202158 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
ef701a0633 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
ffedb662db target/riscv: Convert quadrant 0 of RVXC insns to decodetree
80efd9e0d7 target/riscv: Convert RV priv insns to decodetree
3936560c24 target/riscv: Convert RV64D insns to decodetree
b2cfe9c051 target/riscv: Convert RV32D insns to decodetree
ef187b9c6f target/riscv: Convert RV64F insns to decodetree
549ce3e937 target/riscv: Convert RV32F insns to decodetree
f12ae436a4 target/riscv: Convert RV64A insns to decodetree
d2d3a0129f target/riscv: Convert RV32A insns to decodetree
f2a1e72600 target/riscv: Convert RVXM insns to decodetree
123c4ce4d6 target/riscv: Convert RVXI csr insns to decodetree
0a7cb7b951 target/riscv: Convert RVXI fence insns to decodetree
23c598c7e8 target/riscv: Convert RVXI arithmetic insns to decodetree
251bd0658a target/riscv: Convert RV64I load/store insns to decodetree
b950690c00 target/riscv: Convert RV32I load/store insns to decodetree
c7c44352c5 target/riscv: Convert RVXI branch insns to decodetree
b9b322714c target/riscv: Activate decodetree and implemnt LUI & AUIPC
0b8dcc589a target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 0b8dcc589a0b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b9b322714c83 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit c7c44352c524 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit b950690c000c (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 251bd0658ab8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 23c598c7e86f (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 0a7cb7b951af (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 123c4ce4d6bc (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f2a1e72600c7 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit d2d3a0129f2c (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f12ae436a4b8 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 549ce3e93706 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit ef187b9c6fc5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit b2cfe9c05116 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 3936560c24a0 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 80efd9e0d72c (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit ffedb662dbd3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit ef701a063304 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 399720215811 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit e1a89f8fa301 (target/riscv: Remove gen_jalr())
21/35 Checking commit 8b7259ecd231 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 9724ef941d6a (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 68786b751df4 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 0e4b69edcca1 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 38903407bb7e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 061c8f4edbef (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 44cb4f52be9b (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ae15272edc4d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 52e9366cfe73 (target/riscv: Remove gen_system())
30/35 Checking commit 6800d2f774c2 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 6950276f0be8 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 978ba13fad9b (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 4f6990dd63a1 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit c572ee3c49bf (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 0b8b161ee93a (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:15 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:15 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
0b8b161 target/riscv: Remaining rvc insn reuse 32 bit translators
c572ee3 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
4f6990d target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
978ba13 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
6950276 target/riscv: Convert @cs_2 insns to share translation functions
6800d2f target/riscv: Remove decode_RV32_64G()
52e9366 target/riscv: Remove gen_system()
ae15272 target/riscv: Rename trans_arith to gen_arith
44cb4f5 target/riscv: Remove manual decoding of RV32/64M insn
061c8f4 target/riscv: Remove shift and slt insn manual decoding
3890340 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
0e4b69e target/riscv: Move gen_arith_imm() decoding into trans_* functions
68786b7 target/riscv: Remove manual decoding from gen_store()
9724ef9 target/riscv: Remove manual decoding from gen_load()
8b7259e target/riscv: Remove manual decoding from gen_branch()
e1a89f8 target/riscv: Remove gen_jalr()
3997202 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
ef701a0 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
ffedb66 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
80efd9e target/riscv: Convert RV priv insns to decodetree
3936560 target/riscv: Convert RV64D insns to decodetree
b2cfe9c target/riscv: Convert RV32D insns to decodetree
ef187b9 target/riscv: Convert RV64F insns to decodetree
549ce3e target/riscv: Convert RV32F insns to decodetree
f12ae43 target/riscv: Convert RV64A insns to decodetree
d2d3a01 target/riscv: Convert RV32A insns to decodetree
f2a1e72 target/riscv: Convert RVXM insns to decodetree
123c4ce target/riscv: Convert RVXI csr insns to decodetree
0a7cb7b target/riscv: Convert RVXI fence insns to decodetree
23c598c target/riscv: Convert RVXI arithmetic insns to decodetree
251bd06 target/riscv: Convert RV64I load/store insns to decodetree
b950690 target/riscv: Convert RV32I load/store insns to decodetree
c7c4435 target/riscv: Convert RVXI branch insns to decodetree
b9b3227 target/riscv: Activate decodetree and implemnt LUI & AUIPC
0b8dcc5 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 0b8dcc589a0b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b9b322714c83 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit c7c44352c524 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit b950690c000c (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 251bd0658ab8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 23c598c7e86f (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 0a7cb7b951af (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 123c4ce4d6bc (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f2a1e72600c7 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit d2d3a0129f2c (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f12ae436a4b8 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 549ce3e93706 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit ef187b9c6fc5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit b2cfe9c05116 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 3936560c24a0 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 80efd9e0d72c (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit ffedb662dbd3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit ef701a063304 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 399720215811 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit e1a89f8fa301 (target/riscv: Remove gen_jalr())
21/35 Checking commit 8b7259ecd231 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 9724ef941d6a (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 68786b751df4 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 0e4b69edcca1 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 38903407bb7e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 061c8f4edbef (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 44cb4f52be9b (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ae15272edc4d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 52e9366cfe73 (target/riscv: Remove gen_system())
30/35 Checking commit 6800d2f774c2 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 6950276f0be8 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 978ba13fad9b (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 4f6990dd63a1 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit c572ee3c49bf (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 0b8b161ee93a (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:15 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:15 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
0b8b161 target/riscv: Remaining rvc insn reuse 32 bit translators
c572ee3 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
4f6990d target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
978ba13 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
6950276 target/riscv: Convert @cs_2 insns to share translation functions
6800d2f target/riscv: Remove decode_RV32_64G()
52e9366 target/riscv: Remove gen_system()
ae15272 target/riscv: Rename trans_arith to gen_arith
44cb4f5 target/riscv: Remove manual decoding of RV32/64M insn
061c8f4 target/riscv: Remove shift and slt insn manual decoding
3890340 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
0e4b69e target/riscv: Move gen_arith_imm() decoding into trans_* functions
68786b7 target/riscv: Remove manual decoding from gen_store()
9724ef9 target/riscv: Remove manual decoding from gen_load()
8b7259e target/riscv: Remove manual decoding from gen_branch()
e1a89f8 target/riscv: Remove gen_jalr()
3997202 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
ef701a0 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
ffedb66 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
80efd9e target/riscv: Convert RV priv insns to decodetree
3936560 target/riscv: Convert RV64D insns to decodetree
b2cfe9c target/riscv: Convert RV32D insns to decodetree
ef187b9 target/riscv: Convert RV64F insns to decodetree
549ce3e target/riscv: Convert RV32F insns to decodetree
f12ae43 target/riscv: Convert RV64A insns to decodetree
d2d3a01 target/riscv: Convert RV32A insns to decodetree
f2a1e72 target/riscv: Convert RVXM insns to decodetree
123c4ce target/riscv: Convert RVXI csr insns to decodetree
0a7cb7b target/riscv: Convert RVXI fence insns to decodetree
23c598c target/riscv: Convert RVXI arithmetic insns to decodetree
251bd06 target/riscv: Convert RV64I load/store insns to decodetree
b950690 target/riscv: Convert RV32I load/store insns to decodetree
c7c4435 target/riscv: Convert RVXI branch insns to decodetree
b9b3227 target/riscv: Activate decodetree and implemnt LUI & AUIPC
0b8dcc5 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 0b8dcc589a0b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b9b322714c83 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit c7c44352c524 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit b950690c000c (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 251bd0658ab8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 23c598c7e86f (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 0a7cb7b951af (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 123c4ce4d6bc (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f2a1e72600c7 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit d2d3a0129f2c (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f12ae436a4b8 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 549ce3e93706 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit ef187b9c6fc5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit b2cfe9c05116 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 3936560c24a0 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 80efd9e0d72c (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit ffedb662dbd3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit ef701a063304 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 399720215811 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit e1a89f8fa301 (target/riscv: Remove gen_jalr())
21/35 Checking commit 8b7259ecd231 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 9724ef941d6a (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 68786b751df4 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 0e4b69edcca1 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 38903407bb7e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 061c8f4edbef (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 44cb4f52be9b (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ae15272edc4d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 52e9366cfe73 (target/riscv: Remove gen_system())
30/35 Checking commit 6800d2f774c2 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 6950276f0be8 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 978ba13fad9b (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 4f6990dd63a1 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit c572ee3c49bf (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 0b8b161ee93a (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:18 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:18 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
* [new tag] patchew/20190131210851.9842-1-richard.henderson@linaro.org -> patchew/20190131210851.9842-1-richard.henderson@linaro.org
Switched to a new branch 'test'
8fbe349 target/riscv: Remaining rvc insn reuse 32 bit translators
24ac6df target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
a872fb0 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
b15e98a target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
8620f8c target/riscv: Convert @cs_2 insns to share translation functions
34fdff0 target/riscv: Remove decode_RV32_64G()
18fef41 target/riscv: Remove gen_system()
0c7096a target/riscv: Rename trans_arith to gen_arith
11b4396 target/riscv: Remove manual decoding of RV32/64M insn
03ea617 target/riscv: Remove shift and slt insn manual decoding
b9d345c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f9f6281 target/riscv: Move gen_arith_imm() decoding into trans_* functions
28988be target/riscv: Remove manual decoding from gen_store()
b227163 target/riscv: Remove manual decoding from gen_load()
2d9466d target/riscv: Remove manual decoding from gen_branch()
389dfb1 target/riscv: Remove gen_jalr()
015e21b target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f7599be target/riscv: Convert quadrant 1 of RVXC insns to decodetree
b43b908 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
9def3a0 target/riscv: Convert RV priv insns to decodetree
cb6a85c target/riscv: Convert RV64D insns to decodetree
de12358 target/riscv: Convert RV32D insns to decodetree
3637746 target/riscv: Convert RV64F insns to decodetree
f7f1cee target/riscv: Convert RV32F insns to decodetree
ff48f82 target/riscv: Convert RV64A insns to decodetree
59216b4 target/riscv: Convert RV32A insns to decodetree
ecd3e26 target/riscv: Convert RVXM insns to decodetree
f925ddf target/riscv: Convert RVXI csr insns to decodetree
0521076 target/riscv: Convert RVXI fence insns to decodetree
96ef5df target/riscv: Convert RVXI arithmetic insns to decodetree
720d36f target/riscv: Convert RV64I load/store insns to decodetree
4ca2a53 target/riscv: Convert RV32I load/store insns to decodetree
797e17e target/riscv: Convert RVXI branch insns to decodetree
5fe471c target/riscv: Activate decodetree and implemnt LUI & AUIPC
2f6484f target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 2f6484fc8b40 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 5fe471c8d889 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 797e17e309d8 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 4ca2a533ae0f (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 720d36fcb482 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 96ef5df64035 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 052107679d38 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit f925ddff48df (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit ecd3e263f4d3 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 59216b476599 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit ff48f827e32e (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit f7f1cee6bd8e (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 36377467f850 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit de1235869bc2 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit cb6a85c27a39 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 9def3a0b2d95 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit b43b9081a0f3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit f7599be1fd21 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 015e21b27bf7 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 389dfb149423 (target/riscv: Remove gen_jalr())
21/35 Checking commit 2d9466dce10a (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit b2271639923f (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 28988be5c3bc (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit f9f628120c9c (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit b9d345ca148a (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 03ea61736dc8 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 11b4396056a6 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 0c7096a8d646 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 18fef4163596 (target/riscv: Remove gen_system())
30/35 Checking commit 34fdff00d347 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 8620f8c0fe27 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit b15e98a2cb7b (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit a872fb08fd46 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 24ac6df1be53 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 8fbe34935f3c (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:18 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:18 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
* [new tag] patchew/20190131210851.9842-1-richard.henderson@linaro.org -> patchew/20190131210851.9842-1-richard.henderson@linaro.org
Switched to a new branch 'test'
8fbe349 target/riscv: Remaining rvc insn reuse 32 bit translators
24ac6df target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
a872fb0 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
b15e98a target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
8620f8c target/riscv: Convert @cs_2 insns to share translation functions
34fdff0 target/riscv: Remove decode_RV32_64G()
18fef41 target/riscv: Remove gen_system()
0c7096a target/riscv: Rename trans_arith to gen_arith
11b4396 target/riscv: Remove manual decoding of RV32/64M insn
03ea617 target/riscv: Remove shift and slt insn manual decoding
b9d345c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f9f6281 target/riscv: Move gen_arith_imm() decoding into trans_* functions
28988be target/riscv: Remove manual decoding from gen_store()
b227163 target/riscv: Remove manual decoding from gen_load()
2d9466d target/riscv: Remove manual decoding from gen_branch()
389dfb1 target/riscv: Remove gen_jalr()
015e21b target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f7599be target/riscv: Convert quadrant 1 of RVXC insns to decodetree
b43b908 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
9def3a0 target/riscv: Convert RV priv insns to decodetree
cb6a85c target/riscv: Convert RV64D insns to decodetree
de12358 target/riscv: Convert RV32D insns to decodetree
3637746 target/riscv: Convert RV64F insns to decodetree
f7f1cee target/riscv: Convert RV32F insns to decodetree
ff48f82 target/riscv: Convert RV64A insns to decodetree
59216b4 target/riscv: Convert RV32A insns to decodetree
ecd3e26 target/riscv: Convert RVXM insns to decodetree
f925ddf target/riscv: Convert RVXI csr insns to decodetree
0521076 target/riscv: Convert RVXI fence insns to decodetree
96ef5df target/riscv: Convert RVXI arithmetic insns to decodetree
720d36f target/riscv: Convert RV64I load/store insns to decodetree
4ca2a53 target/riscv: Convert RV32I load/store insns to decodetree
797e17e target/riscv: Convert RVXI branch insns to decodetree
5fe471c target/riscv: Activate decodetree and implemnt LUI & AUIPC
2f6484f target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 2f6484fc8b40 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 5fe471c8d889 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 797e17e309d8 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 4ca2a533ae0f (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 720d36fcb482 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 96ef5df64035 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 052107679d38 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit f925ddff48df (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit ecd3e263f4d3 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 59216b476599 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit ff48f827e32e (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit f7f1cee6bd8e (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 36377467f850 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit de1235869bc2 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit cb6a85c27a39 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 9def3a0b2d95 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit b43b9081a0f3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit f7599be1fd21 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 015e21b27bf7 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 389dfb149423 (target/riscv: Remove gen_jalr())
21/35 Checking commit 2d9466dce10a (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit b2271639923f (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 28988be5c3bc (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit f9f628120c9c (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit b9d345ca148a (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 03ea61736dc8 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 11b4396056a6 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 0c7096a8d646 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 18fef4163596 (target/riscv: Remove gen_system())
30/35 Checking commit 34fdff00d347 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 8620f8c0fe27 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit b15e98a2cb7b (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit a872fb08fd46 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 24ac6df1be53 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 8fbe34935f3c (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:19 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:19 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
0b8b161 target/riscv: Remaining rvc insn reuse 32 bit translators
c572ee3 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
4f6990d target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
978ba13 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
6950276 target/riscv: Convert @cs_2 insns to share translation functions
6800d2f target/riscv: Remove decode_RV32_64G()
52e9366 target/riscv: Remove gen_system()
ae15272 target/riscv: Rename trans_arith to gen_arith
44cb4f5 target/riscv: Remove manual decoding of RV32/64M insn
061c8f4 target/riscv: Remove shift and slt insn manual decoding
3890340 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
0e4b69e target/riscv: Move gen_arith_imm() decoding into trans_* functions
68786b7 target/riscv: Remove manual decoding from gen_store()
9724ef9 target/riscv: Remove manual decoding from gen_load()
8b7259e target/riscv: Remove manual decoding from gen_branch()
e1a89f8 target/riscv: Remove gen_jalr()
3997202 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
ef701a0 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
ffedb66 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
80efd9e target/riscv: Convert RV priv insns to decodetree
3936560 target/riscv: Convert RV64D insns to decodetree
b2cfe9c target/riscv: Convert RV32D insns to decodetree
ef187b9 target/riscv: Convert RV64F insns to decodetree
549ce3e target/riscv: Convert RV32F insns to decodetree
f12ae43 target/riscv: Convert RV64A insns to decodetree
d2d3a01 target/riscv: Convert RV32A insns to decodetree
f2a1e72 target/riscv: Convert RVXM insns to decodetree
123c4ce target/riscv: Convert RVXI csr insns to decodetree
0a7cb7b target/riscv: Convert RVXI fence insns to decodetree
23c598c target/riscv: Convert RVXI arithmetic insns to decodetree
251bd06 target/riscv: Convert RV64I load/store insns to decodetree
b950690 target/riscv: Convert RV32I load/store insns to decodetree
c7c4435 target/riscv: Convert RVXI branch insns to decodetree
b9b3227 target/riscv: Activate decodetree and implemnt LUI & AUIPC
0b8dcc5 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 0b8dcc589a0b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b9b322714c83 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit c7c44352c524 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit b950690c000c (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 251bd0658ab8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 23c598c7e86f (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 0a7cb7b951af (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 123c4ce4d6bc (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f2a1e72600c7 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit d2d3a0129f2c (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f12ae436a4b8 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 549ce3e93706 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit ef187b9c6fc5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit b2cfe9c05116 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 3936560c24a0 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 80efd9e0d72c (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit ffedb662dbd3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit ef701a063304 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 399720215811 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit e1a89f8fa301 (target/riscv: Remove gen_jalr())
21/35 Checking commit 8b7259ecd231 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 9724ef941d6a (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 68786b751df4 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 0e4b69edcca1 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 38903407bb7e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 061c8f4edbef (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 44cb4f52be9b (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ae15272edc4d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 52e9366cfe73 (target/riscv: Remove gen_system())
30/35 Checking commit 6800d2f774c2 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 6950276f0be8 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 978ba13fad9b (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 4f6990dd63a1 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit c572ee3c49bf (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 0b8b161ee93a (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:19 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:19 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
0b8b161 target/riscv: Remaining rvc insn reuse 32 bit translators
c572ee3 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
4f6990d target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
978ba13 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
6950276 target/riscv: Convert @cs_2 insns to share translation functions
6800d2f target/riscv: Remove decode_RV32_64G()
52e9366 target/riscv: Remove gen_system()
ae15272 target/riscv: Rename trans_arith to gen_arith
44cb4f5 target/riscv: Remove manual decoding of RV32/64M insn
061c8f4 target/riscv: Remove shift and slt insn manual decoding
3890340 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
0e4b69e target/riscv: Move gen_arith_imm() decoding into trans_* functions
68786b7 target/riscv: Remove manual decoding from gen_store()
9724ef9 target/riscv: Remove manual decoding from gen_load()
8b7259e target/riscv: Remove manual decoding from gen_branch()
e1a89f8 target/riscv: Remove gen_jalr()
3997202 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
ef701a0 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
ffedb66 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
80efd9e target/riscv: Convert RV priv insns to decodetree
3936560 target/riscv: Convert RV64D insns to decodetree
b2cfe9c target/riscv: Convert RV32D insns to decodetree
ef187b9 target/riscv: Convert RV64F insns to decodetree
549ce3e target/riscv: Convert RV32F insns to decodetree
f12ae43 target/riscv: Convert RV64A insns to decodetree
d2d3a01 target/riscv: Convert RV32A insns to decodetree
f2a1e72 target/riscv: Convert RVXM insns to decodetree
123c4ce target/riscv: Convert RVXI csr insns to decodetree
0a7cb7b target/riscv: Convert RVXI fence insns to decodetree
23c598c target/riscv: Convert RVXI arithmetic insns to decodetree
251bd06 target/riscv: Convert RV64I load/store insns to decodetree
b950690 target/riscv: Convert RV32I load/store insns to decodetree
c7c4435 target/riscv: Convert RVXI branch insns to decodetree
b9b3227 target/riscv: Activate decodetree and implemnt LUI & AUIPC
0b8dcc5 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 0b8dcc589a0b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b9b322714c83 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit c7c44352c524 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit b950690c000c (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 251bd0658ab8 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 23c598c7e86f (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 0a7cb7b951af (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 123c4ce4d6bc (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f2a1e72600c7 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit d2d3a0129f2c (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f12ae436a4b8 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 549ce3e93706 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit ef187b9c6fc5 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit b2cfe9c05116 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 3936560c24a0 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 80efd9e0d72c (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit ffedb662dbd3 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit ef701a063304 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 399720215811 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit e1a89f8fa301 (target/riscv: Remove gen_jalr())
21/35 Checking commit 8b7259ecd231 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 9724ef941d6a (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 68786b751df4 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 0e4b69edcca1 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 38903407bb7e (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 061c8f4edbef (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 44cb4f52be9b (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit ae15272edc4d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 52e9366cfe73 (target/riscv: Remove gen_system())
30/35 Checking commit 6800d2f774c2 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 6950276f0be8 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 978ba13fad9b (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 4f6990dd63a1 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit c572ee3c49bf (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 0b8b161ee93a (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:20 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:20 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
5d3e748344 target/riscv: Remaining rvc insn reuse 32 bit translators
4ebbf1dcb0 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
d254063f14 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
aa3dbf3a29 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
a3eff7f3ed target/riscv: Convert @cs_2 insns to share translation functions
f7b24d5062 target/riscv: Remove decode_RV32_64G()
cbb2c77bce target/riscv: Remove gen_system()
3bbe000ac1 target/riscv: Rename trans_arith to gen_arith
41b7b724e1 target/riscv: Remove manual decoding of RV32/64M insn
8c5199bde1 target/riscv: Remove shift and slt insn manual decoding
3f525d4302 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
8949ae2959 target/riscv: Move gen_arith_imm() decoding into trans_* functions
0269cfffef target/riscv: Remove manual decoding from gen_store()
98e5879319 target/riscv: Remove manual decoding from gen_load()
a02ae5f469 target/riscv: Remove manual decoding from gen_branch()
fefcf6d2fb target/riscv: Remove gen_jalr()
01532a82e7 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
d232ba560a target/riscv: Convert quadrant 1 of RVXC insns to decodetree
165d8337fa target/riscv: Convert quadrant 0 of RVXC insns to decodetree
25c307af64 target/riscv: Convert RV priv insns to decodetree
511cb46131 target/riscv: Convert RV64D insns to decodetree
62ffbad8f1 target/riscv: Convert RV32D insns to decodetree
8caabe5e65 target/riscv: Convert RV64F insns to decodetree
20004c0268 target/riscv: Convert RV32F insns to decodetree
38300733ef target/riscv: Convert RV64A insns to decodetree
bde575d56d target/riscv: Convert RV32A insns to decodetree
d37bad2de8 target/riscv: Convert RVXM insns to decodetree
0c9508a7ec target/riscv: Convert RVXI csr insns to decodetree
a6b3d65e3e target/riscv: Convert RVXI fence insns to decodetree
1e1292029e target/riscv: Convert RVXI arithmetic insns to decodetree
de7f337b02 target/riscv: Convert RV64I load/store insns to decodetree
2a2ed84b3c target/riscv: Convert RV32I load/store insns to decodetree
eb157fbcca target/riscv: Convert RVXI branch insns to decodetree
56bb22ad3e target/riscv: Activate decodetree and implemnt LUI & AUIPC
b6c4484f90 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit b6c4484f903d (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 56bb22ad3e17 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit eb157fbccad3 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 2a2ed84b3ca7 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit de7f337b0271 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 1e1292029e37 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit a6b3d65e3e38 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 0c9508a7ec9b (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit d37bad2de864 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit bde575d56df6 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 38300733ef03 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 20004c02680b (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 8caabe5e6513 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 62ffbad8f168 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 511cb461313f (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 25c307af643b (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 165d8337fac5 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit d232ba560abf (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 01532a82e755 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit fefcf6d2fb01 (target/riscv: Remove gen_jalr())
21/35 Checking commit a02ae5f4694e (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 98e5879319ca (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 0269cfffef18 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 8949ae2959ea (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 3f525d4302db (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 8c5199bde10b (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 41b7b724e122 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 3bbe000ac102 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit cbb2c77bce3c (target/riscv: Remove gen_system())
30/35 Checking commit f7b24d5062da (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit a3eff7f3ed3e (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit aa3dbf3a29e8 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit d254063f1463 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 4ebbf1dcb057 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 5d3e748344c1 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:20 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:20 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
5d3e748344 target/riscv: Remaining rvc insn reuse 32 bit translators
4ebbf1dcb0 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
d254063f14 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
aa3dbf3a29 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
a3eff7f3ed target/riscv: Convert @cs_2 insns to share translation functions
f7b24d5062 target/riscv: Remove decode_RV32_64G()
cbb2c77bce target/riscv: Remove gen_system()
3bbe000ac1 target/riscv: Rename trans_arith to gen_arith
41b7b724e1 target/riscv: Remove manual decoding of RV32/64M insn
8c5199bde1 target/riscv: Remove shift and slt insn manual decoding
3f525d4302 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
8949ae2959 target/riscv: Move gen_arith_imm() decoding into trans_* functions
0269cfffef target/riscv: Remove manual decoding from gen_store()
98e5879319 target/riscv: Remove manual decoding from gen_load()
a02ae5f469 target/riscv: Remove manual decoding from gen_branch()
fefcf6d2fb target/riscv: Remove gen_jalr()
01532a82e7 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
d232ba560a target/riscv: Convert quadrant 1 of RVXC insns to decodetree
165d8337fa target/riscv: Convert quadrant 0 of RVXC insns to decodetree
25c307af64 target/riscv: Convert RV priv insns to decodetree
511cb46131 target/riscv: Convert RV64D insns to decodetree
62ffbad8f1 target/riscv: Convert RV32D insns to decodetree
8caabe5e65 target/riscv: Convert RV64F insns to decodetree
20004c0268 target/riscv: Convert RV32F insns to decodetree
38300733ef target/riscv: Convert RV64A insns to decodetree
bde575d56d target/riscv: Convert RV32A insns to decodetree
d37bad2de8 target/riscv: Convert RVXM insns to decodetree
0c9508a7ec target/riscv: Convert RVXI csr insns to decodetree
a6b3d65e3e target/riscv: Convert RVXI fence insns to decodetree
1e1292029e target/riscv: Convert RVXI arithmetic insns to decodetree
de7f337b02 target/riscv: Convert RV64I load/store insns to decodetree
2a2ed84b3c target/riscv: Convert RV32I load/store insns to decodetree
eb157fbcca target/riscv: Convert RVXI branch insns to decodetree
56bb22ad3e target/riscv: Activate decodetree and implemnt LUI & AUIPC
b6c4484f90 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit b6c4484f903d (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 56bb22ad3e17 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit eb157fbccad3 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 2a2ed84b3ca7 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit de7f337b0271 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 1e1292029e37 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit a6b3d65e3e38 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 0c9508a7ec9b (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit d37bad2de864 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit bde575d56df6 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 38300733ef03 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 20004c02680b (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 8caabe5e6513 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 62ffbad8f168 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 511cb461313f (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 25c307af643b (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 165d8337fac5 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit d232ba560abf (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 01532a82e755 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit fefcf6d2fb01 (target/riscv: Remove gen_jalr())
21/35 Checking commit a02ae5f4694e (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 98e5879319ca (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 0269cfffef18 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 8949ae2959ea (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 3f525d4302db (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 8c5199bde10b (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 41b7b724e122 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 3bbe000ac102 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit cbb2c77bce3c (target/riscv: Remove gen_system())
30/35 Checking commit f7b24d5062da (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit a3eff7f3ed3e (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit aa3dbf3a29e8 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit d254063f1463 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 4ebbf1dcb057 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 5d3e748344c1 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:22 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:22 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
ed5d29b4e2 target/riscv: Remaining rvc insn reuse 32 bit translators
b54031a6e1 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
9b963a191d target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
eb5cc3d89f target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
f31df48270 target/riscv: Convert @cs_2 insns to share translation functions
84991598cd target/riscv: Remove decode_RV32_64G()
3ac75b04e9 target/riscv: Remove gen_system()
28b70192fe target/riscv: Rename trans_arith to gen_arith
c69cef8906 target/riscv: Remove manual decoding of RV32/64M insn
0fee6c7778 target/riscv: Remove shift and slt insn manual decoding
3e8a05f65c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2805954f69 target/riscv: Move gen_arith_imm() decoding into trans_* functions
4ca0f7208f target/riscv: Remove manual decoding from gen_store()
bba5eb03d7 target/riscv: Remove manual decoding from gen_load()
2382078c37 target/riscv: Remove manual decoding from gen_branch()
51720e7871 target/riscv: Remove gen_jalr()
76fe77374a target/riscv: Convert quadrant 2 of RVXC insns to decodetree
cbdbfe4ce6 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
a845ad9167 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
4757f887d3 target/riscv: Convert RV priv insns to decodetree
a45dc64b14 target/riscv: Convert RV64D insns to decodetree
81d433a355 target/riscv: Convert RV32D insns to decodetree
a2817b828e target/riscv: Convert RV64F insns to decodetree
a4b3aa5113 target/riscv: Convert RV32F insns to decodetree
f571c731a1 target/riscv: Convert RV64A insns to decodetree
3099ed9f2a target/riscv: Convert RV32A insns to decodetree
e5cff571cf target/riscv: Convert RVXM insns to decodetree
3e8796163e target/riscv: Convert RVXI csr insns to decodetree
a9ff2a19cb target/riscv: Convert RVXI fence insns to decodetree
fc1d4e4b6f target/riscv: Convert RVXI arithmetic insns to decodetree
40eb746234 target/riscv: Convert RV64I load/store insns to decodetree
18be721131 target/riscv: Convert RV32I load/store insns to decodetree
3a4a0f26ab target/riscv: Convert RVXI branch insns to decodetree
b44b4cc800 target/riscv: Activate decodetree and implemnt LUI & AUIPC
257d7a3545 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 257d7a3545e4 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b44b4cc80078 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 3a4a0f26abd1 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 18be72113172 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 40eb746234ae (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit fc1d4e4b6fdc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit a9ff2a19cbb4 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 3e8796163e96 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit e5cff571cf52 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 3099ed9f2afe (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f571c731a1cf (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit a4b3aa51137d (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit a2817b828ef7 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 81d433a3555c (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit a45dc64b147c (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 4757f887d39f (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit a845ad916796 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit cbdbfe4ce623 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 76fe77374a60 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 51720e787149 (target/riscv: Remove gen_jalr())
21/35 Checking commit 2382078c37bb (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit bba5eb03d70f (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 4ca0f7208f9f (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 2805954f69ea (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 3e8a05f65cb5 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 0fee6c777814 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit c69cef8906b7 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 28b70192feb3 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 3ac75b04e92d (target/riscv: Remove gen_system())
30/35 Checking commit 84991598cd17 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit f31df482709c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit eb5cc3d89f71 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 9b963a191d7b (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit b54031a6e1c5 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit ed5d29b4e2b6 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:22 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:22 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
ed5d29b4e2 target/riscv: Remaining rvc insn reuse 32 bit translators
b54031a6e1 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
9b963a191d target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
eb5cc3d89f target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
f31df48270 target/riscv: Convert @cs_2 insns to share translation functions
84991598cd target/riscv: Remove decode_RV32_64G()
3ac75b04e9 target/riscv: Remove gen_system()
28b70192fe target/riscv: Rename trans_arith to gen_arith
c69cef8906 target/riscv: Remove manual decoding of RV32/64M insn
0fee6c7778 target/riscv: Remove shift and slt insn manual decoding
3e8a05f65c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2805954f69 target/riscv: Move gen_arith_imm() decoding into trans_* functions
4ca0f7208f target/riscv: Remove manual decoding from gen_store()
bba5eb03d7 target/riscv: Remove manual decoding from gen_load()
2382078c37 target/riscv: Remove manual decoding from gen_branch()
51720e7871 target/riscv: Remove gen_jalr()
76fe77374a target/riscv: Convert quadrant 2 of RVXC insns to decodetree
cbdbfe4ce6 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
a845ad9167 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
4757f887d3 target/riscv: Convert RV priv insns to decodetree
a45dc64b14 target/riscv: Convert RV64D insns to decodetree
81d433a355 target/riscv: Convert RV32D insns to decodetree
a2817b828e target/riscv: Convert RV64F insns to decodetree
a4b3aa5113 target/riscv: Convert RV32F insns to decodetree
f571c731a1 target/riscv: Convert RV64A insns to decodetree
3099ed9f2a target/riscv: Convert RV32A insns to decodetree
e5cff571cf target/riscv: Convert RVXM insns to decodetree
3e8796163e target/riscv: Convert RVXI csr insns to decodetree
a9ff2a19cb target/riscv: Convert RVXI fence insns to decodetree
fc1d4e4b6f target/riscv: Convert RVXI arithmetic insns to decodetree
40eb746234 target/riscv: Convert RV64I load/store insns to decodetree
18be721131 target/riscv: Convert RV32I load/store insns to decodetree
3a4a0f26ab target/riscv: Convert RVXI branch insns to decodetree
b44b4cc800 target/riscv: Activate decodetree and implemnt LUI & AUIPC
257d7a3545 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 257d7a3545e4 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b44b4cc80078 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 3a4a0f26abd1 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 18be72113172 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 40eb746234ae (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit fc1d4e4b6fdc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit a9ff2a19cbb4 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 3e8796163e96 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit e5cff571cf52 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 3099ed9f2afe (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f571c731a1cf (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit a4b3aa51137d (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit a2817b828ef7 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 81d433a3555c (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit a45dc64b147c (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 4757f887d39f (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit a845ad916796 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit cbdbfe4ce623 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 76fe77374a60 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 51720e787149 (target/riscv: Remove gen_jalr())
21/35 Checking commit 2382078c37bb (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit bba5eb03d70f (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 4ca0f7208f9f (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 2805954f69ea (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 3e8a05f65cb5 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 0fee6c777814 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit c69cef8906b7 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 28b70192feb3 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 3ac75b04e92d (target/riscv: Remove gen_system())
30/35 Checking commit 84991598cd17 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit f31df482709c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit eb5cc3d89f71 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 9b963a191d7b (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit b54031a6e1c5 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit ed5d29b4e2b6 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:23 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:23 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
ed5d29b target/riscv: Remaining rvc insn reuse 32 bit translators
b54031a target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
9b963a1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
eb5cc3d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
f31df48 target/riscv: Convert @cs_2 insns to share translation functions
8499159 target/riscv: Remove decode_RV32_64G()
3ac75b0 target/riscv: Remove gen_system()
28b7019 target/riscv: Rename trans_arith to gen_arith
c69cef8 target/riscv: Remove manual decoding of RV32/64M insn
0fee6c7 target/riscv: Remove shift and slt insn manual decoding
3e8a05f target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2805954 target/riscv: Move gen_arith_imm() decoding into trans_* functions
4ca0f72 target/riscv: Remove manual decoding from gen_store()
bba5eb0 target/riscv: Remove manual decoding from gen_load()
2382078 target/riscv: Remove manual decoding from gen_branch()
51720e7 target/riscv: Remove gen_jalr()
76fe773 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
cbdbfe4 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
a845ad9 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
4757f88 target/riscv: Convert RV priv insns to decodetree
a45dc64 target/riscv: Convert RV64D insns to decodetree
81d433a target/riscv: Convert RV32D insns to decodetree
a2817b8 target/riscv: Convert RV64F insns to decodetree
a4b3aa5 target/riscv: Convert RV32F insns to decodetree
f571c73 target/riscv: Convert RV64A insns to decodetree
3099ed9 target/riscv: Convert RV32A insns to decodetree
e5cff57 target/riscv: Convert RVXM insns to decodetree
3e87961 target/riscv: Convert RVXI csr insns to decodetree
a9ff2a1 target/riscv: Convert RVXI fence insns to decodetree
fc1d4e4 target/riscv: Convert RVXI arithmetic insns to decodetree
40eb746 target/riscv: Convert RV64I load/store insns to decodetree
18be721 target/riscv: Convert RV32I load/store insns to decodetree
3a4a0f2 target/riscv: Convert RVXI branch insns to decodetree
b44b4cc target/riscv: Activate decodetree and implemnt LUI & AUIPC
257d7a3 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 257d7a3545e4 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b44b4cc80078 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 3a4a0f26abd1 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 18be72113172 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 40eb746234ae (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit fc1d4e4b6fdc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit a9ff2a19cbb4 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 3e8796163e96 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit e5cff571cf52 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 3099ed9f2afe (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f571c731a1cf (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit a4b3aa51137d (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit a2817b828ef7 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 81d433a3555c (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit a45dc64b147c (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 4757f887d39f (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit a845ad916796 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit cbdbfe4ce623 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 76fe77374a60 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 51720e787149 (target/riscv: Remove gen_jalr())
21/35 Checking commit 2382078c37bb (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit bba5eb03d70f (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 4ca0f7208f9f (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 2805954f69ea (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 3e8a05f65cb5 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 0fee6c777814 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit c69cef8906b7 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 28b70192feb3 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 3ac75b04e92d (target/riscv: Remove gen_system())
30/35 Checking commit 84991598cd17 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit f31df482709c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit eb5cc3d89f71 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 9b963a191d7b (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit b54031a6e1c5 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit ed5d29b4e2b6 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:23 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:23 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
ed5d29b target/riscv: Remaining rvc insn reuse 32 bit translators
b54031a target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
9b963a1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
eb5cc3d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
f31df48 target/riscv: Convert @cs_2 insns to share translation functions
8499159 target/riscv: Remove decode_RV32_64G()
3ac75b0 target/riscv: Remove gen_system()
28b7019 target/riscv: Rename trans_arith to gen_arith
c69cef8 target/riscv: Remove manual decoding of RV32/64M insn
0fee6c7 target/riscv: Remove shift and slt insn manual decoding
3e8a05f target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2805954 target/riscv: Move gen_arith_imm() decoding into trans_* functions
4ca0f72 target/riscv: Remove manual decoding from gen_store()
bba5eb0 target/riscv: Remove manual decoding from gen_load()
2382078 target/riscv: Remove manual decoding from gen_branch()
51720e7 target/riscv: Remove gen_jalr()
76fe773 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
cbdbfe4 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
a845ad9 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
4757f88 target/riscv: Convert RV priv insns to decodetree
a45dc64 target/riscv: Convert RV64D insns to decodetree
81d433a target/riscv: Convert RV32D insns to decodetree
a2817b8 target/riscv: Convert RV64F insns to decodetree
a4b3aa5 target/riscv: Convert RV32F insns to decodetree
f571c73 target/riscv: Convert RV64A insns to decodetree
3099ed9 target/riscv: Convert RV32A insns to decodetree
e5cff57 target/riscv: Convert RVXM insns to decodetree
3e87961 target/riscv: Convert RVXI csr insns to decodetree
a9ff2a1 target/riscv: Convert RVXI fence insns to decodetree
fc1d4e4 target/riscv: Convert RVXI arithmetic insns to decodetree
40eb746 target/riscv: Convert RV64I load/store insns to decodetree
18be721 target/riscv: Convert RV32I load/store insns to decodetree
3a4a0f2 target/riscv: Convert RVXI branch insns to decodetree
b44b4cc target/riscv: Activate decodetree and implemnt LUI & AUIPC
257d7a3 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 257d7a3545e4 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b44b4cc80078 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 3a4a0f26abd1 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 18be72113172 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 40eb746234ae (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit fc1d4e4b6fdc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit a9ff2a19cbb4 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 3e8796163e96 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit e5cff571cf52 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 3099ed9f2afe (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f571c731a1cf (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit a4b3aa51137d (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit a2817b828ef7 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 81d433a3555c (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit a45dc64b147c (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 4757f887d39f (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit a845ad916796 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit cbdbfe4ce623 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 76fe77374a60 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 51720e787149 (target/riscv: Remove gen_jalr())
21/35 Checking commit 2382078c37bb (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit bba5eb03d70f (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 4ca0f7208f9f (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 2805954f69ea (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 3e8a05f65cb5 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 0fee6c777814 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit c69cef8906b7 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 28b70192feb3 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 3ac75b04e92d (target/riscv: Remove gen_system())
30/35 Checking commit 84991598cd17 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit f31df482709c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit eb5cc3d89f71 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 9b963a191d7b (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit b54031a6e1c5 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit ed5d29b4e2b6 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:25 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:25 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
9e8165dd94 target/riscv: Remaining rvc insn reuse 32 bit translators
e66c95c9bc target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
efb9740ab1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
3c31768d81 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
795b478c4c target/riscv: Convert @cs_2 insns to share translation functions
110406e271 target/riscv: Remove decode_RV32_64G()
976eb72944 target/riscv: Remove gen_system()
0edf15c5d8 target/riscv: Rename trans_arith to gen_arith
dfa6dc21c3 target/riscv: Remove manual decoding of RV32/64M insn
5a6623cc6d target/riscv: Remove shift and slt insn manual decoding
42aa2541a4 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f6ead4a8ee target/riscv: Move gen_arith_imm() decoding into trans_* functions
132f8da29f target/riscv: Remove manual decoding from gen_store()
2e18729d25 target/riscv: Remove manual decoding from gen_load()
308b594c3a target/riscv: Remove manual decoding from gen_branch()
12f3dae1bf target/riscv: Remove gen_jalr()
663d608c7e target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f689ec99ed target/riscv: Convert quadrant 1 of RVXC insns to decodetree
baba3b6b99 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
222b932a1c target/riscv: Convert RV priv insns to decodetree
57d7252133 target/riscv: Convert RV64D insns to decodetree
85126a61bc target/riscv: Convert RV32D insns to decodetree
4b1f8c614b target/riscv: Convert RV64F insns to decodetree
ca3cfe3dd9 target/riscv: Convert RV32F insns to decodetree
70fd2547e6 target/riscv: Convert RV64A insns to decodetree
d05a7c9118 target/riscv: Convert RV32A insns to decodetree
f56b79ac87 target/riscv: Convert RVXM insns to decodetree
f5805d1ea7 target/riscv: Convert RVXI csr insns to decodetree
0d45dd0abf target/riscv: Convert RVXI fence insns to decodetree
197e9af126 target/riscv: Convert RVXI arithmetic insns to decodetree
f4195b8860 target/riscv: Convert RV64I load/store insns to decodetree
c44be19b1c target/riscv: Convert RV32I load/store insns to decodetree
944c2876b3 target/riscv: Convert RVXI branch insns to decodetree
2b11f0fa7d target/riscv: Activate decodetree and implemnt LUI & AUIPC
a377eafc54 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit a377eafc5405 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 2b11f0fa7dd5 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 944c2876b315 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit c44be19b1c8f (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f4195b886030 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 197e9af1264b (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 0d45dd0abfc6 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit f5805d1ea703 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f56b79ac87ee (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit d05a7c91186f (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 70fd2547e6cf (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit ca3cfe3dd932 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 4b1f8c614b02 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 85126a61bc34 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 57d72521333c (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 222b932a1cf7 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit baba3b6b997c (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit f689ec99ed0e (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 663d608c7ebd (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 12f3dae1bfb8 (target/riscv: Remove gen_jalr())
21/35 Checking commit 308b594c3adb (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 2e18729d253e (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 132f8da29f26 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit f6ead4a8ee53 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 42aa2541a436 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 5a6623cc6dab (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit dfa6dc21c3ce (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 0edf15c5d878 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 976eb72944d8 (target/riscv: Remove gen_system())
30/35 Checking commit 110406e2710f (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 795b478c4c7f (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 3c31768d8171 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit efb9740ab17e (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit e66c95c9bca8 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 9e8165dd9406 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:25 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:25 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
9e8165dd94 target/riscv: Remaining rvc insn reuse 32 bit translators
e66c95c9bc target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
efb9740ab1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
3c31768d81 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
795b478c4c target/riscv: Convert @cs_2 insns to share translation functions
110406e271 target/riscv: Remove decode_RV32_64G()
976eb72944 target/riscv: Remove gen_system()
0edf15c5d8 target/riscv: Rename trans_arith to gen_arith
dfa6dc21c3 target/riscv: Remove manual decoding of RV32/64M insn
5a6623cc6d target/riscv: Remove shift and slt insn manual decoding
42aa2541a4 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f6ead4a8ee target/riscv: Move gen_arith_imm() decoding into trans_* functions
132f8da29f target/riscv: Remove manual decoding from gen_store()
2e18729d25 target/riscv: Remove manual decoding from gen_load()
308b594c3a target/riscv: Remove manual decoding from gen_branch()
12f3dae1bf target/riscv: Remove gen_jalr()
663d608c7e target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f689ec99ed target/riscv: Convert quadrant 1 of RVXC insns to decodetree
baba3b6b99 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
222b932a1c target/riscv: Convert RV priv insns to decodetree
57d7252133 target/riscv: Convert RV64D insns to decodetree
85126a61bc target/riscv: Convert RV32D insns to decodetree
4b1f8c614b target/riscv: Convert RV64F insns to decodetree
ca3cfe3dd9 target/riscv: Convert RV32F insns to decodetree
70fd2547e6 target/riscv: Convert RV64A insns to decodetree
d05a7c9118 target/riscv: Convert RV32A insns to decodetree
f56b79ac87 target/riscv: Convert RVXM insns to decodetree
f5805d1ea7 target/riscv: Convert RVXI csr insns to decodetree
0d45dd0abf target/riscv: Convert RVXI fence insns to decodetree
197e9af126 target/riscv: Convert RVXI arithmetic insns to decodetree
f4195b8860 target/riscv: Convert RV64I load/store insns to decodetree
c44be19b1c target/riscv: Convert RV32I load/store insns to decodetree
944c2876b3 target/riscv: Convert RVXI branch insns to decodetree
2b11f0fa7d target/riscv: Activate decodetree and implemnt LUI & AUIPC
a377eafc54 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit a377eafc5405 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 2b11f0fa7dd5 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 944c2876b315 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit c44be19b1c8f (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f4195b886030 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 197e9af1264b (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 0d45dd0abfc6 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit f5805d1ea703 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f56b79ac87ee (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit d05a7c91186f (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 70fd2547e6cf (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit ca3cfe3dd932 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 4b1f8c614b02 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 85126a61bc34 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 57d72521333c (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 222b932a1cf7 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit baba3b6b997c (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit f689ec99ed0e (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 663d608c7ebd (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 12f3dae1bfb8 (target/riscv: Remove gen_jalr())
21/35 Checking commit 308b594c3adb (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 2e18729d253e (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 132f8da29f26 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit f6ead4a8ee53 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 42aa2541a436 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 5a6623cc6dab (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit dfa6dc21c3ce (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 0edf15c5d878 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 976eb72944d8 (target/riscv: Remove gen_system())
30/35 Checking commit 110406e2710f (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 795b478c4c7f (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 3c31768d8171 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit efb9740ab17e (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit e66c95c9bca8 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 9e8165dd9406 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:26 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:26 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
* [new tag] patchew/20190131211931.16216-1-svens@stackframe.org -> patchew/20190131211931.16216-1-svens@stackframe.org
Switched to a new branch 'test'
9e8165d target/riscv: Remaining rvc insn reuse 32 bit translators
e66c95c target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
efb9740 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
3c31768 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
795b478 target/riscv: Convert @cs_2 insns to share translation functions
110406e target/riscv: Remove decode_RV32_64G()
976eb72 target/riscv: Remove gen_system()
0edf15c target/riscv: Rename trans_arith to gen_arith
dfa6dc2 target/riscv: Remove manual decoding of RV32/64M insn
5a6623c target/riscv: Remove shift and slt insn manual decoding
42aa254 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f6ead4a target/riscv: Move gen_arith_imm() decoding into trans_* functions
132f8da target/riscv: Remove manual decoding from gen_store()
2e18729 target/riscv: Remove manual decoding from gen_load()
308b594 target/riscv: Remove manual decoding from gen_branch()
12f3dae target/riscv: Remove gen_jalr()
663d608 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f689ec9 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
baba3b6 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
222b932 target/riscv: Convert RV priv insns to decodetree
57d7252 target/riscv: Convert RV64D insns to decodetree
85126a6 target/riscv: Convert RV32D insns to decodetree
4b1f8c6 target/riscv: Convert RV64F insns to decodetree
ca3cfe3 target/riscv: Convert RV32F insns to decodetree
70fd254 target/riscv: Convert RV64A insns to decodetree
d05a7c9 target/riscv: Convert RV32A insns to decodetree
f56b79a target/riscv: Convert RVXM insns to decodetree
f5805d1 target/riscv: Convert RVXI csr insns to decodetree
0d45dd0 target/riscv: Convert RVXI fence insns to decodetree
197e9af target/riscv: Convert RVXI arithmetic insns to decodetree
f4195b8 target/riscv: Convert RV64I load/store insns to decodetree
c44be19 target/riscv: Convert RV32I load/store insns to decodetree
944c287 target/riscv: Convert RVXI branch insns to decodetree
2b11f0f target/riscv: Activate decodetree and implemnt LUI & AUIPC
a377eaf target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit a377eafc5405 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 2b11f0fa7dd5 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 944c2876b315 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit c44be19b1c8f (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f4195b886030 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 197e9af1264b (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 0d45dd0abfc6 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit f5805d1ea703 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f56b79ac87ee (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit d05a7c91186f (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 70fd2547e6cf (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit ca3cfe3dd932 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 4b1f8c614b02 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 85126a61bc34 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 57d72521333c (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 222b932a1cf7 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit baba3b6b997c (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit f689ec99ed0e (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 663d608c7ebd (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 12f3dae1bfb8 (target/riscv: Remove gen_jalr())
21/35 Checking commit 308b594c3adb (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 2e18729d253e (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 132f8da29f26 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit f6ead4a8ee53 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 42aa2541a436 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 5a6623cc6dab (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit dfa6dc21c3ce (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 0edf15c5d878 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 976eb72944d8 (target/riscv: Remove gen_system())
30/35 Checking commit 110406e2710f (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 795b478c4c7f (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 3c31768d8171 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit efb9740ab17e (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit e66c95c9bca8 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 9e8165dd9406 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:26 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:26 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
* [new tag] patchew/20190131211931.16216-1-svens@stackframe.org -> patchew/20190131211931.16216-1-svens@stackframe.org
Switched to a new branch 'test'
9e8165d target/riscv: Remaining rvc insn reuse 32 bit translators
e66c95c target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
efb9740 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
3c31768 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
795b478 target/riscv: Convert @cs_2 insns to share translation functions
110406e target/riscv: Remove decode_RV32_64G()
976eb72 target/riscv: Remove gen_system()
0edf15c target/riscv: Rename trans_arith to gen_arith
dfa6dc2 target/riscv: Remove manual decoding of RV32/64M insn
5a6623c target/riscv: Remove shift and slt insn manual decoding
42aa254 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f6ead4a target/riscv: Move gen_arith_imm() decoding into trans_* functions
132f8da target/riscv: Remove manual decoding from gen_store()
2e18729 target/riscv: Remove manual decoding from gen_load()
308b594 target/riscv: Remove manual decoding from gen_branch()
12f3dae target/riscv: Remove gen_jalr()
663d608 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f689ec9 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
baba3b6 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
222b932 target/riscv: Convert RV priv insns to decodetree
57d7252 target/riscv: Convert RV64D insns to decodetree
85126a6 target/riscv: Convert RV32D insns to decodetree
4b1f8c6 target/riscv: Convert RV64F insns to decodetree
ca3cfe3 target/riscv: Convert RV32F insns to decodetree
70fd254 target/riscv: Convert RV64A insns to decodetree
d05a7c9 target/riscv: Convert RV32A insns to decodetree
f56b79a target/riscv: Convert RVXM insns to decodetree
f5805d1 target/riscv: Convert RVXI csr insns to decodetree
0d45dd0 target/riscv: Convert RVXI fence insns to decodetree
197e9af target/riscv: Convert RVXI arithmetic insns to decodetree
f4195b8 target/riscv: Convert RV64I load/store insns to decodetree
c44be19 target/riscv: Convert RV32I load/store insns to decodetree
944c287 target/riscv: Convert RVXI branch insns to decodetree
2b11f0f target/riscv: Activate decodetree and implemnt LUI & AUIPC
a377eaf target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit a377eafc5405 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 2b11f0fa7dd5 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 944c2876b315 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit c44be19b1c8f (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f4195b886030 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 197e9af1264b (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 0d45dd0abfc6 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit f5805d1ea703 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit f56b79ac87ee (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit d05a7c91186f (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 70fd2547e6cf (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit ca3cfe3dd932 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 4b1f8c614b02 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 85126a61bc34 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 57d72521333c (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 222b932a1cf7 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit baba3b6b997c (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit f689ec99ed0e (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 663d608c7ebd (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 12f3dae1bfb8 (target/riscv: Remove gen_jalr())
21/35 Checking commit 308b594c3adb (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 2e18729d253e (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 132f8da29f26 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit f6ead4a8ee53 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 42aa2541a436 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 5a6623cc6dab (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit dfa6dc21c3ce (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 0edf15c5d878 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 976eb72944d8 (target/riscv: Remove gen_system())
30/35 Checking commit 110406e2710f (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 795b478c4c7f (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 3c31768d8171 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit efb9740ab17e (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit e66c95c9bca8 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 9e8165dd9406 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:27 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:27 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
* [new tag] patchew/20190131210851.9842-1-richard.henderson@linaro.org -> patchew/20190131210851.9842-1-richard.henderson@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
ed5d29b target/riscv: Remaining rvc insn reuse 32 bit translators
b54031a target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
9b963a1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
eb5cc3d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
f31df48 target/riscv: Convert @cs_2 insns to share translation functions
8499159 target/riscv: Remove decode_RV32_64G()
3ac75b0 target/riscv: Remove gen_system()
28b7019 target/riscv: Rename trans_arith to gen_arith
c69cef8 target/riscv: Remove manual decoding of RV32/64M insn
0fee6c7 target/riscv: Remove shift and slt insn manual decoding
3e8a05f target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2805954 target/riscv: Move gen_arith_imm() decoding into trans_* functions
4ca0f72 target/riscv: Remove manual decoding from gen_store()
bba5eb0 target/riscv: Remove manual decoding from gen_load()
2382078 target/riscv: Remove manual decoding from gen_branch()
51720e7 target/riscv: Remove gen_jalr()
76fe773 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
cbdbfe4 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
a845ad9 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
4757f88 target/riscv: Convert RV priv insns to decodetree
a45dc64 target/riscv: Convert RV64D insns to decodetree
81d433a target/riscv: Convert RV32D insns to decodetree
a2817b8 target/riscv: Convert RV64F insns to decodetree
a4b3aa5 target/riscv: Convert RV32F insns to decodetree
f571c73 target/riscv: Convert RV64A insns to decodetree
3099ed9 target/riscv: Convert RV32A insns to decodetree
e5cff57 target/riscv: Convert RVXM insns to decodetree
3e87961 target/riscv: Convert RVXI csr insns to decodetree
a9ff2a1 target/riscv: Convert RVXI fence insns to decodetree
fc1d4e4 target/riscv: Convert RVXI arithmetic insns to decodetree
40eb746 target/riscv: Convert RV64I load/store insns to decodetree
18be721 target/riscv: Convert RV32I load/store insns to decodetree
3a4a0f2 target/riscv: Convert RVXI branch insns to decodetree
b44b4cc target/riscv: Activate decodetree and implemnt LUI & AUIPC
257d7a3 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 257d7a3545e4 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b44b4cc80078 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 3a4a0f26abd1 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 18be72113172 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 40eb746234ae (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit fc1d4e4b6fdc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit a9ff2a19cbb4 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 3e8796163e96 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit e5cff571cf52 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 3099ed9f2afe (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f571c731a1cf (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit a4b3aa51137d (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit a2817b828ef7 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 81d433a3555c (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit a45dc64b147c (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 4757f887d39f (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit a845ad916796 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit cbdbfe4ce623 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 76fe77374a60 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 51720e787149 (target/riscv: Remove gen_jalr())
21/35 Checking commit 2382078c37bb (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit bba5eb03d70f (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 4ca0f7208f9f (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 2805954f69ea (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 3e8a05f65cb5 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 0fee6c777814 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit c69cef8906b7 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 28b70192feb3 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 3ac75b04e92d (target/riscv: Remove gen_system())
30/35 Checking commit 84991598cd17 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit f31df482709c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit eb5cc3d89f71 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 9b963a191d7b (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit b54031a6e1c5 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit ed5d29b4e2b6 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:27 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:27 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
* [new tag] patchew/20190131210851.9842-1-richard.henderson@linaro.org -> patchew/20190131210851.9842-1-richard.henderson@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
ed5d29b target/riscv: Remaining rvc insn reuse 32 bit translators
b54031a target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
9b963a1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
eb5cc3d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
f31df48 target/riscv: Convert @cs_2 insns to share translation functions
8499159 target/riscv: Remove decode_RV32_64G()
3ac75b0 target/riscv: Remove gen_system()
28b7019 target/riscv: Rename trans_arith to gen_arith
c69cef8 target/riscv: Remove manual decoding of RV32/64M insn
0fee6c7 target/riscv: Remove shift and slt insn manual decoding
3e8a05f target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2805954 target/riscv: Move gen_arith_imm() decoding into trans_* functions
4ca0f72 target/riscv: Remove manual decoding from gen_store()
bba5eb0 target/riscv: Remove manual decoding from gen_load()
2382078 target/riscv: Remove manual decoding from gen_branch()
51720e7 target/riscv: Remove gen_jalr()
76fe773 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
cbdbfe4 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
a845ad9 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
4757f88 target/riscv: Convert RV priv insns to decodetree
a45dc64 target/riscv: Convert RV64D insns to decodetree
81d433a target/riscv: Convert RV32D insns to decodetree
a2817b8 target/riscv: Convert RV64F insns to decodetree
a4b3aa5 target/riscv: Convert RV32F insns to decodetree
f571c73 target/riscv: Convert RV64A insns to decodetree
3099ed9 target/riscv: Convert RV32A insns to decodetree
e5cff57 target/riscv: Convert RVXM insns to decodetree
3e87961 target/riscv: Convert RVXI csr insns to decodetree
a9ff2a1 target/riscv: Convert RVXI fence insns to decodetree
fc1d4e4 target/riscv: Convert RVXI arithmetic insns to decodetree
40eb746 target/riscv: Convert RV64I load/store insns to decodetree
18be721 target/riscv: Convert RV32I load/store insns to decodetree
3a4a0f2 target/riscv: Convert RVXI branch insns to decodetree
b44b4cc target/riscv: Activate decodetree and implemnt LUI & AUIPC
257d7a3 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 257d7a3545e4 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit b44b4cc80078 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 3a4a0f26abd1 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 18be72113172 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 40eb746234ae (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit fc1d4e4b6fdc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit a9ff2a19cbb4 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 3e8796163e96 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit e5cff571cf52 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 3099ed9f2afe (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f571c731a1cf (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit a4b3aa51137d (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit a2817b828ef7 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 81d433a3555c (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit a45dc64b147c (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 4757f887d39f (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit a845ad916796 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit cbdbfe4ce623 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 76fe77374a60 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 51720e787149 (target/riscv: Remove gen_jalr())
21/35 Checking commit 2382078c37bb (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit bba5eb03d70f (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 4ca0f7208f9f (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 2805954f69ea (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 3e8a05f65cb5 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 0fee6c777814 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit c69cef8906b7 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 28b70192feb3 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 3ac75b04e92d (target/riscv: Remove gen_system())
30/35 Checking commit 84991598cd17 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit f31df482709c (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit eb5cc3d89f71 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 9b963a191d7b (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit b54031a6e1c5 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit ed5d29b4e2b6 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:37 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:37 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
291fb3378a target/riscv: Remaining rvc insn reuse 32 bit translators
f234c9a301 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
16680b13d8 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8c27631fd4 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
d2bb2de935 target/riscv: Convert @cs_2 insns to share translation functions
24f04339fe target/riscv: Remove decode_RV32_64G()
8e284b2972 target/riscv: Remove gen_system()
7fdd5f104c target/riscv: Rename trans_arith to gen_arith
696cd56967 target/riscv: Remove manual decoding of RV32/64M insn
81c0dbfad9 target/riscv: Remove shift and slt insn manual decoding
69947ae047 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
b162444c18 target/riscv: Move gen_arith_imm() decoding into trans_* functions
9d189f830c target/riscv: Remove manual decoding from gen_store()
b9e24ac0d5 target/riscv: Remove manual decoding from gen_load()
543c238dc7 target/riscv: Remove manual decoding from gen_branch()
1ecefc4283 target/riscv: Remove gen_jalr()
4251a010bd target/riscv: Convert quadrant 2 of RVXC insns to decodetree
3a0627ae71 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
135f107593 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8833d537b5 target/riscv: Convert RV priv insns to decodetree
28b613a932 target/riscv: Convert RV64D insns to decodetree
02b797edd5 target/riscv: Convert RV32D insns to decodetree
27cc348b3b target/riscv: Convert RV64F insns to decodetree
b0857e0983 target/riscv: Convert RV32F insns to decodetree
b578a96842 target/riscv: Convert RV64A insns to decodetree
26ca8f5631 target/riscv: Convert RV32A insns to decodetree
0ef195feef target/riscv: Convert RVXM insns to decodetree
d22f711d7d target/riscv: Convert RVXI csr insns to decodetree
34de7f7504 target/riscv: Convert RVXI fence insns to decodetree
da5403e39d target/riscv: Convert RVXI arithmetic insns to decodetree
f8d0548e2d target/riscv: Convert RV64I load/store insns to decodetree
7f40538802 target/riscv: Convert RV32I load/store insns to decodetree
d5b10e4501 target/riscv: Convert RVXI branch insns to decodetree
26e2990ada target/riscv: Activate decodetree and implemnt LUI & AUIPC
2d78010a7d target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 2d78010a7d7b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 26e2990adad9 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit d5b10e450153 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7f40538802f9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f8d0548e2da9 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit da5403e39dfc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 34de7f750472 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d22f711d7ddb (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 0ef195feef49 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 26ca8f56316d (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit b578a9684221 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit b0857e0983f9 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 27cc348b3b41 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 02b797edd5e8 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 28b613a9323b (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8833d537b599 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 135f10759377 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 3a0627ae7139 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 4251a010bd40 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 1ecefc428332 (target/riscv: Remove gen_jalr())
21/35 Checking commit 543c238dc767 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit b9e24ac0d566 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 9d189f830c77 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit b162444c1849 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 69947ae04778 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 81c0dbfad9c7 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 696cd5696710 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7fdd5f104c9d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 8e284b2972e0 (target/riscv: Remove gen_system())
30/35 Checking commit 24f04339fe94 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit d2bb2de93587 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8c27631fd427 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 16680b13d8ee (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit f234c9a30159 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 291fb3378aab (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:37 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:37 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
291fb3378a target/riscv: Remaining rvc insn reuse 32 bit translators
f234c9a301 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
16680b13d8 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8c27631fd4 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
d2bb2de935 target/riscv: Convert @cs_2 insns to share translation functions
24f04339fe target/riscv: Remove decode_RV32_64G()
8e284b2972 target/riscv: Remove gen_system()
7fdd5f104c target/riscv: Rename trans_arith to gen_arith
696cd56967 target/riscv: Remove manual decoding of RV32/64M insn
81c0dbfad9 target/riscv: Remove shift and slt insn manual decoding
69947ae047 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
b162444c18 target/riscv: Move gen_arith_imm() decoding into trans_* functions
9d189f830c target/riscv: Remove manual decoding from gen_store()
b9e24ac0d5 target/riscv: Remove manual decoding from gen_load()
543c238dc7 target/riscv: Remove manual decoding from gen_branch()
1ecefc4283 target/riscv: Remove gen_jalr()
4251a010bd target/riscv: Convert quadrant 2 of RVXC insns to decodetree
3a0627ae71 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
135f107593 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8833d537b5 target/riscv: Convert RV priv insns to decodetree
28b613a932 target/riscv: Convert RV64D insns to decodetree
02b797edd5 target/riscv: Convert RV32D insns to decodetree
27cc348b3b target/riscv: Convert RV64F insns to decodetree
b0857e0983 target/riscv: Convert RV32F insns to decodetree
b578a96842 target/riscv: Convert RV64A insns to decodetree
26ca8f5631 target/riscv: Convert RV32A insns to decodetree
0ef195feef target/riscv: Convert RVXM insns to decodetree
d22f711d7d target/riscv: Convert RVXI csr insns to decodetree
34de7f7504 target/riscv: Convert RVXI fence insns to decodetree
da5403e39d target/riscv: Convert RVXI arithmetic insns to decodetree
f8d0548e2d target/riscv: Convert RV64I load/store insns to decodetree
7f40538802 target/riscv: Convert RV32I load/store insns to decodetree
d5b10e4501 target/riscv: Convert RVXI branch insns to decodetree
26e2990ada target/riscv: Activate decodetree and implemnt LUI & AUIPC
2d78010a7d target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 2d78010a7d7b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 26e2990adad9 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit d5b10e450153 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7f40538802f9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f8d0548e2da9 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit da5403e39dfc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 34de7f750472 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d22f711d7ddb (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 0ef195feef49 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 26ca8f56316d (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit b578a9684221 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit b0857e0983f9 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 27cc348b3b41 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 02b797edd5e8 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 28b613a9323b (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8833d537b599 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 135f10759377 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 3a0627ae7139 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 4251a010bd40 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 1ecefc428332 (target/riscv: Remove gen_jalr())
21/35 Checking commit 543c238dc767 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit b9e24ac0d566 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 9d189f830c77 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit b162444c1849 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 69947ae04778 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 81c0dbfad9c7 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 696cd5696710 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7fdd5f104c9d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 8e284b2972e0 (target/riscv: Remove gen_system())
30/35 Checking commit 24f04339fe94 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit d2bb2de93587 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8c27631fd427 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 16680b13d8ee (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit f234c9a30159 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 291fb3378aab (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:38 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:38 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
291fb33 target/riscv: Remaining rvc insn reuse 32 bit translators
f234c9a target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
16680b1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8c27631 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
d2bb2de target/riscv: Convert @cs_2 insns to share translation functions
24f0433 target/riscv: Remove decode_RV32_64G()
8e284b2 target/riscv: Remove gen_system()
7fdd5f1 target/riscv: Rename trans_arith to gen_arith
696cd56 target/riscv: Remove manual decoding of RV32/64M insn
81c0dbf target/riscv: Remove shift and slt insn manual decoding
69947ae target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
b162444 target/riscv: Move gen_arith_imm() decoding into trans_* functions
9d189f8 target/riscv: Remove manual decoding from gen_store()
b9e24ac target/riscv: Remove manual decoding from gen_load()
543c238 target/riscv: Remove manual decoding from gen_branch()
1ecefc4 target/riscv: Remove gen_jalr()
4251a01 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
3a0627a target/riscv: Convert quadrant 1 of RVXC insns to decodetree
135f107 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8833d53 target/riscv: Convert RV priv insns to decodetree
28b613a target/riscv: Convert RV64D insns to decodetree
02b797e target/riscv: Convert RV32D insns to decodetree
27cc348 target/riscv: Convert RV64F insns to decodetree
b0857e0 target/riscv: Convert RV32F insns to decodetree
b578a96 target/riscv: Convert RV64A insns to decodetree
26ca8f5 target/riscv: Convert RV32A insns to decodetree
0ef195f target/riscv: Convert RVXM insns to decodetree
d22f711 target/riscv: Convert RVXI csr insns to decodetree
34de7f7 target/riscv: Convert RVXI fence insns to decodetree
da5403e target/riscv: Convert RVXI arithmetic insns to decodetree
f8d0548 target/riscv: Convert RV64I load/store insns to decodetree
7f40538 target/riscv: Convert RV32I load/store insns to decodetree
d5b10e4 target/riscv: Convert RVXI branch insns to decodetree
26e2990 target/riscv: Activate decodetree and implemnt LUI & AUIPC
2d78010 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 2d78010a7d7b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 26e2990adad9 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit d5b10e450153 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7f40538802f9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f8d0548e2da9 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit da5403e39dfc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 34de7f750472 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d22f711d7ddb (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 0ef195feef49 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 26ca8f56316d (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit b578a9684221 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit b0857e0983f9 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 27cc348b3b41 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 02b797edd5e8 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 28b613a9323b (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8833d537b599 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 135f10759377 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 3a0627ae7139 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 4251a010bd40 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 1ecefc428332 (target/riscv: Remove gen_jalr())
21/35 Checking commit 543c238dc767 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit b9e24ac0d566 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 9d189f830c77 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit b162444c1849 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 69947ae04778 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 81c0dbfad9c7 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 696cd5696710 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7fdd5f104c9d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 8e284b2972e0 (target/riscv: Remove gen_system())
30/35 Checking commit 24f04339fe94 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit d2bb2de93587 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8c27631fd427 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 16680b13d8ee (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit f234c9a30159 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 291fb3378aab (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:38 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:38 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
291fb33 target/riscv: Remaining rvc insn reuse 32 bit translators
f234c9a target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
16680b1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8c27631 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
d2bb2de target/riscv: Convert @cs_2 insns to share translation functions
24f0433 target/riscv: Remove decode_RV32_64G()
8e284b2 target/riscv: Remove gen_system()
7fdd5f1 target/riscv: Rename trans_arith to gen_arith
696cd56 target/riscv: Remove manual decoding of RV32/64M insn
81c0dbf target/riscv: Remove shift and slt insn manual decoding
69947ae target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
b162444 target/riscv: Move gen_arith_imm() decoding into trans_* functions
9d189f8 target/riscv: Remove manual decoding from gen_store()
b9e24ac target/riscv: Remove manual decoding from gen_load()
543c238 target/riscv: Remove manual decoding from gen_branch()
1ecefc4 target/riscv: Remove gen_jalr()
4251a01 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
3a0627a target/riscv: Convert quadrant 1 of RVXC insns to decodetree
135f107 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8833d53 target/riscv: Convert RV priv insns to decodetree
28b613a target/riscv: Convert RV64D insns to decodetree
02b797e target/riscv: Convert RV32D insns to decodetree
27cc348 target/riscv: Convert RV64F insns to decodetree
b0857e0 target/riscv: Convert RV32F insns to decodetree
b578a96 target/riscv: Convert RV64A insns to decodetree
26ca8f5 target/riscv: Convert RV32A insns to decodetree
0ef195f target/riscv: Convert RVXM insns to decodetree
d22f711 target/riscv: Convert RVXI csr insns to decodetree
34de7f7 target/riscv: Convert RVXI fence insns to decodetree
da5403e target/riscv: Convert RVXI arithmetic insns to decodetree
f8d0548 target/riscv: Convert RV64I load/store insns to decodetree
7f40538 target/riscv: Convert RV32I load/store insns to decodetree
d5b10e4 target/riscv: Convert RVXI branch insns to decodetree
26e2990 target/riscv: Activate decodetree and implemnt LUI & AUIPC
2d78010 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 2d78010a7d7b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 26e2990adad9 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit d5b10e450153 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7f40538802f9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f8d0548e2da9 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit da5403e39dfc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 34de7f750472 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d22f711d7ddb (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 0ef195feef49 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 26ca8f56316d (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit b578a9684221 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit b0857e0983f9 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 27cc348b3b41 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 02b797edd5e8 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 28b613a9323b (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8833d537b599 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 135f10759377 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 3a0627ae7139 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 4251a010bd40 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 1ecefc428332 (target/riscv: Remove gen_jalr())
21/35 Checking commit 543c238dc767 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit b9e24ac0d566 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 9d189f830c77 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit b162444c1849 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 69947ae04778 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 81c0dbfad9c7 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 696cd5696710 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7fdd5f104c9d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 8e284b2972e0 (target/riscv: Remove gen_system())
30/35 Checking commit 24f04339fe94 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit d2bb2de93587 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8c27631fd427 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 16680b13d8ee (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit f234c9a30159 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 291fb3378aab (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
@ 2019-01-31 21:41 ` no-reply
-1 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:41 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, qemu-riscv, peer.adelt, richard.henderson,
qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
* [new tag] patchew/20190131211931.16216-1-svens@stackframe.org -> patchew/20190131211931.16216-1-svens@stackframe.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
291fb33 target/riscv: Remaining rvc insn reuse 32 bit translators
f234c9a target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
16680b1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8c27631 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
d2bb2de target/riscv: Convert @cs_2 insns to share translation functions
24f0433 target/riscv: Remove decode_RV32_64G()
8e284b2 target/riscv: Remove gen_system()
7fdd5f1 target/riscv: Rename trans_arith to gen_arith
696cd56 target/riscv: Remove manual decoding of RV32/64M insn
81c0dbf target/riscv: Remove shift and slt insn manual decoding
69947ae target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
b162444 target/riscv: Move gen_arith_imm() decoding into trans_* functions
9d189f8 target/riscv: Remove manual decoding from gen_store()
b9e24ac target/riscv: Remove manual decoding from gen_load()
543c238 target/riscv: Remove manual decoding from gen_branch()
1ecefc4 target/riscv: Remove gen_jalr()
4251a01 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
3a0627a target/riscv: Convert quadrant 1 of RVXC insns to decodetree
135f107 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8833d53 target/riscv: Convert RV priv insns to decodetree
28b613a target/riscv: Convert RV64D insns to decodetree
02b797e target/riscv: Convert RV32D insns to decodetree
27cc348 target/riscv: Convert RV64F insns to decodetree
b0857e0 target/riscv: Convert RV32F insns to decodetree
b578a96 target/riscv: Convert RV64A insns to decodetree
26ca8f5 target/riscv: Convert RV32A insns to decodetree
0ef195f target/riscv: Convert RVXM insns to decodetree
d22f711 target/riscv: Convert RVXI csr insns to decodetree
34de7f7 target/riscv: Convert RVXI fence insns to decodetree
da5403e target/riscv: Convert RVXI arithmetic insns to decodetree
f8d0548 target/riscv: Convert RV64I load/store insns to decodetree
7f40538 target/riscv: Convert RV32I load/store insns to decodetree
d5b10e4 target/riscv: Convert RVXI branch insns to decodetree
26e2990 target/riscv: Activate decodetree and implemnt LUI & AUIPC
2d78010 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 2d78010a7d7b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 26e2990adad9 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit d5b10e450153 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7f40538802f9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f8d0548e2da9 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit da5403e39dfc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 34de7f750472 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d22f711d7ddb (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 0ef195feef49 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 26ca8f56316d (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit b578a9684221 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit b0857e0983f9 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 27cc348b3b41 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 02b797edd5e8 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 28b613a9323b (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8833d537b599 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 135f10759377 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 3a0627ae7139 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 4251a010bd40 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 1ecefc428332 (target/riscv: Remove gen_jalr())
21/35 Checking commit 543c238dc767 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit b9e24ac0d566 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 9d189f830c77 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit b162444c1849 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 69947ae04778 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 81c0dbfad9c7 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 696cd5696710 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7fdd5f104c9d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 8e284b2972e0 (target/riscv: Remove gen_system())
30/35 Checking commit 24f04339fe94 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit d2bb2de93587 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8c27631fd427 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 16680b13d8ee (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit f234c9a30159 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 291fb3378aab (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
@ 2019-01-31 21:41 ` no-reply
0 siblings, 0 replies; 164+ messages in thread
From: no-reply @ 2019-01-31 21:41 UTC (permalink / raw)
To: kbastian
Cc: fam, sagark, palmer, kbastian, qemu-riscv, peer.adelt,
richard.henderson, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
* [new tag] patchew/20190131211931.16216-1-svens@stackframe.org -> patchew/20190131211931.16216-1-svens@stackframe.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
291fb33 target/riscv: Remaining rvc insn reuse 32 bit translators
f234c9a target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
16680b1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8c27631 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
d2bb2de target/riscv: Convert @cs_2 insns to share translation functions
24f0433 target/riscv: Remove decode_RV32_64G()
8e284b2 target/riscv: Remove gen_system()
7fdd5f1 target/riscv: Rename trans_arith to gen_arith
696cd56 target/riscv: Remove manual decoding of RV32/64M insn
81c0dbf target/riscv: Remove shift and slt insn manual decoding
69947ae target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
b162444 target/riscv: Move gen_arith_imm() decoding into trans_* functions
9d189f8 target/riscv: Remove manual decoding from gen_store()
b9e24ac target/riscv: Remove manual decoding from gen_load()
543c238 target/riscv: Remove manual decoding from gen_branch()
1ecefc4 target/riscv: Remove gen_jalr()
4251a01 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
3a0627a target/riscv: Convert quadrant 1 of RVXC insns to decodetree
135f107 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8833d53 target/riscv: Convert RV priv insns to decodetree
28b613a target/riscv: Convert RV64D insns to decodetree
02b797e target/riscv: Convert RV32D insns to decodetree
27cc348 target/riscv: Convert RV64F insns to decodetree
b0857e0 target/riscv: Convert RV32F insns to decodetree
b578a96 target/riscv: Convert RV64A insns to decodetree
26ca8f5 target/riscv: Convert RV32A insns to decodetree
0ef195f target/riscv: Convert RVXM insns to decodetree
d22f711 target/riscv: Convert RVXI csr insns to decodetree
34de7f7 target/riscv: Convert RVXI fence insns to decodetree
da5403e target/riscv: Convert RVXI arithmetic insns to decodetree
f8d0548 target/riscv: Convert RV64I load/store insns to decodetree
7f40538 target/riscv: Convert RV32I load/store insns to decodetree
d5b10e4 target/riscv: Convert RVXI branch insns to decodetree
26e2990 target/riscv: Activate decodetree and implemnt LUI & AUIPC
2d78010 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 2d78010a7d7b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 26e2990adad9 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit d5b10e450153 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7f40538802f9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f8d0548e2da9 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit da5403e39dfc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 34de7f750472 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d22f711d7ddb (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 0ef195feef49 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 26ca8f56316d (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit b578a9684221 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit b0857e0983f9 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 397 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 27cc348b3b41 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 02b797edd5e8 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 353 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 28b613a9323b (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8833d537b599 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 135f10759377 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit 3a0627ae7139 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 4251a010bd40 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 1ecefc428332 (target/riscv: Remove gen_jalr())
21/35 Checking commit 543c238dc767 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit b9e24ac0d566 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 9d189f830c77 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit b162444c1849 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 69947ae04778 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 81c0dbfad9c7 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 696cd5696710 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7fdd5f104c9d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 8e284b2972e0 (target/riscv: Remove gen_system())
30/35 Checking commit 24f04339fe94 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit d2bb2de93587 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 8c27631fd427 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 16680b13d8ee (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 287 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit f234c9a30159 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 291fb3378aab (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 164+ messages in thread
end of thread, other threads:[~2019-02-01 10:35 UTC | newest]
Thread overview: 164+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-22 9:28 [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:03 ` [Qemu-devel] " Alistair Francis
2019-01-22 23:03 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:38 ` [Qemu-devel] " Alistair Francis
2019-01-22 23:38 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:43 ` [Qemu-devel] " Alistair Francis
2019-01-22 23:43 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:00 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:00 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:08 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:08 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:08 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:08 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:10 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:10 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 1:00 ` [Qemu-devel] " Alistair Francis
2019-01-23 1:00 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:32 ` [Qemu-devel] " Richard Henderson
2019-01-22 21:32 ` [Qemu-riscv] " Richard Henderson
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:36 ` [Qemu-devel] " Richard Henderson
2019-01-22 21:36 ` [Qemu-riscv] " Richard Henderson
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:38 ` [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Richard Henderson
2019-01-22 21:38 ` [Qemu-riscv] " Richard Henderson
2019-01-23 9:15 ` [Qemu-devel] " Bastian Koppelmann
2019-01-23 9:15 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 21:22 ` Alistair Francis
2019-01-23 21:22 ` [Qemu-riscv] " Alistair Francis
2019-01-25 23:54 ` Palmer Dabbelt
2019-01-25 23:54 ` [Qemu-riscv] " Palmer Dabbelt
2019-01-26 8:51 ` [Qemu-devel] " Bastian Koppelmann
2019-01-26 8:51 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-29 19:22 ` Palmer Dabbelt
2019-01-29 19:22 ` [Qemu-riscv] " Palmer Dabbelt
2019-01-29 21:13 ` Alistair Francis
2019-01-29 21:13 ` [Qemu-riscv] " Alistair Francis
2019-01-30 9:08 ` Bastian Koppelmann
2019-01-30 9:08 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-30 18:47 ` Palmer Dabbelt
2019-01-30 18:47 ` [Qemu-riscv] " Palmer Dabbelt
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