From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:58945) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVZ-00068S-1l for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsON-0005h8-7C for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:48 -0500 From: Bastian Koppelmann Date: Tue, 22 Jan 2019 10:28:57 +0100 Message-Id: <20190122092909.5341-24-kbastian@mail.uni-paderborn.de> In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org, qemu-devel@nongnu.org With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_store() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 27 +++++++++++++++++-------- target/riscv/translate.c | 8 +++++--- 2 files changed, 24 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 1ad00bd776..da843b4e99 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -168,22 +168,34 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) return gen_load(ctx, a, MO_TEUW); } -static bool trans_sb(DisasContext *ctx, arg_sb *a) +static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop) { - gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm); + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_addi_tl(t0, t0, a->imm); + gen_get_gpr(dat, a->rs2); + + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); + tcg_temp_free(t0); + tcg_temp_free(dat); return true; } + +static bool trans_sb(DisasContext *ctx, arg_sb *a) +{ + return gen_store(ctx, a, MO_SB); +} + static bool trans_sh(DisasContext *ctx, arg_sh *a) { - gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TESW); } static bool trans_sw(DisasContext *ctx, arg_sw *a) { - gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TESL); } #ifdef TARGET_RISCV64 @@ -199,8 +211,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a) static bool trans_sd(DisasContext *ctx, arg_sd *a) { - gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TEQ); } #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d0fefa8fb9..59452be191 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -55,6 +55,7 @@ typedef struct DisasContext { CPURISCVState *env; } DisasContext; +#ifdef TARGET_RISCV64 /* convert riscv funct3 to qemu memop for load/store */ static const int tcg_memop_lookup[8] = { [0 ... 7] = -1, @@ -68,6 +69,7 @@ static const int tcg_memop_lookup[8] = { [6] = MO_TEUL, #endif }; +#endif #ifdef TARGET_RISCV64 #define CASE_OP_32_64(X) case X: case glue(X, W) @@ -509,9 +511,8 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, tcg_temp_free(t0); tcg_temp_free(t1); } -#endif -static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, +static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, target_long imm) { TCGv t0 = tcg_temp_new(); @@ -530,6 +531,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, tcg_temp_free(t0); tcg_temp_free(dat); } +#endif #ifdef TARGET_RISCV32 static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, @@ -653,7 +655,7 @@ static void decode_RV32_64C0(DisasContext *ctx) case 7: #if defined(TARGET_RISCV64) /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ - gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2, + gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, GET_C_LD_IMM(ctx->opcode)); #else /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1glsVi-0006gS-SC for mharc-qemu-riscv@gnu.org; Tue, 22 Jan 2019 04:38:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVY-0006AI-Vz for qemu-riscv@nongnu.org; Tue, 22 Jan 2019 04:38:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOO-0005j0-5w for qemu-riscv@nongnu.org; Tue, 22 Jan 2019 04:30:48 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:60800) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsON-0005PW-0x; Tue, 22 Jan 2019 04:30:47 -0500 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 nylar) id 1glsNr-0003Iu-NS; Tue, 22 Jan 2019 10:30:15 +0100 Received: from mail.uni-paderborn.de by wormulon with queue id 3100914-5; Tue, 22 Jan 2019 09:30:14 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Jan 2019 10:28:57 +0100 Message-Id: <20190122092909.5341-24-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-riscv] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store() X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Jan 2019 09:38:15 -0000 With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_store() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 27 +++++++++++++++++-------- target/riscv/translate.c | 8 +++++--- 2 files changed, 24 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 1ad00bd776..da843b4e99 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -168,22 +168,34 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) return gen_load(ctx, a, MO_TEUW); } -static bool trans_sb(DisasContext *ctx, arg_sb *a) +static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop) { - gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm); + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_addi_tl(t0, t0, a->imm); + gen_get_gpr(dat, a->rs2); + + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); + tcg_temp_free(t0); + tcg_temp_free(dat); return true; } + +static bool trans_sb(DisasContext *ctx, arg_sb *a) +{ + return gen_store(ctx, a, MO_SB); +} + static bool trans_sh(DisasContext *ctx, arg_sh *a) { - gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TESW); } static bool trans_sw(DisasContext *ctx, arg_sw *a) { - gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TESL); } #ifdef TARGET_RISCV64 @@ -199,8 +211,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a) static bool trans_sd(DisasContext *ctx, arg_sd *a) { - gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TEQ); } #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d0fefa8fb9..59452be191 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -55,6 +55,7 @@ typedef struct DisasContext { CPURISCVState *env; } DisasContext; +#ifdef TARGET_RISCV64 /* convert riscv funct3 to qemu memop for load/store */ static const int tcg_memop_lookup[8] = { [0 ... 7] = -1, @@ -68,6 +69,7 @@ static const int tcg_memop_lookup[8] = { [6] = MO_TEUL, #endif }; +#endif #ifdef TARGET_RISCV64 #define CASE_OP_32_64(X) case X: case glue(X, W) @@ -509,9 +511,8 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, tcg_temp_free(t0); tcg_temp_free(t1); } -#endif -static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, +static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, target_long imm) { TCGv t0 = tcg_temp_new(); @@ -530,6 +531,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, tcg_temp_free(t0); tcg_temp_free(dat); } +#endif #ifdef TARGET_RISCV32 static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, @@ -653,7 +655,7 @@ static void decode_RV32_64C0(DisasContext *ctx) case 7: #if defined(TARGET_RISCV64) /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ - gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2, + gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, GET_C_LD_IMM(ctx->opcode)); #else /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ -- 2.20.1