From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:40344) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gmEnm-0008Sc-1G for qemu-devel@nongnu.org; Wed, 23 Jan 2019 04:26:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gmEnj-0007J9-90 for qemu-devel@nongnu.org; Wed, 23 Jan 2019 04:26:28 -0500 From: Bastian Koppelmann Date: Wed, 23 Jan 2019 10:25:07 +0100 Message-Id: <20190123092538.8004-5-kbastian@mail.uni-paderborn.de> In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> References: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v6 04/35] target/riscv: Convert RV32I load/store insns to decodetree List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, Alistair Francis Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 10 ++++++ target/riscv/insn_trans/trans_rvi.inc.c | 48 +++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 81f56c16b4..076de873c4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -23,6 +23,7 @@ # immediates: %imm_i 20:s12 +%imm_s 25:s7 7:5 %imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 %imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 %imm_u 12:s20 !function=ex_shift_12 @@ -33,6 +34,7 @@ # Formats 32: @i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 +@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1 @u .................... ..... ....... imm=%imm_u %rd @j .................... ..... ....... imm=%imm_j %rd @@ -47,3 +49,11 @@ blt ....... ..... ..... 100 ..... 1100011 @b bge ....... ..... ..... 101 ..... 1100011 @b bltu ....... ..... ..... 110 ..... 1100011 @b bgeu ....... ..... ..... 111 ..... 1100011 @b +lb ............ ..... 000 ..... 0000011 @i +lh ............ ..... 001 ..... 0000011 @i +lw ............ ..... 010 ..... 0000011 @i +lbu ............ ..... 100 ..... 0000011 @i +lhu ............ ..... 101 ..... 0000011 @i +sb ....... ..... ..... 000 ..... 0100011 @s +sh ....... ..... ..... 001 ..... 0100011 @s +sw ....... ..... ..... 010 ..... 0100011 @s diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 0347461ee6..f3b88ebb69 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -82,3 +82,51 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm); return true; } + +static bool trans_lb(DisasContext *ctx, arg_lb *a) +{ + gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lh(DisasContext *ctx, arg_lh *a) +{ + gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lw(DisasContext *ctx, arg_lw *a) +{ + gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lbu(DisasContext *ctx, arg_lbu *a) +{ + gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lhu(DisasContext *ctx, arg_lhu *a) +{ + gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_sb(DisasContext *ctx, arg_sb *a) +{ + gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_sh(DisasContext *ctx, arg_sh *a) +{ + gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_sw(DisasContext *ctx, arg_sw *a) +{ + gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); + return true; +} -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1gmEnr-00007C-UO for mharc-qemu-riscv@gnu.org; Wed, 23 Jan 2019 04:26:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40402) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gmEnp-0008VK-8S for qemu-riscv@nongnu.org; Wed, 23 Jan 2019 04:26:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gmEnn-0007Kt-4K for qemu-riscv@nongnu.org; Wed, 23 Jan 2019 04:26:32 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:58100) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gmEni-0007IO-V1; Wed, 23 Jan 2019 04:26:27 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 telepax) id 1gmEng-00061b-3r; Wed, 23 Jan 2019 10:26:24 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3072077-4; Wed, 23 Jan 2019 09:26:22 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, Alistair Francis Date: Wed, 23 Jan 2019 10:25:07 +0100 Message-Id: <20190123092538.8004-5-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> References: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.23.91816, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-riscv] [PATCH v6 04/35] target/riscv: Convert RV32I load/store insns to decodetree X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Jan 2019 09:26:34 -0000 Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 10 ++++++ target/riscv/insn_trans/trans_rvi.inc.c | 48 +++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 81f56c16b4..076de873c4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -23,6 +23,7 @@ # immediates: %imm_i 20:s12 +%imm_s 25:s7 7:5 %imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 %imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 %imm_u 12:s20 !function=ex_shift_12 @@ -33,6 +34,7 @@ # Formats 32: @i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 +@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1 @u .................... ..... ....... imm=%imm_u %rd @j .................... ..... ....... imm=%imm_j %rd @@ -47,3 +49,11 @@ blt ....... ..... ..... 100 ..... 1100011 @b bge ....... ..... ..... 101 ..... 1100011 @b bltu ....... ..... ..... 110 ..... 1100011 @b bgeu ....... ..... ..... 111 ..... 1100011 @b +lb ............ ..... 000 ..... 0000011 @i +lh ............ ..... 001 ..... 0000011 @i +lw ............ ..... 010 ..... 0000011 @i +lbu ............ ..... 100 ..... 0000011 @i +lhu ............ ..... 101 ..... 0000011 @i +sb ....... ..... ..... 000 ..... 0100011 @s +sh ....... ..... ..... 001 ..... 0100011 @s +sw ....... ..... ..... 010 ..... 0100011 @s diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 0347461ee6..f3b88ebb69 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -82,3 +82,51 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm); return true; } + +static bool trans_lb(DisasContext *ctx, arg_lb *a) +{ + gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lh(DisasContext *ctx, arg_lh *a) +{ + gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lw(DisasContext *ctx, arg_lw *a) +{ + gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lbu(DisasContext *ctx, arg_lbu *a) +{ + gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lhu(DisasContext *ctx, arg_lhu *a) +{ + gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_sb(DisasContext *ctx, arg_sb *a) +{ + gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_sh(DisasContext *ctx, arg_sh *a) +{ + gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_sw(DisasContext *ctx, arg_sw *a) +{ + gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); + return true; +} -- 2.20.1