From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [RFC,v3,1/7] dmaengine: Add Synopsys eDMA IP core driver From: Vinod Koul Message-Id: <20190123130829.GQ4635@vkoul-mobl> Date: Wed, 23 Jan 2019 18:38:29 +0530 To: Gustavo Pimentel Cc: "linux-pci@vger.kernel.org" , "dmaengine@vger.kernel.org" , Dan Williams , Eugeniy Paltsev , Andy Shevchenko , Russell King , Niklas Cassel , Joao Pinto , Jose Abreu , Luis Oliveira , Vitor Soares , Nelson Costa , Pedro Sousa List-ID: T24gMjEtMDEtMTksIDE1OjQ4LCBHdXN0YXZvIFBpbWVudGVsIHdyb3RlOgo+IE9uIDIwLzAxLzIw MTkgMTE6NDQsIFZpbm9kIEtvdWwgd3JvdGU6Cj4gPiBPbiAxMS0wMS0xOSwgMTk6MzMsIEd1c3Rh dm8gUGltZW50ZWwgd3JvdGU6Cj4gPj4gQWRkIFN5bm9wc3lzIGVETUEgSVAgY29yZSBkcml2ZXIg dG8ga2VybmVsLgo+ID4+Cj4gPj4gVGhpcyBjb3JlIGRyaXZlciwgaW5pdGlhbGl6ZXMgYW5kIGNv bmZpZ3VyZXMgdGhlIGVETUEgSVAgdXNpbmcgdm1hLWhlbHBlcnMKPiA+PiBmdW5jdGlvbnMgYW5k IGRtYS1lbmdpbmUgc3Vic3lzdGVtLgo+ID4gCj4gPiBBIGRlc2NyaXB0aW9uIG9mIGVETUEgSVAg d2lsbCBoZWxwIHJldmlldyB0aGUgZHJpdmVyCj4gCj4gSSd2ZSB0aGUgSVAgZGVzY3JpcHRpb24g b24gdGhlIGNvdmVyLWxldHRlciwgYnV0IEknbGwgYnJpbmcgaXQgdG8gdGhpcyBwYXRjaCwgaWYK PiBpdCBoZWxwcy4KCnllYWggY292ZXIgZG9lc250IGdldCBhcHBsaWVkLCBjaGFuZ2Vsb2cgYXJl IHZlcnkgaW1wb3J0YW50CmRvY3VtZW50YXRpb24gZm9yIGtlcm5lbAoKPiA+PiBAQCAtMCwwICsx LDEwNTkgQEAKPiA+PiArLy8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAKPiA+PiAr LyoKPiA+PiArICogQ29weXJpZ2h0IChjKSAyMDE4IFN5bm9wc3lzLCBJbmMuIGFuZC9vciBpdHMg YWZmaWxpYXRlcy4KPiA+IAo+ID4gMjAxOSBub3cKPiAKPiBJJ3ZlIGNoYW5nZWQgdG8gIkNvcHly aWdodCAoYykgMjAxOC1wcmVzZW50IFN5bm9wc3lzLCBJbmMuIGFuZC9vciBpdHMKPiBhZmZpbGlh dGVzLiIgdGhpcyB3YXkgaXQncyBhbHdheXMgdXAgdG8gZGF0ZSBhbmQgSSBhbHNvIGtlcHQgMjAx OCwgYmVjYXVzZSBpdAo+IHdhcyB0aGUgZGF0ZSB0aGF0IEkgc3RhcnRlZCB0byBkZXZlbG9wIHRo aXMgZHJpdmVyLCBpZiB5b3UgZG9uJ3QgbWluZC4KCnllYWggMTggaXMgZmluZSA6KSBpdCBuZWVk IHRvIGVuZCB3aXRoIGN1cnJlbnQgeWVhciBhbHdheXMKCj4gPj4gK3N0YXRpYyBzdHJ1Y3QgZHdf ZWRtYV9jaHVuayAqZHdfZWRtYV9hbGxvY19jaHVuayhzdHJ1Y3QgZHdfZWRtYV9kZXNjICpkZXNj KQo+ID4+ICt7Cj4gPj4gKwlzdHJ1Y3QgZHdfZWRtYV9jaGFuICpjaGFuID0gZGVzYy0+Y2hhbjsK PiA+PiArCXN0cnVjdCBkd19lZG1hICpkdyA9IGNoYW4tPmNoaXAtPmR3Owo+ID4+ICsJc3RydWN0 IGR3X2VkbWFfY2h1bmsgKmNodW5rOwo+ID4+ICsKPiA+PiArCWNodW5rID0ga3Z6YWxsb2Moc2l6 ZW9mKCpjaHVuayksIEdGUF9OT1dBSVQpOwo+ID4+ICsJaWYgKHVubGlrZWx5KCFjaHVuaykpCj4g Pj4gKwkJcmV0dXJuIE5VTEw7Cj4gPj4gKwo+ID4+ICsJSU5JVF9MSVNUX0hFQUQoJmNodW5rLT5s aXN0KTsKPiA+PiArCWNodW5rLT5jaGFuID0gY2hhbjsKPiA+PiArCWNodW5rLT5jYiA9ICEoZGVz Yy0+Y2h1bmtzX2FsbG9jICUgMik7Cj4gPiAKPiA+IGNiIC4uPwo+IAo+IENCID0gY2hhbmdlIGJp dCwgaXMgYSBwcm9wZXJ0eSBvZiB0aGlzIGVETUEgSVAuIEJhc2ljYWxseSBpdCBpcyBhIGtpbmQg b2YKPiBoYW5kc2hha2Ugd2hpY2ggc2VydmVzIHRvIHZhbGlkYXRlIHdoZXRoZXIgdGhlIGxpbmtl ZCBsaXN0IGhhcyBiZWVuIHVwZGF0ZWQgb3IKPiBub3QsIGVzcGVjaWFsbHkgdXNlZnVsIGluIGNh c2VzIG9mIHJlY3ljbGVkIGxpbmtlZCBsaXN0IGVsZW1lbnRzIChldmVyeSBsaW5rZWQKPiBsaXN0 IHJlY3ljbGUgaXMgYSBuZXcgY2h1bmssIHRoaXMgd2lsbCBhbGxvdyB0byBkaWZmZXJlbnRpYXRl IGVhY2ggY2h1bmspLgoKb2theSBwbGVhc2UgYWRkIHRoYXQgc29tZXdoZXJlLiBBbHNvIGl0IHdv dWxkIGhlbHAgbWUgaWYgeW91IGV4cGxhaW4Kd2hhdCBpcyBjaHVuayBhbmQgb3RoZXIgdGVybWlu b2xvZ2llcyB1c2VkIGluIHRoaXMgZHJpdmVyCgo+ID4+ICtzdGF0aWMgaW50IGR3X2VkbWFfZGV2 aWNlX2NvbmZpZyhzdHJ1Y3QgZG1hX2NoYW4gKmRjaGFuLAo+ID4+ICsJCQkJIHN0cnVjdCBkbWFf c2xhdmVfY29uZmlnICpjb25maWcpCj4gPj4gK3sKPiA+PiArCXN0cnVjdCBkd19lZG1hX2NoYW4g KmNoYW4gPSBkY2hhbjJkd19lZG1hX2NoYW4oZGNoYW4pOwo+ID4+ICsJY29uc3Qgc3RydWN0IGR3 X2VkbWFfY29yZV9vcHMgKm9wcyA9IGNoYW4yb3BzKGNoYW4pOwo+ID4+ICsJdW5zaWduZWQgbG9u ZyBmbGFnczsKPiA+PiArCWludCBlcnIgPSAwOwo+ID4+ICsKPiA+PiArCXNwaW5fbG9ja19pcnFz YXZlKCZjaGFuLT52Yy5sb2NrLCBmbGFncyk7Cj4gPj4gKwo+ID4+ICsJaWYgKCFjb25maWcpIHsK PiA+PiArCQllcnIgPSAtRUlOVkFMOwo+ID4+ICsJCWdvdG8gZXJyX2NvbmZpZzsKPiA+PiArCX0K PiA+PiArCj4gPj4gKwlpZiAoY2hhbi0+c3RhdHVzICE9IEVETUFfU1RfSURMRSkgewo+ID4+ICsJ CWRldl9lcnIoY2hhbjJkZXYoY2hhbiksICJjaGFubmVsIGlzIGJ1c3kgb3IgcGF1c2VkXG4iKTsK PiA+PiArCQllcnIgPSAtRVBFUk07Cj4gPiAKPiA+IHRoaXMgaXMgbm90IGNvcnJlY3QgYmVoYXZp b3VyLCBkZXZpY2VfY29uZmlnIGNhbiBiZSBjYWxsZWQgYW55dGltZSBhbmQKPiA+IHZhbHVlcyBj YW4gdGFrZSBhZmZlY3Qgb24gbmV4dCB0cmFuc2FjdGlvbiBzdWJtaXR0ZWQuLgo+IAo+IEh1bSwg SSB0aG91Z2h0IHdlIGNvdWxkIG9ubHkgcmVjb25maWd1cmUgYWZ0ZXIgdHJhbnNmZXIgYmVpbmcg ZmluaXNoZWQuCgpOb3BlLCBhbnl0aW1lLiBUaGV5IHRha2UgZWZmZWN0IGZvciBuZXh0IHByZXBh cmUgd2hlbiB5b3UgdXNlIGl0Cgo+ID4+ICsJZGV2X2RiZyhjaGFuMmRldihjaGFuKSwgImFkZHIo cGh5c2ljYWwpIHNyYz0lcGEsIGRzdD0lcGFcbiIsCj4gPj4gKwkJJmNvbmZpZy0+c3JjX2FkZHIs ICZjb25maWctPmRzdF9hZGRyKTsKPiA+PiArCj4gPj4gKwljaGFuLT5zcmNfYWRkciA9IGNvbmZp Zy0+c3JjX2FkZHI7Cj4gPj4gKwljaGFuLT5kc3RfYWRkciA9IGNvbmZpZy0+ZHN0X2FkZHI7Cj4g Pj4gKwo+ID4+ICsJZXJyID0gb3BzLT5kZXZpY2VfY29uZmlnKGRjaGFuKTsKPiA+IAo+ID4gd2hh dCBkb2VzIHRoaXMgZG8/Cj4gCj4gVGhpcyBpcyBhbiBpbml0aWFsaXphdGlvbiBwcm9jZWR1cmUg dG8gc2V0dXAgaW50ZXJydXB0cyAoZGF0YSBhbmQgYWRkcmVzc2VzKSB0bwo+IGVhY2ggY2hhbm5l bCBvbiB0aGUgZURNQSBJUCwgIGluIG9yZGVyIHRvIGJlIHRyaWdnZXJlZCBhZnRlciB0cmFuc2Zl ciBiZWluZwo+IGNvbXBsZXRlZCBvciBhYm9ydGVkLiBEdWUgdGhlIGZhY3QgdGhlIGNvbmZpZygp IGNhbiBiZSBjYWxsZWQgYXQgYW55dGltZSwKPiBkb2Vzbid0IG1ha2Ugc2Vuc2UgdG8gaGF2ZSB0 aGlzIHByb2NlZHVyZSBoZXJlLCBJJ2xsIG1vdmVkIGl0IHRvIHByb2JlKCkuCgpZZWFoIEkgYW0g bm90IHN0aWxsIGNvbnZpbmNlZCBhYm91dCBoYXZpbmcgYW5vdGhlciBsYXllciEgSGF2ZSB5b3UK dGhvdWdoIGFib3V0IHVzaW5nIGNvbW1vbiBsaWIgZm9yIGNvbW1vbiBwYXJ0cyAuLj8KCj4gPiB0 aGlzIGxvb2tzIGluY29ycmVjdCBpbnRlcnByZXRhdGlvbiB0byBtZS4gVGhlIHN0YXR1cyBpcyB0 byBiZSByZXRyaWV2ZWQKPiA+IGZvciB0aGUgZ2l2ZW4gY29va2llIHBhc3NlZCBhbmQgZ2l2ZW4g dGhhdCB5b3UgZG8gbm90IGV2ZW4gdXNlIHRoaXMKPiA+IGFyZ3VtZW50IHRlbGxzIG1lIHRoYXQg eW91IGhhdmUgdW5kZXJzdG9vZCB0aGlzIGFzICdjaGFubmVsJyBzdGF0dXMKPiA+IHJlcG9ydGlu Zywgd2hpY2ggaXMgbm90IGNvcnJlY3QKPiAKPiBZZXMsIHlvdSdyZSByaWdodCwgbXkgaW50ZXJw cmV0YXRpb24gYXNzdW1lcyB0aGlzIGZ1bmN0aW9uIHJlcG9ydHMKPiBjaGFubmVsL3RyYW5zYWN0 aW9uIHN0YXR1cy4gV2hhdCB3b3VsZCBiZSB0aGUgY29ycmVjdCBpbXBsZW1lbnRhdGlvbj8KPiBT b21ldGhpbmcgbGlrZSB0aGlzPwo+IAo+IHsKPiAJc3RydWN0IGR3X2VkbWFfY2hhbiAqY2hhbiA9 IGRjaGFuMmR3X2VkbWFfY2hhbihkY2hhbik7Cj4gCWNvbnN0IHN0cnVjdCBkd19lZG1hX2NvcmVf b3BzICpvcHMgPSBjaGFuMm9wcyhjaGFuKTsKPiAJc3RydWN0IGR3X2VkbWFfZGVzYyAqZGVzYzsK PiAJc3RydWN0IHZpcnRfZG1hX2Rlc2MgKnZkOwo+IAl1bnNpZ25lZCBsb25nIGZsYWdzOwo+IAll bnVtIGRtYV9zdGF0dXMgcmV0Owo+IAl1MzIgcmVzaWR1ZSA9IDA7Cj4gCj4gCXNwaW5fbG9ja19p cnFzYXZlKCZjaGFuLT52Yy5sb2NrLCBmbGFncyk7Cj4gCj4gCXJldCA9IGRtYV9jb29raWVfc3Rh dHVzKGNoYW4sIGNvb2tpZSwgdHhzdGF0ZSk7Cj4gCWlmIChyZXQgPT0gRE1BX0NPTVBMRVRFKQo+ IAkJZ290byByZXRfc3RhdHVzOwo+IAo+IAl2ZCA9IHZjaGFuX25leHRfZGVzYygmY2hhbi0+dmMp Owo+IAlpZiAoIXZkKQo+IAkJZ290byByZXRfc3RhdHVzOwo+IAo+IAlkZXNjID0gdmQyZHdfZWRt YV9kZXNjKHZkKTsKPiAJaWYgKCFkZXNjKQo+IAkJcmVzaWR1ZSA9IGRlc2MtPmFsbG9jX3N6IC0g ZGVzYy0+eGZlcl9zejsKPiAJCQo+IAlpZiAocmV0ID09IERNQV9JTl9QUk9HUkVTUyAmJiBjaGFu LT5zdGF0dXMgPT0gRURNQV9TVF9QQVVTRSkKPiAJCXJldCA9IERNQV9QQVVTRUQ7Cgp0aGlzIGxv b2tzIGJldHRlciwgcGxlYXNlIGRvIGtlZXAgaW4gbWluZCB0eHN0YXRlIGNhbiBiZSBudWxsLCBz bwpyZXNpZHVlIGNhbG4gY2FuIGJlIHNraXBwZWQKCj4gPj4gK3N0YXRpYyBzdHJ1Y3QgZG1hX2Fz eW5jX3R4X2Rlc2NyaXB0b3IgKgo+ID4+ICtkd19lZG1hX2RldmljZV9wcmVwX3NsYXZlX3NnKHN0 cnVjdCBkbWFfY2hhbiAqZGNoYW4sIHN0cnVjdCBzY2F0dGVybGlzdCAqc2dsLAo+ID4+ICsJCQkg ICAgIHVuc2lnbmVkIGludCBzZ19sZW4sCj4gPj4gKwkJCSAgICAgZW51bSBkbWFfdHJhbnNmZXJf ZGlyZWN0aW9uIGRpcmVjdGlvbiwKPiA+PiArCQkJICAgICB1bnNpZ25lZCBsb25nIGZsYWdzLCB2 b2lkICpjb250ZXh0KQo+ID4+ICt7Cj4gPj4gKwlzdHJ1Y3QgZHdfZWRtYV9jaGFuICpjaGFuID0g ZGNoYW4yZHdfZWRtYV9jaGFuKGRjaGFuKTsKPiA+PiArCXN0cnVjdCBkd19lZG1hX2Rlc2MgKmRl c2M7Cj4gPj4gKwlzdHJ1Y3QgZHdfZWRtYV9jaHVuayAqY2h1bms7Cj4gPj4gKwlzdHJ1Y3QgZHdf ZWRtYV9idXJzdCAqYnVyc3Q7Cj4gPj4gKwlzdHJ1Y3Qgc2NhdHRlcmxpc3QgKnNnOwo+ID4+ICsJ dW5zaWduZWQgbG9uZyBzZmxhZ3M7Cj4gPj4gKwlwaHlzX2FkZHJfdCBzcmNfYWRkcjsKPiA+PiAr CXBoeXNfYWRkcl90IGRzdF9hZGRyOwo+ID4+ICsJaW50IGk7Cj4gPj4gKwo+ID4+ICsJaWYgKHNn X2xlbiA8IDEpIHsKPiA+PiArCQlkZXZfZXJyKGNoYW4yZGV2KGNoYW4pLCAiaW52YWxpZCBzZyBs ZW5ndGggJXVcbiIsIHNnX2xlbik7Cj4gPj4gKwkJcmV0dXJuIE5VTEw7Cj4gPj4gKwl9Cj4gPj4g Kwo+ID4+ICsJaWYgKGRpcmVjdGlvbiA9PSBETUFfREVWX1RPX01FTSAmJiBjaGFuLT5kaXIgPT0g RURNQV9ESVJfV1JJVEUpIHsKPiA+IAo+ID4gd2hhdCBpcyB0aGUgc2Vjb25kIHBhcnQgb2YgdGhl IGNoZWNrLCBjYW4geW91IGV4cGxhaW4gdGhhdCwgd2hvIHNldHMKPiA+IGNoYW4tPmRpcj8KPiAK PiBUaGUgY2hhbi0+ZGlyIGlzIHNldCBvbiBwcm9iZSgpIGR1cmluZyB0aGUgcHJvY2VzcyBvZiBj b25maWd1cmluZyBlYWNoIGNoYW5uZWwuCgpTbyB5b3UgaGF2ZSBjaGFubmVscyB0aGF0IGFyZSB1 bmlkaXJlY3Rpb25hbD8KCj4gPj4gKwkJZGV2X2RiZyhjaGFuMmRldihjaGFuKSwJInByZXBhcmUg b3BlcmF0aW9uIChXUklURSlcbiIpOwo+ID4+ICsJfSBlbHNlIGlmIChkaXJlY3Rpb24gPT0gRE1B X01FTV9UT19ERVYgJiYgY2hhbi0+ZGlyID09IEVETUFfRElSX1JFQUQpIHsKPiA+PiArCQlkZXZf ZGJnKGNoYW4yZGV2KGNoYW4pLAkicHJlcGFyZSBvcGVyYXRpb24gKFJFQUQpXG4iKTsKPiA+PiAr CX0gZWxzZSB7Cj4gPj4gKwkJZGV2X2VycihjaGFuMmRldihjaGFuKSwgImludmFsaWQgZGlyZWN0 aW9uXG4iKTsKPiA+PiArCQlyZXR1cm4gTlVMTDsKPiA+PiArCX0KPiA+PiArCj4gPj4gKwlpZiAo IWNoYW4tPmNvbmZpZ3VyZWQpIHsKPiA+PiArCQlkZXZfZXJyKGNoYW4yZGV2KGNoYW4pLCAiKHBy ZXBfc2xhdmVfc2cpIGNoYW5uZWwgbm90IGNvbmZpZ3VyZWRcbiIpOwo+ID4+ICsJCXJldHVybiBO VUxMOwo+ID4+ICsJfQo+ID4+ICsKPiA+PiArCWlmIChjaGFuLT5zdGF0dXMgIT0gRURNQV9TVF9J RExFKSB7Cj4gPj4gKwkJZGV2X2VycihjaGFuMmRldihjaGFuKSwgImNoYW5uZWwgaXMgYnVzeSBv ciBwYXVzZWRcbiIpOwo+ID4+ICsJCXJldHVybiBOVUxMOwo+ID4+ICsJfQo+ID4gCj4gPiBObywg d3JvbmcgYWdhaW4uIFRoZSB0eG4gbXVzdCBiZSBwcmVwYXJlZCBhbmQgdGhlbiBvbiBzdWJtaXQg YWRkZWQgdG8gYQo+ID4gcXVldWUuIFlvdSBhcmUgd3JpdGluZyBhIGRyaXZlciBmb3IgZG1hZW5n aW5lLCBzdXJlbHkgeW91IGRvbnQgZXhwZWN0Cj4gPiB0aGUgY2hhbm5lbCB0byBiZSBmcmVlIGFu ZCB0aGVuIGRvIGEgdHhuLi4gdGhhdCB3b3VsZCBiZSB2ZXJ5Cj4gPiBpbmVmZmljaWVudCEKPiAK PiBJIGRpZCBub3QgcmVhbGl6ZSB0aGF0IHRoZSBmbG93IGNvdWxkIGJlIGFzIHlvdSBtZW50aW9u ZWQuIFRoZSBkb2N1bWVudGF0aW9uIEkKPiByZWFkIGFib3V0IHRoZSBzdWJzeXN0ZW0gZGlkIG5v dCBnaXZlIG1lIHRoaXMgaWRlYS4gVGhhbmsgeW91IGZvciBjbGFyaWZ5aW5nIG1lLgoKSSB0aGlu ayB3ZSBoYXZlIGltcHJvdmVkICB0aGF0IHBhcnQgYSBsb3QsIHBsZWFzZSBkbyBmZWVsIGZyZWUg dG8gcG9pbnQKb3V0IGluY29uc2lzdGVuY3kKU2VlIERNQSB1c2FnZSBpbiBEb2N1bWVudGF0aW9u L2RyaXZlci1hcGkvZG1hZW5naW5lL2NsaWVudC5yc3QKCj4gPj4gK2ludCBkd19lZG1hX3Byb2Jl KHN0cnVjdCBkd19lZG1hX2NoaXAgKmNoaXApCj4gPj4gK3sKPiA+PiArCXN0cnVjdCBkd19lZG1h ICpkdyA9IGNoaXAtPmR3Owo+ID4+ICsJc3RydWN0IGRldmljZSAqZGV2ID0gY2hpcC0+ZGV2Owo+ ID4+ICsJY29uc3Qgc3RydWN0IGR3X2VkbWFfY29yZV9vcHMgKm9wczsKPiA+PiArCXNpemVfdCBs bF9jaHVuayA9IGR3LT5sbF9yZWdpb24uc3o7Cj4gPj4gKwlzaXplX3QgZHRfY2h1bmsgPSBkdy0+ ZHRfcmVnaW9uLnN6Owo+ID4+ICsJdTMyIGNoX3RvdDsKPiA+PiArCWludCBpLCBqLCBlcnI7Cj4g Pj4gKwo+ID4+ICsJcmF3X3NwaW5fbG9ja19pbml0KCZkdy0+bG9jayk7Cj4gPj4gKwo+ID4+ICsJ LyogQ2FsbGJhY2sgb3BlcmF0aW9uIHNlbGVjdGlvbiBhY2NvcmRpbmdseSB0byBlRE1BIHZlcnNp b24gKi8KPiA+PiArCXN3aXRjaCAoZHctPnZlcnNpb24pIHsKPiA+PiArCWRlZmF1bHQ6Cj4gPj4g KwkJZGV2X2VycihkZXYsICJ1bnN1cHBvcnRlZCB2ZXJzaW9uXG4iKTsKPiA+PiArCQlyZXR1cm4g LUVQRVJNOwo+ID4+ICsJfQo+ID4gCj4gPiBTbyB3ZSBoYXZlIG9ubHkgb25lIGNhc2Ugd2hpY2gg cmV0dXJucyBlcnJvciwgd2FzIHRoaXMgY29kZSB0ZXN0ZWQ/Cj4gCj4gWWVzIGl0IHdhcywgYnV0 IEkgdW5kZXJzdGFuZCB3aGF0IHlvdXIgcG9pbnQgb2Ygdmlldy4KPiBUaGlzIHdhcyBkb25lIGxp a2UgdGhpcywgYmVjYXVzZSBJIHdhbm5hIHRvIHNlZ21lbnQgdGhlIHBhdGNoIHNlcmllcyBsaWtl IHRoaXM6Cj4gIDEpIEFkZGluZyBlRE1BIGRyaXZlciBjb3JlLCB3aGljaCBjb250YWlucyB0aGUg ZHJpdmVyIHNrZWxldG9uIGFuZCB0aGUgd2hvbGUKPiBsb2dpYyBhc3NvY2lhdGVkLgo+ICAyKSBh bmQgMykgQWRkaW5nIHRoZSBjYWxsYmFja3MgZm9yIHRoZSBlRE1BIHJlZ2lzdGVyIG1hcHBpbmcg dmVyc2lvbiAwIChpdCB3aWxsCj4gYXBwZWFyIGluIHRoZSBmdXR1cmUgYSBuZXcgdmVyc2lvbiwg SSB0aG91Z2h0IHRoYXQgdGhpcyBuZXcgdmVyc2lvbiB3b3VsZCBjYW1lCj4gd2hpbGUgSSB3YXMg dHJ5aW5nIHRvIGdldCB0aGUgZmVlZGJhY2sgYWJvdXQgdGhpcyBwYXRjaCBzZXJpZXMsIHRoZXJl Zm9yZSB3b3VsZAo+IGhhdmUgYW5vdGhlciAyIHBhdGNoZXMgZm9yIHRoZSB2ZXJzaW9uIDEgaXNv bGF0ZWQgYW5kIGluZGVwZW5kZW50IGZyb20gdGhlCj4gdmVyc2lvbiAwKS4KPiAgNCkgYW5kIDUp IEFkZGluZyB0aGUgUENJZSBnbHVlLWxvZ2ljIGFuZCBkZXZpY2UgSUQgYXNzb2NpYXRlZC4KPiAg NikgQWRkaW5nIG1haW50YWluZXIgZm9yIHRoaXMgZHJpdmVyLgo+ICA3KSBBZGRpbmcgYSB0ZXN0 IGRyaXZlci4KPiAKPiBTaW5jZSB0aGlzIHN3aXRjaCB3aWxsIG9ubHkgaGF2ZSB0aGUgYXNzb2Np YXRlZCBjYXNlIG9uIHBhdGNoIDIsIHRoYXQgd2h5IG9uCj4gcGF0Y2ggMSBkb2Vzbid0IGFwcGVh ciBhbnkgcG9zc2liaWxpdHkuCj4gCj4gSWYgeW91IGZlZWwgbG9naWMgdG8gc3F1YXNoIHBhdGNo IDIgd2l0aCBwYXRjaCAxLCBqdXN0IHNheSBzb21ldGhpbmcgYW5kIEknbGwgZG8KPiBpdCBmb3Ig eW91IDopCgp3ZWxsIGVhY2ggcGF0Y2ggc2hvdWxkIGJ1aWxkIGFuZCB3b3JrIG9uIGl0cyBvd24s IG90aGVyd2lzZSB3ZSBnZXQKcHJvYmxlbXMgOikgQnV0IHNpbmNlIHRoaXMgaXMgYSBuZXcgZHJp dmVyIGl0IGlzIG9rYXkuIEFueXdheSB0aGlzIHBhdGNoCmlzIHF1aXRlIF9odWdlXyBzbyBsZXRz IG5vdCBhZGQgbW9yZSB0byBpdC4uCgpJIHdvdWxkIGhhdmUgbW92ZWQgdGhlIGNhbGxiYWNrIGNo ZWNrIHRvIHN1YnNlcXVlbnQgb25lLi4KCj4gPj4gKwlwbV9ydW50aW1lX2dldF9zeW5jKGRldik7 Cj4gPj4gKwo+ID4+ICsJLyogRmluZCBvdXQgaG93IG1hbnkgd3JpdGUgY2hhbm5lbHMgYXJlIHN1 cHBvcnRlZCBieSBoYXJkd2FyZSAqLwo+ID4+ICsJZHctPndyX2NoX2NudCA9IG9wcy0+Y2hfY291 bnQoZHcsIEVETUFfRElSX1dSSVRFKTsKPiA+PiArCWlmICghZHctPndyX2NoX2NudCkgewo+ID4+ ICsJCWRldl9lcnIoZGV2LCAiaW52YWxpZCBudW1iZXIgb2Ygd3JpdGUgY2hhbm5lbHMoMClcbiIp Owo+ID4+ICsJCXJldHVybiAtRUlOVkFMOwo+ID4+ICsJfQo+ID4+ICsKPiA+PiArCS8qIEZpbmQg b3V0IGhvdyBtYW55IHJlYWQgY2hhbm5lbHMgYXJlIHN1cHBvcnRlZCBieSBoYXJkd2FyZSAqLwo+ ID4+ICsJZHctPnJkX2NoX2NudCA9IG9wcy0+Y2hfY291bnQoZHcsIEVETUFfRElSX1JFQUQpOwo+ ID4+ICsJaWYgKCFkdy0+cmRfY2hfY250KSB7Cj4gPj4gKwkJZGV2X2VycihkZXYsICJpbnZhbGlk IG51bWJlciBvZiByZWFkIGNoYW5uZWxzKDApXG4iKTsKPiA+PiArCQlyZXR1cm4gLUVJTlZBTDsK PiA+PiArCX0KPiA+PiArCj4gPj4gKwlkZXZfZGJnKGRldiwgIkNoYW5uZWxzOlx0d3JpdGU9JWQs IHJlYWQ9JWRcbiIsCj4gPj4gKwkJZHctPndyX2NoX2NudCwgZHctPnJkX2NoX2NudCk7Cj4gPj4g Kwo+ID4+ICsJY2hfdG90ID0gZHctPndyX2NoX2NudCArIGR3LT5yZF9jaF9jbnQ7Cj4gPj4gKwo+ ID4+ICsJLyogQWxsb2NhdGUgY2hhbm5lbHMgKi8KPiA+PiArCWR3LT5jaGFuID0gZGV2bV9rY2Fs bG9jKGRldiwgY2hfdG90LCBzaXplb2YoKmR3LT5jaGFuKSwgR0ZQX0tFUk5FTCk7Cj4gPiAKPiA+ IHlvdSBtYXkgdXNlIHN0cnVjdF9zaXplKCkgaGVyZQo+IAo+IEh1bSwgdGhpcyB3b3VsZCBiZSB1 c2VmdWwgaWYgSSB3YW50ZWQgdG8gYWxsb2NhdGUgdGhlIGR3IHN0cnVjdCBhcyB3ZWxsLCByaWdo dD8KPiBTaW5jZSBkdyBzdHJ1Y3QgaXMgYWxyZWFkeSBhbGxvY2F0ZWQsIGl0IGxvb2tzIGxpa2Ug dGhpcyBjYW4ndCBiZSB1c2VkLCBvciBhbSBJCj4gbWlzc2luZyBzb21ldGhpbmc/Cgp5ZWFoIHlv dSBjYW4gYWxsb2NhdGUgZHcgKyBjaGFuIG9uZSBzaG90Li4uCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6798CC282C0 for ; Wed, 23 Jan 2019 13:10:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 20FF22133D for ; Wed, 23 Jan 2019 13:10:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548249004; bh=o6DQUVz+6vCdivvnlinheFVyKFvCfnt6SQmN2iiwEcM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=zPaD0i0ngoO7/FZrOW7m/WdYf7dIlJEgkMSEQT0UucZlN4XQGEnv4spu6wdHljgzR wslLdBSosa0zt5eS4RVh1niJrV6d+6jxdcrMvPnMtYFhuDarsPlE+8gbkox765LWbA fRD76c+K5cxSq0YWvOUCMnF0xuiikc7tRfF7fk7s= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726057AbfAWNKD (ORCPT ); Wed, 23 Jan 2019 08:10:03 -0500 Received: from mail.kernel.org ([198.145.29.99]:42362 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725995AbfAWNKD (ORCPT ); Wed, 23 Jan 2019 08:10:03 -0500 Received: from localhost (unknown [106.200.229.238]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4C43620855; Wed, 23 Jan 2019 13:10:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548249002; bh=o6DQUVz+6vCdivvnlinheFVyKFvCfnt6SQmN2iiwEcM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=is3FyitpmqwQgU/oWNtZNc5uVkOi4mJrhIpsJiWIuyclapbpTZwJ89AO/dR9wjOJo cB4OSghVsnzDs7UY2m63Tq53mNzThrUamvRpF48lDXe2vCFReltceFqBAR9wleiFWN 3/ZwvyEuptq/LRfTOl1phWr0FXZF8p15+K+mgYf0= Date: Wed, 23 Jan 2019 18:38:29 +0530 From: Vinod Koul To: Gustavo Pimentel Cc: "linux-pci@vger.kernel.org" , "dmaengine@vger.kernel.org" , Dan Williams , Eugeniy Paltsev , Andy Shevchenko , Russell King , Niklas Cassel , Joao Pinto , Jose Abreu , Luis Oliveira , Vitor Soares , Nelson Costa , Pedro Sousa Subject: Re: [RFC v3 1/7] dmaengine: Add Synopsys eDMA IP core driver Message-ID: <20190123130829.GQ4635@vkoul-mobl> References: <20190120114425.GV4635@vkoul-mobl> <14acfcee-b367-be9c-714b-de0508ff1a7d@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <14acfcee-b367-be9c-714b-de0508ff1a7d@synopsys.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 21-01-19, 15:48, Gustavo Pimentel wrote: > On 20/01/2019 11:44, Vinod Koul wrote: > > On 11-01-19, 19:33, Gustavo Pimentel wrote: > >> Add Synopsys eDMA IP core driver to kernel. > >> > >> This core driver, initializes and configures the eDMA IP using vma-helpers > >> functions and dma-engine subsystem. > > > > A description of eDMA IP will help review the driver > > I've the IP description on the cover-letter, but I'll bring it to this patch, if > it helps. yeah cover doesnt get applied, changelog are very important documentation for kernel > >> @@ -0,0 +1,1059 @@ > >> +// SPDX-License-Identifier: GPL-2.0 > >> +/* > >> + * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. > > > > 2019 now > > I've changed to "Copyright (c) 2018-present Synopsys, Inc. and/or its > affiliates." this way it's always up to date and I also kept 2018, because it > was the date that I started to develop this driver, if you don't mind. yeah 18 is fine :) it need to end with current year always > >> +static struct dw_edma_chunk *dw_edma_alloc_chunk(struct dw_edma_desc *desc) > >> +{ > >> + struct dw_edma_chan *chan = desc->chan; > >> + struct dw_edma *dw = chan->chip->dw; > >> + struct dw_edma_chunk *chunk; > >> + > >> + chunk = kvzalloc(sizeof(*chunk), GFP_NOWAIT); > >> + if (unlikely(!chunk)) > >> + return NULL; > >> + > >> + INIT_LIST_HEAD(&chunk->list); > >> + chunk->chan = chan; > >> + chunk->cb = !(desc->chunks_alloc % 2); > > > > cb ..? > > CB = change bit, is a property of this eDMA IP. Basically it is a kind of > handshake which serves to validate whether the linked list has been updated or > not, especially useful in cases of recycled linked list elements (every linked > list recycle is a new chunk, this will allow to differentiate each chunk). okay please add that somewhere. Also it would help me if you explain what is chunk and other terminologies used in this driver > >> +static int dw_edma_device_config(struct dma_chan *dchan, > >> + struct dma_slave_config *config) > >> +{ > >> + struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan); > >> + const struct dw_edma_core_ops *ops = chan2ops(chan); > >> + unsigned long flags; > >> + int err = 0; > >> + > >> + spin_lock_irqsave(&chan->vc.lock, flags); > >> + > >> + if (!config) { > >> + err = -EINVAL; > >> + goto err_config; > >> + } > >> + > >> + if (chan->status != EDMA_ST_IDLE) { > >> + dev_err(chan2dev(chan), "channel is busy or paused\n"); > >> + err = -EPERM; > > > > this is not correct behaviour, device_config can be called anytime and > > values can take affect on next transaction submitted.. > > Hum, I thought we could only reconfigure after transfer being finished. Nope, anytime. They take effect for next prepare when you use it > >> + dev_dbg(chan2dev(chan), "addr(physical) src=%pa, dst=%pa\n", > >> + &config->src_addr, &config->dst_addr); > >> + > >> + chan->src_addr = config->src_addr; > >> + chan->dst_addr = config->dst_addr; > >> + > >> + err = ops->device_config(dchan); > > > > what does this do? > > This is an initialization procedure to setup interrupts (data and addresses) to > each channel on the eDMA IP, in order to be triggered after transfer being > completed or aborted. Due the fact the config() can be called at anytime, > doesn't make sense to have this procedure here, I'll moved it to probe(). Yeah I am not still convinced about having another layer! Have you though about using common lib for common parts ..? > > this looks incorrect interpretation to me. The status is to be retrieved > > for the given cookie passed and given that you do not even use this > > argument tells me that you have understood this as 'channel' status > > reporting, which is not correct > > Yes, you're right, my interpretation assumes this function reports > channel/transaction status. What would be the correct implementation? > Something like this? > > { > struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan); > const struct dw_edma_core_ops *ops = chan2ops(chan); > struct dw_edma_desc *desc; > struct virt_dma_desc *vd; > unsigned long flags; > enum dma_status ret; > u32 residue = 0; > > spin_lock_irqsave(&chan->vc.lock, flags); > > ret = dma_cookie_status(chan, cookie, txstate); > if (ret == DMA_COMPLETE) > goto ret_status; > > vd = vchan_next_desc(&chan->vc); > if (!vd) > goto ret_status; > > desc = vd2dw_edma_desc(vd); > if (!desc) > residue = desc->alloc_sz - desc->xfer_sz; > > if (ret == DMA_IN_PROGRESS && chan->status == EDMA_ST_PAUSE) > ret = DMA_PAUSED; this looks better, please do keep in mind txstate can be null, so residue caln can be skipped > >> +static struct dma_async_tx_descriptor * > >> +dw_edma_device_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, > >> + unsigned int sg_len, > >> + enum dma_transfer_direction direction, > >> + unsigned long flags, void *context) > >> +{ > >> + struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan); > >> + struct dw_edma_desc *desc; > >> + struct dw_edma_chunk *chunk; > >> + struct dw_edma_burst *burst; > >> + struct scatterlist *sg; > >> + unsigned long sflags; > >> + phys_addr_t src_addr; > >> + phys_addr_t dst_addr; > >> + int i; > >> + > >> + if (sg_len < 1) { > >> + dev_err(chan2dev(chan), "invalid sg length %u\n", sg_len); > >> + return NULL; > >> + } > >> + > >> + if (direction == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_WRITE) { > > > > what is the second part of the check, can you explain that, who sets > > chan->dir? > > The chan->dir is set on probe() during the process of configuring each channel. So you have channels that are unidirectional? > >> + dev_dbg(chan2dev(chan), "prepare operation (WRITE)\n"); > >> + } else if (direction == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_READ) { > >> + dev_dbg(chan2dev(chan), "prepare operation (READ)\n"); > >> + } else { > >> + dev_err(chan2dev(chan), "invalid direction\n"); > >> + return NULL; > >> + } > >> + > >> + if (!chan->configured) { > >> + dev_err(chan2dev(chan), "(prep_slave_sg) channel not configured\n"); > >> + return NULL; > >> + } > >> + > >> + if (chan->status != EDMA_ST_IDLE) { > >> + dev_err(chan2dev(chan), "channel is busy or paused\n"); > >> + return NULL; > >> + } > > > > No, wrong again. The txn must be prepared and then on submit added to a > > queue. You are writing a driver for dmaengine, surely you dont expect > > the channel to be free and then do a txn.. that would be very > > inefficient! > > I did not realize that the flow could be as you mentioned. The documentation I > read about the subsystem did not give me this idea. Thank you for clarifying me. I think we have improved that part a lot, please do feel free to point out inconsistency See DMA usage in Documentation/driver-api/dmaengine/client.rst > >> +int dw_edma_probe(struct dw_edma_chip *chip) > >> +{ > >> + struct dw_edma *dw = chip->dw; > >> + struct device *dev = chip->dev; > >> + const struct dw_edma_core_ops *ops; > >> + size_t ll_chunk = dw->ll_region.sz; > >> + size_t dt_chunk = dw->dt_region.sz; > >> + u32 ch_tot; > >> + int i, j, err; > >> + > >> + raw_spin_lock_init(&dw->lock); > >> + > >> + /* Callback operation selection accordingly to eDMA version */ > >> + switch (dw->version) { > >> + default: > >> + dev_err(dev, "unsupported version\n"); > >> + return -EPERM; > >> + } > > > > So we have only one case which returns error, was this code tested? > > Yes it was, but I understand what your point of view. > This was done like this, because I wanna to segment the patch series like this: > 1) Adding eDMA driver core, which contains the driver skeleton and the whole > logic associated. > 2) and 3) Adding the callbacks for the eDMA register mapping version 0 (it will > appear in the future a new version, I thought that this new version would came > while I was trying to get the feedback about this patch series, therefore would > have another 2 patches for the version 1 isolated and independent from the > version 0). > 4) and 5) Adding the PCIe glue-logic and device ID associated. > 6) Adding maintainer for this driver. > 7) Adding a test driver. > > Since this switch will only have the associated case on patch 2, that why on > patch 1 doesn't appear any possibility. > > If you feel logic to squash patch 2 with patch 1, just say something and I'll do > it for you :) well each patch should build and work on its own, otherwise we get problems :) But since this is a new driver it is okay. Anyway this patch is quite _huge_ so lets not add more to it.. I would have moved the callback check to subsequent one.. > >> + pm_runtime_get_sync(dev); > >> + > >> + /* Find out how many write channels are supported by hardware */ > >> + dw->wr_ch_cnt = ops->ch_count(dw, EDMA_DIR_WRITE); > >> + if (!dw->wr_ch_cnt) { > >> + dev_err(dev, "invalid number of write channels(0)\n"); > >> + return -EINVAL; > >> + } > >> + > >> + /* Find out how many read channels are supported by hardware */ > >> + dw->rd_ch_cnt = ops->ch_count(dw, EDMA_DIR_READ); > >> + if (!dw->rd_ch_cnt) { > >> + dev_err(dev, "invalid number of read channels(0)\n"); > >> + return -EINVAL; > >> + } > >> + > >> + dev_dbg(dev, "Channels:\twrite=%d, read=%d\n", > >> + dw->wr_ch_cnt, dw->rd_ch_cnt); > >> + > >> + ch_tot = dw->wr_ch_cnt + dw->rd_ch_cnt; > >> + > >> + /* Allocate channels */ > >> + dw->chan = devm_kcalloc(dev, ch_tot, sizeof(*dw->chan), GFP_KERNEL); > > > > you may use struct_size() here > > Hum, this would be useful if I wanted to allocate the dw struct as well, right? > Since dw struct is already allocated, it looks like this can't be used, or am I > missing something? yeah you can allocate dw + chan one shot... -- ~Vinod