From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CA52C282C0 for ; Fri, 25 Jan 2019 15:34:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1DB19218CD for ; Fri, 25 Jan 2019 15:34:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=crapouillou.net header.i=@crapouillou.net header.b="soYtqeUS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728732AbfAYPeu (ORCPT ); Fri, 25 Jan 2019 10:34:50 -0500 Received: from outils.crapouillou.net ([89.234.176.41]:37812 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726216AbfAYPet (ORCPT ); Fri, 25 Jan 2019 10:34:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1548430485; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=/4J3YlHXv6Gm+iZIgYgrgwLnXzA8EduTqbFj6NcIEe8=; b=soYtqeUSrku81LDlg0kJhyHAmk3RUvmKEXXUNvtKyDPEjnUn5C1uz6igQF8BlT/AvqINSA Oj3CxD/mtq6NNczGPb6nZe/pd1eQjdcecppuHelCxDw5Qh9ZeeR3dw1CYsSh+VokfjxUWq wyEyMt3b5VLjGYWqmVRWI1Dn5rd2BEs= From: Paul Cercueil To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Cercueil Subject: [PATCH] clk: ingenic: jz4740: Fix gating of UDC clock Date: Fri, 25 Jan 2019 12:34:36 -0300 Message-Id: <20190125153436.13517-1-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The UDC clock is gated when the bit is cleared, not when it is set. Signed-off-by: Paul Cercueil Tested-by: Artur Rojek --- drivers/clk/ingenic/jz4740-cgu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index d8ac7f2e183a..5d0d5be1e6a7 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -165,7 +165,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, .mux = { CGU_REG_CPCCR, 29, 1 }, .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, - .gate = { CGU_REG_SCR, 6 }, + .gate = { CGU_REG_SCR, 6, true }, }, /* Gate-only clocks */ -- 2.20.1