From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gage Eads Subject: [PATCH 0/1] Add 128-bit compare and set Date: Mon, 28 Jan 2019 11:29:44 -0600 Message-ID: <20190128172945.27251-1-gage.eads@intel.com> Cc: olivier.matz@6wind.com, arybchenko@solarflare.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, gavin.hu@arm.com, Honnappa.Nagarahalli@arm.com, nd@arm.com, chaozhu@linux.vnet.ibm.com, jerinj@marvell.com, hemant.agrawal@nxp.com To: dev@dpdk.org Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 7D8005942 for ; Mon, 28 Jan 2019 18:29:03 +0100 (CET) List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch addresses x86-64 only; other architectures can/will be supported in the future. The __atomic intrinsic was considered for the implementation, however libatomic was found[1] to use locks to implement the 128-bit CAS on at least one architecture and so is eschewed here. The interface is modeled after the __atomic_compare_exchange_16 (which itself is based on the C++11 memory model) to best support weak consistency architectures. This patch was originally part of a series that introduces a non-blocking stack mempool handler[2], and is required by a non-blocking ring patchset. This patch was spun off so that the the NB ring depends only on this patch and not the entire non-blocking stack patchset. [1] http://mails.dpdk.org/archives/dev/2019-January/124002.html [1] http://mails.dpdk.org/archives/dev/2019-January/123653.html Gage Eads (1): eal: add 128-bit cmpset (x86-64 only) .../common/include/arch/x86/rte_atomic_64.h | 31 +++++++++++ lib/librte_eal/common/include/generic/rte_atomic.h | 65 ++++++++++++++++++++++ 2 files changed, 96 insertions(+) -- 2.13.6