From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:59170) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gog1H-0003WX-91 for qemu-devel@nongnu.org; Tue, 29 Jan 2019 21:54:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gog1F-0000t9-CO for qemu-devel@nongnu.org; Tue, 29 Jan 2019 21:54:31 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:33090) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gog1F-0000sg-2q for qemu-devel@nongnu.org; Tue, 29 Jan 2019 21:54:29 -0500 Received: by mail-pf1-x441.google.com with SMTP id c123so10723567pfb.0 for ; Tue, 29 Jan 2019 18:54:28 -0800 (PST) From: Jim Wilson Date: Tue, 29 Jan 2019 18:54:21 -0800 Message-Id: <20190130025421.12487-1-jimw@sifive.com> In-Reply-To: References: Subject: [Qemu-devel] [PATCH 1/5 v3] RISC-V: Add 32-bit gdb xml files. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Jim Wilson Signed-off-by: Jim Wilson --- configure | 1 + gdb-xml/riscv-32bit-cpu.xml | 43 ++++++++ gdb-xml/riscv-32bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++ gdb-xml/riscv-32bit-fpu.xml | 46 ++++++++ 4 files changed, 340 insertions(+) create mode 100644 gdb-xml/riscv-32bit-cpu.xml create mode 100644 gdb-xml/riscv-32bit-csr.xml create mode 100644 gdb-xml/riscv-32bit-fpu.xml diff --git a/configure b/configure index b18281c..f30369a 100755 --- a/configure +++ b/configure @@ -7283,6 +7283,7 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml" target_compiler=$cross_cc_riscv32 ;; riscv64) diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml new file mode 100644 index 0000000..c02f86c --- /dev/null +++ b/gdb-xml/riscv-32bit-cpu.xml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml new file mode 100644 index 0000000..4aea9e6 --- /dev/null +++ b/gdb-xml/riscv-32bit-csr.xml @@ -0,0 +1,250 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml new file mode 100644 index 0000000..783287d --- /dev/null +++ b/gdb-xml/riscv-32bit-fpu.xml @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1gog1K-0003Wm-U0 for mharc-qemu-riscv@gnu.org; Tue, 29 Jan 2019 21:54:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59168) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gog1H-0003WW-6B for qemu-riscv@nongnu.org; Tue, 29 Jan 2019 21:54:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gog1F-0000t3-Ba for qemu-riscv@nongnu.org; Tue, 29 Jan 2019 21:54:31 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:43099) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gog1F-0000sd-2h for qemu-riscv@nongnu.org; Tue, 29 Jan 2019 21:54:29 -0500 Received: by mail-pf1-x442.google.com with SMTP id w73so10682255pfk.10 for ; Tue, 29 Jan 2019 18:54:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WGpzAMH52urlB+NkjMQjawjTuD++Cbw0M+qM1hEfsUE=; b=iduwR6tlHsbrPGoM2d3854JwjdRKrCToR2XMeiQgJY1f4bpGwjYJh5+vWrcV4c+TcK SB0KoaNIhcVOvq0gqAQsoh9DKdUs/cc9fnD6iqZFeG1BFGRSbeNDVrM1il8ChoUWFlLV v3xvi/JpIiHqmJExZ++BpfM+JoT2y75Ce15kFGOn+CQE37Plu9ZKquSBN6uQvNK4cWE/ Yq04efvi3vtYPXc7D+rL2xPgC952z+YGP/bNs+2LZFI85qu1vAKAPrIhDB1eiSWxIRzg tHMJK2LjmXl0kU20mK/6BG+UvE9GKhaf08+SUeiU95o5QQs3ngNJDx9ChUXWZ8wMOTDd L2lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WGpzAMH52urlB+NkjMQjawjTuD++Cbw0M+qM1hEfsUE=; b=C7hPhA587gOmM5+lYkcX4CEeMcqoYjWbZUCY14UgUhtUI3I4BF7g/O1eW0diHN7kqt /rxK3qSp8XBFZ+sKr4iMwDR6rsMD4eHv1BcI2DeD+6ZeOoYoU0b/Ws7+DoSBV0EBjJO6 KQH2vT68Q8o8urHeubDyp66Q2YTuV07PMhBJxf69Qy7oATckBTyOsgd5MM5FnBHh7Gso IvsTMo/7WLSyW7ElR2aHHDJRgnZ0SZFwuqPcdZJS93Z7PURtcPJuhHOp2cIqT6ypjwSX peoNnxe088ueiD0Eoz1haqfz83+OaVtTSLPOf8NDAMg8OXsqnYq6G1Zm5Mzn8GYczuWm xAdQ== X-Gm-Message-State: AJcUukew89I7FyxAZyHCgBR5tlQT+/J/2Zt6lvvNZsBhR9XflwsdmbYb iqFBp3ohY8PMlxFZfafvHu34lQ== X-Google-Smtp-Source: ALg8bN4TvfHhBRlrw1pI1AZGp9D6IJ2mApPIbWrS+h/7Z/sTvWe3n9qtxMitWuylaTnejIknDfM0yg== X-Received: by 2002:a62:c21c:: with SMTP id l28mr28485449pfg.74.1548816867549; Tue, 29 Jan 2019 18:54:27 -0800 (PST) Received: from rohan.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id t5sm238596pfb.60.2019.01.29.18.54.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Jan 2019 18:54:27 -0800 (PST) From: Jim Wilson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Jim Wilson Date: Tue, 29 Jan 2019 18:54:21 -0800 Message-Id: <20190130025421.12487-1-jimw@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-riscv] [PATCH 1/5 v3] RISC-V: Add 32-bit gdb xml files. X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Jan 2019 02:54:33 -0000 Signed-off-by: Jim Wilson --- configure | 1 + gdb-xml/riscv-32bit-cpu.xml | 43 ++++++++ gdb-xml/riscv-32bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++ gdb-xml/riscv-32bit-fpu.xml | 46 ++++++++ 4 files changed, 340 insertions(+) create mode 100644 gdb-xml/riscv-32bit-cpu.xml create mode 100644 gdb-xml/riscv-32bit-csr.xml create mode 100644 gdb-xml/riscv-32bit-fpu.xml diff --git a/configure b/configure index b18281c..f30369a 100755 --- a/configure +++ b/configure @@ -7283,6 +7283,7 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml" target_compiler=$cross_cc_riscv32 ;; riscv64) diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml new file mode 100644 index 0000000..c02f86c --- /dev/null +++ b/gdb-xml/riscv-32bit-cpu.xml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml new file mode 100644 index 0000000..4aea9e6 --- /dev/null +++ b/gdb-xml/riscv-32bit-csr.xml @@ -0,0 +1,250 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml new file mode 100644 index 0000000..783287d --- /dev/null +++ b/gdb-xml/riscv-32bit-fpu.xml @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- 2.7.4