tree:   git://people.freedesktop.org/~agd5f/linux.git drm-next-5.1-wip
head:   5daa9c4d3d3cf0da1520ad5a814c7f970160194a
commit: 3cec41769d2182e629692a3262cc8b24ec972b04 [174/192] drm/amd/display: Fix use of uninitialized union
config: i386-randconfig-h1-01290401 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4
reproduce:
        git checkout 3cec41769d2182e629692a3262cc8b24ec972b04
        # save the attached .config to linux build tree
        make ARCH=i386 

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c: In function 'wait_for_training_aux_rd_interval':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:50:8: warning: missing braces around initializer [-Wmissing-braces]
     union training_aux_rd_interval training_rd_interval = {0};
           ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:50:8: warning: (near initialization for 'training_rd_interval.bits') [-Wmissing-braces]

vim +50 drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c

    37	
    38	static bool decide_fallback_link_setting(
    39			struct dc_link_settings initial_link_settings,
    40			struct dc_link_settings *current_link_setting,
    41			enum link_training_result training_result);
    42	static struct dc_link_settings get_common_supported_link_settings(
    43			struct dc_link_settings link_setting_a,
    44			struct dc_link_settings link_setting_b);
    45	
    46	static void wait_for_training_aux_rd_interval(
    47		struct dc_link *link,
    48		uint32_t default_wait_in_micro_secs)
    49	{
  > 50		union training_aux_rd_interval training_rd_interval = {0};
    51	
    52		/* overwrite the delay if rev > 1.1*/
    53		if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
    54			/* DP 1.2 or later - retrieve delay through
    55			 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
    56			core_link_read_dpcd(
    57				link,
    58				DP_TRAINING_AUX_RD_INTERVAL,
    59				(uint8_t *)&training_rd_interval,
    60				sizeof(training_rd_interval));
    61	
    62			if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
    63				default_wait_in_micro_secs =
    64					training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
    65		}
    66	
    67		udelay(default_wait_in_micro_secs);
    68	
    69		DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
    70			__func__,
    71			default_wait_in_micro_secs);
    72	}
    73	

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