[U-Boot] [PATCH 1/3] fsl_sec: fix register layout on Layerscape architectures

[U-Boot] [PATCH 1/3] fsl_sec: fix register layout on Layerscape architectures

[laurentiu.tudor at nxp.com]

From: Laurentiu Tudor <laurentiu.tudor@nxp.com>

On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
 include/fsl_sec.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 16e3fcb5a1..be08a2b88b 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -121,10 +121,18 @@ typedef struct ccsr_sec {
 	u32	chanum_ls;	/* CHA Number Register, LS */
 	u32	secvid_ms;	/* SEC Version ID Register, MS */
 	u32	secvid_ls;	/* SEC Version ID Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+	u8	res9[0x6f020];
+#else
 	u8	res9[0x6020];
+#endif
 	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS */
 	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+	u8	res10[0x8ffd8];
+#else
 	u8	res10[0x8fd8];
+#endif
 } ccsr_sec_t;
 
 #define SEC_CTPR_MS_AXI_LIODN		0x08000000
-- 
2.17.1

[U-Boot] [PATCH] pci: layerscape: add option to statically allocate PCI StreamIDs

[laurentiu.tudor at nxp.com]

From: Laurentiu Tudor <laurentiu.tudor@nxp.com>

Certain PCI scenarios have more dynamic requirements, e.g. endpoints
are "hot-plugged" later in the system lifetime. Add a Kconfig option
that allows specifying a maximum number of end-points, per PCI controller
and allocate a StreamID for each one.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 28 +++++++++++++++++
 drivers/pci/pcie_layerscape_fixup.c       | 38 +++++++++++++++++++++++
 2 files changed, 66 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 2b086da79b..1d633d71a8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -571,3 +571,31 @@ config TFABOOT
        help
          Enabling this will make a U-Boot binary that is capable of being
          booted via TFA.
+
+menuconfig FSL_PCIE_STATIC_STREAM_IDS
+	bool "Allocate PCI streamIDs statically"
+	default n
+	depends on PCIE_LAYERSCAPE
+	help
+	  Statically allocate a certain number of StreamIDs for each PCI
+	  controller, instead of enumerating the connected endpoints and
+	  allocate a StreamID for each one. This allocation method can
+	  be used in more dynamic PCI scenarios, e.g. where endpoints are
+	  "hot-plugged" later in the system bringup, by statically specifying
+	  a maximum number of StreamIDs expected for each PCI controller.
+
+if FSL_PCIE_STATIC_STREAM_IDS
+
+config FSL_PCIE1_STREAM_IDS_COUNT
+	default 3
+	int "Maximum number of streamIDs to allocate for PCI1 controller"
+
+config FSL_PCIE2_STREAM_IDS_COUNT
+	default 3
+	int "Maximum number of streamIDs to allocate for PCI2 controller"
+
+config FSL_PCIE3_STREAM_IDS_COUNT
+	default 3
+	int "Maximum number of streamIDs to allocate for PCI3 controller"
+
+endif
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 1a17bd98aa..32355cbf2e 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -177,6 +177,7 @@ static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
 
 static void fdt_fixup_pcie(void *blob)
 {
+#if !CONFIG_FSL_PCIE_STATIC_STREAM_IDS
 	struct udevice *dev, *bus;
 	struct ls_pcie *pcie;
 	int streamid;
@@ -215,6 +216,43 @@ static void fdt_fixup_pcie(void *blob)
 		fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
 					     streamid);
 	}
+#else
+	static const int streamid_cnt[] = {
+		CONFIG_FSL_PCIE1_STREAM_IDS_COUNT,
+		CONFIG_FSL_PCIE2_STREAM_IDS_COUNT,
+		CONFIG_FSL_PCIE3_STREAM_IDS_COUNT
+	};
+	struct ls_pcie *pcie;
+	int i, streamid, index;
+	pci_dev_t bdf;
+
+	list_for_each_entry(pcie, &ls_pcie_list, list) {
+		for (i = 0; i < streamid_cnt[pcie->idx]; i++) {
+			streamid = ls_pcie_next_streamid();
+			if (streamid < 0) {
+				debug("ERROR: no stream ids free\n");
+				continue;
+			}
+
+			index = ls_pcie_next_lut_index(pcie);
+			if (index < 0) {
+				debug("ERROR: no LUT indexes free\n");
+				continue;
+			}
+
+			bdf = PCI_BDF(i, 0, 0);
+			/* map PCI b.d.f to streamID in LUT */
+			ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
+						streamid);
+			/* update msi-map in device tree */
+			fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
+						   streamid);
+			/* update iommu-map in device tree */
+			fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
+						     streamid);
+		}
+	}
+#endif /* !CONFIG_FSL_PCIE_STATIC_STREAM_IDS */
 }
 #endif
 
-- 
2.17.1

[U-Boot] [PATCH 2/3] armv8: fsl-layerscape: fix SEC QI ICID setup

[laurentiu.tudor at nxp.com]

From: Laurentiu Tudor <laurentiu.tudor@nxp.com>

The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c      | 2 +-
 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c      | 2 +-
 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 3 +--
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
index 0e8649427e..3bd993bebf 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
@@ -43,7 +43,7 @@ struct icid_id_table icid_tbl[] = {
 	SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
 	SET_QE_ICID(FSL_QE_STREAM_ID),
 #ifdef CONFIG_FSL_CAAM
-	SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+	SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
 	SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
 	SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
 	SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 2da9adab5b..abd847b5be 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -41,7 +41,7 @@ struct icid_id_table icid_tbl[] = {
 	SET_ETR_ICID(FSL_ETR_STREAM_ID),
 	SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
 #ifdef CONFIG_FSL_CAAM
-	SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+	SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
 	SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
 	SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
 	SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index f375fe7115..e7a8801262 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -93,8 +93,7 @@ void fdt_fixup_icid(void *blob);
 
 #define SET_SEC_QI_ICID(streamid) \
 	SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
-		(((streamid) << 16) | (streamid)), \
-		offsetof(ccsr_sec_t, qilcr_ls) + \
+		0, offsetof(ccsr_sec_t, qilcr_ls) + \
 		CONFIG_SYS_FSL_SEC_ADDR, \
 		CONFIG_SYS_FSL_SEC_ADDR)
 
-- 
2.17.1

[U-Boot] [PATCH 3/3] armv8: fsl-layerscape: avoid DT fixup warning

[laurentiu.tudor at nxp.com]

From: Laurentiu Tudor <laurentiu.tudor@nxp.com>

sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:

WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.

Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index e7a8801262..f971af8d26 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -9,6 +9,7 @@
 #include <asm/types.h>
 #include <fsl_qbman.h>
 #include <fsl_sec.h>
+#include <asm/armv8/sec_firmware.h>
 
 struct icid_id_table {
 	const char *compat;
@@ -98,7 +99,13 @@ void fdt_fixup_icid(void *blob);
 		CONFIG_SYS_FSL_SEC_ADDR)
 
 #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
-	SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
+	SET_ICID_ENTRY( \
+		(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \
+		(FSL_SEC_JR##jr_num##_OFFSET ==  \
+			SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
+			? NULL \
+			: "fsl,sec-v4.0-job-ring"), \
+		streamid, \
 		(((streamid) << 16) | (streamid)), \
 		offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
 		CONFIG_SYS_FSL_SEC_ADDR, \
-- 
2.17.1

[U-Boot] [PATCH 1/3] fsl_sec: fix register layout on Layerscape architectures

[Horia Geanta]

On 1/30/2019 2:01 PM, laurentiu.tudor at nxp.com wrote:
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> 
> On Layerscape architectures the SEC memory map is 1MB and the
> register blocks contained in it are 64KB aligned, not 4KB as
> the ccsr_sec structure currently assumes. Fix the layout of
> the structure for these architectures.
> 
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
For the series:
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>

Thanks,
Horia

[U-Boot] [upstream-release] [PATCH] pci: layerscape: add option to statically allocate PCI StreamIDs

[Bharat Bhushan]

> -----Original Message-----
> From: upstream-release-bounces at linux.nxdi.nxp.com <upstream-release-
> bounces at linux.nxdi.nxp.com> On Behalf Of laurentiu.tudor at nxp.com
> Sent: Wednesday, January 30, 2019 5:31 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; York Sun <york.sun@nxp.com>
> Cc: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> Subject: [upstream-release] [PATCH] pci: layerscape: add option to statically
> allocate PCI StreamIDs
> 
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> 
> Certain PCI scenarios have more dynamic requirements, e.g. endpoints are
> "hot-plugged" later in the system lifetime. Add a Kconfig option that allows
> specifying a maximum number of end-points, per PCI controller and allocate
> a StreamID for each one.
> 
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 28 +++++++++++++++++
>  drivers/pci/pcie_layerscape_fixup.c       | 38 +++++++++++++++++++++++
>  2 files changed, 66 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 2b086da79b..1d633d71a8 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -571,3 +571,31 @@ config TFABOOT
>         help
>           Enabling this will make a U-Boot binary that is capable of being
>           booted via TFA.
> +
> +menuconfig FSL_PCIE_STATIC_STREAM_IDS
> +	bool "Allocate PCI streamIDs statically"
> +	default n
> +	depends on PCIE_LAYERSCAPE
> +	help
> +	  Statically allocate a certain number of StreamIDs for each PCI
> +	  controller, instead of enumerating the connected endpoints and
> +	  allocate a StreamID for each one. This allocation method can
> +	  be used in more dynamic PCI scenarios, e.g. where endpoints are
> +	  "hot-plugged" later in the system bringup, by statically specifying
> +	  a maximum number of StreamIDs expected for each PCI controller.
> +
> +if FSL_PCIE_STATIC_STREAM_IDS
> +
> +config FSL_PCIE1_STREAM_IDS_COUNT
> +	default 3
> +	int "Maximum number of streamIDs to allocate for PCI1 controller"
> +
> +config FSL_PCIE2_STREAM_IDS_COUNT
> +	default 3
> +	int "Maximum number of streamIDs to allocate for PCI2 controller"
> +
> +config FSL_PCIE3_STREAM_IDS_COUNT
> +	default 3
> +	int "Maximum number of streamIDs to allocate for PCI3 controller"
> +
> +endif
> diff --git a/drivers/pci/pcie_layerscape_fixup.c
> b/drivers/pci/pcie_layerscape_fixup.c
> index 1a17bd98aa..32355cbf2e 100644
> --- a/drivers/pci/pcie_layerscape_fixup.c
> +++ b/drivers/pci/pcie_layerscape_fixup.c
> @@ -177,6 +177,7 @@ static void fdt_pcie_set_iommu_map_entry(void
> *blob, struct ls_pcie *pcie,
> 
>  static void fdt_fixup_pcie(void *blob)
>  {
> +#if !CONFIG_FSL_PCIE_STATIC_STREAM_IDS
>  	struct udevice *dev, *bus;
>  	struct ls_pcie *pcie;
>  	int streamid;
> @@ -215,6 +216,43 @@ static void fdt_fixup_pcie(void *blob)
>  		fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
>  					     streamid);
>  	}
> +#else
> +	static const int streamid_cnt[] = {
> +		CONFIG_FSL_PCIE1_STREAM_IDS_COUNT,
> +		CONFIG_FSL_PCIE2_STREAM_IDS_COUNT,
> +		CONFIG_FSL_PCIE3_STREAM_IDS_COUNT

Why 3 controllers?

> +	};
> +	struct ls_pcie *pcie;
> +	int i, streamid, index;
> +	pci_dev_t bdf;
> +
> +	list_for_each_entry(pcie, &ls_pcie_list, list) {
> +		for (i = 0; i < streamid_cnt[pcie->idx]; i++) {
> +			streamid = ls_pcie_next_streamid();
> +			if (streamid < 0) {
> +				debug("ERROR: no stream ids free\n");
> +				continue;

Why to continue if we are out of stream-ids?

> +			}
> +
> +			index = ls_pcie_next_lut_index(pcie);
> +			if (index < 0) {
> +				debug("ERROR: no LUT indexes free\n");
> +				continue;

We can error out when out of LUT entry

> +			}
> +
> +			bdf = PCI_BDF(i, 0, 0);
> +			/* map PCI b.d.f to streamID in LUT */
> +			ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
> +						streamid);
> +			/* update msi-map in device tree */
> +			fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
> +						   streamid);
> +			/* update iommu-map in device tree */
> +			fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >>
> 8,
> +						     streamid);
> +		}
> +	}
> +#endif /* !CONFIG_FSL_PCIE_STATIC_STREAM_IDS */
>  }
>  #endif
> 
> --
> 2.17.1
> 
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[U-Boot] [upstream-release] [PATCH 1/3] fsl_sec: fix register layout on Layerscape architectures

[Bharat Bhushan]

> -----Original Message-----
> From: upstream-release-bounces at linux.nxdi.nxp.com <upstream-release-
> bounces at linux.nxdi.nxp.com> On Behalf Of laurentiu.tudor at nxp.com
> Sent: Wednesday, January 30, 2019 5:31 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; York Sun <york.sun@nxp.com>
> Cc: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> Subject: [upstream-release] [PATCH 1/3] fsl_sec: fix register layout on
> Layerscape architectures
> 
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> 
> On Layerscape architectures the SEC memory map is 1MB and the register
> blocks contained in it are 64KB aligned, not 4KB as the ccsr_sec structure
> currently assumes. Fix the layout of the structure for these architectures.
> 
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>


> ---
>  include/fsl_sec.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/include/fsl_sec.h b/include/fsl_sec.h index
> 16e3fcb5a1..be08a2b88b 100644
> --- a/include/fsl_sec.h
> +++ b/include/fsl_sec.h
> @@ -121,10 +121,18 @@ typedef struct ccsr_sec {
>  	u32	chanum_ls;	/* CHA Number Register, LS */
>  	u32	secvid_ms;	/* SEC Version ID Register, MS */
>  	u32	secvid_ls;	/* SEC Version ID Register, LS */
> +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
> +	u8	res9[0x6f020];
> +#else
>  	u8	res9[0x6020];
> +#endif
>  	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS
> */
>  	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
> +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
> +	u8	res10[0x8ffd8];
> +#else
>  	u8	res10[0x8fd8];
> +#endif
>  } ccsr_sec_t;
> 
>  #define SEC_CTPR_MS_AXI_LIODN		0x08000000
> --
> 2.17.1
> 
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[U-Boot] [upstream-release] [PATCH 3/3] armv8: fsl-layerscape: avoid DT fixup warning

[Bharat Bhushan]

> -----Original Message-----
> From: upstream-release-bounces at linux.nxdi.nxp.com <upstream-release-
> bounces at linux.nxdi.nxp.com> On Behalf Of laurentiu.tudor at nxp.com
> Sent: Wednesday, January 30, 2019 5:31 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; York Sun <york.sun@nxp.com>
> Cc: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> Subject: [upstream-release] [PATCH 3/3] armv8: fsl-layerscape: avoid DT
> fixup warning
> 
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> 
> sec_firmware reserves JR3 for it's own usage and deletes the JR3 node from
> the device tree. This causes this warning to be issued when doing the device
> tree fixup:

Do you think it is fair to assume that firmware will always reserve JR3? 

Thanks
-Bharat

> 
> WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
> 
> Fix it by excluding the device tree fixup for the JR reserved by sec_firmware.
> 
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> ---
>  arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> index e7a8801262..f971af8d26 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> @@ -9,6 +9,7 @@
>  #include <asm/types.h>
>  #include <fsl_qbman.h>
>  #include <fsl_sec.h>
> +#include <asm/armv8/sec_firmware.h>
> 
>  struct icid_id_table {
>  	const char *compat;
> @@ -98,7 +99,13 @@ void fdt_fixup_icid(void *blob);
>  		CONFIG_SYS_FSL_SEC_ADDR)
> 
>  #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
> -	SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
> +	SET_ICID_ENTRY( \
> +		(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \
> +		(FSL_SEC_JR##jr_num##_OFFSET ==  \
> +			SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
> +			? NULL \
> +			: "fsl,sec-v4.0-job-ring"), \
> +		streamid, \
>  		(((streamid) << 16) | (streamid)), \
>  		offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
>  		CONFIG_SYS_FSL_SEC_ADDR, \
> --
> 2.17.1
> 
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[U-Boot] [upstream-release] [PATCH] pci: layerscape: add option to statically allocate PCI StreamIDs

[Laurentiu Tudor]

Hi Bharat,

Actually I've sent this patch by mistake, sorry for that.
I'll drop it and resend the patch series.

---
Best Regards, Laurentiu

On 30.01.2019 16:41, Bharat Bhushan wrote:
> 
> 
>> -----Original Message-----
>> From: upstream-release-bounces at linux.nxdi.nxp.com <upstream-release-
>> bounces at linux.nxdi.nxp.com> On Behalf Of laurentiu.tudor at nxp.com
>> Sent: Wednesday, January 30, 2019 5:31 PM
>> To: u-boot at lists.denx.de; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>; York Sun <york.sun@nxp.com>
>> Cc: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>> Subject: [upstream-release] [PATCH] pci: layerscape: add option to statically
>> allocate PCI StreamIDs
>>
>> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>>
>> Certain PCI scenarios have more dynamic requirements, e.g. endpoints are
>> "hot-plugged" later in the system lifetime. Add a Kconfig option that allows
>> specifying a maximum number of end-points, per PCI controller and allocate
>> a StreamID for each one.
>>
>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>> ---
>>   arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 28 +++++++++++++++++
>>   drivers/pci/pcie_layerscape_fixup.c       | 38 +++++++++++++++++++++++
>>   2 files changed, 66 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> index 2b086da79b..1d633d71a8 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> @@ -571,3 +571,31 @@ config TFABOOT
>>          help
>>            Enabling this will make a U-Boot binary that is capable of being
>>            booted via TFA.
>> +
>> +menuconfig FSL_PCIE_STATIC_STREAM_IDS
>> +	bool "Allocate PCI streamIDs statically"
>> +	default n
>> +	depends on PCIE_LAYERSCAPE
>> +	help
>> +	  Statically allocate a certain number of StreamIDs for each PCI
>> +	  controller, instead of enumerating the connected endpoints and
>> +	  allocate a StreamID for each one. This allocation method can
>> +	  be used in more dynamic PCI scenarios, e.g. where endpoints are
>> +	  "hot-plugged" later in the system bringup, by statically specifying
>> +	  a maximum number of StreamIDs expected for each PCI controller.
>> +
>> +if FSL_PCIE_STATIC_STREAM_IDS
>> +
>> +config FSL_PCIE1_STREAM_IDS_COUNT
>> +	default 3
>> +	int "Maximum number of streamIDs to allocate for PCI1 controller"
>> +
>> +config FSL_PCIE2_STREAM_IDS_COUNT
>> +	default 3
>> +	int "Maximum number of streamIDs to allocate for PCI2 controller"
>> +
>> +config FSL_PCIE3_STREAM_IDS_COUNT
>> +	default 3
>> +	int "Maximum number of streamIDs to allocate for PCI3 controller"
>> +
>> +endif
>> diff --git a/drivers/pci/pcie_layerscape_fixup.c
>> b/drivers/pci/pcie_layerscape_fixup.c
>> index 1a17bd98aa..32355cbf2e 100644
>> --- a/drivers/pci/pcie_layerscape_fixup.c
>> +++ b/drivers/pci/pcie_layerscape_fixup.c
>> @@ -177,6 +177,7 @@ static void fdt_pcie_set_iommu_map_entry(void
>> *blob, struct ls_pcie *pcie,
>>
>>   static void fdt_fixup_pcie(void *blob)
>>   {
>> +#if !CONFIG_FSL_PCIE_STATIC_STREAM_IDS
>>   	struct udevice *dev, *bus;
>>   	struct ls_pcie *pcie;
>>   	int streamid;
>> @@ -215,6 +216,43 @@ static void fdt_fixup_pcie(void *blob)
>>   		fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
>>   					     streamid);
>>   	}
>> +#else
>> +	static const int streamid_cnt[] = {
>> +		CONFIG_FSL_PCIE1_STREAM_IDS_COUNT,
>> +		CONFIG_FSL_PCIE2_STREAM_IDS_COUNT,
>> +		CONFIG_FSL_PCIE3_STREAM_IDS_COUNT
> 
> Why 3 controllers?
> 
>> +	};
>> +	struct ls_pcie *pcie;
>> +	int i, streamid, index;
>> +	pci_dev_t bdf;
>> +
>> +	list_for_each_entry(pcie, &ls_pcie_list, list) {
>> +		for (i = 0; i < streamid_cnt[pcie->idx]; i++) {
>> +			streamid = ls_pcie_next_streamid();
>> +			if (streamid < 0) {
>> +				debug("ERROR: no stream ids free\n");
>> +				continue;
> 
> Why to continue if we are out of stream-ids?
> 
>> +			}
>> +
>> +			index = ls_pcie_next_lut_index(pcie);
>> +			if (index < 0) {
>> +				debug("ERROR: no LUT indexes free\n");
>> +				continue;
> 
> We can error out when out of LUT entry
> 
>> +			}
>> +
>> +			bdf = PCI_BDF(i, 0, 0);
>> +			/* map PCI b.d.f to streamID in LUT */
>> +			ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
>> +						streamid);
>> +			/* update msi-map in device tree */
>> +			fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
>> +						   streamid);
>> +			/* update iommu-map in device tree */
>> +			fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >>
>> 8,
>> +						     streamid);
>> +		}
>> +	}
>> +#endif /* !CONFIG_FSL_PCIE_STATIC_STREAM_IDS */
>>   }
>>   #endif
>>
>> --
>> 2.17.1
>>
>> _______________________________________________
>> upstream-release mailing list
>> upstream-release at linux.nxdi.nxp.com
>> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flin
>> ux.nxdi.nxp.com%2Fmailman%2Flistinfo%2Fupstream-
>> release&amp;data=02%7C01%7Cbharat.bhushan%40nxp.com%7C58a43424e
>> 5724733c5f908d686aa9f3f%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
>> %7C636844464703698542&amp;sdata=TZpx5GzIpO%2FUoGWMzDNPIy5SpH
>> UZFkSIDQLkZn%2FZMJE%3D&amp;reserved=0

[U-Boot] [u-boot] [PATCH] pci: layerscape: add option to statically allocate PCI StreamIDs

[Pankaj Bansal]

Hi Laurentiu,

> -----Original Message-----
> From: u-boot-bounces at linux.nxdi.nxp.com [mailto:u-boot-
> bounces at linux.nxdi.nxp.com] On Behalf Of laurentiu.tudor at nxp.com
> Sent: Wednesday, 30 January, 2019 05:31 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; York Sun <york.sun@nxp.com>
> Subject: [u-boot] [PATCH] pci: layerscape: add option to statically allocate PCI
> StreamIDs
> 
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> 
> Certain PCI scenarios have more dynamic requirements, e.g. endpoints are "hot-
> plugged" later in the system lifetime. Add a Kconfig option that allows specifying
> a maximum number of end-points, per PCI controller and allocate a StreamID
> for each one.
> 
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 28 +++++++++++++++++
>  drivers/pci/pcie_layerscape_fixup.c       | 38 +++++++++++++++++++++++
>  2 files changed, 66 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 2b086da79b..1d633d71a8 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -571,3 +571,31 @@ config TFABOOT
>         help
>           Enabling this will make a U-Boot binary that is capable of being
>           booted via TFA.
> +
> +menuconfig FSL_PCIE_STATIC_STREAM_IDS
> +	bool "Allocate PCI streamIDs statically"
> +	default n
> +	depends on PCIE_LAYERSCAPE
> +	help
> +	  Statically allocate a certain number of StreamIDs for each PCI
> +	  controller, instead of enumerating the connected endpoints and
> +	  allocate a StreamID for each one. This allocation method can
> +	  be used in more dynamic PCI scenarios, e.g. where endpoints are
> +	  "hot-plugged" later in the system bringup, by statically specifying
> +	  a maximum number of StreamIDs expected for each PCI controller.
> +
> +if FSL_PCIE_STATIC_STREAM_IDS
> +
> +config FSL_PCIE1_STREAM_IDS_COUNT
> +	default 3
> +	int "Maximum number of streamIDs to allocate for PCI1 controller"
> +
> +config FSL_PCIE2_STREAM_IDS_COUNT
> +	default 3
> +	int "Maximum number of streamIDs to allocate for PCI2 controller"
> +
> +config FSL_PCIE3_STREAM_IDS_COUNT
> +	default 3
> +	int "Maximum number of streamIDs to allocate for PCI3 controller"
> +
> +endif
> diff --git a/drivers/pci/pcie_layerscape_fixup.c
> b/drivers/pci/pcie_layerscape_fixup.c
> index 1a17bd98aa..32355cbf2e 100644
> --- a/drivers/pci/pcie_layerscape_fixup.c
> +++ b/drivers/pci/pcie_layerscape_fixup.c
> @@ -177,6 +177,7 @@ static void fdt_pcie_set_iommu_map_entry(void *blob,
> struct ls_pcie *pcie,
> 
>  static void fdt_fixup_pcie(void *blob)
>  {
> +#if !CONFIG_FSL_PCIE_STATIC_STREAM_IDS
>  	struct udevice *dev, *bus;
>  	struct ls_pcie *pcie;
>  	int streamid;
> @@ -215,6 +216,43 @@ static void fdt_fixup_pcie(void *blob)
>  		fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
>  					     streamid);
>  	}
> +#else
> +	static const int streamid_cnt[] = {
> +		CONFIG_FSL_PCIE1_STREAM_IDS_COUNT,
> +		CONFIG_FSL_PCIE2_STREAM_IDS_COUNT,
> +		CONFIG_FSL_PCIE3_STREAM_IDS_COUNT
> +	};
> +	struct ls_pcie *pcie;
> +	int i, streamid, index;
> +	pci_dev_t bdf;
> +
> +	list_for_each_entry(pcie, &ls_pcie_list, list) {
> +		for (i = 0; i < streamid_cnt[pcie->idx]; i++) {
> +			streamid = ls_pcie_next_streamid();
> +			if (streamid < 0) {
> +				debug("ERROR: no stream ids free\n");
> +				continue;
> +			}
> +
> +			index = ls_pcie_next_lut_index(pcie);
> +			if (index < 0) {
> +				debug("ERROR: no LUT indexes free\n");
> +				continue;
> +			}
> +
> +			bdf = PCI_BDF(i, 0, 0);

As per my understanding, the BUS number in our SOCs would always be 0 for each PCIE controller.
Only the device number and function number would change depending on the device(s) attached to PCIE controller.

> +			/* map PCI b.d.f to streamID in LUT */
> +			ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
> +						streamid);
> +			/* update msi-map in device tree */
> +			fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
> +						   streamid);
> +			/* update iommu-map in device tree */
> +			fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
> +						     streamid);
> +		}
> +	}
> +#endif /* !CONFIG_FSL_PCIE_STATIC_STREAM_IDS */
>  }
>  #endif

Wouldn't the better alternative is to fix some stream IDs against BDF in device tree itself for all the PCIE devices that we know for sure would be attached to board.
And limit the available streamIDs to be used by bootloader for dynamically discovered PCIE devices.

> 
> --
> 2.17.1
> 
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