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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+
Date: Mon,  4 Feb 2019 20:45:20 +0200	[thread overview]
Message-ID: <20190204184523.28097-1-ville.syrjala@linux.intel.com> (raw)

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When adding the early latency==0 check back I neglected to
realize that we no longer have a way to return a failure
from the wm computation like we had in the past (since we
now calculate wms before ddb allocations). Also plane_en
being false doesn't actually indicate that the level is
invalid as it wil also happen when the plane is not
enabled.

skl_allocate_pipe_ddb() starts scanning from the maximum
watermark level and it stops as soon as it finds a level
that is deemed viable. The assumption being that if level
n+1 is valid then level n is valid as well. Thus if we
now disable any watermark level by zeroing its latency
the code will think that level to be actually valid
and won't confirm whether the actually enabled lower
watermark level(s) actually fit into the allotted ddb
space. This results in hilarious watermark values that
exceed the ddb allocation of the plane.

The way we must now indicate a failure is to assign an
unreasoanbly big value to min_ddb_alloc which will then
make skl_allocate_pipe_ddb() reject the entire level.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ed9786241307..d6186c90bc10 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4694,8 +4694,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
 	uint_fixed_16_16_t selected_result;
 	u32 res_blocks, res_lines, min_ddb_alloc = 0;
 
-	if (latency == 0)
+	if (latency == 0) {
+		/* reject it */
+		result->min_ddb_alloc = U16_MAX;
 		return;
+	}
 
 	/* Display WA #1141: kbl,cfl */
 	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
-- 
2.19.2

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             reply	other threads:[~2019-02-04 18:45 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-04 18:45 Ville Syrjala [this message]
2019-02-04 18:45 ` [PATCH 2/4] drm/i915: Extract skl_set_pipe_chicken() Ville Syrjala
2019-02-04 20:21   ` [PATCH v2 2/4] drm/i915: Extract icl_set_pipe_chicken() Ville Syrjala
2019-02-04 23:28     ` Matt Roper
2019-02-04 18:45 ` [PATCH 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too Ville Syrjala
2019-02-04 20:22   ` [PATCH v2 " Ville Syrjala
2019-02-04 23:28     ` Matt Roper
2019-02-05 11:21     ` Maarten Lankhorst
2019-02-05 13:39       ` Ville Syrjälä
2019-02-05 14:49         ` Maarten Lankhorst
2019-02-05 18:30           ` Ville Syrjälä
2019-02-04 18:45 ` [PATCH 4/4] drm/i915: W/A for underruns with WM1+ disabled on icl Ville Syrjala
2019-02-04 20:22   ` [PATCH v2 " Ville Syrjala
2019-02-04 23:29     ` Matt Roper
2019-02-04 19:22 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ Patchwork
2019-02-04 21:08 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev4) Patchwork
2019-02-04 21:58 ` ✓ Fi.CI.IGT: " Patchwork
2019-02-04 23:07 ` [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Matt Roper
2019-02-05 13:35   ` Ville Syrjälä
2019-02-05 13:42 ` [PATCH v2 " Ville Syrjala
2019-02-05 15:32   ` Matt Roper
2019-02-05 15:50 ` [PATCH v3 " Ville Syrjala
2019-02-05 16:46 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev6) Patchwork
2019-02-05 19:47 ` ✓ Fi.CI.IGT: " Patchwork

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