From mboxrd@z Thu Jan 1 00:00:00 1970 From: Evan Green Subject: [PATCH v3 4/8] arm64: dts: sdm845: Add UFS PHY reset Date: Tue, 5 Feb 2019 10:58:58 -0800 Message-ID: <20190205185902.106085-5-evgreen@chromium.org> References: <20190205185902.106085-1-evgreen@chromium.org> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20190205185902.106085-1-evgreen@chromium.org> Sender: linux-kernel-owner@vger.kernel.org To: Andy Gross , Kishon Vijay Abraham I Cc: Stephen Boyd , Marc Gonzalez , Can Guo , Vivek Gautam , Douglas Anderson , Asutosh Das , Evan Green , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , David Brown , Mark Rutland List-Id: linux-arm-msm@vger.kernel.org Wire up the reset controller in the Qcom UFS controller for the PHY. This will be used to toggle PHY reset during initialization of the PHY. Signed-off-by: Evan Green Reviewed-by: Stephen Boyd --- This commit is based atop the series at [1]. Patches 1 and 2 of that series have landed, but 3, 4, and 5 are still outstanding. [1] https://lore.kernel.org/lkml/20181210192826.241350-1-evgreen@chromium.org/ Changes in v3: None Changes in v2: None arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b29332b265d9..029ab66405cf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -990,6 +990,7 @@ phy-names = "ufsphy"; lanes-per-direction = <2>; power-domains = <&gcc UFS_PHY_GDSC>; + #reset-cells = <1>; clock-names = "core_clk", @@ -1033,6 +1034,8 @@ clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; status = "disabled"; ufs_mem_phy_lanes: lanes@1d87400 { -- 2.20.1