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From: Simon Horman <horms+renesas@verge.net.au>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Magnus Damm <magnus.damm@gmail.com>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	Fabrizio Castro <fabrizio.castro@bp.renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	linux-kernel@vger.kernel.org,
	Simon Horman <horms+renesas@verge.net.au>
Subject: [PATCH v4 0/5] clk: renesas: r8a77990, r8a774c0: Add Z2 clock
Date: Thu,  7 Feb 2019 14:35:45 +0100	[thread overview]
Message-ID: <20190207133550.13967-1-horms+renesas@verge.net.au> (raw)

Hi,

this series adds the Z2 clock as a clock with both a fixed and variable
divisor with a parent of PLL0 to the CPG-MSSR drivers for the R-Car E3
(r8a77990) and RZ/G2E (r8a774c0) SoCs.

In order to do so this series:

1. Parameterise Z and Z2 clock fixed divisor in shared Gen-3 CPG
   driver code to allow fixed divisors other than 2 - the E3 Z2
   clock has a fixed divisor of 4

2. Parameterise offset of Z and Z2 clock control bits -
   the offsets on E3 differ to other R-Car Gen 3 SoCs

3. Support Z and Z2 clocks with high frequency parents.
   The parent of the E3 Z2 clock, PLL0, is 4.8GHz and thus
   when expressed in HZ must be treated as a 64bit value.

4. Actually add the Z2 clocks

Changes since v3
----------------
* Add and use DIV64_U64_ROUND_CLOSEST in the patch to allow
  high frequency parents. This corrects the patch for 32bit platforms.
* Accumulate review and testing tags.

Changes since v2
----------------
* Parameterise control bit offset rather than using a quirk
* Revised RZ/G2E patch - I was confused and updating the file for
  the wrong part number


Testing Overview
----------------

This patchset has been tested on Ebisu-4D/E3 with
top of renesas-devel-20190207-v5.0-rc5. This allowed CPUFreq
to be successfully exercised, showing scaling of the Z2 clock as per the
results below.

This patchset was also tested for regressions Salvator-X/M3-W ES1.0.
As per the results below CPUFreq was used to show that with these
patches applied Z and Z2 clocks still scale as expected.

This v3 of this patchset has been independently tested RZ/G2E.
It is not expected that v4 will have any behavioural differences
on that (or any other 64bit) platform.


Patches List by Author
----------------------

Simon Horman (3):
  clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
  clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency
    parents
  clk: renesas: r8a774c0: Add Z2 clock

Takeshi Kihara (2):
  clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
  clk: renesas: r8a77990: Add Z2 clock

 drivers/clk/renesas/r8a774a1-cpg-mssr.c |  4 ++--
 drivers/clk/renesas/r8a774c0-cpg-mssr.c |  1 +
 drivers/clk/renesas/r8a7795-cpg-mssr.c  |  5 +++--
 drivers/clk/renesas/r8a7796-cpg-mssr.c  |  5 +++--
 drivers/clk/renesas/r8a77965-cpg-mssr.c |  2 +-
 drivers/clk/renesas/r8a77990-cpg-mssr.c |  1 +
 drivers/clk/renesas/rcar-gen3-cpg.c     | 27 +++++++++++++--------------
 drivers/clk/renesas/rcar-gen3-cpg.h     |  4 ++++
 include/linux/math64.h                  | 13 +++++++++++++
 9 files changed, 41 insertions(+), 21 deletions(-)

Ebisu-4D/E3 Test Results
------------------------

# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
performance
# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
800000 1000000 1200000 
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z2/clk_rate:1200000000
# echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:975000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:975000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000
/sys/kernel/debug/clk/z2/clk_rate:975000000
# echo 800000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:787500
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:800000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:787500
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:800000
/sys/kernel/debug/clk/z2/clk_rate:787500000
# echo 1200000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z2/clk_rate:1200000000


Salvator-X/M3-W ES1 Test Results
--------------------------------

# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
performance
# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
500000 1000000 1500000 
# cat /sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies
800000 1000000 1200000 
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z/clk_rate /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1499999
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1500000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1499999
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1500000
/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z/clk_rate:1499999940
/sys/kernel/debug/clk/z2/clk_rate:1199999952
# echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z/clk_rate /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:984374
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:984374
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z/clk_rate:984374961
/sys/kernel/debug/clk/z2/clk_rate:1199999952
# echo 1000000 > /sys/devices/system/cpu/cpu2/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z/clk_rate /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:984374
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:984374
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_cur_freq:974999
/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_cur_freq:974999
/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq:974999
/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_cur_freq:974999
/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq:1000000
/sys/kernel/debug/clk/z/clk_rate:984374961
/sys/kernel/debug/clk/z2/clk_rate:974999961
# echo 500000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# echo 800000 > /sys/devices/system/cpu/cpu2/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z/clk_rate /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:468749
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:500000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:468749
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:500000
/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_cur_freq:787499
/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq:800000
/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_cur_freq:787499
/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq:800000
/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq:787499
/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq:800000
/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_cur_freq:787499
/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq:800000
/sys/kernel/debug/clk/z/clk_rate:468749981
/sys/kernel/debug/clk/z2/clk_rate:787499969
# echo 1500000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# echo 1200000 > /sys/devices/system/cpu/cpu2/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z/clk_rate /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1499999
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1500000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1499999
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1500000
/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z/clk_rate:1499999940
/sys/kernel/debug/clk/z2/clk_rate:1199999952

-- 
2.11.0

             reply	other threads:[~2019-02-07 13:36 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-07 13:35 Simon Horman [this message]
2019-02-07 13:35 ` [PATCH v4 1/5] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor Simon Horman
2019-02-07 13:35 ` [PATCH v4 2/5] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset Simon Horman
2019-02-07 13:35 ` [PATCH v4 3/5] clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents Simon Horman
2019-02-07 15:05   ` Geert Uytterhoeven
2019-02-07 15:22     ` Simon Horman
2019-02-07 13:35 ` [PATCH v4 4/5] clk: renesas: r8a77990: Add Z2 clock Simon Horman
2019-02-07 13:35 ` [PATCH v4 5/5] clk: renesas: r8a774c0: " Simon Horman

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