From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDCE9C282C4 for ; Sat, 9 Feb 2019 06:53:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8FE3E21773 for ; Sat, 9 Feb 2019 06:53:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ehP7hbZl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725925AbfBIGxP (ORCPT ); Sat, 9 Feb 2019 01:53:15 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:38523 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725903AbfBIGxP (ORCPT ); Sat, 9 Feb 2019 01:53:15 -0500 Received: by mail-wm1-f65.google.com with SMTP id v26so7024254wmh.3 for ; Fri, 08 Feb 2019 22:53:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=CCjAbKEkvsv7KSRjWRJNLfAFs51tWrXfMxRarcLUvcs=; b=ehP7hbZlr6UUJ/RU5b6Sjpqav6vtIX+zDNctenlpPwwXEZEzq2wvoilYZDqbDr43Na O+c1B8oco3RpxbEHcaGEcfkCrab9YaViVh73fXbaxn+rKeoaqdeAx4Xir2Q6aRFihEUO v1V1ayctlpJuhXVzbfJ0Ggh2KMr71GUnlyg58sKDpHJacMy7DyglnuYIcMkMaOAInyVU f5N2W/DLNO16H57N64U8qhS4+BiC+bBnJUYp2Jdk/DxiaPZXg4K6M2ofLco//h2Ss2cr bB3FDYzU2uLZDl3uSUtyNKfC0fMjP7T4b+x5eSW+mxxo3LTKEjXVYi/HVdNto8jyDUTj At4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=CCjAbKEkvsv7KSRjWRJNLfAFs51tWrXfMxRarcLUvcs=; b=o0pFB0FL61loiJt9ICSH/zX+qELuxMI7VAqXX5SLBxm3xJVW4o4Nt1gsgOJlDQjssv VZvaBvn8RRjIZ3VzKKqLs3+KW1051zBWL/ks5Tce0f1ufG09fFFiTMI32/y3EHg6a/rU u5g2DX4iGhW9w1WxBWO6ZRlTlBcdrn/1zIn3MmK34FKCTlIC4Ssld6nLmX0d7ndsjrNS ds31BBvqESGgLLQ2D5ysN/pc5QFvDJcTVciHLYEdc4yWNyGCA8+suIgaXiezokvWL/B8 a95OpmYMHwaV9zklb6x4G8cQS6+JiPeMFsgn4viIxxZjT04UXy7h+T4ReUqDemUKGFuH b6gw== X-Gm-Message-State: AHQUAubYIQq2pUT+EIBF026INtkjoja6pBGDjLC9QLCC6kDPrVEnENVy VqCq8hoLIpl9/n+EN8kC/fQ= X-Google-Smtp-Source: AHgI3IZwEc9hq/BFJ+MikEmegFXUK6st/Ir+qsOSahhruyKDd+wXRZsMRSJDDSqTSIcvHAheRwR2UQ== X-Received: by 2002:a5d:53cd:: with SMTP id a13mr5415314wrw.146.1549695192927; Fri, 08 Feb 2019 22:53:12 -0800 (PST) Received: from twisty.cin.medizin.uni-tuebingen.de ([2a01:c23:7830:ac00:e9fd:d3f1:412c:598a]) by smtp.gmail.com with ESMTPSA id h71sm2205913wme.20.2019.02.08.22.53.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Feb 2019 22:53:12 -0800 (PST) From: Mario Kleiner To: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, mario.kleiner.de@gmail.com, stable@vger.kernel.org, Nicholas Kazlauskas , Harry Wentland , Alex Deucher , =?UTF-8?q?Michel=20D=C3=A4nzer?= Subject: [PATCH] drm/amd/display: Use vrr friendly pageflip throttling in DC. Date: Sat, 9 Feb 2019 07:52:55 +0100 Message-Id: <20190209065255.9480-1-mario.kleiner.de@gmail.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org In VRR mode, keep track of the vblank count of the last completed pageflip in amdgpu_crtc->last_flip_vblank, as recorded in the pageflip completion handler after each completed flip. Use that count to prevent mmio programming a new pageflip within the same vblank in which the last pageflip completed, iow. to throttle pageflips to at most one flip per video frame, while at the same time allowing to request a flip not only before start of vblank, but also anywhere within vblank. The old logic did the same, and made sense for regular fixed refresh rate flipping, but in vrr mode it prevents requesting a flip anywhere inside the possibly huge vblank, thereby reducing framerate in vrr mode instead of improving it, by delaying a slightly delayed flip requests up to a maximum vblank duration + 1 scanout duration. This would limit VRR usefulness to only help applications with a very high GPU demand, which can submit the flip request before start of vblank, but then have to wait long for fences to complete. With this method a flip can be both requested and - after fences have completed - executed, ie. it doesn't matter if the request (amdgpu_dm_do_flip()) gets delayed until deep into the extended vblank due to cpu execution delays. This also allows clients which want to regulate framerate within the vrr range a much more fine-grained control of flip timing, a feature that might be useful for video playback, and is very useful for neuroscience/vision research applications. In regular non-VRR mode, retain the old flip submission behavior. This to keep flip scheduling for fullscreen X11/GLX OpenGL clients intact, if they use the GLX_OML_sync_control extensions glXSwapBufferMscOML(, ..., target_msc,...) function with a specific target_msc target vblank count. glXSwapBuffersMscOML() or DRI3/Present PresentPixmap() will not flip at the proper target_msc for a non-zero target_msc if VRR mode is active with this patch. They'd often flip one frame too early. However, this limitation should not matter much in VRR mode, as scheduling based on vblank counts is pretty futile/unusable under variable refresh duration anyway, so no real extra harm is done. According to some testing already done with this patch by Nicholas on top of my tests, IGT tests didn't report any problems. If fixes stuttering and flickering when flipping at rates below the minimum vrr refresh rate. Fixes: bb47de736661 ("drm/amdgpu: Set FreeSync state using drm VRR properties") Signed-off-by: Mario Kleiner Cc: Cc: Nicholas Kazlauskas Cc: Harry Wentland Cc: Alex Deucher Cc: Michel Dänzer --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 ++++++++++++++++--- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index bfa394ffd6d2..87ca5746f861 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -411,6 +411,7 @@ struct amdgpu_crtc { struct amdgpu_flip_work *pflip_works; enum amdgpu_flip_status pflip_status; int deferred_flip_completion; + u64 last_flip_vblank; /* pll sharing */ struct amdgpu_atom_ss ss; bool ss_enabled; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d59bafc84475..d4da331aa349 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -303,12 +303,11 @@ static void dm_pflip_high_irq(void *interrupt_params) return; } + /* Update to correct count(s) if racing with vblank irq */ + amdgpu_crtc->last_flip_vblank = drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); /* wake up userspace */ if (amdgpu_crtc->event) { - /* Update to correct count(s) if racing with vblank irq */ - drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); - drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event); /* page flip completed. clean up */ @@ -4736,6 +4735,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct amdgpu_bo *abo; uint64_t tiling_flags, dcc_address; uint32_t target, target_vblank; + uint64_t last_flip_vblank; + bool vrr_active = acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE; struct { struct dc_surface_update surface_updates[MAX_SURFACES]; @@ -4889,7 +4890,31 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * hopefully eliminating dc_*_update structs in their entirety. */ if (flip_count) { - target = (uint32_t)drm_crtc_vblank_count(pcrtc) + *wait_for_vblank; + if (!vrr_active) { + /* Use old throttling in non-vrr fixed refresh rate mode + * to keep flip scheduling based on target vblank counts + * working in a backwards compatible way, e.g., for + * clients using the GLX_OML_sync_control extension or + * DRI3/Present extension with defined target_msc. + */ + last_flip_vblank = drm_crtc_vblank_count(pcrtc); + } + else { + /* For variable refresh rate mode only: + * Get vblank of last completed flip to avoid > 1 vrr + * flips per video frame by use of throttling, but allow + * flip programming anywhere in the possibly large + * variable vrr vblank interval for fine-grained flip + * timing control and more opportunity to avoid stutter + * on late submission of flips. + */ + spin_lock_irqsave(&pcrtc->dev->event_lock, flags); + last_flip_vblank = acrtc_attach->last_flip_vblank; + spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); + } + + target = (uint32_t)last_flip_vblank + *wait_for_vblank; + /* Prepare wait for target vblank early - before the fence-waits */ target_vblank = target - (uint32_t)drm_crtc_vblank_count(pcrtc) + amdgpu_get_vblank_counter_kms(pcrtc->dev, acrtc_attach->crtc_id); -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mario Kleiner Subject: [PATCH] drm/amd/display: Use vrr friendly pageflip throttling in DC. Date: Sat, 9 Feb 2019 07:52:55 +0100 Message-ID: <20190209065255.9480-1-mario.kleiner.de@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: amd-gfx@lists.freedesktop.org Cc: =?UTF-8?q?Michel=20D=C3=A4nzer?= , stable@vger.kernel.org, dri-devel@lists.freedesktop.org, Alex Deucher , Nicholas Kazlauskas List-Id: dri-devel@lists.freedesktop.org SW4gVlJSIG1vZGUsIGtlZXAgdHJhY2sgb2YgdGhlIHZibGFuayBjb3VudCBvZiB0aGUgbGFzdApj b21wbGV0ZWQgcGFnZWZsaXAgaW4gYW1kZ3B1X2NydGMtPmxhc3RfZmxpcF92YmxhbmssIGFzCnJl Y29yZGVkIGluIHRoZSBwYWdlZmxpcCBjb21wbGV0aW9uIGhhbmRsZXIgYWZ0ZXIgZWFjaApjb21w bGV0ZWQgZmxpcC4KClVzZSB0aGF0IGNvdW50IHRvIHByZXZlbnQgbW1pbyBwcm9ncmFtbWluZyBh IG5ldyBwYWdlZmxpcAp3aXRoaW4gdGhlIHNhbWUgdmJsYW5rIGluIHdoaWNoIHRoZSBsYXN0IHBh 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