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[90.86.93.32]) by smtp.gmail.com with ESMTPSA id c14sm3708656wrn.12.2019.02.12.02.39.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Feb 2019 02:39:27 -0800 (PST) From: Bartosz Golaszewski To: Sekhar Nori , Kevin Hilman , Thomas Gleixner , Jason Cooper , Marc Zyngier , David Lechner Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v3 27/37] ARM: davinci: cp-intc: use a common prefix for all symbols Date: Tue, 12 Feb 2019 11:38:25 +0100 Message-Id: <20190212103835.7768-28-brgl@bgdev.pl> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190212103835.7768-1-brgl@bgdev.pl> References: <20190212103835.7768-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bartosz Golaszewski In preparation for moving the driver to drivers/irqchip do some cleanup: use a common prefix for all symbols. Signed-off-by: Bartosz Golaszewski Reviewed-by: David Lechner --- arch/arm/mach-davinci/cp_intc.c | 144 ++++++++++---------- arch/arm/mach-davinci/da830.c | 2 +- arch/arm/mach-davinci/da850.c | 2 +- arch/arm/mach-davinci/include/mach/common.h | 2 +- 4 files changed, 77 insertions(+), 73 deletions(-) diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 82110d332c82..bf77b6950273 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -22,63 +22,67 @@ #include #include -#define CP_INTC_CTRL 0x04 -#define CP_INTC_HOST_CTRL 0x0C -#define CP_INTC_GLOBAL_ENABLE 0x10 -#define CP_INTC_SYS_STAT_IDX_CLR 0x24 -#define CP_INTC_SYS_ENABLE_IDX_SET 0x28 -#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C -#define CP_INTC_HOST_ENABLE_IDX_SET 0x34 -#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38 -#define CP_INTC_PRIO_IDX 0x80 -#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2)) -#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2)) -#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2)) -#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2)) -#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2)) -#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2)) - +#define DAVINCI_CP_INTC_CTRL 0x04 +#define DAVINCI_CP_INTC_HOST_CTRL 0x0C +#define DAVINCI_CP_INTC_GLOBAL_ENABLE 0x10 +#define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR 0x24 +#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET 0x28 +#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR 0x2C +#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34 +#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38 +#define DAVINCI_CP_INTC_PRIO_IDX 0x80 +#define DAVINCI_CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2)) +#define DAVINCI_CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2)) +#define DAVINCI_CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2)) +#define DAVINCI_CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2)) +#define DAVINCI_CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2)) +#define DAVINCI_CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2)) #define DAVINCI_CP_INTC_PRI_INDX_MASK GENMASK(9, 0) #define DAVINCI_CP_INTC_GPIR_NONE BIT(31) -static void __iomem *davinci_intc_base; +static void __iomem *davinci_cp_intc_base; +static struct irq_domain *davinci_cp_intc_irq_domain; -static inline unsigned int cp_intc_read(unsigned offset) +static inline unsigned int davinci_cp_intc_read(unsigned int offset) { - return __raw_readl(davinci_intc_base + offset); + return __raw_readl(davinci_cp_intc_base + offset); } -static inline void cp_intc_write(unsigned long value, unsigned offset) +static inline void davinci_cp_intc_write(unsigned long value, + unsigned int offset) { - __raw_writel(value, davinci_intc_base + offset); + __raw_writel(value, davinci_cp_intc_base + offset); } -static void cp_intc_ack_irq(struct irq_data *d) +static void davinci_cp_intc_ack_irq(struct irq_data *d) { - cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR); + davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_STAT_IDX_CLR); } /* Disable interrupt */ -static void cp_intc_mask_irq(struct irq_data *d) +static void davinci_cp_intc_mask_irq(struct irq_data *d) { /* XXX don't know why we need to disable nIRQ here... */ - cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR); - cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR); - cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); + davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR); + davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR); + davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET); } /* Enable interrupt */ -static void cp_intc_unmask_irq(struct irq_data *d) +static void davinci_cp_intc_unmask_irq(struct irq_data *d) { - cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET); + davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET); } -static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type) +static int davinci_cp_intc_set_irq_type(struct irq_data *d, + unsigned int flow_type) { unsigned reg = BIT_WORD(d->hwirq); unsigned mask = BIT_MASK(d->hwirq); - unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg)); - unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg)); + unsigned polarity = davinci_cp_intc_read( + DAVINCI_CP_INTC_SYS_POLARITY(reg)); + unsigned type = davinci_cp_intc_read( + DAVINCI_CP_INTC_SYS_TYPE(reg)); switch (flow_type) { case IRQ_TYPE_EDGE_RISING: @@ -101,25 +105,23 @@ static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type) return -EINVAL; } - cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg)); - cp_intc_write(type, CP_INTC_SYS_TYPE(reg)); + davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg)); + davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg)); return 0; } -static struct irq_chip cp_intc_irq_chip = { +static struct irq_chip davinci_cp_intc_irq_chip = { .name = "cp_intc", - .irq_ack = cp_intc_ack_irq, - .irq_mask = cp_intc_mask_irq, - .irq_unmask = cp_intc_unmask_irq, - .irq_set_type = cp_intc_set_irq_type, + .irq_ack = davinci_cp_intc_ack_irq, + .irq_mask = davinci_cp_intc_mask_irq, + .irq_unmask = davinci_cp_intc_unmask_irq, + .irq_set_type = davinci_cp_intc_set_irq_type, .flags = IRQCHIP_SKIP_SET_WAKE, }; -static struct irq_domain *cp_intc_domain; - static asmlinkage void __exception_irq_entry -cp_intc_handle_irq(struct pt_regs *regs) +davinci_cp_intc_handle_irq(struct pt_regs *regs) { int gpir, irqnr, none; @@ -128,7 +130,7 @@ cp_intc_handle_irq(struct pt_regs *regs) * indicates a spurious irq. */ - gpir = cp_intc_read(CP_INTC_PRIO_IDX); + gpir = davinci_cp_intc_read(DAVINCI_CP_INTC_PRIO_IDX); irqnr = gpir & DAVINCI_CP_INTC_PRI_INDX_MASK; none = gpir & DAVINCI_CP_INTC_GPIR_NONE; @@ -137,27 +139,27 @@ cp_intc_handle_irq(struct pt_regs *regs) return; } - handle_domain_irq(cp_intc_domain, irqnr, regs); + handle_domain_irq(davinci_cp_intc_irq_domain, irqnr, regs); } -static int cp_intc_host_map(struct irq_domain *h, unsigned int virq, +static int davinci_cp_intc_host_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw); - irq_set_chip(virq, &cp_intc_irq_chip); + irq_set_chip(virq, &davinci_cp_intc_irq_chip); irq_set_probe(virq); irq_set_handler(virq, handle_edge_irq); return 0; } -static const struct irq_domain_ops cp_intc_host_ops = { - .map = cp_intc_host_map, +static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = { + .map = davinci_cp_intc_host_map, .xlate = irq_domain_xlate_onetwocell, }; -static int __init cp_intc_of_init(struct device_node *node, - struct device_node *parent) +static int __init davinci_cp_intc_of_init(struct device_node *node, + struct device_node *parent) { u32 num_irq = davinci_soc_info.intc_irq_num; u8 *irq_prio = davinci_soc_info.intc_irq_prios; @@ -165,35 +167,35 @@ static int __init cp_intc_of_init(struct device_node *node, int i, irq_base; if (node) { - davinci_intc_base = of_iomap(node, 0); + davinci_cp_intc_base = of_iomap(node, 0); if (of_property_read_u32(node, "ti,intc-size", &num_irq)) pr_warn("unable to get intc-size, default to %d\n", num_irq); } else { - davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); + davinci_cp_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); } - if (WARN_ON(!davinci_intc_base)) + if (WARN_ON(!davinci_cp_intc_base)) return -EINVAL; - cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); + davinci_cp_intc_write(0, DAVINCI_CP_INTC_GLOBAL_ENABLE); /* Disable all host interrupts */ - cp_intc_write(0, CP_INTC_HOST_ENABLE(0)); + davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0)); /* Disable system interrupts */ for (i = 0; i < num_reg; i++) - cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i)); + davinci_cp_intc_write(~0, DAVINCI_CP_INTC_SYS_ENABLE_CLR(i)); /* Set to normal mode, no nesting, no priority hold */ - cp_intc_write(0, CP_INTC_CTRL); - cp_intc_write(0, CP_INTC_HOST_CTRL); + davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL); + davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL); /* Clear system interrupt status */ for (i = 0; i < num_reg; i++) - cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i)); + davinci_cp_intc_write(~0, DAVINCI_CP_INTC_SYS_STAT_CLR(i)); /* Enable nIRQ (what about nFIQ?) */ - cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); + davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET); /* * Priority is determined by host channel: lower channel number has @@ -212,7 +214,7 @@ static int __init cp_intc_of_init(struct device_node *node, val |= irq_prio[k] << 24; } - cp_intc_write(val, CP_INTC_CHAN_MAP(i)); + davinci_cp_intc_write(val, DAVINCI_CP_INTC_CHAN_MAP(i)); } } else { /* @@ -221,7 +223,8 @@ static int __init cp_intc_of_init(struct device_node *node, * are mapped to nIRQ. */ for (i = 0; i < num_reg; i++) - cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i)); + davinci_cp_intc_write(0x0f0f0f0f, + DAVINCI_CP_INTC_CHAN_MAP(i)); } irq_base = irq_alloc_descs(-1, 0, num_irq, 0); @@ -231,25 +234,26 @@ static int __init cp_intc_of_init(struct device_node *node, } /* create a legacy host */ - cp_intc_domain = irq_domain_add_legacy(node, num_irq, - irq_base, 0, &cp_intc_host_ops, NULL); + davinci_cp_intc_irq_domain = irq_domain_add_legacy( + node, num_irq, irq_base, 0, + &davinci_cp_intc_irq_domain_ops, NULL); - if (!cp_intc_domain) { + if (!davinci_cp_intc_irq_domain) { pr_err("cp_intc: failed to allocate irq host!\n"); return -EINVAL; } - set_handle_irq(cp_intc_handle_irq); + set_handle_irq(davinci_cp_intc_handle_irq); /* Enable global interrupt */ - cp_intc_write(1, CP_INTC_GLOBAL_ENABLE); + davinci_cp_intc_write(1, DAVINCI_CP_INTC_GLOBAL_ENABLE); return 0; } -void __init cp_intc_init(void) +void __init davinci_cp_intc_init(void) { - cp_intc_of_init(NULL, NULL); + davinci_cp_intc_of_init(NULL, NULL); } -IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", cp_intc_of_init); +IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init); diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 38af72be1a85..0eb48ed2d423 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -833,7 +833,7 @@ static const struct davinci_cp_intc_config da830_cp_intc_config = { void __init da830_init_irq(void) { - cp_intc_init(); + davinci_cp_intc_init(); } void __init da830_init_time(void) diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 9a3ce68c0de4..fe274ab63fc8 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -771,7 +771,7 @@ static const struct davinci_cp_intc_config da850_cp_intc_config = { void __init da850_init_irq(void) { - cp_intc_init(); + davinci_cp_intc_init(); } void __init da850_init_time(void) diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index 3f3f1169d47e..7ad79171b4b5 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -22,7 +22,7 @@ #define DAVINCI_INTC_START NR_IRQS #define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum)) -void cp_intc_init(void); +void davinci_cp_intc_init(void); void davinci_timer_init(struct clk *clk); struct davinci_timer_instance { -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D17BC282C4 for ; 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[90.86.93.32]) by smtp.gmail.com with ESMTPSA id c14sm3708656wrn.12.2019.02.12.02.39.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Feb 2019 02:39:27 -0800 (PST) From: Bartosz Golaszewski To: Sekhar Nori , Kevin Hilman , Thomas Gleixner , Jason Cooper , Marc Zyngier , David Lechner Subject: [PATCH v3 27/37] ARM: davinci: cp-intc: use a common prefix for all symbols Date: Tue, 12 Feb 2019 11:38:25 +0100 Message-Id: <20190212103835.7768-28-brgl@bgdev.pl> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190212103835.7768-1-brgl@bgdev.pl> References: <20190212103835.7768-1-brgl@bgdev.pl> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190212_023930_164136_4EEDC344 X-CRM114-Status: GOOD ( 19.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Bartosz Golaszewski In preparation for moving the driver to drivers/irqchip do some cleanup: use a common prefix for all symbols. Signed-off-by: Bartosz Golaszewski Reviewed-by: David Lechner --- arch/arm/mach-davinci/cp_intc.c | 144 ++++++++++---------- arch/arm/mach-davinci/da830.c | 2 +- arch/arm/mach-davinci/da850.c | 2 +- arch/arm/mach-davinci/include/mach/common.h | 2 +- 4 files changed, 77 insertions(+), 73 deletions(-) diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 82110d332c82..bf77b6950273 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -22,63 +22,67 @@ #include #include -#define CP_INTC_CTRL 0x04 -#define CP_INTC_HOST_CTRL 0x0C -#define CP_INTC_GLOBAL_ENABLE 0x10 -#define CP_INTC_SYS_STAT_IDX_CLR 0x24 -#define CP_INTC_SYS_ENABLE_IDX_SET 0x28 -#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C -#define CP_INTC_HOST_ENABLE_IDX_SET 0x34 -#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38 -#define CP_INTC_PRIO_IDX 0x80 -#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2)) -#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2)) -#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2)) -#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2)) -#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2)) -#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2)) - +#define DAVINCI_CP_INTC_CTRL 0x04 +#define DAVINCI_CP_INTC_HOST_CTRL 0x0C +#define DAVINCI_CP_INTC_GLOBAL_ENABLE 0x10 +#define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR 0x24 +#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET 0x28 +#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR 0x2C +#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34 +#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38 +#define DAVINCI_CP_INTC_PRIO_IDX 0x80 +#define DAVINCI_CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2)) +#define DAVINCI_CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2)) +#define DAVINCI_CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2)) +#define DAVINCI_CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2)) +#define DAVINCI_CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2)) +#define DAVINCI_CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2)) #define DAVINCI_CP_INTC_PRI_INDX_MASK GENMASK(9, 0) #define DAVINCI_CP_INTC_GPIR_NONE BIT(31) -static void __iomem *davinci_intc_base; +static void __iomem *davinci_cp_intc_base; +static struct irq_domain *davinci_cp_intc_irq_domain; -static inline unsigned int cp_intc_read(unsigned offset) +static inline unsigned int davinci_cp_intc_read(unsigned int offset) { - return __raw_readl(davinci_intc_base + offset); + return __raw_readl(davinci_cp_intc_base + offset); } -static inline void cp_intc_write(unsigned long value, unsigned offset) +static inline void davinci_cp_intc_write(unsigned long value, + unsigned int offset) { - __raw_writel(value, davinci_intc_base + offset); + __raw_writel(value, davinci_cp_intc_base + offset); } -static void cp_intc_ack_irq(struct irq_data *d) +static void davinci_cp_intc_ack_irq(struct irq_data *d) { - cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR); + davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_STAT_IDX_CLR); } /* Disable interrupt */ -static void cp_intc_mask_irq(struct irq_data *d) +static void davinci_cp_intc_mask_irq(struct irq_data *d) { /* XXX don't know why we need to disable nIRQ here... */ - cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR); - cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR); - cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); + davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR); + davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR); + davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET); } /* Enable interrupt */ -static void cp_intc_unmask_irq(struct irq_data *d) +static void davinci_cp_intc_unmask_irq(struct irq_data *d) { - cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET); + davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET); } -static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type) +static int davinci_cp_intc_set_irq_type(struct irq_data *d, + unsigned int flow_type) { unsigned reg = BIT_WORD(d->hwirq); unsigned mask = BIT_MASK(d->hwirq); - unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg)); - unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg)); + unsigned polarity = davinci_cp_intc_read( + DAVINCI_CP_INTC_SYS_POLARITY(reg)); + unsigned type = davinci_cp_intc_read( + DAVINCI_CP_INTC_SYS_TYPE(reg)); switch (flow_type) { case IRQ_TYPE_EDGE_RISING: @@ -101,25 +105,23 @@ static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type) return -EINVAL; } - cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg)); - cp_intc_write(type, CP_INTC_SYS_TYPE(reg)); + davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg)); + davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg)); return 0; } -static struct irq_chip cp_intc_irq_chip = { +static struct irq_chip davinci_cp_intc_irq_chip = { .name = "cp_intc", - .irq_ack = cp_intc_ack_irq, - .irq_mask = cp_intc_mask_irq, - .irq_unmask = cp_intc_unmask_irq, - .irq_set_type = cp_intc_set_irq_type, + .irq_ack = davinci_cp_intc_ack_irq, + .irq_mask = davinci_cp_intc_mask_irq, + .irq_unmask = davinci_cp_intc_unmask_irq, + .irq_set_type = davinci_cp_intc_set_irq_type, .flags = IRQCHIP_SKIP_SET_WAKE, }; -static struct irq_domain *cp_intc_domain; - static asmlinkage void __exception_irq_entry -cp_intc_handle_irq(struct pt_regs *regs) +davinci_cp_intc_handle_irq(struct pt_regs *regs) { int gpir, irqnr, none; @@ -128,7 +130,7 @@ cp_intc_handle_irq(struct pt_regs *regs) * indicates a spurious irq. */ - gpir = cp_intc_read(CP_INTC_PRIO_IDX); + gpir = davinci_cp_intc_read(DAVINCI_CP_INTC_PRIO_IDX); irqnr = gpir & DAVINCI_CP_INTC_PRI_INDX_MASK; none = gpir & DAVINCI_CP_INTC_GPIR_NONE; @@ -137,27 +139,27 @@ cp_intc_handle_irq(struct pt_regs *regs) return; } - handle_domain_irq(cp_intc_domain, irqnr, regs); + handle_domain_irq(davinci_cp_intc_irq_domain, irqnr, regs); } -static int cp_intc_host_map(struct irq_domain *h, unsigned int virq, +static int davinci_cp_intc_host_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw); - irq_set_chip(virq, &cp_intc_irq_chip); + irq_set_chip(virq, &davinci_cp_intc_irq_chip); irq_set_probe(virq); irq_set_handler(virq, handle_edge_irq); return 0; } -static const struct irq_domain_ops cp_intc_host_ops = { - .map = cp_intc_host_map, +static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = { + .map = davinci_cp_intc_host_map, .xlate = irq_domain_xlate_onetwocell, }; -static int __init cp_intc_of_init(struct device_node *node, - struct device_node *parent) +static int __init davinci_cp_intc_of_init(struct device_node *node, + struct device_node *parent) { u32 num_irq = davinci_soc_info.intc_irq_num; u8 *irq_prio = davinci_soc_info.intc_irq_prios; @@ -165,35 +167,35 @@ static int __init cp_intc_of_init(struct device_node *node, int i, irq_base; if (node) { - davinci_intc_base = of_iomap(node, 0); + davinci_cp_intc_base = of_iomap(node, 0); if (of_property_read_u32(node, "ti,intc-size", &num_irq)) pr_warn("unable to get intc-size, default to %d\n", num_irq); } else { - davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); + davinci_cp_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); } - if (WARN_ON(!davinci_intc_base)) + if (WARN_ON(!davinci_cp_intc_base)) return -EINVAL; - cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); + davinci_cp_intc_write(0, DAVINCI_CP_INTC_GLOBAL_ENABLE); /* Disable all host interrupts */ - cp_intc_write(0, CP_INTC_HOST_ENABLE(0)); + davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0)); /* Disable system interrupts */ for (i = 0; i < num_reg; i++) - cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i)); + davinci_cp_intc_write(~0, DAVINCI_CP_INTC_SYS_ENABLE_CLR(i)); /* Set to normal mode, no nesting, no priority hold */ - cp_intc_write(0, CP_INTC_CTRL); - cp_intc_write(0, CP_INTC_HOST_CTRL); + davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL); + davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL); /* Clear system interrupt status */ for (i = 0; i < num_reg; i++) - cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i)); + davinci_cp_intc_write(~0, DAVINCI_CP_INTC_SYS_STAT_CLR(i)); /* Enable nIRQ (what about nFIQ?) */ - cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); + davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET); /* * Priority is determined by host channel: lower channel number has @@ -212,7 +214,7 @@ static int __init cp_intc_of_init(struct device_node *node, val |= irq_prio[k] << 24; } - cp_intc_write(val, CP_INTC_CHAN_MAP(i)); + davinci_cp_intc_write(val, DAVINCI_CP_INTC_CHAN_MAP(i)); } } else { /* @@ -221,7 +223,8 @@ static int __init cp_intc_of_init(struct device_node *node, * are mapped to nIRQ. */ for (i = 0; i < num_reg; i++) - cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i)); + davinci_cp_intc_write(0x0f0f0f0f, + DAVINCI_CP_INTC_CHAN_MAP(i)); } irq_base = irq_alloc_descs(-1, 0, num_irq, 0); @@ -231,25 +234,26 @@ static int __init cp_intc_of_init(struct device_node *node, } /* create a legacy host */ - cp_intc_domain = irq_domain_add_legacy(node, num_irq, - irq_base, 0, &cp_intc_host_ops, NULL); + davinci_cp_intc_irq_domain = irq_domain_add_legacy( + node, num_irq, irq_base, 0, + &davinci_cp_intc_irq_domain_ops, NULL); - if (!cp_intc_domain) { + if (!davinci_cp_intc_irq_domain) { pr_err("cp_intc: failed to allocate irq host!\n"); return -EINVAL; } - set_handle_irq(cp_intc_handle_irq); + set_handle_irq(davinci_cp_intc_handle_irq); /* Enable global interrupt */ - cp_intc_write(1, CP_INTC_GLOBAL_ENABLE); + davinci_cp_intc_write(1, DAVINCI_CP_INTC_GLOBAL_ENABLE); return 0; } -void __init cp_intc_init(void) +void __init davinci_cp_intc_init(void) { - cp_intc_of_init(NULL, NULL); + davinci_cp_intc_of_init(NULL, NULL); } -IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", cp_intc_of_init); +IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init); diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 38af72be1a85..0eb48ed2d423 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -833,7 +833,7 @@ static const struct davinci_cp_intc_config da830_cp_intc_config = { void __init da830_init_irq(void) { - cp_intc_init(); + davinci_cp_intc_init(); } void __init da830_init_time(void) diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 9a3ce68c0de4..fe274ab63fc8 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -771,7 +771,7 @@ static const struct davinci_cp_intc_config da850_cp_intc_config = { void __init da850_init_irq(void) { - cp_intc_init(); + davinci_cp_intc_init(); } void __init da850_init_time(void) diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index 3f3f1169d47e..7ad79171b4b5 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -22,7 +22,7 @@ #define DAVINCI_INTC_START NR_IRQS #define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum)) -void cp_intc_init(void); +void davinci_cp_intc_init(void); void davinci_timer_init(struct clk *clk); struct davinci_timer_instance { -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel