[U-Boot] [PATCH v2 0/3] ddr: vybrid: Support for vf610 built-in DDR3 memory calibration

[U-Boot] [PATCH v2 0/3] ddr: vybrid: Support for vf610 built-in DDR3 memory calibration

[Lukasz Majewski]

This patch series provides code to perform read leveling - RDLVL, which
is adjusting the DQS strobe in relation to the DQ signals so that the
strobe edge is centered in the window of valid read data.

The code is based on Vybrid's Reference Manual's:
"VFxxx Controller Reference Manual, Rev. 0, 10/2016", page 1600,
10.1.6.16.4.1 "Software Read Leveling in MC Evaluation Mode"

and uses clarification provided by following NXP's community thread:
"Vybrid: About DDR leveling feature on DDRMC."
https://community.nxp.com/thread/395323

It depends on a BITMAP rework patch:
usb: composite: Move bitmap related operations to ./include/linux/bitmap.h
http://patchwork.ozlabs.org/patch/1006448/


Changes in v2:
- CR93_SWLVL_EXIT -> CR94_SWLVL_EXIT (EXIT is in CR94)
- Add more defines to imx-regs.h (moved from *-calibration.h)
 - CR93_SWLVL_EXIT -> CR94_SWLVL_EXIT (EXIT is in CR94)
 - Update Kconfig information regarding DDRMC_VF610_CALIBRATION
 - Update ddrmc-vf610-calibration. comment
 - Update code after extending imx-regs.h
 - Remove not needed #ifdef

Lukasz Majewski (3):
  ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ)
  ddr: vybrid: Provide code to perform on-boot calibration
  ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup
    code

 arch/arm/include/asm/arch-vf610/imx-regs.h  |  14 +-
 arch/arm/mach-imx/Kconfig                   |  12 +
 arch/arm/mach-imx/Makefile                  |   1 +
 arch/arm/mach-imx/ddrmc-vf610-calibration.c | 342 ++++++++++++++++++++++++++++
 arch/arm/mach-imx/ddrmc-vf610-calibration.h |  45 ++++
 arch/arm/mach-imx/ddrmc-vf610.c             |   5 +
 6 files changed, 418 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-imx/ddrmc-vf610-calibration.c
 create mode 100644 arch/arm/mach-imx/ddrmc-vf610-calibration.h

-- 
2.11.0

[U-Boot] [PATCH v2 1/3] ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ)

[Lukasz Majewski]

This commit provides extra defines needed for DDR memory controller
calibration (read leveling performing).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>

---

Changes in v2:
- CR93_SWLVL_EXIT -> CR94_SWLVL_EXIT (EXIT is in CR94)
- Add more defines to imx-regs.h (moved from *-calibration.h)

 arch/arm/include/asm/arch-vf610/imx-regs.h | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 08ba8e94f8..e3209b0f56 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -206,15 +206,27 @@
 #define DDRMC_CR88_TODTL_CMD(v)				(((v) & 0x1f) << 16)
 #define DDRMC_CR89_AODT_RWSMCS(v)			((v) & 0xf)
 #define DDRMC_CR91_R2W_SMCSDL(v)			(((v) & 0x7) << 16)
+#define DDRMC_CR93_SW_LVL_MODE_OFF			(8)
+#define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << DDRMC_CR93_SW_LVL_MODE_OFF)
+#define DDRMC_CR93_SWLVL_LOAD				BIT(16)
+#define DDRMC_CR93_SWLVL_START				BIT(24)
+#define DDRMC_CR94_SWLVL_EXIT				BIT(0)
+#define DDRMC_CR94_SWLVL_OP_DONE			BIT(8)
+#define DDRMC_CR94_SWLVL_RESP_0_OFF			(24)
+#define DDRMC_CR95_SWLVL_RESP_1_OFF			(0)
 #define DDRMC_CR96_WLMRD(v)				(((v) & 0x3f) << 8)
 #define DDRMC_CR96_WLDQSEN(v)				((v) & 0x3f)
 #define DDRMC_CR97_WRLVL_EN				(1 << 24)
 #define DDRMC_CR98_WRLVL_DL_0(v)			((v) & 0xffff)
 #define DDRMC_CR99_WRLVL_DL_1(v)			((v) & 0xffff)
+#define DDRMC_CR101_PHY_RDLVL_EDGE_OFF			(24)
+#define DDRMC_CR101_PHY_RDLVL_EDGE BIT(DDRMC_CR101_PHY_RDLVL_EDGE_OFF)
 #define DDRMC_CR102_RDLVL_GT_REGEN			(1 << 16)
 #define DDRMC_CR102_RDLVL_REG_EN			(1 << 8)
-#define DDRMC_CR105_RDLVL_DL_0(v)			(((v) & 0xff) << 8)
+#define DDRMC_CR105_RDLVL_DL_0_OFF			(8)
+#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << DDRMC_CR105_RDLVL_DL_0_OFF)
 #define DDRMC_CR106_RDLVL_GTDL_0(v)			((v) & 0xff)
+#define DDRMC_CR110_RDLVL_DL_1_OFF			(0)
 #define DDRMC_CR110_RDLVL_DL_1(v)			((v) & 0xff)
 #define DDRMC_CR110_RDLVL_GTDL_1(v)			(((v) & 0xff) << 16)
 #define DDRMC_CR114_RDLVL_GTDL_2(v)			(((v) & 0xffff) << 8)
-- 
2.11.0

[U-Boot] [PATCH v2 2/3] ddr: vybrid: Provide code to perform on-boot calibration

[Lukasz Majewski]

This patch provides the code to calibrate the DDR's
DQS to DQ signals (RDLVL).

It is based on:
VFxxx Controller Reference Manual, Rev. 0, 10/2016, page 1600
10.1.6.16.4.1 "Software Read Leveling in MC Evaluation Mode"

and NXP's community thread:
"Vybrid: About DDR leveling feature on DDRMC."
https://community.nxp.com/thread/395323

Signed-off-by: Lukasz Majewski <lukma@denx.de>

---

Changes in v2:
 - CR93_SWLVL_EXIT -> CR94_SWLVL_EXIT (EXIT is in CR94)
 - Update Kconfig information regarding DDRMC_VF610_CALIBRATION
 - Update ddrmc-vf610-calibration. comment
 - Update code after extending imx-regs.h

 arch/arm/mach-imx/Kconfig                   |  12 +
 arch/arm/mach-imx/Makefile                  |   1 +
 arch/arm/mach-imx/ddrmc-vf610-calibration.c | 342 ++++++++++++++++++++++++++++
 arch/arm/mach-imx/ddrmc-vf610-calibration.h |  45 ++++
 4 files changed, 400 insertions(+)
 create mode 100644 arch/arm/mach-imx/ddrmc-vf610-calibration.c
 create mode 100644 arch/arm/mach-imx/ddrmc-vf610-calibration.h

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index a1566cc2ad..8631fbd481 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -78,3 +78,15 @@ config NXP_BOARD_REVISION
 	  NXP boards based on i.MX6/7 contain the board revision information
 	  stored in the fuses. Select this option if you want to be able to
 	  retrieve the board revision information.
+
+config DDRMC_VF610_CALIBRATION
+	bool "Enable DDRMC (DDR3) on-chip calibration"
+	depends on ARCH_VF610
+	help
+	  Vybrid (vf610) SoC provides some on-chip facility to tune the DDR3
+	  memory parameters. Select this option if you want to calculate them
+	  at boot time.
+	  NOTE:
+	  NXP does NOT recommend to perform this calibration at each boot. One
+	  shall perform it on a new PCB and then use those values to program
+	  the ddrmc_cr_setting on relevant board file.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 53d9e5f42b..4a07b1ea69 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_SECURE_BOOT) += hab.o
 endif
 ifeq ($(SOC),$(filter $(SOC),vf610))
 obj-y += ddrmc-vf610.o
+obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o
 endif
 ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
diff --git a/arch/arm/mach-imx/ddrmc-vf610-calibration.c b/arch/arm/mach-imx/ddrmc-vf610-calibration.c
new file mode 100644
index 0000000000..f29de74c39
--- /dev/null
+++ b/arch/arm/mach-imx/ddrmc-vf610-calibration.c
@@ -0,0 +1,342 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ddrmc DDR3 calibration code for NXP's VF610
+ *
+ * Copyright (C) 2018 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ *
+ */
+/* #define DEBUG */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/bitmap.h>
+
+#include "ddrmc-vf610-calibration.h"
+
+/*
+ * Documents:
+ *
+ * [1] "Vybrid: About DDR leveling feature on DDRMC."
+ * https://community.nxp.com/thread/395323
+ *
+ * [2] VFxxx Controller Reference Manual, Rev. 0, 10/2016
+ *
+ *
+ * NOTE
+ * ====
+ *
+ * NXP recommends setting 'fixed' parameters instead of performing the
+ * training at each boot.
+ *
+ * Use those functions to determine those values on new HW, read the
+ * calculated value from registers and add them to the board specific
+ * struct ddrmc_cr_setting.
+ *
+ * SW leveling supported operations - CR93[SW_LVL_MODE]:
+ *
+ * - 0x0 (b'00) - No leveling
+ *
+ * - 0x1 (b'01) - WRLVL_DL_X - It is not recommended to perform this tuning
+ *                             on HW designs utilizing non-flyback topology
+ *                             (Single DDR3 with x16).
+ *                             Instead the WRLVL_DL_0/1 fields shall be set
+ *                             based on trace length differences from their
+ *                             layout.
+ *                             Mismatches up to 25% or tCK (clock period) are
+ *                             allowed, so the value in the filed doesn’t have
+ *                             to be very accurate.
+ *
+ * - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation
+ *                             to the DQ signals so that the strobe edge is
+ *                             centered in the window of valid read data.
+ *
+ * - 0x3 (b'11) - RDLVL_GTDL_0/1 - refers to the delay the PHY uses to un-gate
+ *                             the Read DQS strobe pad from the time that the
+ *                             PHY enables the pad to input the strobe signal.
+ *
+ */
+static int ddr_cal_get_first_edge_index(unsigned long *bmap, enum edge e,
+					int samples, int start, int max)
+{
+	int i, ret = -1;
+
+	/*
+	 * We look only for the first value (and filter out
+	 * some wrong data)
+	 */
+	switch (e) {
+	case RISING_EDGE:
+		for (i = start; i <= max - samples; i++) {
+			if (test_bit(i, bmap)) {
+				if (!test_bit(i - 1, bmap) &&
+				    test_bit(i + 1, bmap) &&
+				    test_bit(i + 2, bmap) &&
+				    test_bit(i + 3, bmap)) {
+					return i;
+				}
+			}
+		}
+		break;
+	case FALLING_EDGE:
+		for (i = start; i <= max - samples; i++) {
+			if (!test_bit(i, bmap)) {
+				if (test_bit(i - 1, bmap) &&
+				    test_bit(i - 2, bmap) &&
+				    test_bit(i - 3, bmap)) {
+					return i;
+				}
+			}
+		}
+	}
+
+	return ret;
+}
+
+static void bitmap_print(unsigned long *bmap, int max)
+{
+	int i;
+
+	debug("BITMAP [0x%p]:\n", bmap);
+	for (i = 0; i <= max; i++) {
+		debug("%d ", test_bit(i, bmap) ? 1 : 0);
+		if (i && (i % 32) == (32 - 1))
+			debug("\n");
+	}
+	debug("\n");
+}
+
+#define sw_leveling_op_done \
+	while (!(readl(&ddrmr->cr[94]) & DDRMC_CR94_SWLVL_OP_DONE))
+
+#define sw_leveling_load_value \
+	do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_LOAD, \
+			     DDRMC_CR93_SWLVL_LOAD); } while (0)
+
+#define sw_leveling_start \
+	do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_START, \
+			     DDRMC_CR93_SWLVL_START); } while (0)
+
+#define sw_leveling_exit \
+	do { clrsetbits_le32(&ddrmr->cr[94], DDRMC_CR94_SWLVL_EXIT, \
+			     DDRMC_CR94_SWLVL_EXIT); } while (0)
+
+/*
+ * RDLVL_DL calibration:
+ *
+ * NXP is _NOT_ recommending performing the leveling at each
+ * boot. Instead - one shall run this procedure on new boards
+ * and then use hardcoded values.
+ *
+ */
+static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
+{
+	DECLARE_BITMAP(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
+	int rdlvl_dl_0_min = -1, rdlvl_dl_0_max = -1;
+	int rdlvl_dl_1_min = -1, rdlvl_dl_1_max = -1;
+	int rdlvl_dl_0, rdlvl_dl_1;
+	u8 swlvl_rsp;
+	u32 tmp;
+	int i;
+
+	/* Read defaults */
+	u16 rdlvl_dl_0_def =
+		(readl(&ddrmr->cr[105]) >> DDRMC_CR105_RDLVL_DL_0_OFF) & 0xFFFF;
+	u16 rdlvl_dl_1_def = readl(&ddrmr->cr[110]) & 0xFFFF;
+
+	debug("\nRDLVL: ======================\n");
+	debug("RDLVL: DQS to DQ (RDLVL)\n");
+
+	debug("RDLVL: RDLVL_DL_0_DFL:\t 0x%x\n", rdlvl_dl_0_def);
+	debug("RDLVL: RDLVL_DL_1_DFL:\t 0x%x\n", rdlvl_dl_1_def);
+
+	/*
+	 * Set/Read setup for calibration
+	 *
+	 * Values necessary for leveling from Vybrid RM [2] - page 1600
+	 */
+	writel(0x40703030, &ddrmr->cr[144]);
+	writel(0x40, &ddrmr->cr[145]);
+	writel(0x40, &ddrmr->cr[146]);
+
+	tmp = readl(&ddrmr->cr[144]);
+	debug("RDLVL: PHY_RDLVL_RES:\t 0x%x\n", (tmp >> 24) & 0xFF);// set 0x40
+	debug("RDLVL: PHY_RDLV_LOAD:\t 0x%x\n", (tmp >> 16) & 0xFF);// set 0x70
+	debug("RDLVL: PHY_RDLV_DLL:\t 0x%x\n", (tmp >> 8) & 0xFF); // set 0x30
+	debug("RDLVL: PHY_RDLV_EN:\t 0x%x\n", tmp & 0xFF); //set 0x30
+
+	tmp = readl(&ddrmr->cr[145]);
+	debug("RDLVL: PHY_RDLV_RR:\t 0x%x\n", tmp & 0x3FF); //set 0x40
+
+	tmp = readl(&ddrmr->cr[146]);
+	debug("RDLVL: PHY_RDLV_RESP:\t 0x%x\n", tmp); //set 0x40
+
+	/*
+	 * Program/read the leveling edge RDLVL_EDGE = 0
+	 *
+	 * 0x00 is the correct output on SWLVL_RSP_X
+	 * If by any chance 1s are visible -> wrong number read
+	 */
+	clrbits_le32(&ddrmr->cr[101], DDRMC_CR101_PHY_RDLVL_EDGE);
+
+	tmp = readl(&ddrmr->cr[101]);
+	debug("RDLVL: PHY_RDLVL_EDGE:\t 0x%x\n",
+	      (tmp >> DDRMC_CR101_PHY_RDLVL_EDGE_OFF) & 0x1); //set 0
+
+	/* Program Leveling mode - CR93[SW_LVL_MODE] to ’b10 */
+	clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SW_LVL_MODE(0x3),
+			DDRMC_CR93_SW_LVL_MODE(0x2));
+	tmp = readl(&ddrmr->cr[93]);
+	debug("RDLVL: SW_LVL_MODE:\t 0x%x\n",
+	      (tmp >> DDRMC_CR93_SW_LVL_MODE_OFF) & 0x3);
+
+	/* Start procedure - CR93[SWLVL_START] to ’b1 */
+	sw_leveling_start;
+
+	/* Poll CR94[SWLVL_OP_DONE] */
+	sw_leveling_op_done;
+
+	/*
+	 * Program delays for RDLVL_DL_0
+	 *
+	 * The procedure is to increase the delay values from 0 to 0xFF
+	 * and read the response from the DDRMC
+	 */
+	debug("\nRDLVL: ---> RDLVL_DL_0\n");
+	bitmap_zero(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
+
+	for (i = 0; i <= DDRMC_DQS_DQ_MAX_DELAY; i++) {
+		clrsetbits_le32(&ddrmr->cr[105],
+				0xFFFF << DDRMC_CR105_RDLVL_DL_0_OFF,
+				i << DDRMC_CR105_RDLVL_DL_0_OFF);
+
+		/* Load values CR93[SWLVL_LOAD] to ’b1 */
+		sw_leveling_load_value;
+
+		/* Poll CR94[SWLVL_OP_DONE] */
+		sw_leveling_op_done;
+
+		/*
+		 * Read Responses - SWLVL_RESP_0
+		 *
+		 * The 0x00 (correct response when PHY_RDLVL_EDGE = 0)
+		 * -> 1 in the bit vector
+		 */
+		swlvl_rsp = (readl(&ddrmr->cr[94]) >>
+			     DDRMC_CR94_SWLVL_RESP_0_OFF) & 0xF;
+		if (swlvl_rsp == 0)
+			generic_set_bit(i, rdlvl_rsp);
+	}
+
+	bitmap_print(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY);
+
+	/*
+	 * First test for rising edge 0x0 -> 0x1 in bitmap
+	 */
+	rdlvl_dl_0_min = ddr_cal_get_first_edge_index(rdlvl_rsp, RISING_EDGE,
+						      N_SAMPLES, N_SAMPLES,
+						      DDRMC_DQS_DQ_MAX_DELAY);
+
+	/*
+	 * Secondly test for falling edge 0x1 -> 0x0 in bitmap
+	 */
+	rdlvl_dl_0_max = ddr_cal_get_first_edge_index(rdlvl_rsp, FALLING_EDGE,
+						      N_SAMPLES, rdlvl_dl_0_min,
+						      DDRMC_DQS_DQ_MAX_DELAY);
+
+	debug("RDLVL: DL_0 min: %d [0x%x] DL_0 max: %d [0x%x]\n",
+	      rdlvl_dl_0_min, rdlvl_dl_0_min, rdlvl_dl_0_max, rdlvl_dl_0_max);
+	rdlvl_dl_0 = (rdlvl_dl_0_max - rdlvl_dl_0_min) / 2;
+
+	if (rdlvl_dl_0_max == -1 || rdlvl_dl_0_min == -1 || rdlvl_dl_0 <= 0) {
+		debug("RDLVL: The DQS to DQ delay cannot be found!\n");
+		debug("RDLVL: Using default - slice 0: %d!\n", rdlvl_dl_0_def);
+		rdlvl_dl_0 = rdlvl_dl_0_def;
+	}
+
+	debug("\nRDLVL: ---> RDLVL_DL_1\n");
+	bitmap_zero(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
+
+	for (i = 0; i <= DDRMC_DQS_DQ_MAX_DELAY; i++) {
+		clrsetbits_le32(&ddrmr->cr[110],
+				0xFFFF << DDRMC_CR110_RDLVL_DL_1_OFF,
+				i << DDRMC_CR110_RDLVL_DL_1_OFF);
+
+		/* Load values CR93[SWLVL_LOAD] to ’b1 */
+		sw_leveling_load_value;
+
+		/* Poll CR94[SWLVL_OP_DONE] */
+		sw_leveling_op_done;
+
+		/*
+		 * Read Responses - SWLVL_RESP_1
+		 *
+		 * The 0x00 (correct response when PHY_RDLVL_EDGE = 0)
+		 * -> 1 in the bit vector
+		 */
+		swlvl_rsp = (readl(&ddrmr->cr[95]) >>
+			     DDRMC_CR95_SWLVL_RESP_1_OFF) & 0xF;
+		if (swlvl_rsp == 0)
+			generic_set_bit(i, rdlvl_rsp);
+	}
+
+	bitmap_print(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY);
+
+	/*
+	 * First test for rising edge 0x0 -> 0x1 in bitmap
+	 */
+	rdlvl_dl_1_min = ddr_cal_get_first_edge_index(rdlvl_rsp, RISING_EDGE,
+						      N_SAMPLES, N_SAMPLES,
+						      DDRMC_DQS_DQ_MAX_DELAY);
+
+	/*
+	 * Secondly test for falling edge 0x1 -> 0x0 in bitmap
+	 */
+	rdlvl_dl_1_max = ddr_cal_get_first_edge_index(rdlvl_rsp, FALLING_EDGE,
+						      N_SAMPLES, rdlvl_dl_1_min,
+						      DDRMC_DQS_DQ_MAX_DELAY);
+
+	debug("RDLVL: DL_1 min: %d [0x%x] DL_1 max: %d [0x%x]\n",
+	      rdlvl_dl_1_min, rdlvl_dl_1_min, rdlvl_dl_1_max, rdlvl_dl_1_max);
+	rdlvl_dl_1 = (rdlvl_dl_1_max - rdlvl_dl_1_min) / 2;
+
+	if (rdlvl_dl_1_max == -1 || rdlvl_dl_1_min == -1 || rdlvl_dl_1 <= 0) {
+		debug("RDLVL: The DQS to DQ delay cannot be found!\n");
+		debug("RDLVL: Using default - slice 1: %d!\n", rdlvl_dl_1_def);
+		rdlvl_dl_1 = rdlvl_dl_1_def;
+	}
+
+	debug("RDLVL: CALIBRATED: rdlvl_dl_0: 0x%x\t rdlvl_dl_1: 0x%x\n",
+	      rdlvl_dl_0, rdlvl_dl_1);
+
+	/* Write new delay values */
+	writel(DDRMC_CR105_RDLVL_DL_0(rdlvl_dl_0), &ddrmr->cr[105]);
+	writel(DDRMC_CR110_RDLVL_DL_1(rdlvl_dl_1), &ddrmr->cr[110]);
+
+	sw_leveling_load_value;
+	sw_leveling_op_done;
+
+	/* Exit procedure - CR94[SWLVL_EXIT] to ’b1 */
+	sw_leveling_exit;
+
+	/* Poll CR94[SWLVL_OP_DONE] */
+	sw_leveling_op_done;
+
+	return 0;
+}
+
+/*
+ * WRLVL_DL calibration:
+ *
+ * For non-flyback memory architecture - where one have a single DDR3 x16
+ * memory - it is NOT necessary to perform "Write Leveling"
+ * [3] 'Vybrid DDR3 write leveling' https://community.nxp.com/thread/429362
+ *
+ */
+
+int ddrmc_calibration(struct ddrmr_regs *ddrmr)
+{
+	ddrmc_cal_dqs_to_dq(ddrmr);
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/ddrmc-vf610-calibration.h b/arch/arm/mach-imx/ddrmc-vf610-calibration.h
new file mode 100644
index 0000000000..e82e217ab3
--- /dev/null
+++ b/arch/arm/mach-imx/ddrmc-vf610-calibration.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ddrmc DDR3 calibration code for NXP's VF610
+ *
+ * Copyright (C) 2018 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ *
+ */
+
+#ifndef __DDRMC_VF610_CALIBRATOIN_H_
+#define __DDRMC_VF610_CALIBRATOIN_H_
+
+/*
+ * Number of "samples" in the calibration bitmap
+ * to be considered during calibration.
+ */
+#define N_SAMPLES 3
+
+/*
+ * Constants to indicate if we are looking for a rising or
+ * falling edge in the calibration bitmap
+ */
+enum edge {
+	FALLING_EDGE = 1,
+	RISING_EDGE
+};
+
+/*
+ * The max number of delay elements when DQS to DQ setting
+ */
+#define DDRMC_DQS_DQ_MAX_DELAY 0xFF
+
+/**
+ * ddrmc_calibration - Vybrid's (VF610) DDR3 calibration code
+ *
+ * This function is calculating proper memory controller values
+ * during run time.
+ *
+ * @param ddrmr_regs - memory controller registers
+ *
+ * @return 0 on success, otherwise error code
+ */
+int ddrmc_calibration(struct ddrmr_regs *ddrmr);
+
+#endif /* __DDRMC_VF610_CALIBRATOIN_H_ */
-- 
2.11.0

[U-Boot] [PATCH v2 3/3] ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup code

[Lukasz Majewski]

This patch extends the vf610 DDR memory controller code to support SW
leveling.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>


---

Changes in v2:
 - Remove not needed #ifdef

 arch/arm/mach-imx/ddrmc-vf610.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c
index ea6a49e0fa..2f59ec907f 100644
--- a/arch/arm/mach-imx/ddrmc-vf610.c
+++ b/arch/arm/mach-imx/ddrmc-vf610.c
@@ -10,6 +10,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux-vf610.h>
 #include <asm/arch/ddrmc-vf610.h>
+#include "ddrmc-vf610-calibration.h"
 
 void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
 {
@@ -233,4 +234,8 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 
 	while (!(readl(&ddrmr->cr[80]) & 0x100))
 		udelay(10);
+
+#ifdef CONFIG_DDRMC_VF610_CALIBRATION
+	ddrmc_calibration(ddrmr);
+#endif
 }
-- 
2.11.0

[U-Boot] [PATCH] imx: hab: Convert non-NULL IVT DCD pointer warning to an error

[Breno Matheus Lima]

The following NXP application notes and manual recommend to ensure the
IVT DCD pointer is Null prior to calling HAB API authenticate_image()
function:

- AN12263: HABv4 RVT Guidelines and Recommendations
- AN4581: Secure Boot on i.MX50, i.MX53, i.MX 6 and i.MX7 Series using
  HABv4
- CST docs: High Assurance Boot Version 4 Application Programming
  Interface Reference Manual

Commit ca89df7dd46f ("imx: hab: Convert DCD non-NULL error to warning")
converted DCD non-NULL error to warning due to the lack of documentation
at the time of first patch submission. We have warned U-Boot users since
v2018.03, and it makes sense now to follow the NXP recommendation to
ensure the IVT DCD pointer is Null.

DCD commands should only be present in the initial boot image loaded by
the SoC ROM. Starting in HAB v4.3.7 the HAB code  will generate an error
if a DCD pointer is present in an image being authenticated by calling the
HAB RVT API. Older versions of HAB will process and run DCD if it is
present, and this could lead to an incorrect authentication boot flow.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
---
 arch/arm/mach-imx/hab.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index b88acd13da..e07076c726 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -560,8 +560,10 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
 	}
 
 	/* Verify if IVT DCD pointer is NULL */
-	if (ivt->dcd)
-		puts("Warning: DCD pointer should be NULL\n");
+	if (ivt->dcd) {
+		puts("Error: DCD pointer must be NULL\n");
+		goto hab_authentication_exit;
+	}
 
 	start = ddr_start;
 	bytes = image_size;
-- 
2.17.1

[U-Boot] [PATCH v4 1/2] Enable FEC driver to retrieve PHY address from device tree

[Martyn Welch]

Currently if we have more than one phy on the MDIO bus, we do not have a
good mechanism for determining which should be used at runtime. Enable the
FEC driver to determine the address for the PHY from the device tree.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>

---

Changes in v4:
- No changes in v4

Changes in v3:
- No changes in v3

Changes in v2:
- New in v2

 drivers/net/fec_mxc.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 99c5c649a0..425f6197cb 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1264,11 +1264,32 @@ static const struct eth_ops fecmxc_ops = {
 	.read_rom_hwaddr	= fecmxc_read_rom_hwaddr,
 };
 
+static int device_get_phy_addr(struct udevice *dev)
+{
+	struct ofnode_phandle_args phandle_args;
+	int reg;
+
+	if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+				       &phandle_args)) {
+		debug("Failed to find phy-handle");
+		return -ENODEV;
+	}
+
+	reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+	return reg;
+}
+
 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
 {
 	struct phy_device *phydev;
+	int addr;
 	int mask = 0xffffffff;
 
+	addr = device_get_phy_addr(dev);
+	if (addr >= 0)
+		mask = 1 << addr;
+
 #ifdef CONFIG_FEC_MXC_PHYADDR
 	mask = 1 << CONFIG_FEC_MXC_PHYADDR;
 #endif
-- 
2.19.2

[U-Boot] [PATCH v4 2/2] imx: Add PHYTEC phyBOARD-i.MX6UL-Segin

[Martyn Welch]

Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
the PHYTEC phyCORE-i.MX6UL SOM (PCL063).

CPU:   Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 44C
Reset cause: POR
Board: PHYTEC phyCORE-i.MX6UL
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:    serial
Out:   serial
Err:   serial
Net:   FEC0

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART (1 & 5)
 - USB (host & otg)

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>

---

Changes in v4:
- Added PXE boot option
- Switched i2c to DM support

Changes in v3:
- Correct spelling of Phytec
- Remove unneeded license information
- Correct image name in documentation
- Correct whitespacing
- Enable SPL to boot from MMC
- Simplify defconfig, remove non-SPL build

Changes in v2:
- Switch to driver model

 arch/arm/dts/Makefile                 |   3 +-
 arch/arm/dts/imx6ul-pcl063.dtsi       | 173 +++++++++++++++++++++
 arch/arm/dts/imx6ul-phycore-segin.dts |  76 ++++++++++
 arch/arm/mach-imx/mx6/Kconfig         |  13 ++
 board/phytec/pcl063/Kconfig           |  12 ++
 board/phytec/pcl063/MAINTAINERS       |   8 +
 board/phytec/pcl063/Makefile          |   7 +
 board/phytec/pcl063/README            |  26 ++++
 board/phytec/pcl063/pcl063.c          | 206 ++++++++++++++++++++++++++
 board/phytec/pcl063/spl.c             | 160 ++++++++++++++++++++
 configs/phycore_pcl063_defconfig      |  62 ++++++++
 include/configs/pcl063.h              |  94 ++++++++++++
 12 files changed, 839 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx6ul-pcl063.dtsi
 create mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts
 create mode 100644 board/phytec/pcl063/Kconfig
 create mode 100644 board/phytec/pcl063/MAINTAINERS
 create mode 100644 board/phytec/pcl063/Makefile
 create mode 100644 board/phytec/pcl063/README
 create mode 100644 board/phytec/pcl063/pcl063.c
 create mode 100644 board/phytec/pcl063/spl.c
 create mode 100644 configs/phycore_pcl063_defconfig
 create mode 100644 include/configs/pcl063.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 949ee472fc..68411623e5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -453,7 +453,8 @@ dtb-$(CONFIG_MX6UL) += \
 	imx6ul-isiot-nand.dtb \
 	imx6ul-opos6uldev.dtb \
 	imx6ul-14x14-evk.dtb \
-	imx6ul-9x9-evk.dtb
+	imx6ul-9x9-evk.dtb \
+	imx6ul-phycore-segin.dtb
 
 dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
 
diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/imx6ul-pcl063.dtsi
new file mode 100644
index 0000000000..24a6a47983
--- /dev/null
+++ b/arch/arm/dts/imx6ul-pcl063.dtsi
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on dts[i] from Phytec barebox port:
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+
+#include "imx6ul.dtsi"
+
+/ {
+	model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
+	compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
+
+	memory {
+		reg = <0x80000000 0x20000000>;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy at 1 {
+			reg = <1>;
+			micrel,led-mode = <1>;
+		};
+	};
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	nand-on-flash-bbt;
+	fsl,no-blockmark-swap;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition at 0 {
+		label = "uboot";
+		reg = <0x0 0x400000>;
+	};
+
+	partition at 400000 {
+		label = "uboot-env";
+		reg = <0x400000 0x100000>;
+	};
+
+	partition at 500000 {
+		label = "root";
+		reg = <0x500000 0x0>;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	eeprom at 52 {
+		compatible = "cat,24c32";
+		reg = <0x52>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+	bus-width = <0x4>;
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
+			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0X1b0b0
+			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+		>;
+	};
+
+	pinctrl_gpmi_nand: gpminandgrp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x0b0b1
+			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x0b0b1
+			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0x0b0b1
+			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x0b000
+			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x0b0b1
+			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x0b0b1
+			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x0b0b1
+			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x0b0b1
+			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x0b0b1
+			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x0b0b1
+			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x0b0b1
+			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x0b0b1
+			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x0b0b1
+			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x0b0b1
+			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x0b0b1
+		>;
+	};
+
+	pinctrl_i2c1: i2cgrp {
+		fsl,pins = <
+			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL       0x4001b8b0
+			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA       0x4001b8b0
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1grp_gpio {
+		fsl,pins = <
+			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
+			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
+			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
+			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
+
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts b/arch/arm/dts/imx6ul-phycore-segin.dts
new file mode 100644
index 0000000000..a46012e2b4
--- /dev/null
+++ b/arch/arm/dts/imx6ul-phycore-segin.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on dts[i] from Phytec barebox port:
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6ul-pcl063.dtsi"
+
+/ {
+	model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
+	compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063",
+		     "fsl,imx6ul";
+};
+
+&i2c1 {
+	i2c_rtc: rtc at 68 {
+		compatible = "microcrystal,rv4162";
+		reg = <0x68>;
+		status = "okay";
+	};
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&usbotg1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1_id>;
+	dr_mode = "otg";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <
+			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
+			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0b1
+			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
+			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
+		>;
+	};
+
+	pinctrl_usb_otg1_id: usbotg1idgrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
+		>;
+	};
+
+};
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 06c25bae36..e253f495c5 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -428,6 +428,18 @@ config TARGET_PFLA02
 	select MX6QDL
 	select SUPPORT_SPL
 
+config TARGET_PCL063
+	bool "PHYTEC PCL063 (phyCORE-i.MX6UL)"
+	select MX6UL
+	select DM
+	select DM_ETH
+	select DM_GPIO
+	select DM_I2C
+	select DM_MMC
+	select DM_SERIAL
+	select DM_THERMAL
+	select SUPPORT_SPL
+
 config TARGET_SECOMX6
 	bool "secomx6 boards"
 
@@ -550,6 +562,7 @@ source "board/freescale/mx6ullevk/Kconfig"
 source "board/grinn/liteboard/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/phytec/pfla02/Kconfig"
+source "board/phytec/pcl063/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/samtec/vining_2000/Kconfig"
diff --git a/board/phytec/pcl063/Kconfig b/board/phytec/pcl063/Kconfig
new file mode 100644
index 0000000000..977db70f64
--- /dev/null
+++ b/board/phytec/pcl063/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PCL063
+
+config SYS_BOARD
+	default "pcl063"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "pcl063"
+
+endif
diff --git a/board/phytec/pcl063/MAINTAINERS b/board/phytec/pcl063/MAINTAINERS
new file mode 100644
index 0000000000..c65a951f3d
--- /dev/null
+++ b/board/phytec/pcl063/MAINTAINERS
@@ -0,0 +1,8 @@
+PCL063 BOARD
+M:	Martyn Welch <martyn.welch@collabora.com>
+S:	Maintained
+F:	arch/arm/dts/imx6ul-pcl063.dtsi
+F:	arch/arm/dts/imx6ul-phycore-segin.dts
+F:	board/phytec/pcl063/
+F:	configs/phycore_pcl063_defconfig
+F:	include/configs/pcl063.h
diff --git a/board/phytec/pcl063/Makefile b/board/phytec/pcl063/Makefile
new file mode 100644
index 0000000000..53c73c9b08
--- /dev/null
+++ b/board/phytec/pcl063/Makefile
@@ -0,0 +1,7 @@
+# Copyright (C) 2018 Collabora Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := pcl063.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/phytec/pcl063/README b/board/phytec/pcl063/README
new file mode 100644
index 0000000000..be83bdb0d8
--- /dev/null
+++ b/board/phytec/pcl063/README
@@ -0,0 +1,26 @@
+How to use U-Boot on PHYTEC phyBOARD-i.MX6UL-Segin
+--------------------------------------------------
+
+- Configure and build U-Boot for phyCORE-i.MX6UL:
+
+    $ make mrproper
+    $ make phycore_pcl063_defconfig
+    $ make
+
+  This will generate SPL and u-boot-dtb.img images.
+
+- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card:
+
+    $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+    $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+  JP1:   Open: Boot from NAND
+       Closed: Boot from SD/MMC1
+
+- Connect the Serial cable to UART0 and the PC for the console.
+
+- Insert the micro SD card in the board and power it up.
+
+- U-Boot messages should come up.
diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c
new file mode 100644
index 0000000000..38b233d1b0
--- /dev/null
+++ b/board/phytec/pcl063/pcl063.c
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on board/ccv/xpress/xpress.c:
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <linux/bitops.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE         | PAD_CTL_PUE       | \
+			PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | \
+			PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart5_pads[] = {
+	MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+}
+
+#ifdef CONFIG_NAND_MXS
+
+#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
+
+#define NANDREADYPC MUX_PAD_CTRL(NAND_PAD_READY0_CTRL)
+
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B		| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B		| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B	| NANDREADYPC,
+};
+
+static void setup_gpmi_nand(void)
+{
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+	setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+			  (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+}
+
+#endif /* CONFIG_NAND_MXS */
+
+#ifdef CONFIG_FEC_MXC
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE       | \
+			   PAD_CTL_SPEED_HIGH  | PAD_CTL_DSE_48ohm | \
+			   PAD_CTL_SRE_FAST)
+
+#define MDIO_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE      | \
+			   PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | \
+			   PAD_CTL_ODE)
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_pads[] = {
+	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+	imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	/*
+	 * Use 50M anatop loopback REF_CLK1 for ENET1,
+	 * clear gpr1[13], set gpr1[17].
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	/*
+	 * Use 50M anatop loopback REF_CLK2 for ENET2,
+	 * clear gpr1[14], set gpr1[18].
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/*
+	 * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
+	 * 50 MHz RMII clock mode.
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif /* CONFIG_FEC_MXC */
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_iomux_fec();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: PHYTEC phyCORE-i.MX6UL\n");
+
+	return 0;
+}
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
new file mode 100644
index 0000000000..b93cd493f2
--- /dev/null
+++ b/board/phytec/pcl063/spl.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on board/ccv/xpress/spl.c:
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/crm_regs.h>
+#include <fsl_esdhc.h>
+
+/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x41480148,
+	.p0_mprddlctl = 0x40403E42,
+	.p0_mpwrdlctl = 0x40405852,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,		/* Bus size = 16bit */
+	.cs_density = 18,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 1,
+	.rtt_nom = 1,
+	.walat = 1,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.pd_fast_exit = 1,
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 933,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 1,
+	.trcd = 1391,
+	.trcmin = 4791,
+	.trasmin = 3400,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE         | PAD_CTL_PUE       | \
+			PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
+			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | \
+			PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+	{
+		.esdhc_base = USDHC1_BASE_ADDR,
+		.max_bus_width = 4,
+	},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+#endif /* CONFIG_FSL_ESDHC */
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* Setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* Setup iomux and fec */
+	board_early_init_f();
+
+	/* Setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
new file mode 100644
index 0000000000..02c659de23
--- /dev/null
+++ b/configs/phycore_pcl063_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_PCL063=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_BOOTDELAY=3
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_CACHE=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_DEFAULT="gpmi-nand:4m(uboot),1m(env),-(root)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin"
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Phytec"
+CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
new file mode 100644
index 0000000000..4ceab519cb
--- /dev/null
+++ b/include/configs/pcl063.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on include/configs/xpress.h:
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ */
+#ifndef __PCL063_H
+#define __PCL063_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/*
+ * There is a bug in some i.MX6UL processors that results in the initial
+ * portion of OCRAM being unavailable when booting from (at least) an SD
+ * card.
+ *
+ * Tweak the SPL text base address to avoid this.
+ */
+#undef CONFIG_SPL_TEXT_BASE
+#define CONFIG_SPL_TEXT_BASE            0x00909000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+/* Console configs */
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			SZ_256M
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_SIZE			(16 << 10)
+#define CONFIG_ENV_OFFSET		(512 << 10)
+
+/* NAND */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc0,115200n8\0" \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"pxefile_addr_r=0x87100000\0" \
+	"ramdisk_addr_r=0x82100000\0" \
+	"scriptaddr=0x87000000\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(UBIFS, ubifs, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#endif /* __PCL063_H */
-- 
2.19.2

[U-Boot] [PATCH 1/3] mx7: Do not call lcdif_power_down() in the SPL case

[Otavio Salvador]

From: Fabio Estevam <festevam@gmail.com>

Like it was done on imx6 in commit 9236269de57d ("imx: mx6: Fix
implementantion reset_misc")

Do not call lcdif_power_down() in the SPL case to fix the following
build error:

  LD      spl/u-boot-spl
  MKIMAGE u-boot.img
arch/arm/mach-imx/built-in.o: In function `reset_misc':
/home/fabio/ossystems/u-boot/arch/arm/mach-imx/mx7/soc.c:372: undefined reference to `lcdif_power_down'
scripts/Makefile.spl:375: recipe for target 'spl/u-boot-spl' failed

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---

 arch/arm/mach-imx/mx7/soc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 3f74f8a3ed..7cfdff0981 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -368,8 +368,10 @@ void s_init(void)
 
 void reset_misc(void)
 {
+#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_VIDEO_MXS
 	lcdif_power_down();
 #endif
+#endif
 }
 
-- 
2.20.0

[U-Boot] [PATCH 2/3] pico-imx7d: Add LCD support

[Otavio Salvador]

From: Fabio Estevam <festevam@gmail.com>

Add support for the VXT VL050-8048NT-C01 panel connected through
the 24 bit parallel LCDIF interface.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---

 board/technexion/pico-imx7d/pico-imx7d.c | 55 ++++++++++++++++++++++++
 configs/pico-hobbit-imx7d_defconfig      |  1 +
 configs/pico-imx7d_defconfig             |  1 +
 configs/pico-pi-imx7d_defconfig          |  1 +
 include/configs/pico-imx7d.h             | 12 ++++++
 5 files changed, 70 insertions(+)

diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c
index 53e14693a5..767d13dfe5 100644
--- a/board/technexion/pico-imx7d/pico-imx7d.c
+++ b/board/technexion/pico-imx7d/pico-imx7d.c
@@ -39,8 +39,16 @@ DECLARE_GLOBAL_DATA_PTR;
 #define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
 	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
 
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
+			 PAD_CTL_DSE_3P3V_49OHM)
+
+#define LCD_SYNC_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
+			      PAD_CTL_DSE_3P3V_196OHM)
+
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
 /* I2C4 for PMIC */
 static struct i2c_pads_info i2c_pad_info4 = {
 	.scl = {
@@ -246,11 +254,58 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
+	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
+	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
+	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_GPIO1_IO06__GPIO1_IO6	| MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_lcd(void)
+{
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+	/* Set Brightness to high */
+	gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
+	/* Set LCD enable to high */
+	gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
+}
+#endif
+
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_VIDEO_MXS
+	setup_lcd();
+#endif
 #ifdef CONFIG_FEC_MXC
 	setup_fec();
 #endif
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index b02cae5237..0095050d43 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -57,4 +57,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index f355f07be7..3c715f743b 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -57,4 +57,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index 3a182dcb81..0097c816a4 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -57,4 +57,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index 333c0b49c1..97503a9efb 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h
@@ -64,10 +64,12 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
+	"splashpos=m,m\0" \
 	"console=ttymxc4\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \
 	BOOTMENU_ENV \
 	"fdt_addr=0x83000000\0" \
 	"fdt_addr_r=0x83000000\0" \
@@ -131,6 +133,16 @@
 #define CONFIG_POWER_PFUZE3000
 #define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
 
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
 /* FLASH and environment organization */
 #define CONFIG_ENV_SIZE			SZ_8K
 
-- 
2.20.0

[U-Boot] [PATCH 3/3] logos: Add the TechNexion's logo

[Otavio Salvador]

From: Fabio Estevam <festevam@gmail.com>

Add the TechNexion's logo from their internal U-Boot tree.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---

 tools/logos/technexion.bmp | Bin 0 -> 22390 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 tools/logos/technexion.bmp

diff --git a/tools/logos/technexion.bmp b/tools/logos/technexion.bmp
new file mode 100644
index 0000000000000000000000000000000000000000..bccde2de5922cb5d015ce302b74937b2812404ee
GIT binary patch
literal 22390
zcmeHOO=x4+6+TbDw(PMaTejrbV_UL4mL*HFq)Rt}HZ+U0gsf)KMV8rSIdqdnD9kd;
zKwGj%7lG1d5lSFX8c5p|l0ufDr4Z6AvI~Sl7D+du_nx2cz9-A6-6;))_h9tiyXV|<
z&OP`1-sk!LGe7<j@%5b&QQtrH6QUpZdqOKb{=|KvcQ at pp9}ED#sw*qBwzfuFTU)fZ
zw?`)@Cv<k!r{Qo&lgTB`=W}}e@yF?V-+h9feDX<p>Zu>n(@#H5_wV1QXP<qRo_p>&
zdj9$6>A`~s^uh}-(2FnrgdRS8NH4wg621KL%k<Nq{hVHT<rRAM)nCwSuf0aU{ME1N
z_19mgH{SRSz4_*w^wwLyrQf~%Hof!C at 9CXC{E^;$_fPcR`+uhQ-+P}v_}~Nj at WT)3
zFMs_Tee}^s^zp}^(BD7#gg*WBQ~K<)&*<~d|3P1T@dbVP<yZ9OSO281zy4YlmH*}%
z$Tg5_AlE>yfm{Q*267GL8pt(}YarJ^u7O+wxdw6#<Qm8|kZa)E(?GIPZ#EhmRXv4W
z6r{A)Xf_+Q!s7UU>%CZOG#d4qKP!IJs}LxyKLVlh-f at qwlg=WQq;YTV^t#wxT@<x;
zFg56SuLfxIROp@F;i2Nb&_6z?g!f`w*>$%tgJ at Id9Jf<4lsaRhKRw+n3i`GX?{&{~
zfaq>l$BtV>rMvoaH?_4%^IR!i9 at SIhb(Q6`&cq8HeLuXiRuAu)Fm3 at _ItGLvF8ncn
zyh?{z=s?s$RJHM*AcG1|Pqqvkz9#5Z>e}F?NF2tSmo~`v`M#*|%toiW;3VR$6BTw9
zK8ey+O-l@##tkYOEtO@@-ZxFM)O}}W&}K^2e&?eC4WSnuY*9 at f<v?~g$}LQ`%<9@a
zd(DWAqY180Y|vp5O`8VLWs?bF(PN>%8WDs14a0v-z(kd(NP$h(3^X)kS$V at S_hGDt
zNwf;<?q#4&qmjCgu(r+As6C#uK_(r07uzVA5-!*vDt!gdb|6EFl`5OcFhir}@2u$p
z7I(%3HnGp$u-cj}=TylTPEr))ac-<z25K;J(e_}x;93kdpmV9<Kn3Gxr1(BoYcAX3
zvrtxJ&BhKzQqUJQwheqFVDBr?taB6H37Cap^L;OvWEqk%gMDD|VvBe6edN6`Tz3FZ
zJ?smtY(uJ4_<wYNK@7hg1nV>uVaB=9DI{|f;l5!EviEU_)g`muOX0C?INNO9(7?HT
z;q;CHO?ph(*#flbru{xF#_b0ZtJtKDe>3~EZEhJmHJW9H>D(^MmSABb>ZbW{Cq@{7
z_}`iV-I2H{L!vJP?X5tXan-*jaT#uM*aZRC_pV!bOeLL4XfN9`hs=D{v@)}32?GrC
z_SpGLr?%SD at E*OK*SBFiG2f&FZWws`Ys0j7z^h4&khj%?<0vTy!eqyw>UcJHoOUfH
z>wgUBTuM*SgqrAqr#S8(wzq<w3P^Ty7Q6xeVH4}he7+|fuxaJ+o*=8po>CIE;3rNP
zsbZ at ii~W{7gUdm0Z(DK=g8Xcw3hG-TeaZ6AIlFMlG~v3Qc at fMVZ{n&!1JGYE2Lxgn
z=ilhzmfQWX8HF=vtjc!ri~<~aBy<W;lviWbwtFBzs9cg6DuXkwsHg~HEHo<ys~@NX
z6w0YRB-%C`9X)2uoGlH}j_q~DG~t92(tAIcOv$u75m6!APKKQT*Ffq(2Es2EXL^bt
zZ%^13n_;EM^vG{ou)T1NB>`9D%{kHA`h~vF#Mn!Sk38N95>^I^V|q$+56`>VNgjK^
zhUh^kyo8bxa#}{vkqvBmMo1x3Nl=hwyd*%8&2%n`)3iZf<X*XAwTLREKHP8Bt3urz
zY2KEZaBMco1opGd;C169_i;cfSu(${)i26mdx6Oay(M#=K8FZHP|K&pOn(*_Z5UX?
zi}|}-#y9fRT<QtHb1(Y~*TCB|*4AB=KfJG-FB}Ur>j{L{UNHSwZ>h*34Wg``4;Q%i
z`?`X~JSN5&7$SHESAbez1MrmKm(jt)Orn<QZJBvs)$Xof``?01xO(^QQ$c*dgwzB2
zkfGFT(7E&nb+fNo@XITO8s~E}$*bIFwgNL7K}nVO=m1*5g`rQg5DO9Pi3scyiOmT6
zW`3z<QFOd1h7)AwtD+WT?44K<go)w7N+w-XY-QLl3s_<3L?D^*VF@>EBWyI@&y-bS
zF^oZ0$a`RUq{t`1UJ*dh5`le?-N5rui}}muW{PeBQH*VKOB#_t6cA6|#BIN48iI_H
z+)*c}*CTmKiv~YG^dZ71fjUdLv~LlVVTdc?%4nE_wv5N at 9?Th7l12OoI0o6#TOJ4F
zBSJ+5weqn1SjFQU;xeJ8j|;FT at 0}=4#g$UD!ehm{`k at 3oIQA(cLX9(D8C<nnb}Yzi
zOmSBaNrg}bY55cw>{v1k+kzTq8p3+Gu(F|lK|?>0#J-T6c>;c7FtY5K3Z=7Fslpdp
z8SfeJ>#0 at MAQm1_H%Rk<J(a_d*e>{NjP>Ioh);LS0ZwaWVQ<bnwE%^DATwhi#|c3<
zm>wED?Ke{_10y5rq$-Ya-^?~3=@nD;W$cvEPMFEW<@sq1TNVd_Kxe(ZVWE-`O63fr
zc%j%@G9k9^ConaK!bU;^s$cQdSmv9}$Ec^or34D1n2wnedLZphi4glj{Hj}Wp0YtD
zh+fMK0IRl=#}kM(n9hhKd^j#3$Y=nR_G8p-H~dDdAjWbUFIvswWKWys7_$P@;m|+J
zA=J7pwx`-haM0Qo=50IXq^$L#!_s)^sFAb-OfVrBMH!CI**O}6#0Za(y5O?TjK>3O
zCh0(oEGC$cwvgSORCq-zTc*JPtjTh2x>>H+S%-7%Q&hl?!bRLPuI`*AL-3b#2DFXt
zh`|vZ%SP)06>?{f#@wB;%3GMgSqm}3&06J>orn5<QrKjEi|~YtkSz7uGJ<jfhbSZc
za-=w at 7pa6joQ6PwHp)ooeJsWS<30g=kKpK22@SBxc1T6>s739`{KXAnX>$`EFfK&m
zX~$)IwVKKh!S4u%DG)^-5cdO;Ua=8Dlnf9!#ca1$X}}0(GRu<M0)0Mei>IVnsKyAS
z<_O)OqOHy!mxL=E638`dR#&ktTIs-M+(E3OCz{iMEcv!>?XD5jJG03gf29!gScq}(
z6MJD~g#d$@rRF==(`jgiGSD#>A~1#w%<1tyYT^hjq`GSj4am_E%RgO8VuSs<&DiF+
zp`1aW15n#TZ=9i|>xeNT1C_WA4ar0Kp5gR`lfswMKo<!2vB}{sijK=j!<-dASJZgw
zwTpnuy|9-chRqZatrxBNap5}=jwqbAf3SUB#|CUOMM=UgwG?@f6-ti~lz`si$sUK{
z2uyjiaY!YCCEA#=)5k)zmr>?Os}h7hBN|+-VvB(c#mr>Jok^WgwUjBRixp%oZmwei
zXE`vQsvAc%v*?9uNF4!ZDxoy0f}c<sIL-40Us?375ywUauf=Uu{!-QwA=ngA$$5+;
zofmV0P78r0S_PcH(2DvHOcf7Zznd^g94EWGVJm7%)@kSDhZcAI6ze!w<gM7!_>p@|
zckw6kv3kWYl19cJ_d%W!3Y(c2IZ|6r<$ya>MpnB3(FN^~*b1Arx_)F*>X?-UAScs6
zBy#Nu%?*r%uW#ru=El))!)}_Ad`@Jj>HN4vI5l>cQG`gspVPqRmc*}et2gpIrWf5U
z at v8JpTG{RmJ#;?lcVZh&$PD2dNws}Gb+bXLw``e8<i5*Nt=U4f*%CI%olbu;5A^p?
zau@2jtZiGhkw%bl&EC?>E!^4ddk2_}yY?NPITX{lm3BXfDrbmTXT8&wYX=VQdOJGS
zNq>yTl$$=7B4(Wb7H7q@&UoUjIJjDL{>9n<^LMoFwyMm1kjZ_w6b_9|%E%%Kw0z8P
zW~s;6chhDNXMJl=vAZz|Gxw!SyrHn@)AjpPc3S!qps&c(o$Ka!BRO8o&biH7Qftb^
zUU-|C%W-3OlTnbqXlu26>c1N`g43ml$VdT=PiQ?_+%`KrSvvP7gH2_h>g;ba?K+(6
zx*OqguI0{kv%hg12PM{ZWw0{^jTIAwhGQYEW~ScgrDg?1s<Xe*#N|lw1Vr_py)CV^
zmQ%ViiuQEr*)Tq-c!qi);VEF-;?NbkHyc2PA6Y`Y*}UtpmUbpkmL5G_H~AaK(Zoq5
zxQGiiIv0&6{!Ldro?M)G!}pdhBGcL5aPAVc>rOy~OZflu|LIk*EtoIeQT(Nn4^NQ=
zoHbPkM(Ayx>gIST?r$^u3hs3$Ai5im5}+)UI{g!yEN}d!l1o>W*tYXWsYwDSe9Xvp
z_E{lr at pjn1cjcR_4cr@`0=@-BLoE-K&hi~?4w&)1zW(VYPpfuS9Q=8dQM>iMbuJ4#
zMwYlWiF`t?fm{Q*267GL8pt(}YarJ^u7O+wxdw6#<Qm8|kZT~<K(2vY1GxtNuQc#4
D8(^5`

literal 0
HcmV?d00001

-- 
2.20.0

[U-Boot] [PATCH 1/3] mx7: Do not call lcdif_power_down() in the SPL case

[Peng Fan]

> -----Original Message-----
> From: Otavio Salvador [mailto:otavio at ossystems.com.br]
> Sent: 2018年12月12日 2:41
> To: U-Boot Mailing List <u-boot@lists.denx.de>
> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
> <fabio.estevam@nxp.com>; Marek Vasut <marex@denx.de>; Richard Hu
> <richard.hu@technexion.com>; John Weber <john.weber@technexion.com>;
> Fabio Estevam <festevam@gmail.com>; Otavio Salvador
> <otavio@ossystems.com.br>; Ye Li <ye.li@nxp.com>; Peng Fan
> <peng.fan@nxp.com>; Bryan O'Donoghue <bryan.odonoghue@linaro.org>;
> Albert Aribaud <albert.u.boot@aribaud.net>; Rui Miguel Silva
> <rui.silva@linaro.org>; Anson Huang <anson.huang@nxp.com>; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: [PATCH 1/3] mx7: Do not call lcdif_power_down() in the SPL case
> 
> From: Fabio Estevam <festevam@gmail.com>
> 
> Like it was done on imx6 in commit 9236269de57d ("imx: mx6: Fix
> implementantion reset_misc")
> 
> Do not call lcdif_power_down() in the SPL case to fix the following build error:
> 
>   LD      spl/u-boot-spl
>   MKIMAGE u-boot.img
> arch/arm/mach-imx/built-in.o: In function `reset_misc':
> /home/fabio/ossystems/u-boot/arch/arm/mach-imx/mx7/soc.c:372:
> undefined reference to `lcdif_power_down'
> scripts/Makefile.spl:375: recipe for target 'spl/u-boot-spl' failed
> 
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> ---
> 
>  arch/arm/mach-imx/mx7/soc.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
> index 3f74f8a3ed..7cfdff0981 100644
> --- a/arch/arm/mach-imx/mx7/soc.c
> +++ b/arch/arm/mach-imx/mx7/soc.c
> @@ -368,8 +368,10 @@ void s_init(void)
> 
>  void reset_misc(void)
>  {
> +#ifndef CONFIG_SPL_BUILD
>  #ifdef CONFIG_VIDEO_MXS
>  	lcdif_power_down();
>  #endif
> +#endif
>  }
> 

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> --
> 2.20.0

[U-Boot] [PATCH V2 00/10] i.MX8QXP: MEK: support SPL

[Peng Fan]

This is to support SPL for i.MX8QXP MEK board and default support SPL.
In this patchset, use SPL FIT, but actually we could not use SPL FIT
for secure boot, in NXP vendor tree, there is another format called
container, NXP use SPL + container for secure boot. The container
support is on my TODO list. But to make SPL work in upstream, use
SPL FIT here.

V2:
 Correct patch 9/10 10/10, SPL_TEXT_BASE is patch 9/10 is wrong, however 10/10
 corrected, so clean that.

Peng Fan (10):
  imx8qxp: add SUPPORT_SPL option
  imx8: scu: use dedicated MU for SPL
  arm: imx: build mach-imx for i.MX8
  gpio: introduce CONFIG_SPL_DM_PCA953X
  spl: imx8: add spl boot device
  dts: imx8qxp-mek: introduce u-boot dtsi
  imx: mkimage_fit_atf: introduce BL33_BASE_ADDR
  imx: build flash.bin for i.MX8
  imx8qxp: mek: default enable SPL
  imx8qxp: mek: update README

 Makefile                                 |   2 +-
 arch/arm/Makefile                        |   2 +-
 arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 112 +++++++++++++++++++++++++++++++
 arch/arm/dts/fsl-imx8qxp-mek.dts         |   1 +
 arch/arm/mach-imx/Makefile               |  15 ++++-
 arch/arm/mach-imx/imx8/Kconfig           |   8 +++
 arch/arm/mach-imx/mkimage_fit_atf.sh     |   3 +-
 arch/arm/mach-imx/spl.c                  |  14 +++-
 board/freescale/imx8qxp_mek/Makefile     |   1 +
 board/freescale/imx8qxp_mek/README       |   8 ++-
 board/freescale/imx8qxp_mek/imximage.cfg |   4 +-
 board/freescale/imx8qxp_mek/spl.c        |  75 +++++++++++++++++++++
 configs/imx8qxp_mek_defconfig            |  24 +++++++
 drivers/gpio/Kconfig                     |  23 +++++++
 drivers/gpio/Makefile                    |   2 +-
 drivers/misc/imx8/scu.c                  |   4 ++
 include/configs/imx8qxp_mek.h            |  26 +++++++
 17 files changed, 311 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
 create mode 100644 board/freescale/imx8qxp_mek/spl.c

-- 
2.14.1

[U-Boot] [PATCH V2 01/10] imx8qxp: add SUPPORT_SPL option

[Peng Fan]

Enable SUPPORT_SPL option for i.MX8QXP, then we could enable SPL.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 0d3a87cd74..9671107cb6 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -5,6 +5,7 @@ config IMX8
 
 config IMX8QXP
 	select IMX8
+	select SUPPORT_SPL
 	bool
 
 config SYS_SOC
-- 
2.14.1

[U-Boot] [PATCH V2 02/10] imx8: scu: use dedicated MU for SPL

[Peng Fan]

SPL runs in EL3 mode, except MU0_A, others are not powered on,
and could not be used. However normal U-Boot use MU1_A, so we
could not reuse the one in dts. And we could not replace the one
in dts with MU0_A, because MU0_A is reserved in secure world.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8/Kconfig | 7 +++++++
 drivers/misc/imx8/scu.c        | 4 ++++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 9671107cb6..f76a139684 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -3,6 +3,13 @@ if ARCH_IMX8
 config IMX8
 	bool
 
+config MU_BASE_SPL
+	hex "MU base address used in SPL"
+	default 0x5d1b0000
+	help
+	  SPL runs in EL3 mode, it use MU0_A to communicate with SCU.
+	  So we could not reuse the one in dts which is for normal U-Boot.
+
 config IMX8QXP
 	select IMX8
 	select SUPPORT_SPL
diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c
index 15101b3e5f..1b9c49c99c 100644
--- a/drivers/misc/imx8/scu.c
+++ b/drivers/misc/imx8/scu.c
@@ -191,7 +191,11 @@ static int imx8_scu_probe(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
+#ifdef CONFIG_SPL_BUILD
+	plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL;
+#else
 	plat->base = (struct mu_type *)addr;
+#endif
 
 	/* U-Boot not enable interrupts, so need to enable RX interrupts */
 	mu_hal_init(plat->base);
-- 
2.14.1

[U-Boot] [PATCH V2 03/10] arm: imx: build mach-imx for i.MX8

[Peng Fan]

To enable SPL for i.MX8, we could reuse code in arch/arm/mach-imx.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/Makefile          | 2 +-
 arch/arm/mach-imx/Makefile | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 87d9d4b9f7..0e2cfd4534 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -103,7 +103,7 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8))
 libs-y += arch/arm/mach-imx/
 endif
 else
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 04783fa04e..5424848ad3 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -24,7 +24,7 @@ obj-y	+= cpu.o speed.o
 obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8))
 obj-y	+= misc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
-- 
2.14.1

[U-Boot] [PATCH V2 04/10] gpio: introduce CONFIG_SPL_DM_PCA953X

[Peng Fan]

Introduce CONFIG_SPL_DM_PCA953X for SPL usage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/gpio/Kconfig  | 23 +++++++++++++++++++++++
 drivers/gpio/Makefile |  2 +-
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 35344e57c6..b1c9404aaf 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -292,6 +292,29 @@ config DM_PCA953X
 	  Now, max 24 bits chips and PCA953X compatible chips are
 	  supported
 
+config SPL_DM_PCA953X
+	bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports in SPL"
+	depends on DM_GPIO
+	help
+	  Say yes here to provide access to several register-oriented
+	  SMBus I/O expanders, made mostly by NXP or TI.  Compatible
+	  models include:
+
+	  4 bits:	pca9536, pca9537
+
+	  8 bits:	max7310, max7315, pca6107, pca9534, pca9538, pca9554,
+			pca9556, pca9557, pca9574, tca6408, xra1202
+
+	  16 bits:	max7312, max7313, pca9535, pca9539, pca9555, pca9575,
+			tca6416
+
+	  24 bits:	tca6424
+
+	  40 bits:	pca9505, pca9698
+
+	  Now, max 24 bits chips and PCA953X compatible chips are
+	  supported
+
 config MPC8XXX_GPIO
 	bool "Freescale MPC8XXX GPIO driver"
 	depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7ed9a4ec42..dac238ae06 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_AXP_GPIO)		+= axp_gpio.o
 endif
 obj-$(CONFIG_DM_GPIO)		+= gpio-uclass.o
 
-obj-$(CONFIG_DM_PCA953X)	+= pca953x_gpio.o
+obj-$(CONFIG_$(SPL_)DM_PCA953X)	+= pca953x_gpio.o
 obj-$(CONFIG_DM_74X164)		+= 74x164_gpio.o
 
 obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
-- 
2.14.1

[U-Boot] [PATCH V2 05/10] spl: imx8: add spl boot device

[Peng Fan]

Add spl_boot_device for i.MX8, also add BOOT_DEVICE_MMC2_2 for
spl_boot_mode.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/spl.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 58a92278df..3ee5061b08 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -96,7 +96,7 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_NONE;
 }
 
-#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
+#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
 /* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
 u32 spl_boot_device(void)
 {
@@ -134,6 +134,15 @@ u32 spl_boot_device(void)
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		return BOOT_DEVICE_MMC1;
+#elif defined(CONFIG_IMX8)
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD2_BOOT:
+		return BOOT_DEVICE_MMC2_2;
+	case SD3_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case FLEXSPI_BOOT:
+		return BOOT_DEVICE_SPI;
 #elif defined(CONFIG_IMX8M)
 	case SD1_BOOT:
 	case MMC1_BOOT:
@@ -152,7 +161,7 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_NONE;
 	}
 }
-#endif /* CONFIG_MX7 || CONFIG_IMX8M */
+#endif /* CONFIG_MX7 || CONFIG_IMX8M || CONFIG_IMX8 */
 
 #ifdef CONFIG_SPL_USB_GADGET_SUPPORT
 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
@@ -171,6 +180,7 @@ u32 spl_boot_mode(const u32 boot_device)
 	/* for MMC return either RAW or FAT mode */
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
 #if defined(CONFIG_SPL_FAT_SUPPORT)
 		return MMCSD_MODE_FS;
 #elif defined(CONFIG_SUPPORT_EMMC_BOOT)
-- 
2.14.1

[U-Boot] [PATCH V2 06/10] dts: imx8qxp-mek: introduce u-boot dtsi

[Peng Fan]

Introduce u-boot dtsi for i.MX8QXP MEK board.
we do not introduce a common dtsi for SoC, because different board
has different requirement on which needs to be enabled in SPL DM.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 112 +++++++++++++++++++++++++++++++
 arch/arm/dts/fsl-imx8qxp-mek.dts         |   1 +
 2 files changed, 113 insertions(+)
 create mode 100644 arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi

diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
new file mode 100644
index 0000000000..5d50eb028e
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-spl;
+};
+
+&gpio0 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&gpio6 {
+	u-boot,dm-spl;
+};
+
+&gpio7 {
+	u-boot,dm-spl;
+};
+
+&lpuart0 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
index adab494cdf..41f7ec1763 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek.dts
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "fsl-imx8qxp.dtsi"
+#include "fsl-imx8qxp-mek-u-boot.dtsi"
 
 / {
 	model = "Freescale i.MX8QXP MEK";
-- 
2.14.1

[U-Boot] [PATCH V2 07/10] imx: mkimage_fit_atf: introduce BL33_BASE_ADDR

[Peng Fan]

Introduce BL33_BASE_ADDR, then we could reuse this script for i.MX8QXP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/mkimage_fit_atf.sh | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh
index 77f7143263..38c9858e84 100755
--- a/arch/arm/mach-imx/mkimage_fit_atf.sh
+++ b/arch/arm/mach-imx/mkimage_fit_atf.sh
@@ -9,6 +9,7 @@
 [ -z "$BL31" ] && BL31="bl31.bin"
 [ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000"
 [ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000"
+[ -z "$BL33_LOAD_ADDR" ] && BL33_LOAD_ADDR="0x40200000"
 
 if [ ! -f $BL31 ]; then
 	echo "ERROR: BL31 file $BL31 NOT found" >&2
@@ -58,7 +59,7 @@ cat << __HEADER_EOF
 			type = "standalone";
 			arch = "arm64";
 			compression = "none";
-			load = <0x40200000>;
+			load = <$BL33_LOAD_ADDR>;
 		};
 		atf at 1 {
 			description = "ARM Trusted Firmware";
-- 
2.14.1

[U-Boot] [PATCH V2 08/10] imx: build flash.bin for i.MX8

[Peng Fan]

Build flash.bin for i.MX8 when SPL enabled.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 Makefile                   |  2 +-
 arch/arm/mach-imx/Makefile | 13 +++++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 74d4259eb6..e9a0d3ab3a 100644
--- a/Makefile
+++ b/Makefile
@@ -1200,7 +1200,7 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
 SPL: spl/u-boot-spl.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 
-ifeq ($(CONFIG_ARCH_IMX8M), y)
+ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
 flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5424848ad3..e84798b35c 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -105,6 +105,7 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%)
 ifeq ($(CONFIG_ARCH_IMX8), y)
 CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh
 IMAGE_TYPE := imx8image
+SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout ]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi)
 DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
 else ifeq ($(CONFIG_ARCH_IMX8M), y)
 IMAGE_TYPE := imx8mimage
@@ -153,6 +154,18 @@ ifeq ($(DEPFILE_EXISTS),0)
 endif
 endif
 
+ifeq ($(CONFIG_ARCH_IMX8), y)
+SPL:
+
+MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout -T $(IMAGE_TYPE) -e 0x100000
+flash.bin: MKIMAGEOUTPUT = flash.log
+
+flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
+ifeq ($(SPL_DEPFILE_EXISTS),0)
+	$(call if_changed,mkimage)
+endif
+endif
+
 else
 MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
 		   -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
-- 
2.14.1

[U-Boot] [PATCH V2 09/10] imx8qxp: mek: default enable SPL

[Peng Fan]

Enable SPL for i.MX8QXP MEK, and currently use SPL FIT.
The SPL enable SPL_DM to use MMC/PINCTRL/POWER DOMAIN/CLK.

Note: SPL FIT could not support secure boot chain, because i.MX8/8X
only support i.MX container format. This container format has
not been upstreamed, so we use FIT for now. When SPL container
supported, we could switch to that.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8qxp_mek/Makefile     |  1 +
 board/freescale/imx8qxp_mek/imximage.cfg |  4 +-
 board/freescale/imx8qxp_mek/spl.c        | 75 ++++++++++++++++++++++++++++++++
 configs/imx8qxp_mek_defconfig            | 24 ++++++++++
 include/configs/imx8qxp_mek.h            | 26 +++++++++++
 5 files changed, 127 insertions(+), 3 deletions(-)
 create mode 100644 board/freescale/imx8qxp_mek/spl.c

diff --git a/board/freescale/imx8qxp_mek/Makefile b/board/freescale/imx8qxp_mek/Makefile
index f9ee8aeff3..acaadcd84a 100644
--- a/board/freescale/imx8qxp_mek/Makefile
+++ b/board/freescale/imx8qxp_mek/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += imx8qxp_mek.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/freescale/imx8qxp_mek/imximage.cfg b/board/freescale/imx8qxp_mek/imximage.cfg
index bbffb1a88f..259a1646bf 100644
--- a/board/freescale/imx8qxp_mek/imximage.cfg
+++ b/board/freescale/imx8qxp_mek/imximage.cfg
@@ -19,6 +19,4 @@ CONTAINER
 /* Add scfw image with exec attribute */
 IMAGE SCU mx8qx-mek-scfw-tcm.bin
 /* Add ATF image with exec attribute */
-IMAGE A35 bl31.bin 0x80000000
-/* Add U-Boot image with load attribute */
-DATA A35 u-boot-dtb.bin 0x80020000
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c
new file mode 100644
index 0000000000..95ce9f37e8
--- /dev/null
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+	int offset;
+
+	uclass_find_first_device(UCLASS_MISC, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
+	while (offset != -FDT_ERR_NOTFOUND) {
+		lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
+			       NULL, true);
+		offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
+						       "nxp,imx8-pd");
+	}
+
+	uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index 58b4ca0861..a87dbd17ff 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -1,11 +1,28 @@
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
 CONFIG_NR_DRAM_BANKS=3
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg"
 CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMPORTENV is not set
 CONFIG_CMD_CLK=y
@@ -18,8 +35,11 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
 CONFIG_CLK_IMX8=y
 CONFIG_CPU=y
 CONFIG_DM_GPIO=y
@@ -41,12 +61,16 @@ CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_IMX8_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
 # CONFIG_EFI_LOADER is not set
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index d34d174cac..312e30dc6c 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -9,6 +9,32 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_TEXT_BASE				0x0
+#define CONFIG_SPL_MAX_SIZE				(124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0x250
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION		0
+
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x013E000
+#define CONFIG_SPL_BSS_START_ADDR	0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x00120000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x3000	/* 12 KB */
+#define CONFIG_SERIAL_LPUART_BASE	0x5a060000
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_MALLOC_F_ADDR		0x00120000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_OF_EMBED
+#endif
+
 #define CONFIG_REMAKE_ELF
 
 #define CONFIG_BOARD_EARLY_INIT_F
-- 
2.14.1

[U-Boot] [PATCH V2 10/10] imx8qxp: mek: update README

[Peng Fan]

Update README after we switch to use SPL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8qxp_mek/README | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/board/freescale/imx8qxp_mek/README b/board/freescale/imx8qxp_mek/README
index e91e193d11..f32290e3a2 100644
--- a/board/freescale/imx8qxp_mek/README
+++ b/board/freescale/imx8qxp_mek/README
@@ -39,16 +39,18 @@ $ cp imx-sc-firmware-0.7/mx8qx-mek-scfw-tcm.bin	.
 
 Build U-Boot
 ============
-
+$ export ATF_LOAD_ADDR=0x80000000
+$ export BL33_LOAD_ADDR=0x80020000
 $ make imx8qxp_mek_defconfig
-$ make
+$ make flash.bin
+$ dd if=u-boot.itb of=flash.bin bs=512 seek=528
 
 Flash the binary into the SD card
 =================================
 
 Burn the flash.bin binary to SD card offset 32KB:
 
-$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=1024 seek=32
+$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
 
 Boot
 ====
-- 
2.14.1

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Baruch Siach]

Use a single '=' to test string equality for compatibility with non-bash
shells. Otherwise, if /bin/sh is dash, build fails:

./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
WARNING './spl/u-boot-spl-ddr.bin' not found, resulting binary is not-functional

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
 tools/imx8m_image.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh
index 6346fb64d8c5..ec0881a12812 100755
--- a/tools/imx8m_image.sh
+++ b/tools/imx8m_image.sh
@@ -12,7 +12,7 @@ blobs=`awk '/^SIGNED_HDMI/ {print $2} /^LOADER/ {print $2} /^SECOND_LOADER/ {pri
 for f in $blobs; do
 	tmp=$srctree/$f
 
-	if [ $f == "spl/u-boot-spl-ddr.bin" ] || [ $f == "u-boot.itb" ]; then
+	if [ $f = "spl/u-boot-spl-ddr.bin" ] || [ $f = "u-boot.itb" ]; then
 		continue
 	fi
 
@@ -28,7 +28,7 @@ for f in $blobs; do
 	sed -in "s;$f;$tmp;" $file
 done
 
-if [ $post_process == 1 ]; then
+if [ $post_process = 1 ]; then
 	if [ -f $srctree/lpddr4_pmu_train_1d_imem.bin ]; then
 		objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_imem_pad.bin
 		objcopy -I binary -O binary --pad-to 0x4000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_dmem_pad.bin
-- 
2.19.2

[U-Boot] [PATCH 2/2] imx8mq_evk/README: remove ARCH environment variable

[Baruch Siach]

There is no need to set the ARCH variable when building U-Boot. In fact,
the ARCH name in U-Boot is 'arm'.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
 board/freescale/imx8mq_evk/README | 1 -
 1 file changed, 1 deletion(-)

diff --git a/board/freescale/imx8mq_evk/README b/board/freescale/imx8mq_evk/README
index 07dbfb01fed8..1da6eaf24277 100644
--- a/board/freescale/imx8mq_evk/README
+++ b/board/freescale/imx8mq_evk/README
@@ -23,7 +23,6 @@ $ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srcte
 
 Build U-Boot
 ====================
-$ export ARCH=arm64
 $ export CROSS_COMPILE=aarch64-poky-linux-
 $ make imx8mq_evk_defconfig
 $ make flash.bin
-- 
2.19.2

[U-Boot] [PATCH v2 0/3] ddr: vybrid: Support for vf610 built-in DDR3 memory calibration

[Lukasz Majewski]

Hi Fabio, Stefano,

> This patch series provides code to perform read leveling - RDLVL,
> which is adjusting the DQS strobe in relation to the DQ signals so
> that the strobe edge is centered in the window of valid read data.
> 
> The code is based on Vybrid's Reference Manual's:
> "VFxxx Controller Reference Manual, Rev. 0, 10/2016", page 1600,
> 10.1.6.16.4.1 "Software Read Leveling in MC Evaluation Mode"
> 
> and uses clarification provided by following NXP's community thread:
> "Vybrid: About DDR leveling feature on DDRMC."
> https://community.nxp.com/thread/395323
> 
> It depends on a BITMAP rework patch:
> usb: composite: Move bitmap related operations
> to ./include/linux/bitmap.h http://patchwork.ozlabs.org/patch/1006448/
> 

The above patch has found its way to main line, so there is no
obstacles to pull this code.

Moreover, some Stefan's patches:
[U-Boot,v1,0/4] ddr: vybrid: various fixes

http://patchwork.ozlabs.org/cover/1007547/

Are also related to DDR_MC setup on Vybrid and fix/cleanup some issues.

> 
> Changes in v2:
> - CR93_SWLVL_EXIT -> CR94_SWLVL_EXIT (EXIT is in CR94)
> - Add more defines to imx-regs.h (moved from *-calibration.h)
>  - CR93_SWLVL_EXIT -> CR94_SWLVL_EXIT (EXIT is in CR94)
>  - Update Kconfig information regarding DDRMC_VF610_CALIBRATION
>  - Update ddrmc-vf610-calibration. comment
>  - Update code after extending imx-regs.h
>  - Remove not needed #ifdef
> 
> Lukasz Majewski (3):
>   ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ)
>   ddr: vybrid: Provide code to perform on-boot calibration
>   ddr: vybrid: Add calibration code to memory controler's (DDRMC)
> setup code
> 
>  arch/arm/include/asm/arch-vf610/imx-regs.h  |  14 +-
>  arch/arm/mach-imx/Kconfig                   |  12 +
>  arch/arm/mach-imx/Makefile                  |   1 +
>  arch/arm/mach-imx/ddrmc-vf610-calibration.c | 342
> ++++++++++++++++++++++++++++
> arch/arm/mach-imx/ddrmc-vf610-calibration.h |  45 ++++
> arch/arm/mach-imx/ddrmc-vf610.c             |   5 + 6 files changed,
> 418 insertions(+), 1 deletion(-) create mode 100644
> arch/arm/mach-imx/ddrmc-vf610-calibration.c create mode 100644
> arch/arm/mach-imx/ddrmc-vf610-calibration.h
> 




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190102/0f609e40/attachment.sig>

[U-Boot] [PATCH 0/3] Migrate i.MX53 based cx9020 to CONFIG_DM_MMC=y

[linux-kernel-dev at beckhoff.com]

From: Patrick Bruenn <p.bruenn@beckhoff.com>


This series is based on v2019.01-rc2. It enables compatible
"fsl,imx53-esdhc" for fsl_esdhc driver and copies esdhc1 and esdhc2
device tree nodes from Linux 4.20 into imx53.dtsi. The last patch
enables these nodes for imx53-cx9020.dts and adds CONFIG_DM_MMC=y
for mx53cx9020_defconfig.

I have no other imx53 platform available for testing, but I could add
esdhc3/4 and convert more imx53 boards, if wanted.


Patrick Bruenn (3):
  mmc: fsl_esdhc: add compatible for fsl,imx53-esdhc
  arm: imx: Add esdhc1/2 nodes to imx53.dtsi
  dm: arm: imx: migrate cx9020 to CONFIG_DM_MMC

 arch/arm/dts/imx53-cx9020.dts | 52 +++++++++++++++++++++++++++++++------------
 arch/arm/dts/imx53.dtsi       | 34 ++++++++++++++++++++++++++++
 configs/mx53cx9020_defconfig  |  1 +
 drivers/mmc/fsl_esdhc.c       |  1 +
 4 files changed, 74 insertions(+), 14 deletions(-)

-- 
2.11.0

[U-Boot] [PATCH 1/3] mmc: fsl_esdhc: add compatible for fsl, imx53-esdhc

[linux-kernel-dev at beckhoff.com]

From: Patrick Bruenn <p.bruenn@beckhoff.com>

Add compatible "fsl,imx53-esdhc" to keep mmc working on i.MX53 platforms
with CONFIG_DM_MMC=y

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
---

 drivers/mmc/fsl_esdhc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 3cdfa7f5a68..ff912645f05 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -1579,6 +1579,7 @@ static struct esdhc_soc_data usdhc_imx7d_data = {
 };
 
 static const struct udevice_id fsl_esdhc_ids[] = {
+	{ .compatible = "fsl,imx53-esdhc", },
 	{ .compatible = "fsl,imx6ul-usdhc", },
 	{ .compatible = "fsl,imx6sx-usdhc", },
 	{ .compatible = "fsl,imx6sl-usdhc", },
-- 
2.11.0

[U-Boot] [PATCH 2/3] arm: imx: Add esdhc1/2 nodes to imx53.dtsi

[linux-kernel-dev at beckhoff.com]

From: Patrick Bruenn <p.bruenn@beckhoff.com>

These nodes are required by CX9020 when build with CONFIG_DM_MMC=y
They are copied from Linux 4.20

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
---

 arch/arm/dts/imx53.dtsi | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index 64591f9d476..e13009c8708 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -31,6 +31,8 @@
 		i2c0 = &i2c1;
 		i2c1 = &i2c2;
 		i2c2 = &i2c3;
+		mmc0 = &esdhc1;
+		mmc1 = &esdhc2;
 	};
 
 	tzic: tz-interrupt-controller at fffc000 {
@@ -54,6 +56,38 @@
 			reg = <0x50000000 0x10000000>;
 			ranges;
 
+			spba at 50000000 {
+				compatible = "fsl,spba-bus", "simple-bus";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x50000000 0x40000>;
+				ranges;
+
+				esdhc1: esdhc at 50004000 {
+					compatible = "fsl,imx53-esdhc";
+					reg = <0x50004000 0x4000>;
+					interrupts = <1>;
+					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
+						 <&clks IMX5_CLK_DUMMY>,
+						 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
+					clock-names = "ipg", "ahb", "per";
+					bus-width = <4>;
+					status = "disabled";
+				};
+
+				esdhc2: esdhc at 50008000 {
+					compatible = "fsl,imx53-esdhc";
+					reg = <0x50008000 0x4000>;
+					interrupts = <2>;
+					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
+						 <&clks IMX5_CLK_DUMMY>,
+						 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
+					clock-names = "ipg", "ahb", "per";
+					bus-width = <4>;
+					status = "disabled";
+				};
+			};
+
 			iomuxc: iomuxc at 53fa8000 {
 				compatible = "fsl,imx53-iomuxc";
 				reg = <0x53fa8000 0x4000>;
-- 
2.11.0

[U-Boot] [PATCH 3/3] dm: arm: imx: migrate cx9020 to CONFIG_DM_MMC

[linux-kernel-dev at beckhoff.com]

From: Patrick Bruenn <p.bruenn@beckhoff.com>

Enable esdhc1/2 device nodes for cx9020 and build with CONFIG_DM_MMC=y

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>

---

 arch/arm/dts/imx53-cx9020.dts | 52 +++++++++++++++++++++++++++++++------------
 configs/mx53cx9020_defconfig  |  1 +
 2 files changed, 39 insertions(+), 14 deletions(-)

diff --git a/arch/arm/dts/imx53-cx9020.dts b/arch/arm/dts/imx53-cx9020.dts
index c2e7d86c1b8..36ceae36aa9 100644
--- a/arch/arm/dts/imx53-cx9020.dts
+++ b/arch/arm/dts/imx53-cx9020.dts
@@ -99,20 +99,6 @@
 				MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS	0x80000000
 				MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD	0x80000000
 
-				MX53_PAD_SD1_DATA0__ESDHC1_DAT0		0x1d5
-				MX53_PAD_SD1_DATA1__ESDHC1_DAT1		0x1d5
-				MX53_PAD_SD1_DATA2__ESDHC1_DAT2		0x1d5
-				MX53_PAD_SD1_DATA3__ESDHC1_DAT3		0x1d5
-				MX53_PAD_SD1_CMD__ESDHC1_CMD		0x1d5
-				MX53_PAD_SD1_CLK__ESDHC1_CLK		0x1d5
-
-				MX53_PAD_SD2_DATA0__ESDHC2_DAT0		0x1d5
-				MX53_PAD_SD2_DATA1__ESDHC2_DAT1		0x1d5
-				MX53_PAD_SD2_DATA2__ESDHC2_DAT2		0x1d5
-				MX53_PAD_SD2_DATA3__ESDHC2_DAT3		0x1d5
-				MX53_PAD_SD2_CMD__ESDHC2_CMD		0x1d5
-				MX53_PAD_SD2_CLK__ESDHC2_CLK		0x1d5
-
 				MX53_PAD_FEC_MDC__FEC_MDC		0x4
 				MX53_PAD_FEC_MDIO__FEC_MDIO		0x1fc
 				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK	0x180
@@ -162,6 +148,28 @@
 			>;
 		};
 
+		pinctrl_esdhc1: esdhc1grp {
+			fsl,pins = <
+				MX53_PAD_SD1_DATA0__ESDHC1_DAT0		0x1d5
+				MX53_PAD_SD1_DATA1__ESDHC1_DAT1		0x1d5
+				MX53_PAD_SD1_DATA2__ESDHC1_DAT2		0x1d5
+				MX53_PAD_SD1_DATA3__ESDHC1_DAT3		0x1d5
+				MX53_PAD_SD1_CMD__ESDHC1_CMD		0x1d5
+				MX53_PAD_SD1_CLK__ESDHC1_CLK		0x1d5
+			>;
+		};
+
+		pinctrl_esdhc2: esdhc2grp {
+			fsl,pins = <
+				MX53_PAD_SD2_DATA0__ESDHC2_DAT0		0x1d5
+				MX53_PAD_SD2_DATA1__ESDHC2_DAT1		0x1d5
+				MX53_PAD_SD2_DATA2__ESDHC2_DAT2		0x1d5
+				MX53_PAD_SD2_DATA3__ESDHC2_DAT3		0x1d5
+				MX53_PAD_SD2_CMD__ESDHC2_CMD		0x1d5
+				MX53_PAD_SD2_CLK__ESDHC2_CLK		0x1d5
+			>;
+		};
+
 		pinctrl_uart2: uart2grp {
 			fsl,pins = <
 				MX53_PAD_EIM_D26__UART2_RXD_MUX	0x1e4
@@ -181,6 +189,22 @@
 	status = "okay";
 };
 
+&esdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esdhc1>;
+	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&esdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esdhc2>;
+	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	status = "okay";
+};
+
 &fec {
 	pinctrl-names = "default";
 	phy-mode = "rmii";
diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig
index 3cff52031a0..ddd65e8ee15 100644
--- a/configs/mx53cx9020_defconfig
+++ b/configs/mx53cx9020_defconfig
@@ -19,6 +19,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM_MMC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020"
 CONFIG_ENV_IS_IN_MMC=y
-- 
2.11.0

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Christopher Spencer]

On Wed, 2 Jan 2019 at 07:00, Baruch Siach <baruch@tkos.co.il> wrote:
> Use a single '=' to test string equality for compatibility with non-bash
> shells. Otherwise, if /bin/sh is dash, build fails:
> 
> ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
> ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
> ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
> ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
> WARNING './spl/u-boot-spl-ddr.bin' not found, resulting binary is not-functional
> 
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>

Tested-by: Chris Spencer <christopher.spencer@sea.co.uk>

Thanks,
Chris

Disclaimer: 

This email has been scanned for all known viruses by the MessageLabs Email Security System.

The contents of this email (including any attachments) are intended for the use of the mail addressee(s) shown, hence is private and in addition may include commercially sensitive information. If you are not the intended recipient of this email any disclosure, copying, distribution or use of its contents is strictly prohibited. You should notify the sender immediately and then delete it (including any attachments) from your system.

The information contained in or attached to this message may also be subject to the export control laws and regulations of the United Kingdom and the United States. This specifically includes, but is not limited to, the Arms Export Control Act (22 U.S.C. 2751-2794) and the International Traffic in Arms Regulation (22 C.F.R 120-130) as well as the Export Administration Act (50 U.S.C. App. 2401-2420), the Export Administration Regulation (15 C.F.R. 730-774) and the UK Export Control Act 2002.

Please help out the environment by only printing this e-mail if absolutely necessary - Thank you. 

SEA is the brand name of Systems Engineering & Assessment Ltd (registered office: Beckington Castle, 17 Castle Corner, Beckington, Frome, Somerset, BA11 6TA, UK - company number 02302168).

[U-Boot] [PATCH] ARM: imx: fix: Provide correct enum values for ONENAND/NOR boot recognition

[Lukasz Majewski]

According to "Table 5-1. Boot Device Select" (page 335,
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 4, 09/2017)
the BOOT_CFG1[3] have following values (regarding EIM booting):
0 - NOR flash and 1 - ONENAND

This commit provides correct identification of the boot medium for IMX6Q
boards booting from NOR memory (MCCMON6 is one of them).

Signed-off-by: Lukasz Majewski <lukma@denx.de>

---

 arch/arm/include/asm/mach-imx/sys_proto.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 8d6832a331..d0f866b630 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -67,8 +67,8 @@ enum imx6_bmode_serial_rom {
 };
 
 enum imx6_bmode_emi {
-	IMX6_BMODE_ONENAND,
 	IMX6_BMODE_NOR,
+	IMX6_BMODE_ONENAND,
 };
 
 enum imx6_bmode {
-- 
2.11.0

[U-Boot] [PATCH v2 00/11] arm: Colibri iMX7 fixes and DM_MMC conversion

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

This patchset fixes some small issues with Colibri iMX7 and
converts the board to use DM_MMC. It also adds the so far
missing configuration for the eMMC variant.

This patchset gets rid of all but one deprecation warning.
The remaining warning is due to CONFIG_USB still being used.
Fixing this is not entirly trivial due to missing GPIO host/
peripheral switch capabilities and will be tackled later.

--
Stefan

Changes in v2:
- Remove imx7-colibri.dtb from Makefile
- Remove unnecessary properties
- New patch
- New patch
- Add CONFIG_FIT/DFU/CRC32_VERIFY/CMD_GPT/DFU_MMC and FAT_WRITE

Stefan Agner (11):
  colibri_imx7: fix boot commands
  arm: dts: imx7: colibri: split dt for raw NAND and eMMC devices
  configs: colibri_imx7: enable DM for raw NAND devices
  configs: colibri_imx7: use separate device tree
  arm: dts: imx7: colibri: add usdhci peripherals to device tree
  configs: colibri_imx7: use DM_MMC
  colibri_imx7: drop legacy usdhc support
  configs: colibri_imx7: enable CAAM driver
  configs: colibri_imx7: use DFU for NAND instead of MMC
  configs: colibri_imx7: use distro defaults
  configs: add default configuraiton for Colibri iMX7 with eMMC

 arch/arm/dts/Makefile                         |  3 +-
 arch/arm/dts/imx7-colibri-emmc.dts            | 47 +++++++++
 arch/arm/dts/imx7-colibri-rawnand.dts         | 46 +++++++++
 .../{imx7-colibri.dts => imx7-colibri.dtsi}   | 65 ++++++-------
 board/toradex/colibri_imx7/MAINTAINERS        |  3 +
 board/toradex/colibri_imx7/colibri_imx7.c     | 97 -------------------
 configs/colibri_imx7_defconfig                | 27 +++---
 configs/colibri_imx7_emmc_defconfig           | 66 +++++++++++++
 include/configs/colibri_imx7.h                |  5 +-
 9 files changed, 207 insertions(+), 152 deletions(-)
 create mode 100644 arch/arm/dts/imx7-colibri-emmc.dts
 create mode 100644 arch/arm/dts/imx7-colibri-rawnand.dts
 rename arch/arm/dts/{imx7-colibri.dts => imx7-colibri.dtsi} (68%)
 create mode 100644 configs/colibri_imx7_emmc_defconfig

-- 
2.20.1

[U-Boot] [PATCH v2 01/11] colibri_imx7: fix boot commands

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

Fix mixed up boot commands between raw NAND and eMMC variant. Also
make sure that the boot_file is defined for the eMMC boot command.

Fixes: a62c60610f51 ("colibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module support")
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

Changes in v2: None

 include/configs/colibri_imx7.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index c31cf2888a..5a4b9801cb 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -110,13 +110,13 @@
 		"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
 
 #if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND)
-#define CONFIG_BOOTCOMMAND "run emmcboot ; echo ; echo emmcboot failed ; " \
+#define CONFIG_BOOTCOMMAND "run ubiboot ; echo ; echo ubiboot failed ; " \
 	"setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;"
 #define MODULE_EXTRA_ENV_SETTINGS \
 	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
 	UBI_BOOTCMD
 #elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC)
-#define CONFIG_BOOTCOMMAND "run ubiboot ; echo ; echo ubiboot failed ; " \
+#define CONFIG_BOOTCOMMAND "run emmcboot ; echo ; echo emmcboot failed ; " \
 	"setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb && run distro_bootcmd;"
 #define MODULE_EXTRA_ENV_SETTINGS \
 	"variant=-emmc\0" \
@@ -143,6 +143,7 @@
 	NFS_BOOTCMD \
 	SD_BOOTCMD \
 	MODULE_EXTRA_ENV_SETTINGS \
+	"boot_file=zImage\0" \
 	"console=ttymxc0\0" \
 	"defargs=\0" \
 	"fdt_board=eval-v3\0" \
-- 
2.20.1

[U-Boot] [PATCH v2 02/11] arm: dts: imx7: colibri: split dt for raw NAND and eMMC devices

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

In preparation of adding CONFIG_DM_MMC support use separate device
trees for raw NAND and eMMC devices.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

Changes in v2:
- Remove imx7-colibri.dtb from Makefile

 arch/arm/dts/Makefile                         |  3 +-
 arch/arm/dts/imx7-colibri-emmc.dts            | 16 +++++++
 arch/arm/dts/imx7-colibri-rawnand.dts         | 46 +++++++++++++++++++
 .../{imx7-colibri.dts => imx7-colibri.dtsi}   | 39 +---------------
 board/toradex/colibri_imx7/MAINTAINERS        |  3 ++
 configs/colibri_imx7_defconfig                |  2 +-
 6 files changed, 68 insertions(+), 41 deletions(-)
 create mode 100644 arch/arm/dts/imx7-colibri-emmc.dts
 create mode 100644 arch/arm/dts/imx7-colibri-rawnand.dts
 rename arch/arm/dts/{imx7-colibri.dts => imx7-colibri.dtsi} (65%)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dda4e59491..768965a9fe 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -458,8 +458,7 @@ dtb-$(CONFIG_MX6UL) += \
 
 dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
 
-dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
-	imx7d-sdb.dtb \
+dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
 	imx7d-sdb-qspi.dtb
 
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
diff --git a/arch/arm/dts/imx7-colibri-emmc.dts b/arch/arm/dts/imx7-colibri-emmc.dts
new file mode 100644
index 0000000000..295ca05916
--- /dev/null
+++ b/arch/arm/dts/imx7-colibri-emmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+/dts-v1/;
+#include "imx7-colibri.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX7D 1GB (eMMC)";
+	compatible = "toradex,imx7d-colibri-emmc", "fsl,imx7d";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+};
diff --git a/arch/arm/dts/imx7-colibri-rawnand.dts b/arch/arm/dts/imx7-colibri-rawnand.dts
new file mode 100644
index 0000000000..4eb86fb011
--- /dev/null
+++ b/arch/arm/dts/imx7-colibri-rawnand.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+/dts-v1/;
+#include "imx7-colibri.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX7S/D";
+	compatible = "toradex,imx7-colibri", "fsl,imx7";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	fsl,use-minimum-ecc;
+	nand-on-flash-bbt;
+	nand-ecc-mode = "hw";
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_gpmi_nand: gpmi-nand-grp {
+		fsl,pins = <
+			MX7D_PAD_SD3_CLK__NAND_CLE		0x71
+			MX7D_PAD_SD3_CMD__NAND_ALE		0x71
+			MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
+			MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
+			MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
+			MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
+			MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
+			MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
+			MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
+			MX7D_PAD_SD3_DATA3__NAND_DATA03		0x71
+			MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
+			MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
+			MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
+			MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dtsi
similarity index 65%
rename from arch/arm/dts/imx7-colibri.dts
rename to arch/arm/dts/imx7-colibri.dtsi
index dca501be25..47295117aa 100644
--- a/arch/arm/dts/imx7-colibri.dts
+++ b/arch/arm/dts/imx7-colibri.dtsi
@@ -1,30 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2016 Toradex AG
+ * Copyright 2016-2019 Toradex AG
  */
 
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
 #include "imx7d.dtsi"
 
-/ {
-	model = "Toradex Colibri iMX7S/D";
-	compatible = "toradex,imx7-colibri", "fsl,imx7";
-
-	chosen {
-		stdout-path = &uart1;
-	};
-};
-
-&gpmi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	fsl,use-minimum-ecc;
-	nand-on-flash-bbt;
-	nand-ecc-mode = "hw";
-	status = "okay";
-};
-
 &i2c1 {
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
@@ -57,25 +39,6 @@
 };
 
 &iomuxc {
-	pinctrl_gpmi_nand: gpmi-nand-grp {
-		fsl,pins = <
-			MX7D_PAD_SD3_CLK__NAND_CLE		0x71
-			MX7D_PAD_SD3_CMD__NAND_ALE		0x71
-			MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
-			MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
-			MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
-			MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
-			MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
-			MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
-			MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
-			MX7D_PAD_SD3_DATA3__NAND_DATA03		0x71
-			MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
-			MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
-			MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
-			MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
-		>;
-	};
-
 	pinctrl_i2c4: i2c4-grp {
 		fsl,pins = <
 			MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA	0x4000007f
diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS
index 9c1d42aa8c..f55f8045f4 100644
--- a/board/toradex/colibri_imx7/MAINTAINERS
+++ b/board/toradex/colibri_imx7/MAINTAINERS
@@ -8,3 +8,6 @@ F:	board/toradex/colibri_imx7/
 F:	include/configs/colibri_imx7.h
 F:	configs/colibri_imx7_defconfig
 F:	configs/colibri_imx7_emmc_defconfig
+F:	arch/arm/dts/imx7-colibri.dtsi
+F:	arch/arm/dts/imx7-colibri-emmc.dts
+F:	arch/arm/dts/imx7-colibri-rawnand.dts
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 7b496bcea9..7441102ed4 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -43,7 +43,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx7-bcb),1536k(u-boot1)ro,1536k
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri"
+CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DFU_MMC=y
-- 
2.20.1

[U-Boot] [PATCH v2 03/11] configs: colibri_imx7: enable DM for raw NAND devices

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

Use DM and device trees for raw NAND devices by default. This
fixes -74 NAND read errors since it makes sure the ECC settings
are the same as used in Linux and our downstream U-Boot.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
---

Changes in v2: None

 configs/colibri_imx7_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 7441102ed4..3aaf1a417d 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -25,6 +25,7 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_NAND_TORTURE=y
 CONFIG_CMD_USB=y
@@ -50,7 +51,9 @@ CONFIG_DFU_MMC=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
 CONFIG_NAND=y
+CONFIG_NAND_MXS_DT=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
-- 
2.20.1

[U-Boot] [PATCH v2 04/11] configs: colibri_imx7: use separate device tree

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

Use OF_SEPARATE as suggested by the build system.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

Changes in v2: None

 configs/colibri_imx7_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 3aaf1a417d..0c9467e136 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -43,7 +43,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx7-bcb),1536k(u-boot1)ro,1536k(u-boot2)ro,512k(u-boot-env),-(ubi)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-- 
2.20.1

[U-Boot] [PATCH v2 05/11] arm: dts: imx7: colibri: add usdhci peripherals to device tree

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

Add usdhci peripherals to device tree. This allows to use DM_MMC
for Colibri iMX7 devices.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
---

Changes in v2:
- Remove unnecessary properties

 arch/arm/dts/imx7-colibri-emmc.dts | 31 ++++++++++++++++++++++++++++++
 arch/arm/dts/imx7-colibri.dtsi     | 26 +++++++++++++++++++++++++
 2 files changed, 57 insertions(+)

diff --git a/arch/arm/dts/imx7-colibri-emmc.dts b/arch/arm/dts/imx7-colibri-emmc.dts
index 295ca05916..efd600091d 100644
--- a/arch/arm/dts/imx7-colibri-emmc.dts
+++ b/arch/arm/dts/imx7-colibri-emmc.dts
@@ -10,7 +10,38 @@
 	model = "Toradex Colibri iMX7D 1GB (eMMC)";
 	compatible = "toradex,imx7d-colibri-emmc", "fsl,imx7d";
 
+	aliases {
+		mmc0 = &usdhc3;
+		mmc1 = &usdhc1;
+	};
+
 	chosen {
 		stdout-path = &uart1;
 	};
 };
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
+			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
+			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
+			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
+			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
+			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
+			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
+			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
+			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
+			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
+			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx7-colibri.dtsi b/arch/arm/dts/imx7-colibri.dtsi
index 47295117aa..a85702f519 100644
--- a/arch/arm/dts/imx7-colibri.dtsi
+++ b/arch/arm/dts/imx7-colibri.dtsi
@@ -38,6 +38,15 @@
 	status = "okay";
 };
 
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
+	no-1-8-v;
+	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	status = "okay";
+};
+
 &iomuxc {
 	pinctrl_i2c4: i2c4-grp {
 		fsl,pins = <
@@ -68,6 +77,17 @@
 			MX7D_PAD_SD2_DATA0__GPIO5_IO14		0x14 /* DTR */
 		>;
 	};
+
+	pinctrl_usdhc1: usdhc1-grp {
+		fsl,pins = <
+			MX7D_PAD_SD1_CMD__SD1_CMD	0x59
+			MX7D_PAD_SD1_CLK__SD1_CLK	0x19
+			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x59
+			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x59
+			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x59
+			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x59
+		>;
+	};
 };
 
 &iomuxc_lpsr {
@@ -84,4 +104,10 @@
 			MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4	0x4000007f
 		>;
 	};
+
+	pinctrl_cd_usdhc1: usdhc1-cd-grp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x59 /* CD */
+		>;
+	};
 };
-- 
2.20.1

[U-Boot] [PATCH v2 06/11] configs: colibri_imx7: use DM_MMC

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

Now that device tree is in place use DM_MMC for Colibri iMX7
devices.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

Changes in v2: None

 configs/colibri_imx7_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 0c9467e136..af976bab12 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -49,6 +49,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DFU_MMC=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_NAND=y
@@ -63,7 +64,6 @@ CONFIG_DM_PMIC=y
 CONFIG_PMIC_RN5T567=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-- 
2.20.1

[U-Boot] [PATCH v2 07/11] colibri_imx7: drop legacy usdhc support

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

Drop legacy pinmux/usdhc board configuration.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

Changes in v2: None

 board/toradex/colibri_imx7/colibri_imx7.c | 97 -----------------------
 1 file changed, 97 deletions(-)

diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index a4c99626b4..392fda92da 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -33,9 +33,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
 	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
-	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
 
@@ -64,17 +61,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-	MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
-	MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
 #ifdef CONFIG_USB_EHCI_MX7
 static iomux_v3_cfg_t const usb_cdet_pads[] = {
 	MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -109,24 +95,6 @@ static void setup_gpmi_nand(void)
 }
 #endif
 
-#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
-static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
-	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_STROBE__SD3_STROBE	 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
-	MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-#endif
-
 #ifdef CONFIG_VIDEO_MXS
 static iomux_v3_cfg_t const lcd_pads[] = {
 	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
@@ -211,71 +179,6 @@ static void setup_iomux_uart(void)
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
-
-#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 0)
-
-static struct fsl_esdhc_cfg usdhc_cfg[] = {
-#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
-	{USDHC3_BASE_ADDR},
-#endif
-	{USDHC1_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC1_BASE_ADDR:
-		ret = !gpio_get_value(USDHC1_CD_GPIO);
-		break;
-#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
-	case USDHC3_BASE_ADDR:
-		ret = 1;
-		break;
-#endif
-	}
-
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int i, ret;
-	/* USDHC1 is mmc0, USDHC3 is mmc1 */
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-			gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
-			gpio_direction_input(USDHC1_CD_GPIO);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-			break;
-#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads,
-				ARRAY_SIZE(usdhc3_emmc_pads));
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			break;
-#endif
-		default:
-			printf("Warning: you configured more USDHC controllers"
-				"(%d) than supported by the board\n", i + 1);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_FEC_MXC
 int board_eth_init(bd_t *bis)
 {
-- 
2.20.1

[U-Boot] [PATCH v2 08/11] configs: colibri_imx7: enable CAAM driver

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

Access to CAAM in non-secure mode must be enabled by the boot
loader first. The U-Boot CAAM driver enables access to CAAM in
non-secure mode by default. Hence enable the CAAM driver to
allow Linux accessing CAAM directly. This prevents error
messages like the following on Linux boot:
  caam 30900000.caam: Entropy delay = 3200
  caam 30900000.caam: failed to acquire DECO 0
  caam 30900000.caam: failed to instantiate RNG

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

Changes in v2: None

 configs/colibri_imx7_defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index af976bab12..c6fd7f3f4e 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -2,9 +2,11 @@ CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_MX7=y
 CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SECURE_BOOT=y
 CONFIG_TARGET_COLIBRI_IMX7=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
+# CONFIG_CMD_DEKBLOB is not set
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
@@ -35,6 +37,7 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+# CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
@@ -46,6 +49,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_CAAM=y
 CONFIG_DFU_MMC=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
-- 
2.20.1

[U-Boot] [PATCH v2 09/11] configs: colibri_imx7: use DFU for NAND instead of MMC

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

The colibri_imx7_defconfig is for Colibri iMX7 raw NAND devices.
Hence DFU for NAND is more useful then for MMC devices.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
---

Changes in v2:
- New patch

 configs/colibri_imx7_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index c6fd7f3f4e..2e675a0c1d 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -50,7 +50,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_FSL_CAAM=y
-CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-- 
2.20.1

[U-Boot] [PATCH v2 10/11] configs: colibri_imx7: use distro defaults

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

The defconfig already use most features implied by distro defaults.
Make sure we enable all features required by distro boot by making
use of CONFIG_DISTRO_DEFAULTS.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
---

Changes in v2:
- New patch

 configs/colibri_imx7_defconfig | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 2e675a0c1d..91577ed36b 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -7,18 +7,17 @@ CONFIG_TARGET_COLIBRI_IMX7=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 # CONFIG_CMD_DEKBLOB is not set
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
 CONFIG_BOOTDELAY=1
+# CONFIG_USE_BOOTCOMMAND is not set
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri iMX7 # "
 # CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_ASKENV=y
@@ -32,19 +31,15 @@ CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_NAND_TORTURE=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+# CONFIG_BOOTP_PXE is not set
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 # CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx7-bcb),1536k(u-boot1)ro,1536k(u-boot2)ro,512k(u-boot-env),-(ubi)"
 CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand"
 CONFIG_ENV_IS_IN_NAND=y
-- 
2.20.1

[U-Boot] [PATCH v2 11/11] configs: add default configuraiton for Colibri iMX7 with eMMC

[Stefan Agner]

From: Stefan Agner <stefan.agner@toradex.com>

Add a default configuration for Colibri iMX7D 1GB (with eMMC
NAND flash).

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
---

Changes in v2:
- Add CONFIG_FIT/DFU/CRC32_VERIFY/CMD_GPT/DFU_MMC and FAT_WRITE

 configs/colibri_imx7_emmc_defconfig | 66 +++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 configs/colibri_imx7_emmc_defconfig

diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig
new file mode 100644
index 0000000000..5e2a204a88
--- /dev/null
+++ b/configs/colibri_imx7_emmc_defconfig
@@ -0,0 +1,66 @@
+CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SECURE_BOOT=y
+CONFIG_TARGET_COLIBRI_IMX7=y
+CONFIG_TARGET_COLIBRI_IMX7_EMMC=y
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+# CONFIG_CMD_DEKBLOB is not set
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
+CONFIG_BOOTDELAY=1
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SYS_PROMPT="Colibri iMX7 # "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_HASH is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-emmc"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_CAAM=y
+CONFIG_DFU_MMC=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RN5T567=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Toradex"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
-- 
2.20.1

[U-Boot] [PATCH] imx: hab: Convert non-NULL IVT DCD pointer warning to an error

[Fabio Estevam]

On Fri, Dec 7, 2018 at 8:32 PM Breno Matheus Lima <breno.lima@nxp.com> wrote:
>
> The following NXP application notes and manual recommend to ensure the
> IVT DCD pointer is Null prior to calling HAB API authenticate_image()
> function:
>
> - AN12263: HABv4 RVT Guidelines and Recommendations
> - AN4581: Secure Boot on i.MX50, i.MX53, i.MX 6 and i.MX7 Series using
>   HABv4
> - CST docs: High Assurance Boot Version 4 Application Programming
>   Interface Reference Manual
>
> Commit ca89df7dd46f ("imx: hab: Convert DCD non-NULL error to warning")
> converted DCD non-NULL error to warning due to the lack of documentation
> at the time of first patch submission. We have warned U-Boot users since
> v2018.03, and it makes sense now to follow the NXP recommendation to
> ensure the IVT DCD pointer is Null.
>
> DCD commands should only be present in the initial boot image loaded by
> the SoC ROM. Starting in HAB v4.3.7 the HAB code  will generate an error
> if a DCD pointer is present in an image being authenticated by calling the
> HAB RVT API. Older versions of HAB will process and run DCD if it is
> present, and this could lead to an incorrect authentication boot flow.
>
> Signed-off-by: Breno Lima <breno.lima@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH] imx8: cpu: restrict checking ROM passover info for revA

[Peng Fan]

Passover info only for revA.

move get_cpu_rev out of CONFIG_CPU to avoid build failure when using
get_cpu_rev in SPL.
Add a CONFIG_SPL_BUILD for passover usage, no need to execute it again
in normal U-Boot stage. Also if still checking passover info in normal
U-Boot stage, need to make the passover code executed after
arch_cpu_init_dm.
So to make it easy and clean, only execute the code for SPL stage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8/cpu.c | 39 ++++++++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 303cdc3c9a..ac65ae74fd 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -35,15 +35,20 @@ struct pass_over_info_t *get_pass_over_info(void)
 
 int arch_cpu_init(void)
 {
-	struct pass_over_info_t *pass_over = get_pass_over_info();
-
-	if (pass_over && pass_over->g_ap_mu == 0) {
-		/*
-		 * When ap_mu is 0, means the U-Boot booted
-		 * from first container
-		 */
-		sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
+#ifdef CONFIG_SPL_BUILD
+	struct pass_over_info_t *pass_over;
+
+	if (is_soc_rev(CHIP_REV_A)) {
+		pass_over = get_pass_over_info();
+		if (pass_over && pass_over->g_ap_mu == 0) {
+			/*
+			 * When ap_mu is 0, means the U-Boot booted
+			 * from first container
+			 */
+			sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
+		}
 	}
+#endif
 
 	return 0;
 }
@@ -507,15 +512,6 @@ err:
 	printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
 }
 
-#if CONFIG_IS_ENABLED(CPU)
-struct cpu_imx_platdata {
-	const char *name;
-	const char *rev;
-	const char *type;
-	u32 cpurev;
-	u32 freq_mhz;
-};
-
 u32 get_cpu_rev(void)
 {
 	u32 id = 0, rev = 0;
@@ -531,6 +527,15 @@ u32 get_cpu_rev(void)
 	return (id << 12) | rev;
 }
 
+#if CONFIG_IS_ENABLED(CPU)
+struct cpu_imx_platdata {
+	const char *name;
+	const char *rev;
+	const char *type;
+	u32 cpurev;
+	u32 freq_mhz;
+};
+
 const char *get_imx8_type(u32 imxtype)
 {
 	switch (imxtype) {
-- 
2.14.1

[U-Boot] [PATCH v4 2/2] imx: Add PHYTEC phyBOARD-i.MX6UL-Segin

[Martyn Welch]

Hi All,

Is there anything preventing this series being merged? I don't think
I've seen any further issues raised.

Sorry if it's already been merged somewhere and I've missed it...

Martyn

On Tue, 2018-12-11 at 11:34 +0000, Martyn Welch wrote:
> Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer.
> Based on
> the PHYTEC phyCORE-i.MX6UL SOM (PCL063).
> 
> CPU:   Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
> CPU:   Industrial temperature grade (-40C to 105C) at 44C
> Reset cause: POR
> Board: PHYTEC phyCORE-i.MX6UL
> I2C:   ready
> DRAM:  256 MiB
> NAND:  512 MiB
> MMC:   FSL_SDHC: 0
> In:    serial
> Out:   serial
> Err:   serial
> Net:   FEC0
> 
> Working:
>  - Eth0
>  - i2C
>  - MMC/SD
>  - NAND
>  - UART (1 & 5)
>  - USB (host & otg)
> 
> Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
> 
> ---
> 
> Changes in v4:
> - Added PXE boot option
> - Switched i2c to DM support
> 
> Changes in v3:
> - Correct spelling of Phytec
> - Remove unneeded license information
> - Correct image name in documentation
> - Correct whitespacing
> - Enable SPL to boot from MMC
> - Simplify defconfig, remove non-SPL build
> 
> Changes in v2:
> - Switch to driver model
> 
>  arch/arm/dts/Makefile                 |   3 +-
>  arch/arm/dts/imx6ul-pcl063.dtsi       | 173 +++++++++++++++++++++
>  arch/arm/dts/imx6ul-phycore-segin.dts |  76 ++++++++++
>  arch/arm/mach-imx/mx6/Kconfig         |  13 ++
>  board/phytec/pcl063/Kconfig           |  12 ++
>  board/phytec/pcl063/MAINTAINERS       |   8 +
>  board/phytec/pcl063/Makefile          |   7 +
>  board/phytec/pcl063/README            |  26 ++++
>  board/phytec/pcl063/pcl063.c          | 206
> ++++++++++++++++++++++++++
>  board/phytec/pcl063/spl.c             | 160 ++++++++++++++++++++
>  configs/phycore_pcl063_defconfig      |  62 ++++++++
>  include/configs/pcl063.h              |  94 ++++++++++++
>  12 files changed, 839 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/imx6ul-pcl063.dtsi
>  create mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts
>  create mode 100644 board/phytec/pcl063/Kconfig
>  create mode 100644 board/phytec/pcl063/MAINTAINERS
>  create mode 100644 board/phytec/pcl063/Makefile
>  create mode 100644 board/phytec/pcl063/README
>  create mode 100644 board/phytec/pcl063/pcl063.c
>  create mode 100644 board/phytec/pcl063/spl.c
>  create mode 100644 configs/phycore_pcl063_defconfig
>  create mode 100644 include/configs/pcl063.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 949ee472fc..68411623e5 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -453,7 +453,8 @@ dtb-$(CONFIG_MX6UL) += \
>  	imx6ul-isiot-nand.dtb \
>  	imx6ul-opos6uldev.dtb \
>  	imx6ul-14x14-evk.dtb \
> -	imx6ul-9x9-evk.dtb
> +	imx6ul-9x9-evk.dtb \
> +	imx6ul-phycore-segin.dtb
>  
>  dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
>  
> diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/imx6ul-
> pcl063.dtsi
> new file mode 100644
> index 0000000000..24a6a47983
> --- /dev/null
> +++ b/arch/arm/dts/imx6ul-pcl063.dtsi
> @@ -0,0 +1,173 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 Collabora Ltd.
> + *
> + * Based on dts[i] from Phytec barebox port:
> + * Copyright (C) 2016 PHYTEC Messtechnik GmbH
> + * Author: Christian Hemp <c.hemp@phytec.de>
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6ul.dtsi"
> +
> +/ {
> +	model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
> +	compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
> +
> +	memory {
> +		reg = <0x80000000 0x20000000>;
> +	};
> +
> +	chosen {
> +		stdout-path = &uart1;
> +	};
> +};
> +
> +&fec1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_enet1>;
> +	phy-mode = "rmii";
> +	phy-handle = <&ethphy0>;
> +	status = "okay";
> +
> +	mdio: mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy0: ethernet-phy at 1 {
> +			reg = <1>;
> +			micrel,led-mode = <1>;
> +		};
> +	};
> +};
> +
> +&gpmi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_gpmi_nand>;
> +	nand-on-flash-bbt;
> +	fsl,no-blockmark-swap;
> +	status = "okay";
> +
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	partition at 0 {
> +		label = "uboot";
> +		reg = <0x0 0x400000>;
> +	};
> +
> +	partition at 400000 {
> +		label = "uboot-env";
> +		reg = <0x400000 0x100000>;
> +	};
> +
> +	partition at 500000 {
> +		label = "root";
> +		reg = <0x500000 0x0>;
> +	};
> +};
> +
> +&i2c1 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default", "gpio";
> +	pinctrl-0 = <&pinctrl_i2c1>;
> +	pinctrl-1 = <&pinctrl_i2c1_gpio>;
> +	scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
> +	sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +
> +	eeprom at 52 {
> +		compatible = "cat,24c32";
> +		reg = <0x52>;
> +	};
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	status = "okay";
> +};
> +
> +&usdhc1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc1>;
> +	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
> +	bus-width = <0x4>;
> +	pinctrl-0 = <&pinctrl_usdhc1>;
> +	no-1-8-v;
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +
> +	pinctrl_enet1: enet1grp {
> +		fsl,pins = <
> +			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
> +			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0X1b0
> b0
> +			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0
> b0
> +			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0
> b0
> +			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0
> b0
> +			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0
> b0
> +			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0
> b0
> +			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0
> b0
> +			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0
> b0
> +			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x400
> 1b031
> +		>;
> +	};
> +
> +	pinctrl_gpmi_nand: gpminandgrp {
> +		fsl,pins = <
> +			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x0b0
> b1
> +			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x0b0
> b1
> +			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0x0b0b1
> +			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x0b0
> 00
> +			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x0b0
> b1
> +			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x0b0b1
> +			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x0b0b1
> +			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x0b0
> b1
> +			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x0b0
> b1
> +			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x0b0
> b1
> +			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x0b0
> b1
> +			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x0b0
> b1
> +			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x0b0
> b1
> +			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x0b0
> b1
> +			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x0b0
> b1
> +		>;
> +	};
> +
> +	pinctrl_i2c1: i2cgrp {
> +		fsl,pins = <
> +			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL       0x4001b
> 8b0
> +			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA       0x4001b
> 8b0
> +		>;
> +	};
> +
> +	pinctrl_i2c1_gpio: i2c1grp_gpio {
> +		fsl,pins = <
> +			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
> +			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
> +		>;
> +	};
> +
> +	pinctrl_uart1: uart1grp {
> +		fsl,pins = <
> +			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
> +			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
> +		>;
> +	};
> +
> +	pinctrl_usdhc1: usdhc1grp {
> +		fsl,pins = <
> +			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170
> 59
> +			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100
> 59
> +			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
> +			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
> +			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
> +			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
> +			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
> +
> +		>;
> +	};
> +};
> diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts
> b/arch/arm/dts/imx6ul-phycore-segin.dts
> new file mode 100644
> index 0000000000..a46012e2b4
> --- /dev/null
> +++ b/arch/arm/dts/imx6ul-phycore-segin.dts
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 Collabora Ltd.
> + *
> + * Based on dts[i] from Phytec barebox port:
> + * Copyright (C) 2016 PHYTEC Messtechnik GmbH
> + * Author: Christian Hemp <c.hemp@phytec.de>
> + *
> + * The code contained herein is licensed under the GNU General
> Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6ul-pcl063.dtsi"
> +
> +/ {
> +	model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
> +	compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-
> pcl063",
> +		     "fsl,imx6ul";
> +};
> +
> +&i2c1 {
> +	i2c_rtc: rtc at 68 {
> +		compatible = "microcrystal,rv4162";
> +		reg = <0x68>;
> +		status = "okay";
> +	};
> +};
> +
> +&uart5 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart5>;
> +	uart-has-rtscts;
> +	status = "okay";
> +};
> +
> +&usbotg1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usb_otg1_id>;
> +	dr_mode = "otg";
> +	srp-disable;
> +	hnp-disable;
> +	adp-disable;
> +	status = "okay";
> +};
> +
> +&usbotg2 {
> +	dr_mode = "host";
> +	disable-over-current;
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +
> +	pinctrl_uart5: uart5grp {
> +		fsl,pins = <
> +			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0
> b1
> +			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0
> b1
> +			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0
> b1
> +			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0
> b1
> +		>;
> +	};
> +
> +	pinctrl_usb_otg1_id: usbotg1idgrp {
> +		fsl,pins = <
> +			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
> +		>;
> +	};
> +
> +};
> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-
> imx/mx6/Kconfig
> index 06c25bae36..e253f495c5 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -428,6 +428,18 @@ config TARGET_PFLA02
>  	select MX6QDL
>  	select SUPPORT_SPL
>  
> +config TARGET_PCL063
> +	bool "PHYTEC PCL063 (phyCORE-i.MX6UL)"
> +	select MX6UL
> +	select DM
> +	select DM_ETH
> +	select DM_GPIO
> +	select DM_I2C
> +	select DM_MMC
> +	select DM_SERIAL
> +	select DM_THERMAL
> +	select SUPPORT_SPL
> +
>  config TARGET_SECOMX6
>  	bool "secomx6 boards"
>  
> @@ -550,6 +562,7 @@ source "board/freescale/mx6ullevk/Kconfig"
>  source "board/grinn/liteboard/Kconfig"
>  source "board/phytec/pcm058/Kconfig"
>  source "board/phytec/pfla02/Kconfig"
> +source "board/phytec/pcl063/Kconfig"
>  source "board/gateworks/gw_ventana/Kconfig"
>  source "board/kosagi/novena/Kconfig"
>  source "board/samtec/vining_2000/Kconfig"
> diff --git a/board/phytec/pcl063/Kconfig
> b/board/phytec/pcl063/Kconfig
> new file mode 100644
> index 0000000000..977db70f64
> --- /dev/null
> +++ b/board/phytec/pcl063/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_PCL063
> +
> +config SYS_BOARD
> +	default "pcl063"
> +
> +config SYS_VENDOR
> +	default "phytec"
> +
> +config SYS_CONFIG_NAME
> +	default "pcl063"
> +
> +endif
> diff --git a/board/phytec/pcl063/MAINTAINERS
> b/board/phytec/pcl063/MAINTAINERS
> new file mode 100644
> index 0000000000..c65a951f3d
> --- /dev/null
> +++ b/board/phytec/pcl063/MAINTAINERS
> @@ -0,0 +1,8 @@
> +PCL063 BOARD
> +M:	Martyn Welch <martyn.welch@collabora.com>
> +S:	Maintained
> +F:	arch/arm/dts/imx6ul-pcl063.dtsi
> +F:	arch/arm/dts/imx6ul-phycore-segin.dts
> +F:	board/phytec/pcl063/
> +F:	configs/phycore_pcl063_defconfig
> +F:	include/configs/pcl063.h
> diff --git a/board/phytec/pcl063/Makefile
> b/board/phytec/pcl063/Makefile
> new file mode 100644
> index 0000000000..53c73c9b08
> --- /dev/null
> +++ b/board/phytec/pcl063/Makefile
> @@ -0,0 +1,7 @@
> +# Copyright (C) 2018 Collabora Ltd.
> +#
> +# SPDX-License-Identifier:	GPL-2.0+
> +#
> +
> +obj-y  := pcl063.o
> +obj-$(CONFIG_SPL_BUILD) += spl.o
> diff --git a/board/phytec/pcl063/README b/board/phytec/pcl063/README
> new file mode 100644
> index 0000000000..be83bdb0d8
> --- /dev/null
> +++ b/board/phytec/pcl063/README
> @@ -0,0 +1,26 @@
> +How to use U-Boot on PHYTEC phyBOARD-i.MX6UL-Segin
> +--------------------------------------------------
> +
> +- Configure and build U-Boot for phyCORE-i.MX6UL:
> +
> +    $ make mrproper
> +    $ make phycore_pcl063_defconfig
> +    $ make
> +
> +  This will generate SPL and u-boot-dtb.img images.
> +
> +- The SPL and u-boot-dtb.img images need to be flashed into the
> micro SD card:
> +
> +    $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
> +    $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
> +
> +- Jumper settings:
> +
> +  JP1:   Open: Boot from NAND
> +       Closed: Boot from SD/MMC1
> +
> +- Connect the Serial cable to UART0 and the PC for the console.
> +
> +- Insert the micro SD card in the board and power it up.
> +
> +- U-Boot messages should come up.
> diff --git a/board/phytec/pcl063/pcl063.c
> b/board/phytec/pcl063/pcl063.c
> new file mode 100644
> index 0000000000..38b233d1b0
> --- /dev/null
> +++ b/board/phytec/pcl063/pcl063.c
> @@ -0,0 +1,206 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 Collabora Ltd.
> + *
> + * Based on board/ccv/xpress/xpress.c:
> + * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
> + */
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <fsl_esdhc.h>
> +#include <linux/bitops.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <usb.h>
> +#include <usb/ehci-ci.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> +	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
> PHYS_SDRAM_SIZE);
> +
> +	return 0;
> +}
> +
> +#define UART_PAD_CTRL  (PAD_CTL_PKE         | PAD_CTL_PUE       | \
> +			PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> +			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | \
> +			PAD_CTL_HYS)
> +
> +static iomux_v3_cfg_t const uart1_pads[] = {
> +	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const uart5_pads[] = {
> +	MX6_PAD_UART5_TX_DATA__UART5_DCE_TX |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MX6_PAD_UART5_RX_DATA__UART5_DCE_RX |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static void setup_iomux_uart(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(uart1_pads,
> ARRAY_SIZE(uart1_pads));
> +	imx_iomux_v3_setup_multiple_pads(uart5_pads,
> ARRAY_SIZE(uart5_pads));
> +}
> +
> +#ifdef CONFIG_NAND_MXS
> +
> +#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW |
> PAD_CTL_HYS)
> +
> +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm |
> PAD_CTL_PUS_22K_UP)
> +
> +#define NANDREADYPC MUX_PAD_CTRL(NAND_PAD_READY0_CTRL)
> +
> +static iomux_v3_cfg_t const gpmi_pads[] = {
> +	MX6_PAD_NAND_DATA00__RAWNAND_DATA00	|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_DATA01__RAWNAND_DATA01	|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_DATA02__RAWNAND_DATA02	|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_DATA03__RAWNAND_DATA03	|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_DATA04__RAWNAND_DATA04	|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_DATA05__RAWNAND_DATA05	|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_DATA06__RAWNAND_DATA06	|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_DATA07__RAWNAND_DATA07	|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_CLE__RAWNAND_CLE		|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_ALE__RAWNAND_ALE		|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_RE_B__RAWNAND_RE_B		|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_WE_B__RAWNAND_WE_B		|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B	|
> MUX_PAD_CTRL(NAND_PAD_CTRL),
> +	MX6_PAD_NAND_READY_B__RAWNAND_READY_B	| NANDREADYPC,
> +};
> +
> +static void setup_gpmi_nand(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(gpmi_pads,
> ARRAY_SIZE(gpmi_pads));
> +
> +	setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
> +			  (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
> +}
> +
> +#endif /* CONFIG_NAND_MXS */
> +
> +#ifdef CONFIG_FEC_MXC
> +
> +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
> +
> +#define ENET_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE       |
> \
> +			   PAD_CTL_SPEED_HIGH  | PAD_CTL_DSE_48ohm | \
> +			   PAD_CTL_SRE_FAST)
> +
> +#define MDIO_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE      |
> \
> +			   PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | \
> +			   PAD_CTL_ODE)
> +
> +static iomux_v3_cfg_t const fec1_pads[] = {
> +	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
> +	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 |
> MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 |
> MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 |
> MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
> +	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 |
> MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 |
> MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const fec2_pads[] = {
> +	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 |
> MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 |
> MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 |
> MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
> +	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 |
> MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 |
> MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +};
> +
> +static void setup_iomux_fec(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(fec1_pads,
> ARRAY_SIZE(fec1_pads));
> +	imx_iomux_v3_setup_multiple_pads(fec2_pads,
> ARRAY_SIZE(fec2_pads));
> +}
> +
> +static int setup_fec(void)
> +{
> +	struct iomuxc *const iomuxc_regs = (struct iomuxc
> *)IOMUXC_BASE_ADDR;
> +	int ret;
> +
> +	/*
> +	 * Use 50M anatop loopback REF_CLK1 for ENET1,
> +	 * clear gpr1[13], set gpr1[17].
> +	 */
> +	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
> +			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
> +
> +	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Use 50M anatop loopback REF_CLK2 for ENET2,
> +	 * clear gpr1[14], set gpr1[18].
> +	 */
> +	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
> +			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
> +
> +	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
> +	if (ret)
> +		return ret;
> +
> +	enable_enet_clk(1);
> +
> +	return 0;
> +}
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> +	/*
> +	 * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) &
> select
> +	 * 50 MHz RMII clock mode.
> +	 */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
> +
> +	if (phydev->drv->config)
> +		phydev->drv->config(phydev);
> +
> +	return 0;
> +}
> +#endif /* CONFIG_FEC_MXC */
> +
> +int board_early_init_f(void)
> +{
> +	setup_iomux_uart();
> +	setup_iomux_fec();
> +
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	/* Address of boot parameters */
> +	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> +#ifdef CONFIG_NAND_MXS
> +	setup_gpmi_nand();
> +#endif
> +
> +#ifdef CONFIG_FEC_MXC
> +	setup_fec();
> +#endif
> +	return 0;
> +}
> +
> +int checkboard(void)
> +{
> +	puts("Board: PHYTEC phyCORE-i.MX6UL\n");
> +
> +	return 0;
> +}
> diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
> new file mode 100644
> index 0000000000..b93cd493f2
> --- /dev/null
> +++ b/board/phytec/pcl063/spl.c
> @@ -0,0 +1,160 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 Collabora Ltd.
> + *
> + * Based on board/ccv/xpress/spl.c:
> + * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <asm/arch/clock.h>
> +#include <asm/io.h>
> +#include <asm/arch/mx6-ddr.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/arch/crm_regs.h>
> +#include <fsl_esdhc.h>
> +
> +/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 ->
> 256MiB */
> +
> +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
> +	.grp_addds = 0x00000030,
> +	.grp_ddrmode_ctl = 0x00020000,
> +	.grp_b0ds = 0x00000030,
> +	.grp_ctlds = 0x00000030,
> +	.grp_b1ds = 0x00000030,
> +	.grp_ddrpke = 0x00000000,
> +	.grp_ddrmode = 0x00020000,
> +	.grp_ddr_type = 0x000c0000,
> +};
> +
> +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
> +	.dram_dqm0 = 0x00000030,
> +	.dram_dqm1 = 0x00000030,
> +	.dram_ras = 0x00000030,
> +	.dram_cas = 0x00000030,
> +	.dram_odt0 = 0x00000030,
> +	.dram_odt1 = 0x00000030,
> +	.dram_sdba2 = 0x00000000,
> +	.dram_sdclk_0 = 0x00000030,
> +	.dram_sdqs0 = 0x00000030,
> +	.dram_sdqs1 = 0x00000030,
> +	.dram_reset = 0x00000030,
> +};
> +
> +static struct mx6_mmdc_calibration mx6_mmcd_calib = {
> +	.p0_mpwldectrl0 = 0x00000000,
> +	.p0_mpdgctrl0 = 0x41480148,
> +	.p0_mprddlctl = 0x40403E42,
> +	.p0_mpwrdlctl = 0x40405852,
> +};
> +
> +struct mx6_ddr_sysinfo ddr_sysinfo = {
> +	.dsize = 0,		/* Bus size = 16bit */
> +	.cs_density = 18,
> +	.ncs = 1,
> +	.cs1_mirror = 0,
> +	.rtt_wr = 1,
> +	.rtt_nom = 1,
> +	.walat = 1,		/* Write additional latency */
> +	.ralat = 5,		/* Read additional latency */
> +	.mif3_mode = 3,		/* Command prediction working mode */
> +	.bi_on = 1,		/* Bank interleaving enabled */
> +	.pd_fast_exit = 1,
> +	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default)
> */
> +	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default)
> */
> +	.ddr_type = DDR_TYPE_DDR3,
> +	.refsel = 1,		/* Refresh cycles at 32KHz */
> +	.refr = 7,		/* 8 refresh commands per refresh
> cycle */
> +};
> +
> +static struct mx6_ddr3_cfg mem_ddr = {
> +	.mem_speed = 933,
> +	.density = 4,
> +	.width = 16,
> +	.banks = 8,
> +	.rowaddr = 14,
> +	.coladdr = 10,
> +	.pagesz = 1,
> +	.trcd = 1391,
> +	.trcmin = 4791,
> +	.trasmin = 3400,
> +};
> +
> +static void ccgr_init(void)
> +{
> +	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +
> +	writel(0xFFFFFFFF, &ccm->CCGR0);
> +	writel(0xFFFFFFFF, &ccm->CCGR1);
> +	writel(0xFFFFFFFF, &ccm->CCGR2);
> +	writel(0xFFFFFFFF, &ccm->CCGR3);
> +	writel(0xFFFFFFFF, &ccm->CCGR4);
> +	writel(0xFFFFFFFF, &ccm->CCGR5);
> +	writel(0xFFFFFFFF, &ccm->CCGR6);
> +}
> +
> +static void spl_dram_init(void)
> +{
> +	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs,
> &mx6_grp_ioregs);
> +	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
> +}
> +
> +#ifdef CONFIG_FSL_ESDHC
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_PKE         | PAD_CTL_PUE       | \
> +			PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
> +			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | \
> +			PAD_CTL_HYS)
> +
> +static iomux_v3_cfg_t const usdhc1_pads[] = {
> +	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +static struct fsl_esdhc_cfg usdhc_cfg[] = {
> +	{
> +		.esdhc_base = USDHC1_BASE_ADDR,
> +		.max_bus_width = 4,
> +	},
> +};
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> +	return 1;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> +	imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
> ARRAY_SIZE(usdhc1_pads));
> +	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> +
> +	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
> +}
> +
> +#endif /* CONFIG_FSL_ESDHC */
> +
> +void board_init_f(ulong dummy)
> +{
> +	ccgr_init();
> +
> +	/* Setup AIPS and disable watchdog */
> +	arch_cpu_init();
> +
> +	/* Setup iomux and fec */
> +	board_early_init_f();
> +
> +	/* Setup GP timer */
> +	timer_init();
> +
> +	/* UART clocks enabled and gd valid - init serial console */
> +	preloader_console_init();
> +
> +	/* DDR initialization */
> +	spl_dram_init();
> +}
> diff --git a/configs/phycore_pcl063_defconfig
> b/configs/phycore_pcl063_defconfig
> new file mode 100644
> index 0000000000..02c659de23
> --- /dev/null
> +++ b/configs/phycore_pcl063_defconfig
> @@ -0,0 +1,62 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX6=y
> +CONFIG_SYS_TEXT_BASE=0x87800000
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_TARGET_PCL063=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_NR_DRAM_BANKS=8
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
> +CONFIG_BOOTDELAY=3
> +# CONFIG_USE_BOOTCOMMAND is not set
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SPL_USB_HOST_SUPPORT=y
> +CONFIG_SPL_USB_GADGET_SUPPORT=y
> +CONFIG_SPL_USB_SDP_SUPPORT=y
> +CONFIG_SPL_WATCHDOG_SUPPORT=y
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_CMD_DM=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +# CONFIG_RANDOM_UUID is not set
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_MTD=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_SDP=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
> +CONFIG_MTDPARTS_DEFAULT="gpmi-nand:4m(uboot),1m(env),-(root)"
> +CONFIG_CMD_UBI=y
> +# CONFIG_ISO_PARTITION is not set
> +CONFIG_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin"
> +CONFIG_DM_I2C_GPIO=y
> +CONFIG_SYS_I2C_MXC=y
> +CONFIG_FSL_ESDHC=y
> +CONFIG_MTD=y
> +CONFIG_NAND=y
> +CONFIG_NAND_MXS=y
> +CONFIG_NAND_MXS_DT=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_MICREL=y
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX6=y
> +CONFIG_DM_PMIC=y
> +# CONFIG_SPL_PMIC_CHILDREN is not set
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_MXC_UART=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_MANUFACTURER="Phytec"
> +CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
> +CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
> +CONFIG_CI_UDC=y
> +CONFIG_USB_GADGET_DOWNLOAD=y
> diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
> new file mode 100644
> index 0000000000..4ceab519cb
> --- /dev/null
> +++ b/include/configs/pcl063.h
> @@ -0,0 +1,94 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2018 Collabora Ltd.
> + *
> + * Based on include/configs/xpress.h:
> + * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
> + */
> +#ifndef __PCL063_H
> +#define __PCL063_H
> +
> +#include <linux/sizes.h>
> +#include "mx6_common.h"
> +
> +/* SPL options */
> +#include "imx6_spl.h"
> +
> +/*
> + * There is a bug in some i.MX6UL processors that results in the
> initial
> + * portion of OCRAM being unavailable when booting from (at least)
> an SD
> + * card.
> + *
> + * Tweak the SPL text base address to avoid this.
> + */
> +#undef CONFIG_SPL_TEXT_BASE
> +#define CONFIG_SPL_TEXT_BASE            0x00909000
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
> +
> +/* Console configs */
> +#define CONFIG_MXC_UART_BASE		UART1_BASE
> +
> +/* MMC Configs */
> +#define CONFIG_FSL_USDHC
> +
> +#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_MEMTEST_START	0x80000000
> +#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_STA
> RT + 0x10000000)
> +
> +#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
> +#define CONFIG_SYS_HZ			1000
> +
> +/* Physical Memory Map */
> +#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
> +#define PHYS_SDRAM_SIZE			SZ_256M
> +
> +#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> +	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> +	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#define CONFIG_ENV_SIZE			(16 << 10)
> +#define CONFIG_ENV_OFFSET		(512 << 10)
> +
> +/* NAND */
> +#define CONFIG_SYS_MAX_NAND_DEVICE	1
> +#define CONFIG_SYS_NAND_BASE		0x40000000
> +
> +/* USB Configs */
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> +#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI |
> PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS		0
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
> +
> +#define CONFIG_IMX_THERMAL
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +	"console=ttymxc0,115200n8\0" \
> +	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
> +	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
> +	"fdt_addr_r=0x82000000\0" \
> +	"fdt_high=0xffffffff\0" \
> +	"initrd_high=0xffffffff\0" \
> +	"kernel_addr_r=0x81000000\0" \
> +	"pxefile_addr_r=0x87100000\0" \
> +	"ramdisk_addr_r=0x82100000\0" \
> +	"scriptaddr=0x87000000\0" \
> +	BOOTENV
> +
> +#define BOOT_TARGET_DEVICES(func) \
> +	func(MMC, mmc, 0) \
> +	func(UBIFS, ubifs, 0) \
> +	func(PXE, pxe, na) \
> +	func(DHCP, dhcp, na)
> +
> +#include <config_distro_bootcmd.h>
> +
> +#endif /* __PCL063_H */

[U-Boot] [U-Boot, 1/3] mmc: fsl_esdhc: add compatible for fsl, imx53-esdhc

[sbabic at denx.de]

> From: Patrick Bruenn <p.bruenn@beckhoff.com>
> Add compatible "fsl,imx53-esdhc" to keep mmc working on i.MX53 platforms
> with CONFIG_DM_MMC=y
> Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 1/3] mx7: Do not call lcdif_power_down() in the SPL case

[sbabic at denx.de]

> From: Fabio Estevam <festevam@gmail.com>
> Like it was done on imx6 in commit 9236269de57d ("imx: mx6: Fix
> implementantion reset_misc")
> Do not call lcdif_power_down() in the SPL case to fix the following
> build error:
>   LD      spl/u-boot-spl
>   MKIMAGE u-boot.img
> arch/arm/mach-imx/built-in.o: In function `reset_misc':
> /home/fabio/ossystems/u-boot/arch/arm/mach-imx/mx7/soc.c:372: undefined reference to `lcdif_power_down'
> scripts/Makefile.spl:375: recipe for target 'spl/u-boot-spl' failed
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] imx8: cpu: restrict checking ROM passover info for revA

[sbabic at denx.de]

> Passover info only for revA.
> move get_cpu_rev out of CONFIG_CPU to avoid build failure when using
> get_cpu_rev in SPL.
> Add a CONFIG_SPL_BUILD for passover usage, no need to execute it again
> in normal U-Boot stage. Also if still checking passover info in normal
> U-Boot stage, need to make the passover code executed after
> arch_cpu_init_dm.
> So to make it easy and clean, only execute the code for SPL stage.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 11/11] configs: add default configuraiton for Colibri iMX7 with eMMC

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Add a default configuration for Colibri iMX7D 1GB (with eMMC
> NAND flash).
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, V2, 06/10] dts: imx8qxp-mek: introduce u-boot dtsi

[sbabic at denx.de]

> Introduce u-boot dtsi for i.MX8QXP MEK board.
> we do not introduce a common dtsi for SoC, because different board
> has different requirement on which needs to be enabled in SPL DM.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 3/3] dm: arm: imx: migrate cx9020 to CONFIG_DM_MMC

[sbabic at denx.de]

> From: Patrick Bruenn <p.bruenn@beckhoff.com>
> Enable esdhc1/2 device nodes for cx9020 and build with CONFIG_DM_MMC=y
> Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,V2,08/10] imx: build flash.bin for i.MX8

[sbabic at denx.de]

> Build flash.bin for i.MX8 when SPL enabled.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,V2,10/10] imx8qxp: mek: update README

[sbabic at denx.de]

> Update README after we switch to use SPL
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,V2,09/10] imx8qxp: mek: default enable SPL

[sbabic at denx.de]

> Enable SPL for i.MX8QXP MEK, and currently use SPL FIT.
> The SPL enable SPL_DM to use MMC/PINCTRL/POWER DOMAIN/CLK.
> Note: SPL FIT could not support secure boot chain, because i.MX8/8X
> only support i.MX container format. This container format has
> not been upstreamed, so we use FIT for now. When SPL container
> supported, we could switch to that.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 04/11] configs: colibri_imx7: use separate device tree

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Use OF_SEPARATE as suggested by the build system.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,2/3] pico-imx7d: Add LCD support

[sbabic at denx.de]

> From: Fabio Estevam <festevam@gmail.com>
> Add support for the VXT VL050-8048NT-C01 panel connected through
> the 24 bit parallel LCDIF interface.
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 10/11] configs: colibri_imx7: use distro defaults

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> The defconfig already use most features implied by distro defaults.
> Make sure we enable all features required by distro boot by making
> use of CONFIG_DISTRO_DEFAULTS.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 02/11] arm: dts: imx7: colibri: split dt for raw NAND and eMMC devices

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> In preparation of adding CONFIG_DM_MMC support use separate device
> trees for raw NAND and eMMC devices.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,V2,01/10] imx8qxp: add SUPPORT_SPL option

[sbabic at denx.de]

> Enable SUPPORT_SPL option for i.MX8QXP, then we could enable SPL.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,V2,03/10] arm: imx: build mach-imx for i.MX8

[sbabic at denx.de]

> To enable SPL for i.MX8, we could reuse code in arch/arm/mach-imx.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v2,01/11] colibri_imx7: fix boot commands

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Fix mixed up boot commands between raw NAND and eMMC variant. Also
> make sure that the boot_file is defined for the eMMC boot command.
> Fixes: a62c60610f51 ("colibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module support")
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 07/11] colibri_imx7: drop legacy usdhc support

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Drop legacy pinmux/usdhc board configuration.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v4,2/2] imx: Add PHYTEC phyBOARD-i.MX6UL-Segin

[sbabic at denx.de]

> Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
> the PHYTEC phyCORE-i.MX6UL SOM (PCL063).
> CPU:   Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
> CPU:   Industrial temperature grade (-40C to 105C) at 44C
> Reset cause: POR
> Board: PHYTEC phyCORE-i.MX6UL
> I2C:   ready
> DRAM:  256 MiB
> NAND:  512 MiB
> MMC:   FSL_SDHC: 0
> In:    serial
> Out:   serial
> Err:   serial
> Net:   FEC0
> Working:
>  - Eth0
>  - i2C
>  - MMC/SD
>  - NAND
>  - UART (1 & 5)
>  - USB (host & otg)
> Signed-off-by: Martyn Welch <martyn.welch@collabora.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,V2,05/10] spl: imx8: add spl boot device

[sbabic at denx.de]

> Add spl_boot_device for i.MX8, also add BOOT_DEVICE_MMC2_2 for
> spl_boot_mode.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, V2, 07/10] imx: mkimage_fit_atf: introduce BL33_BASE_ADDR

[sbabic at denx.de]

> Introduce BL33_BASE_ADDR, then we could reuse this script for i.MX8QXP.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] ARM: imx: fix: Provide correct enum values for ONENAND/NOR boot recognition

[sbabic at denx.de]

> According to "Table 5-1. Boot Device Select" (page 335,
> i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 4, 09/2017)
> the BOOT_CFG1[3] have following values (regarding EIM booting):
> 0 - NOR flash and 1 - ONENAND
> This commit provides correct identification of the boot medium for IMX6Q
> boards booting from NOR memory (MCCMON6 is one of them).
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,V2,04/10] gpio: introduce CONFIG_SPL_DM_PCA953X

[sbabic at denx.de]

> Introduce CONFIG_SPL_DM_PCA953X for SPL usage.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 03/11] configs: colibri_imx7: enable DM for raw NAND devices

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Use DM and device trees for raw NAND devices by default. This
> fixes -74 NAND read errors since it makes sure the ECC settings
> are the same as used in Linux and our downstream U-Boot.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 2/2] imx8mq_evk/README: remove ARCH environment variable

[sbabic at denx.de]

> There is no need to set the ARCH variable when building U-Boot. In fact,
> the ARCH name in U-Boot is 'arm'.
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v2,06/11] configs: colibri_imx7: use DM_MMC

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Now that device tree is in place use DM_MMC for Colibri iMX7
> devices.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] imx: hab: Convert non-NULL IVT DCD pointer warning to an error

[sbabic at denx.de]

> The following NXP application notes and manual recommend to ensure the
> IVT DCD pointer is Null prior to calling HAB API authenticate_image()
> function:
> - AN12263: HABv4 RVT Guidelines and Recommendations
> - AN4581: Secure Boot on i.MX50, i.MX53, i.MX 6 and i.MX7 Series using
>   HABv4
> - CST docs: High Assurance Boot Version 4 Application Programming
>   Interface Reference Manual
> Commit ca89df7dd46f ("imx: hab: Convert DCD non-NULL error to warning")
> converted DCD non-NULL error to warning due to the lack of documentation
> at the time of first patch submission. We have warned U-Boot users since
> v2018.03, and it makes sense now to follow the NXP recommendation to
> ensure the IVT DCD pointer is Null.
> DCD commands should only be present in the initial boot image loaded by
> the SoC ROM. Starting in HAB v4.3.7 the HAB code  will generate an error
> if a DCD pointer is present in an image being authenticated by calling the
> HAB RVT API. Older versions of HAB will process and run DCD if it is
> present, and this could lead to an incorrect authentication boot flow.
> Signed-off-by: Breno Lima <breno.lima@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 05/11] arm: dts: imx7: colibri: add usdhci peripherals to device tree

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Add usdhci peripherals to device tree. This allows to use DM_MMC
> for Colibri iMX7 devices.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 09/11] configs: colibri_imx7: use DFU for NAND instead of MMC

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> The colibri_imx7_defconfig is for Colibri iMX7 raw NAND devices.
> Hence DFU for NAND is more useful then for MMC devices.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 08/11] configs: colibri_imx7: enable CAAM driver

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Access to CAAM in non-secure mode must be enabled by the boot
> loader first. The U-Boot CAAM driver enables access to CAAM in
> non-secure mode by default. Hence enable the CAAM driver to
> allow Linux accessing CAAM directly. This prevents error
> messages like the following on Linux boot:
>   caam 30900000.caam: Entropy delay = 3200
>   caam 30900000.caam: failed to acquire DECO 0
>   caam 30900000.caam: failed to instantiate RNG
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,2/3] arm: imx: Add esdhc1/2 nodes to imx53.dtsi

[sbabic at denx.de]

> From: Patrick Bruenn <p.bruenn@beckhoff.com>
> These nodes are required by CX9020 when build with CONFIG_DM_MMC=y
> They are copied from Linux 4.20
> Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 1/2] Enable FEC driver to retrieve PHY address from device tree

[sbabic at denx.de]

> Currently if we have more than one phy on the MDIO bus, we do not have a
> good mechanism for determining which should be used at runtime. Enable the
> FEC driver to determine the address for the PHY from the device tree.
> Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,V2,02/10] imx8: scu: use dedicated MU for SPL

[sbabic at denx.de]

> SPL runs in EL3 mode, except MU0_A, others are not powered on,
> and could not be used. However normal U-Boot use MU1_A, so we
> could not reuse the one in dts. And we could not replace the one
> in dts with MU0_A, because MU0_A is reserved in secure world.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 2/2] imx8mq_evk/README: remove ARCH environment variable

[Baruch Siach]

Hi Stefano,

On Wed, Jan 30, 2019 at 10:40:19AM +0200, sbabic at denx.de wrote:
> > There is no need to set the ARCH variable when building U-Boot. In fact,
> > the ARCH name in U-Boot is 'arm'.
> > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> 
> Applied to u-boot-imx, master, thanks !

Thanks.

What about patch #1 in this series? It fixes build failure when /bin/sh is not 
bash.

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -

[U-Boot] [U-Boot, 2/2] imx8mq_evk/README: remove ARCH environment variable

[Stefano Babic]

Hi Baruch,

On 30/01/19 10:48, Baruch Siach wrote:
> Hi Stefano,
> 
> On Wed, Jan 30, 2019 at 10:40:19AM +0200, sbabic at denx.de wrote:
>>> There is no need to set the ARCH variable when building U-Boot. In fact,
>>> the ARCH name in U-Boot is 'arm'.
>>> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
>>
>> Applied to u-boot-imx, master, thanks !
> 
> Thanks.
> 
> What about patch #1 in this series? It fixes build failure when /bin/sh is not 
> bash.
> 

I suffer from the prejudice that a single "=" is always bad in a
comparison.....I am surely influenced from bugs in C/C++ due to a
missing "=" in my experience as developer.

I searched for such as comparison in other parts of build to justify
this patch : I have just found it in "test/fs" (ok, this is not really
part of build) and in ./lib/lzma/import_lzmasdk.sh. I fully agree that
this could be just a problem of mine, and I confess I was already merged
your patch and then removed again..

Apart of this,  it looks like that a single "=" was already avoided in
U-Boot scripts like the pest. Apart of the single entry I found above,
it was avoided..

What about to substitute "=" with an explicit "-eq" ? Like :

	[ $f -eq "spl/u-boot-spl-ddr.bin" ]

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 2/2] imx8mq_evk/README: remove ARCH environment variable

[Baruch Siach]

Hi Stefano,

On Wed, Jan 30, 2019 at 03:33:21PM +0100, Stefano Babic wrote:
> On 30/01/19 10:48, Baruch Siach wrote:
> > On Wed, Jan 30, 2019 at 10:40:19AM +0200, sbabic at denx.de wrote:
> >>> There is no need to set the ARCH variable when building U-Boot. In fact,
> >>> the ARCH name in U-Boot is 'arm'.
> >>> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> >>
> >> Applied to u-boot-imx, master, thanks !
> > 
> > Thanks.
> > 
> > What about patch #1 in this series? It fixes build failure when /bin/sh is not 
> > bash.
> 
> I suffer from the prejudice that a single "=" is always bad in a
> comparison.....I am surely influenced from bugs in C/C++ due to a
> missing "=" in my experience as developer.
> 
> I searched for such as comparison in other parts of build to justify
> this patch : I have just found it in "test/fs" (ok, this is not really
> part of build) and in ./lib/lzma/import_lzmasdk.sh. I fully agree that
> this could be just a problem of mine, and I confess I was already merged
> your patch and then removed again..
> 
> Apart of this,  it looks like that a single "=" was already avoided in
> U-Boot scripts like the pest. Apart of the single entry I found above,
> it was avoided..
> 
> What about to substitute "=" with an explicit "-eq" ? Like :
> 
> 	[ $f -eq "spl/u-boot-spl-ddr.bin" ]

The '-eq' operator only accept integers:

$ [ f -eq "spl/u-boot-spl-ddr.bin" ]
bash: test: f: integer expression expected

The alternative is to set the script shebang to /bin/bash. I don't like this 
solution. What do you think?

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -

[U-Boot] [U-Boot, 2/2] imx8mq_evk/README: remove ARCH environment variable

[Stefano Babic]

On 30/01/19 16:13, Baruch Siach wrote:
> Hi Stefano,
> 
> On Wed, Jan 30, 2019 at 03:33:21PM +0100, Stefano Babic wrote:
>> On 30/01/19 10:48, Baruch Siach wrote:
>>> On Wed, Jan 30, 2019 at 10:40:19AM +0200, sbabic at denx.de wrote:
>>>>> There is no need to set the ARCH variable when building U-Boot. In fact,
>>>>> the ARCH name in U-Boot is 'arm'.
>>>>> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
>>>>
>>>> Applied to u-boot-imx, master, thanks !
>>>
>>> Thanks.
>>>
>>> What about patch #1 in this series? It fixes build failure when /bin/sh is not 
>>> bash.
>>
>> I suffer from the prejudice that a single "=" is always bad in a
>> comparison.....I am surely influenced from bugs in C/C++ due to a
>> missing "=" in my experience as developer.
>>
>> I searched for such as comparison in other parts of build to justify
>> this patch : I have just found it in "test/fs" (ok, this is not really
>> part of build) and in ./lib/lzma/import_lzmasdk.sh. I fully agree that
>> this could be just a problem of mine, and I confess I was already merged
>> your patch and then removed again..
>>
>> Apart of this,  it looks like that a single "=" was already avoided in
>> U-Boot scripts like the pest. Apart of the single entry I found above,
>> it was avoided..
>>
>> What about to substitute "=" with an explicit "-eq" ? Like :
>>
>> 	[ $f -eq "spl/u-boot-spl-ddr.bin" ]
> 
> The '-eq' operator only accept integers:
> 
> $ [ f -eq "spl/u-boot-spl-ddr.bin" ]
> bash: test: f: integer expression expected
> 
> The alternative is to set the script shebang to /bin/bash. I don't like this 
> solution. What do you think?

Is not possible to change the behavior of the script filtering the
$blobs variable before evaluating ? The check is just for skipping these
two files.

Something like :

 blobs=`awk '/^SIGNED_HDMI/ {print $2} /^LOADER/ {print $2}
/^SECOND_LOADER/ {print $2} /^DDR_FW/ {print $2}' $file` | grep -v
""spl/u-boot-spl-ddr.bin" | ......

It look to me better to put in $blobs just the values that must be
evaluated instead of checking them later. $blobs is not evaluated anymore.

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v1 0/3] imx: cpu.c, serial_mxc, dts fixes/improvements

[Marcel Ziswiler]

This series addresses some shortcomings concerning reset cause in SPL,
serial in DTE mode and fixes some device-tree address/size-cells
warnings.


Marcel Ziswiler (1):
  ARM: dts: i.MX6Q, i.MX6QDL: fix address/size-cells warnings

Max Krummenacher (2):
  imx: serial_mxc: disable ri and dcd irq in dte mode
  imx: cpu.c: give access to reset cause in spl

 arch/arm/dts/imx6q.dtsi     |  4 ----
 arch/arm/dts/imx6qdl.dtsi   |  9 ---------
 arch/arm/mach-imx/cpu.c     | 27 +++++++++++++++------------
 drivers/serial/serial_mxc.c | 13 +++++++++----
 4 files changed, 24 insertions(+), 29 deletions(-)

-- 
2.20.1

[U-Boot] [PATCH v1 1/3] ARM: dts: i.MX6Q, i.MX6QDL: fix address/size-cells warnings

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

This fixes the following warnings:

arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /clocks: unnecessary #address-cells/#size-cells without "ranges" or
 child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/aips-bus at 02100000/mipi at 021e0000: unnecessary #address-cells/
 #size-cells without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu at 02400000/port at 2: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu at 02400000/port at 3: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu at 02800000/port at 2: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu at 02800000/port at 3: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 arch/arm/dts/imx6q.dtsi   | 4 ----
 arch/arm/dts/imx6qdl.dtsi | 9 ---------
 2 files changed, 13 deletions(-)

diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
index c30c8368ca..7f5d91d7f0 100644
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@@ -150,8 +150,6 @@
 			};
 
 			ipu2_di0: port at 2 {
-				#address-cells = <1>;
-				#size-cells = <0>;
 				reg = <2>;
 
 				ipu2_di0_disp0: disp0-endpoint {
@@ -175,8 +173,6 @@
 			};
 
 			ipu2_di1: port at 3 {
-				#address-cells = <1>;
-				#size-cells = <0>;
 				reg = <3>;
 
 				ipu2_di1_hdmi: hdmi-endpoint {
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index b13b0b2db8..476cf93445 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -49,9 +49,6 @@
 	};
 
 	clocks {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
 		ckil {
 			compatible = "fsl,imx-ckil", "fixed-clock";
 			#clock-cells = <0>;
@@ -1125,8 +1122,6 @@
 			};
 
 			mipi_dsi: mipi at 021e0000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
 				reg = <0x021e0000 0x4000>;
 				status = "disabled";
 
@@ -1228,8 +1223,6 @@
 			};
 
 			ipu1_di0: port at 2 {
-				#address-cells = <1>;
-				#size-cells = <0>;
 				reg = <2>;
 
 				ipu1_di0_disp0: disp0-endpoint {
@@ -1253,8 +1246,6 @@
 			};
 
 			ipu1_di1: port at 3 {
-				#address-cells = <1>;
-				#size-cells = <0>;
 				reg = <3>;
 
 				ipu1_di1_disp1: disp1-endpoint {
-- 
2.20.1

[U-Boot] [PATCH v1 2/3] imx: serial_mxc: disable ri and dcd irq in dte mode

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

If the UART is used in DTE mode the RI and DCD bits in UCR3 become
irq enable bits. Both are set to enabled after reset and both likely
are pending.

Disable the bits to prevent an interrupt storm when Linux enables
the UART interrupts.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 drivers/serial/serial_mxc.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 7e4e6d36b8..df35ac9114 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -138,13 +138,18 @@ struct mxc_uart {
 	u32 ts;
 };
 
-static void _mxc_serial_init(struct mxc_uart *base)
+static void _mxc_serial_init(struct mxc_uart *base, int use_dte)
 {
 	writel(0, &base->cr1);
 	writel(0, &base->cr2);
 
 	while (!(readl(&base->cr2) & UCR2_SRST));
 
+	if (use_dte)
+		writel(0x404 | UCR3_ADNIMP, &base->cr3);
+	else
+		writel(0x704 | UCR3_ADNIMP, &base->cr3);
+
 	writel(0x704 | UCR3_ADNIMP, &base->cr3);
 	writel(0x8000, &base->cr4);
 	writel(0x2b, &base->esc);
@@ -226,7 +231,7 @@ static int mxc_serial_tstc(void)
  */
 static int mxc_serial_init(void)
 {
-	_mxc_serial_init(mxc_base);
+	_mxc_serial_init(mxc_base, false);
 
 	serial_setbrg();
 
@@ -271,7 +276,7 @@ static int mxc_serial_probe(struct udevice *dev)
 {
 	struct mxc_serial_platdata *plat = dev->platdata;
 
-	_mxc_serial_init(plat->reg);
+	_mxc_serial_init(plat->reg, plat->use_dte);
 
 	return 0;
 }
@@ -367,7 +372,7 @@ static inline void _debug_uart_init(void)
 {
 	struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
 
-	_mxc_serial_init(base);
+	_mxc_serial_init(base, false);
 	_mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
 			   CONFIG_BAUDRATE, false);
 }
-- 
2.20.1

[U-Boot] [PATCH v1 3/3] imx: cpu.c: give access to reset cause in spl

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

This makes get_imx_reset_cause() accessible in SPL, but keeps the SRSR
register content intact so that U-Boot proper can evaluated the
reset_cause again should this be needed.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 arch/arm/mach-imx/cpu.c | 27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 80d9ff48a4..6b83f92662 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -25,19 +25,27 @@
 #include <fsl_esdhc.h>
 #endif
 
-#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
 static u32 reset_cause = -1;
 
-static char *get_reset_cause(void)
+u32 get_imx_reset_cause(void)
 {
-	u32 cause;
 	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 
-	cause = readl(&src_regs->srsr);
-	writel(cause, &src_regs->srsr);
-	reset_cause = cause;
+	if (reset_cause == -1) {
+		reset_cause = readl(&src_regs->srsr);
+/* preserve the value for U-Boot proper */
+#if !defined(CONFIG_SPL_BUILD)
+		writel(reset_cause, &src_regs->srsr);
+#endif
+	}
+
+	return reset_cause;
+}
 
-	switch (cause) {
+#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
+static char *get_reset_cause(void)
+{
+	switch (get_imx_reset_cause()) {
 	case 0x00001:
 	case 0x00011:
 		return "POR";
@@ -77,11 +85,6 @@ static char *get_reset_cause(void)
 		return "unknown reset";
 	}
 }
-
-u32 get_imx_reset_cause(void)
-{
-	return reset_cause;
-}
 #endif
 
 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
-- 
2.20.1

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Abel Vesa]

The third version is here:
https://lists.denx.de/pipermail/u-boot/2019-January/356903.html

So, this time I hope I got it right. Before, I was stupidly trying
to put a fit in another fit without a really good reason. To my
excuse, that was working even with the spl_image->os set to 0,
bug which I (hope) I fixed in the first patch (a new one)
of this series.

Changes since v3:
 * Reduced the SPL size by disabling EXT_SUPPORT, otherwise the
   6qp-sabresd wouldn't boot due to having its dtb last in the fit.
   I forgot to mention in the last version that EFI and DOS SPL support
   also had to be disabled to get the size right.
 * Dropped the fit_spl.its file
 * Dropped the (now) unnecessary updates to the README files. We're
   sticking to the u-boot.img since it's exactly what is needed.
 * Fixed a bug related to FIT_IMAGE_TINY when CONFIG_SPL_OS_BOOT
   is enabled. The short story here is that spl_image->os was
   remaining set to 0. (see first patch in the series for details)


Abel Vesa (20):
  common: spl_fit: Fix the spl_fit_image_get_os for FIT_IMAGE_TINY
  usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGE
  usb: ehci-mx6: Make regulator DM_REGULATOR dependent
  configs: imx6sabreauto: Add DM_MMC support
  configs: imx6sabreauto: Add DM_USB support
  mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL builds
  board: mx6sabresd: Add board_fit_config_name_match to support FIT in
    SPL
  board: mx6sabreauto: Add board_fit_config_name_match to support FIT in
    SPL
  arm: dts: Add all the imx6[q|qp|dl] sabre[auto|sd] u-boot dts[i] files
  arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd]
  configs: mx6sabreauto: Add SPL FIT and DM support
  configs: mx6sabresd: Add SPL FIT and DM support
  mx6sabreauto: Add DM_GPIO support
  mx6sabresd: Add DM_GPIO support
  configs: mx6sabreauto: Add DM_SPI_FLASH necessary configs
  configs: mx6sabresd: Add DM_SPI_FLASH necessary configs
  board: mx6sabreauto: Remove the non-DM code
  board: mx6sabresd: Remove non-DM code
  board: mx6sabresd: Remove the enet reset gpio handling
  configs: mx6sabresd: Reduce SPL size by disabling DOS, EXT and EFI
    support

 arch/arm/dts/Makefile                       |   8 +-
 arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi   |   6 +
 arch/arm/dts/imx6dl-sabreauto.dts           |  13 +
 arch/arm/dts/imx6dl-sabresd-u-boot.dtsi     |   6 +
 arch/arm/dts/imx6dl-sabresd.dts             |  18 +
 arch/arm/dts/imx6dl.dtsi                    | 306 ++++++++++-
 arch/arm/dts/imx6q-sabreauto-u-boot.dtsi    |   6 +
 arch/arm/dts/imx6q-sabreauto.dts            |  18 +
 arch/arm/dts/imx6q-sabresd-u-boot.dtsi      |   6 +
 arch/arm/dts/imx6q-sabresd.dts              |  23 +
 arch/arm/dts/imx6q.dtsi                     | 310 +++++++++--
 arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi  |  21 +
 arch/arm/dts/imx6qdl-sabreauto.dtsi         | 810 ++++++++++++++++++++++++++++
 arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi    |  14 +
 arch/arm/dts/imx6qdl-sabresd.dtsi           | 741 +++++++++++++++++++++++++
 arch/arm/dts/imx6qdl-u-boot.dtsi            |   4 +-
 arch/arm/dts/imx6qdl.dtsi                   | 455 +++++++++-------
 arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi   |   6 +
 arch/arm/dts/imx6qp-sabreauto.dts           |  55 ++
 arch/arm/dts/imx6qp-sabresd-u-boot.dtsi     |   6 +
 arch/arm/dts/imx6qp-sabresd.dts             |  55 ++
 arch/arm/dts/imx6qp.dtsi                    | 115 ++++
 arch/arm/include/asm/arch-am33xx/spl.h      |   2 +-
 arch/arm/mach-omap2/boot-common.c           |   2 +-
 board/freescale/mx6sabreauto/mx6sabreauto.c |  91 +---
 board/freescale/mx6sabresd/mx6sabresd.c     |  78 +--
 common/Makefile                             |   5 +-
 common/spl/Kconfig                          |   4 +-
 common/spl/Makefile                         |   2 +-
 common/spl/spl_fit.c                        |   4 -
 common/spl/spl_usb.c                        |   4 -
 configs/am43xx_evm_usbhost_boot_defconfig   |   2 +-
 configs/am43xx_hs_evm_defconfig             |   2 +-
 configs/mx6sabreauto_defconfig              |  20 +-
 configs/mx6sabresd_defconfig                |  26 +-
 drivers/mmc/fsl_esdhc.c                     |   8 +-
 drivers/usb/host/ehci-mx6.c                 |   7 +-
 37 files changed, 2847 insertions(+), 412 deletions(-)
 create mode 100644 arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6dl-sabreauto.dts
 create mode 100644 arch/arm/dts/imx6dl-sabresd-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6dl-sabresd.dts
 create mode 100644 arch/arm/dts/imx6q-sabreauto-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6q-sabreauto.dts
 create mode 100644 arch/arm/dts/imx6q-sabresd-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6q-sabresd.dts
 create mode 100644 arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-sabreauto.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-sabresd.dtsi
 create mode 100644 arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6qp-sabreauto.dts
 create mode 100644 arch/arm/dts/imx6qp-sabresd-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6qp-sabresd.dts
 create mode 100644 arch/arm/dts/imx6qp.dtsi

-- 
2.7.4

[U-Boot] [PATCH v4 01/20] common: spl_fit: Fix the spl_fit_image_get_os for FIT_IMAGE_TINY

[Abel Vesa]

There is not really reducing codesize here since there is only
a call. The function is always built in if CONFIG_$(SPL_TPL_)FIT is set.
Plus, there was a change in behavior if CONFIG_SPL_OS_BOOT is defined.
If CONFIG_FIT_IMAGE_TINY is defined, the spl_fit_image_get_os was
returning -ENOTSUPP and then if CONFIG_SPL_OS_BOOT was also
defined, the spl_image->os was left set to 0 which in turn
was skipping the fdt appending resulting in boot-up failure.

Fixes: 337bbb6297775e spl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 common/spl/spl_fit.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index db43626..a87d02d 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -333,11 +333,7 @@ static int spl_fit_record_loadable(const void *fit, int images, int index,
 
 static int spl_fit_image_get_os(const void *fit, int noffset, uint8_t *os)
 {
-#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
-	return -ENOTSUPP;
-#else
 	return fit_image_get_os(fit, noffset, os);
-#endif
 }
 
 int spl_load_simple_fit(struct spl_image_info *spl_image,
-- 
2.7.4

[U-Boot] [PATCH v4 02/20] usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGE

[Abel Vesa]

Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in SPL,
makes more sense to rename the SPL_USB_SUPPORT as SPL_USB_STORAGE.
Everything that is not part of the usb storage support in SPL is now
build under SPL_USB_HOST_SUPPORT.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
 arch/arm/include/asm/arch-am33xx/spl.h    | 2 +-
 arch/arm/mach-omap2/boot-common.c         | 2 +-
 common/Makefile                           | 5 +++--
 common/spl/Kconfig                        | 4 ++--
 common/spl/Makefile                       | 2 +-
 common/spl/spl_usb.c                      | 4 ----
 configs/am43xx_evm_usbhost_boot_defconfig | 2 +-
 configs/am43xx_hs_evm_defconfig           | 2 +-
 8 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 0bf8c17..f3910c2 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -62,7 +62,7 @@
 #define BOOT_DEVICE_CPGMAC	0x47
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
-#ifdef CONFIG_SPL_USB_SUPPORT
+#ifdef CONFIG_SPL_USB_STORAGE
 #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_USB
 #else
 #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
index 2db1922..c8b8ac6 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -93,7 +93,7 @@ void save_omap_boot_params(void)
 			sys_boot_device = 1;
 			break;
 #endif
-#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_SUPPORT)
+#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_STORAGE)
 		case BOOT_DEVICE_USB:
 			sys_boot_device = 1;
 			break;
diff --git a/common/Makefile b/common/Makefile
index ad390d0..8c92feb 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -75,8 +75,9 @@ obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
 
 ifdef CONFIG_SPL_USB_HOST_SUPPORT
-obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o
-obj-$(CONFIG_USB_STORAGE) += usb_storage.o
+obj-y += usb.o
+obj-y += usb_hub.o
+obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o
 else
 obj-$(CONFIG_USB_MUSB_HOST) += usb.o
 endif
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 54b0dc3..8b0627e 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -766,9 +766,9 @@ config SPL_USB_HOST_SUPPORT
 	  device can be attached. This option enables the drivers in
 	  drivers/usb/host as part of an SPL build.
 
-config SPL_USB_SUPPORT
+config SPL_USB_STORAGE
 	bool "Support loading from USB"
-	depends on SPL_USB_HOST_SUPPORT
+	depends on SPL_USB_HOST_SUPPORT && !(BLK && !DM_USB)
 	help
 	  Enable support for USB devices in SPL. This allows use of USB
 	  devices such as hard drives and flash drivers for loading U-Boot.
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 6f8d759..a3980ce 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
 obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
 obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
 obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
-obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
+obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
 obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o
 obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o
 obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o
diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
index c8d8231..e29d579 100644
--- a/common/spl/spl_usb.c
+++ b/common/spl/spl_usb.c
@@ -15,9 +15,7 @@
 #include <usb.h>
 #include <fat.h>
 
-#ifdef CONFIG_USB_STORAGE
 static int usb_stor_curr_dev = -1; /* current device */
-#endif
 
 static int spl_usb_load_image(struct spl_image_info *spl_image,
 			      struct spl_boot_device *bootdev)
@@ -34,13 +32,11 @@ static int spl_usb_load_image(struct spl_image_info *spl_image,
 		return err;
 	}
 
-#ifdef CONFIG_USB_STORAGE
 	/* try to recognize storage devices immediately */
 	usb_stor_curr_dev = usb_stor_scan(1);
 	stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, usb_stor_curr_dev);
 	if (!stor_dev)
 		return -ENODEV;
-#endif
 
 	debug("boot mode - FAT\n");
 
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 5131f19..5bd919b 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -14,7 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_SUPPORT=y
+CONFIG_SPL_USB_STORAGE=y
 CONFIG_CMD_SPL=y
 CONFIG_CMD_SPL_NAND_OFS=0x00100000
 CONFIG_CMD_SPL_WRITE_SIZE=0x40000
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 99e4ccb..c01fda9 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -24,7 +24,7 @@ CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_NET_SUPPORT=y
 CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
 CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_SUPPORT=y
+CONFIG_SPL_USB_STORAGE=y
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_USB_ETHER=y
 # CONFIG_CMD_FLASH is not set
-- 
2.7.4

[U-Boot] [PATCH v4 03/20] usb: ehci-mx6: Make regulator DM_REGULATOR dependent

[Abel Vesa]

Do the regulator related work only if the build has the DM_REGULATOR.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/usb/host/ehci-mx6.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 1acf08d..9483947 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -404,6 +404,7 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
 	if (ret)
 		return ret;
 
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
 	if (priv->vbus_supply) {
 		ret = regulator_set_enable(priv->vbus_supply,
 					   (type == USB_INIT_DEVICE) ?
@@ -413,6 +414,7 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
 			return ret;
 		}
 	}
+#endif
 
 	if (type == USB_INIT_DEVICE)
 		return 0;
@@ -514,15 +516,17 @@ static int ehci_usb_probe(struct udevice *dev)
 	priv->portnr = dev->seq;
 	priv->init_type = type;
 
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
 	ret = device_get_supply_regulator(dev, "vbus-supply",
 					  &priv->vbus_supply);
 	if (ret)
 		debug("%s: No vbus supply\n", dev->name);
-
+#endif
 	ret = ehci_mx6_common_init(ehci, priv->portnr);
 	if (ret)
 		return ret;
 
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
 	if (priv->vbus_supply) {
 		ret = regulator_set_enable(priv->vbus_supply,
 					   (type == USB_INIT_DEVICE) ?
@@ -532,6 +536,7 @@ static int ehci_usb_probe(struct udevice *dev)
 			return ret;
 		}
 	}
+#endif
 
 	if (priv->init_type == USB_INIT_HOST) {
 		setbits_le32(&ehci->usbmode, CM_HOST);
-- 
2.7.4

[U-Boot] [PATCH v4 04/20] configs: imx6sabreauto: Add DM_MMC support

[Abel Vesa]

Add DM_MMC config to imx6sabreauto defconfig.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 configs/mx6sabreauto_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 40386c2..a3d63a2 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -44,6 +44,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_SF=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
-- 
2.7.4

[U-Boot] [PATCH v4 05/20] configs: imx6sabreauto: Add DM_USB support

[Abel Vesa]

Add the DM support for USB. For that, DM_REGULATOR is needed.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 configs/mx6sabreauto_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index a3d63a2..4bdcbb1 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -52,9 +52,11 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
+CONFIG_DM_REGULATOR=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
-- 
2.7.4

[U-Boot] [PATCH v4 06/20] mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL builds

[Abel Vesa]

Since the fsl_esdhc will also be used by SPL, make the
preprocessor switches more generic to allow any kind of build.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 drivers/mmc/fsl_esdhc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 21fa2ab..9e34557 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -804,7 +804,7 @@ static int esdhc_set_voltage(struct mmc *mmc)
 	case MMC_SIGNAL_VOLTAGE_330:
 		if (priv->vs18_enable)
 			return -EIO;
-#ifdef CONFIG_DM_REGULATOR
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
 		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
 			ret = regulator_set_value(priv->vqmmc_dev, 3300000);
 			if (ret) {
@@ -823,7 +823,7 @@ static int esdhc_set_voltage(struct mmc *mmc)
 
 		return -EAGAIN;
 	case MMC_SIGNAL_VOLTAGE_180:
-#ifdef CONFIG_DM_REGULATOR
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
 		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
 			ret = regulator_set_value(priv->vqmmc_dev, 1800000);
 			if (ret) {
@@ -1442,7 +1442,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
 	int node = dev_of_offset(dev);
 	struct esdhc_soc_data *data =
 		(struct esdhc_soc_data *)dev_get_driver_data(dev);
-#ifdef CONFIG_DM_REGULATOR
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
 	struct udevice *vqmmc_dev;
 #endif
 	fdt_addr_t addr;
@@ -1500,7 +1500,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
 
 	priv->vs18_enable = 0;
 
-#ifdef CONFIG_DM_REGULATOR
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
 	/*
 	 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
 	 * otherwise, emmc will work abnormally.
-- 
2.7.4

[U-Boot] [PATCH v4 07/20] board: mx6sabresd: Add board_fit_config_name_match to support FIT in SPL

[Abel Vesa]

This matches one of the following three boards (or fails):
 - imx6q-sabresd
 - imx6qp-sabresd
 - imx6dl-sabresd

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/mx6sabresd/mx6sabresd.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 0183ede..4688095 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -1062,3 +1062,21 @@ void board_init_f(ulong dummy)
 	board_init_r(NULL, 0);
 }
 #endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_mx6dq()) {
+		if (!strcmp(name, "imx6q-sabresd"))
+			return 0;
+	} else if (is_mx6dqp()) {
+		if (!strcmp(name, "imx6qp-sabresd"))
+			return 0;
+	} else if (is_mx6dl()) {
+		if (!strcmp(name, "imx6dl-sabresd"))
+			return 0;
+	}
+
+	return -1;
+}
+#endif
-- 
2.7.4

[U-Boot] [PATCH v4 08/20] board: mx6sabreauto: Add board_fit_config_name_match to support FIT in SPL

[Abel Vesa]

This matches one of the following three boards (or fails):
 - imx6q-sabreauto
 - imx6qp-sabreauto
 - imx6dl-sabreauto

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/mx6sabreauto/mx6sabreauto.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
index c1bef85..c8f1263 100644
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -1097,3 +1097,21 @@ void board_init_f(ulong dummy)
 	board_init_r(NULL, 0);
 }
 #endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_mx6dq()) {
+		if (!strcmp(name, "imx6q-sabreauto"))
+			return 0;
+	} else if (is_mx6dqp()) {
+		if (!strcmp(name, "imx6qp-sabreauto"))
+			return 0;
+	} else if (is_mx6dl()) {
+		if (!strcmp(name, "imx6dl-sabreauto"))
+			return 0;
+	}
+
+	return -1;
+}
+#endif
-- 
2.7.4

[U-Boot] [PATCH v4 09/20] arm: dts: Add all the imx6[q|qp|dl] sabre[auto|sd] u-boot dts[i] files

[Abel Vesa]

This allows us to keep the basic dts[i] files up-to-date with
the ones in kernel, but at the same time allowing the u-boot
to add its own properties to the existing nodes.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi  |  6 ++++++
 arch/arm/dts/imx6dl-sabresd-u-boot.dtsi    |  6 ++++++
 arch/arm/dts/imx6q-sabreauto-u-boot.dtsi   |  6 ++++++
 arch/arm/dts/imx6q-sabresd-u-boot.dtsi     |  6 ++++++
 arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi | 21 +++++++++++++++++++++
 arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi   | 14 ++++++++++++++
 arch/arm/dts/imx6qdl-u-boot.dtsi           |  4 ++--
 arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi  |  6 ++++++
 arch/arm/dts/imx6qp-sabresd-u-boot.dtsi    |  6 ++++++
 9 files changed, 73 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6dl-sabresd-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6q-sabreauto-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6q-sabresd-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx6qp-sabresd-u-boot.dtsi

diff --git a/arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi
new file mode 100644
index 0000000..d75fcc1
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 NXP
+ */
+
+#include "imx6qdl-sabreauto-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6dl-sabresd-u-boot.dtsi b/arch/arm/dts/imx6dl-sabresd-u-boot.dtsi
new file mode 100644
index 0000000..e4d7d28
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sabresd-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 NXP
+ */
+
+#include "imx6qdl-sabresd-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6q-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6q-sabreauto-u-boot.dtsi
new file mode 100644
index 0000000..d75fcc1
--- /dev/null
+++ b/arch/arm/dts/imx6q-sabreauto-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 NXP
+ */
+
+#include "imx6qdl-sabreauto-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6q-sabresd-u-boot.dtsi b/arch/arm/dts/imx6q-sabresd-u-boot.dtsi
new file mode 100644
index 0000000..e4d7d28
--- /dev/null
+++ b/arch/arm/dts/imx6q-sabresd-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 NXP
+ */
+
+#include "imx6qdl-sabresd-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi
new file mode 100644
index 0000000..ea90f40
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 NXP
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+/ {
+	aliases {
+		mmc0 = &usdhc3;
+	};
+};
+
+&usdhc3 {
+	no-1-8-v;
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi b/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi
new file mode 100644
index 0000000..45f02b1
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 NXP
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6qdl-u-boot.dtsi b/arch/arm/dts/imx6qdl-u-boot.dtsi
index dffc21b..45ae2fa 100644
--- a/arch/arm/dts/imx6qdl-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-u-boot.dtsi
@@ -7,11 +7,11 @@
 	soc {
 		u-boot,dm-spl;
 
-		aips-bus at 02000000 {
+		aips-bus at 2000000 {
 			u-boot,dm-spl;
 		};
 
-		aips-bus at 02100000 {
+		aips-bus at 2100000 {
 			u-boot,dm-spl;
 		};
 	};
diff --git a/arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi
new file mode 100644
index 0000000..d75fcc1
--- /dev/null
+++ b/arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 NXP
+ */
+
+#include "imx6qdl-sabreauto-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6qp-sabresd-u-boot.dtsi b/arch/arm/dts/imx6qp-sabresd-u-boot.dtsi
new file mode 100644
index 0000000..e4d7d28
--- /dev/null
+++ b/arch/arm/dts/imx6qp-sabresd-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 NXP
+ */
+
+#include "imx6qdl-sabresd-u-boot.dtsi"
-- 
2.7.4

[U-Boot] [PATCH v4 10/20] arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd]

[Abel Vesa]

Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the ones
from kernel v4.20 (commit 8fe28cb58bcb2).

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/dts/Makefile               |   8 +-
 arch/arm/dts/imx6dl-sabreauto.dts   |  13 +
 arch/arm/dts/imx6dl-sabresd.dts     |  18 +
 arch/arm/dts/imx6dl.dtsi            | 306 ++++++++++++--
 arch/arm/dts/imx6q-sabreauto.dts    |  18 +
 arch/arm/dts/imx6q-sabresd.dts      |  23 +
 arch/arm/dts/imx6q.dtsi             | 310 ++++++++++++--
 arch/arm/dts/imx6qdl-sabreauto.dtsi | 810 ++++++++++++++++++++++++++++++++++++
 arch/arm/dts/imx6qdl-sabresd.dtsi   | 741 +++++++++++++++++++++++++++++++++
 arch/arm/dts/imx6qdl.dtsi           | 455 +++++++++++---------
 arch/arm/dts/imx6qp-sabreauto.dts   |  55 +++
 arch/arm/dts/imx6qp-sabresd.dts     |  55 +++
 arch/arm/dts/imx6qp.dtsi            | 115 +++++
 13 files changed, 2669 insertions(+), 258 deletions(-)
 create mode 100644 arch/arm/dts/imx6dl-sabreauto.dts
 create mode 100644 arch/arm/dts/imx6dl-sabresd.dts
 create mode 100644 arch/arm/dts/imx6q-sabreauto.dts
 create mode 100644 arch/arm/dts/imx6q-sabresd.dts
 create mode 100644 arch/arm/dts/imx6qdl-sabreauto.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-sabresd.dtsi
 create mode 100644 arch/arm/dts/imx6qp-sabreauto.dts
 create mode 100644 arch/arm/dts/imx6qp-sabresd.dts
 create mode 100644 arch/arm/dts/imx6qp.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 46f1d69..e8512af 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -443,7 +443,13 @@ dtb-$(CONFIG_MX6QDL) += \
 	imx6q-icore.dtb \
 	imx6q-icore-mipi.dtb \
 	imx6q-icore-rqs.dtb \
-	imx6q-logicpd.dtb
+	imx6q-logicpd.dtb \
+	imx6q-sabreauto.dtb \
+	imx6q-sabresd.dtb \
+	imx6dl-sabreauto.dtb \
+	imx6dl-sabresd.dtb \
+	imx6qp-sabreauto.dtb \
+	imx6qp-sabresd.dtb
 
 dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
 
diff --git a/arch/arm/dts/imx6dl-sabreauto.dts b/arch/arm/dts/imx6dl-sabreauto.dts
new file mode 100644
index 0000000..660d52a
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sabreauto.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2013 Freescale Semiconductor, Inc.
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-sabreauto.dtsi"
+
+/ {
+	model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
+	compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
+};
diff --git a/arch/arm/dts/imx6dl-sabresd.dts b/arch/arm/dts/imx6dl-sabresd.dts
new file mode 100644
index 0000000..cd6bbf2
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sabresd.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2013 Freescale Semiconductor, Inc.
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-sabresd.dtsi"
+
+/ {
+	model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
+	compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
+};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+	clock-lanes = <0>;
+	data-lanes = <1 2>;
+};
diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
index 9a4c22c..f0607eb 100644
--- a/arch/arm/dts/imx6dl.dtsi
+++ b/arch/arm/dts/imx6dl.dtsi
@@ -1,12 +1,6 @@
-
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "imx6dl-pinfunc.h"
@@ -39,6 +33,7 @@
 				396000	1175000
 			>;
 			clock-latency = <61036>; /* two CLK32 periods */
+			#cooling-cells = <2>;
 			clocks = <&clks IMX6QDL_CLK_ARM>,
 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 				 <&clks IMX6QDL_CLK_STEP>,
@@ -56,39 +51,57 @@
 			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
+			operating-points = <
+				/* kHz    uV */
+				996000  1250000
+				792000  1175000
+				396000  1150000
+			>;
+			fsl,soc-operating-points = <
+				/* ARM kHz  SOC-PU uV */
+				996000	1175000
+				792000	1175000
+				396000	1175000
+			>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clks IMX6QDL_CLK_ARM>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+				 <&clks IMX6QDL_CLK_STEP>,
+				 <&clks IMX6QDL_CLK_PLL1_SW>,
+				 <&clks IMX6QDL_CLK_PLL1_SYS>;
+			clock-names = "arm", "pll2_pfd2_396m", "step",
+				      "pll1_sw", "pll1_sys";
+			arm-supply = <&reg_arm>;
+			pu-supply = <&reg_pu>;
+			soc-supply = <&reg_soc>;
 		};
 	};
 
 	soc {
-		ocram: sram at 00900000 {
+		ocram: sram at 900000 {
 			compatible = "mmio-sram";
 			reg = <0x00900000 0x20000>;
 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
 		};
 
-		aips1: aips-bus at 02000000 {
-			iomuxc: iomuxc at 020e0000 {
+		aips1: aips-bus at 2000000 {
+			iomuxc: iomuxc at 20e0000 {
 				compatible = "fsl,imx6dl-iomuxc";
 			};
 
-			pxp: pxp at 020f0000 {
+			pxp: pxp at 20f0000 {
 				reg = <0x020f0000 0x4000>;
 				interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			epdc: epdc at 020f4000 {
+			epdc: epdc at 20f4000 {
 				reg = <0x020f4000 0x4000>;
 				interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 			};
-
-			lcdif: lcdif at 020f8000 {
-				reg = <0x020f8000 0x4000>;
-				interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
-			};
 		};
 
-		aips2: aips-bus at 02100000 {
-			i2c4: i2c at 021f8000 {
+		aips2: aips-bus at 2100000 {
+			i2c4: i2c at 21f8000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
@@ -100,14 +113,177 @@
 		};
 	};
 
+	capture-subsystem {
+		compatible = "fsl,imx-capture-subsystem";
+		ports = <&ipu1_csi0>, <&ipu1_csi1>;
+	};
+
 	display-subsystem {
 		compatible = "fsl,imx-display-subsystem";
 		ports = <&ipu1_di0>, <&ipu1_di1>;
 	};
+};
+
+&gpio1 {
+	gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
+		      <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
+		      <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
+		      <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
+		      <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
+		      <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
+		      <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
+};
+
+&gpio2 {
+	gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
+		      <&iomuxc 17  73 1>, <&iomuxc 18  72 1>, <&iomuxc 19  71 1>,
+		      <&iomuxc 20  70 1>, <&iomuxc 21  69 1>, <&iomuxc 22  68 1>,
+		      <&iomuxc 23  79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
+		      <&iomuxc 28 113 4>;
+};
+
+&gpio3 {
+	gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
+		      <&iomuxc 16 81 16>;
+};
+
+&gpio4 {
+	gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7 150 1>,
+		      <&iomuxc  8 146 1>, <&iomuxc  9 151 1>, <&iomuxc 10 147 1>,
+		      <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
+		      <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16  39 7>,
+		      <&iomuxc 23  56 1>, <&iomuxc 24  61 7>, <&iomuxc 31  46 1>;
+};
 
-	gpu-subsystem {
-		compatible = "fsl,imx-gpu-subsystem";
-		cores = <&gpu_2d>, <&gpu_3d>;
+&gpio5 {
+	gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
+		      <&iomuxc  5  47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
+		      <&iomuxc 19  36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
+		      <&iomuxc 22  29 6>, <&iomuxc 28 19 4>;
+};
+
+&gpio6 {
+	gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
+		      <&iomuxc  8 155 1>, <&iomuxc  9 170 1>, <&iomuxc 10 169 1>,
+		      <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
+		      <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
+		      <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
+		      <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31  78 1>;
+};
+
+&gpio7 {
+	gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
+		      <&iomuxc 3 195 1>, <&iomuxc  4 197 4>, <&iomuxc  8 205 1>,
+		      <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
+};
+
+&gpr {
+	ipu1_csi0_mux {
+		compatible = "video-mux";
+		mux-controls = <&mux 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port at 0 {
+			reg = <0>;
+
+			ipu1_csi0_mux_from_mipi_vc0: endpoint {
+				remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+			};
+		};
+
+		port at 1 {
+			reg = <1>;
+
+			ipu1_csi0_mux_from_mipi_vc1: endpoint {
+				remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
+			};
+		};
+
+		port at 2 {
+			reg = <2>;
+
+			ipu1_csi0_mux_from_mipi_vc2: endpoint {
+				remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
+			};
+		};
+
+		port at 3 {
+			reg = <3>;
+
+			ipu1_csi0_mux_from_mipi_vc3: endpoint {
+				remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
+			};
+		};
+
+		port at 4 {
+			reg = <4>;
+
+			ipu1_csi0_mux_from_parallel_sensor: endpoint {
+			};
+		};
+
+		port at 5 {
+			reg = <5>;
+
+			ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+				remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+			};
+		};
+	};
+
+	ipu1_csi1_mux {
+		compatible = "video-mux";
+		mux-controls = <&mux 1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port at 0 {
+			reg = <0>;
+
+			ipu1_csi1_mux_from_mipi_vc0: endpoint {
+				remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
+			};
+		};
+
+		port at 1 {
+			reg = <1>;
+
+			ipu1_csi1_mux_from_mipi_vc1: endpoint {
+				remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
+			};
+		};
+
+		port at 2 {
+			reg = <2>;
+
+			ipu1_csi1_mux_from_mipi_vc2: endpoint {
+				remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
+			};
+		};
+
+		port at 3 {
+			reg = <3>;
+
+			ipu1_csi1_mux_from_mipi_vc3: endpoint {
+				remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
+			};
+		};
+
+		port at 4 {
+			reg = <4>;
+
+			ipu1_csi1_mux_from_parallel_sensor: endpoint {
+			};
+		};
+
+		port at 5 {
+			reg = <5>;
+
+			ipu1_csi1_mux_to_ipu1_csi1: endpoint {
+				remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
+			};
+		};
 	};
 };
 
@@ -119,6 +295,12 @@
 	compatible = "fsl,imx6dl-hdmi";
 };
 
+&ipu1_csi1 {
+	ipu1_csi1_from_ipu1_csi1_mux: endpoint {
+		remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
+	};
+};
+
 &ldb {
 	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -128,6 +310,82 @@
 		      "di0", "di1";
 };
 
+&mipi_csi {
+	port at 1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mipi_vc0_to_ipu1_csi0_mux: endpoint at 0 {
+			reg = <0>;
+			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+		};
+
+		mipi_vc0_to_ipu1_csi1_mux: endpoint at 1 {
+			reg = <1>;
+			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
+		};
+	};
+
+	port at 2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mipi_vc1_to_ipu1_csi0_mux: endpoint at 0 {
+			reg = <0>;
+			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
+		};
+
+		mipi_vc1_to_ipu1_csi1_mux: endpoint at 1 {
+			reg = <1>;
+			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
+		};
+	};
+
+	port at 3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mipi_vc2_to_ipu1_csi0_mux: endpoint at 0 {
+			reg = <0>;
+			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
+		};
+
+		mipi_vc2_to_ipu1_csi1_mux: endpoint at 1 {
+			reg = <1>;
+			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
+		};
+	};
+
+	port at 4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mipi_vc3_to_ipu1_csi0_mux: endpoint at 0 {
+			reg = <0>;
+			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
+		};
+
+		mipi_vc3_to_ipu1_csi1_mux: endpoint at 1 {
+			reg = <1>;
+			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
+		};
+	};
+};
+
+&mux {
+	mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
+			<0x34 0x00000038>, /* IPU_CSI1_MUX */
+			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
+			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
+			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
+			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
+			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
+};
+
 &vpu {
 	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
 };
diff --git a/arch/arm/dts/imx6q-sabreauto.dts b/arch/arm/dts/imx6q-sabreauto.dts
new file mode 100644
index 0000000..6e981a3
--- /dev/null
+++ b/arch/arm/dts/imx6q-sabreauto.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-sabreauto.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad SABRE Automotive Board";
+	compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+};
+
+&sata {
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6q-sabresd.dts b/arch/arm/dts/imx6q-sabresd.dts
new file mode 100644
index 0000000..eec9446
--- /dev/null
+++ b/arch/arm/dts/imx6q-sabresd.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-sabresd.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad SABRE Smart Device Board";
+	compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
+};
+
+&sata {
+	status = "okay";
+};
+
+&ipu1_csi1_from_mipi_vc1 {
+	clock-lanes = <0>;
+	data-lanes = <1 2>;
+};
diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
index c30c836..8381d24 100644
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@@ -1,12 +1,6 @@
-
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "imx6q-pinfunc.h"
@@ -44,6 +38,7 @@
 				396000	1175000
 			>;
 			clock-latency = <61036>; /* two CLK32 periods */
+			#cooling-cells = <2>;
 			clocks = <&clks IMX6QDL_CLK_ARM>,
 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 				 <&clks IMX6QDL_CLK_STEP>,
@@ -56,38 +51,119 @@
 			soc-supply = <&reg_soc>;
 		};
 
-		cpu at 1 {
+		cpu1: cpu at 1 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
+			operating-points = <
+				/* kHz    uV */
+				1200000 1275000
+				996000  1250000
+				852000  1250000
+				792000  1175000
+				396000  975000
+			>;
+			fsl,soc-operating-points = <
+				/* ARM kHz  SOC-PU uV */
+				1200000 1275000
+				996000	1250000
+				852000	1250000
+				792000	1175000
+				396000	1175000
+			>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clks IMX6QDL_CLK_ARM>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+				 <&clks IMX6QDL_CLK_STEP>,
+				 <&clks IMX6QDL_CLK_PLL1_SW>,
+				 <&clks IMX6QDL_CLK_PLL1_SYS>;
+			clock-names = "arm", "pll2_pfd2_396m", "step",
+				      "pll1_sw", "pll1_sys";
+			arm-supply = <&reg_arm>;
+			pu-supply = <&reg_pu>;
+			soc-supply = <&reg_soc>;
 		};
 
-		cpu at 2 {
+		cpu2: cpu at 2 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <2>;
 			next-level-cache = <&L2>;
+			operating-points = <
+				/* kHz    uV */
+				1200000 1275000
+				996000  1250000
+				852000  1250000
+				792000  1175000
+				396000  975000
+			>;
+			fsl,soc-operating-points = <
+				/* ARM kHz  SOC-PU uV */
+				1200000 1275000
+				996000	1250000
+				852000	1250000
+				792000	1175000
+				396000	1175000
+			>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clks IMX6QDL_CLK_ARM>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+				 <&clks IMX6QDL_CLK_STEP>,
+				 <&clks IMX6QDL_CLK_PLL1_SW>,
+				 <&clks IMX6QDL_CLK_PLL1_SYS>;
+			clock-names = "arm", "pll2_pfd2_396m", "step",
+				      "pll1_sw", "pll1_sys";
+			arm-supply = <&reg_arm>;
+			pu-supply = <&reg_pu>;
+			soc-supply = <&reg_soc>;
 		};
 
-		cpu at 3 {
+		cpu3: cpu at 3 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <3>;
 			next-level-cache = <&L2>;
+			operating-points = <
+				/* kHz    uV */
+				1200000 1275000
+				996000  1250000
+				852000  1250000
+				792000  1175000
+				396000  975000
+			>;
+			fsl,soc-operating-points = <
+				/* ARM kHz  SOC-PU uV */
+				1200000 1275000
+				996000	1250000
+				852000	1250000
+				792000	1175000
+				396000	1175000
+			>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clks IMX6QDL_CLK_ARM>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+				 <&clks IMX6QDL_CLK_STEP>,
+				 <&clks IMX6QDL_CLK_PLL1_SW>,
+				 <&clks IMX6QDL_CLK_PLL1_SYS>;
+			clock-names = "arm", "pll2_pfd2_396m", "step",
+				      "pll1_sw", "pll1_sys";
+			arm-supply = <&reg_arm>;
+			pu-supply = <&reg_pu>;
+			soc-supply = <&reg_soc>;
 		};
 	};
 
 	soc {
-		ocram: sram at 00900000 {
+		ocram: sram at 900000 {
 			compatible = "mmio-sram";
 			reg = <0x00900000 0x40000>;
 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
 		};
 
-		aips-bus at 02000000 { /* AIPS1 */
-			spba-bus at 02000000 {
-				ecspi5: ecspi at 02018000 {
+		aips-bus at 2000000 { /* AIPS1 */
+			spba-bus at 2000000 {
+				ecspi5: spi at 2018000 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -96,18 +172,18 @@
 					clocks = <&clks IMX6Q_CLK_ECSPI5>,
 						 <&clks IMX6Q_CLK_ECSPI5>;
 					clock-names = "ipg", "per";
-					dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
+					dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
 					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 			};
 
-			iomuxc: iomuxc at 020e0000 {
+			iomuxc: iomuxc at 20e0000 {
 				compatible = "fsl,imx6q-iomuxc";
 			};
 		};
 
-		sata: sata at 02200000 {
+		sata: sata at 2200000 {
 			compatible = "fsl,imx6q-ahci";
 			reg = <0x02200000 0x4000>;
 			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
@@ -118,17 +194,17 @@
 			status = "disabled";
 		};
 
-		gpu_vg: gpu at 02204000 {
+		gpu_vg: gpu at 2204000 {
 			compatible = "vivante,gc";
 			reg = <0x02204000 0x4000>;
 			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
 			clock-names = "bus", "core";
-			power-domains = <&gpc 1>;
+			power-domains = <&pd_pu>;
 		};
 
-		ipu2: ipu at 02800000 {
+		ipu2: ipu at 2800000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "fsl,imx6q-ipu";
@@ -143,10 +219,18 @@
 
 			ipu2_csi0: port at 0 {
 				reg = <0>;
+
+				ipu2_csi0_from_mipi_vc2: endpoint {
+					remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
+				};
 			};
 
 			ipu2_csi1: port at 1 {
 				reg = <1>;
+
+				ipu2_csi1_from_ipu2_csi1_mux: endpoint {
+					remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
+				};
 			};
 
 			ipu2_di0: port at 2 {
@@ -154,22 +238,27 @@
 				#size-cells = <0>;
 				reg = <2>;
 
-				ipu2_di0_disp0: disp0-endpoint {
+				ipu2_di0_disp0: endpoint at 0 {
+					reg = <0>;
 				};
 
-				ipu2_di0_hdmi: hdmi-endpoint {
+				ipu2_di0_hdmi: endpoint at 1 {
+					reg = <1>;
 					remote-endpoint = <&hdmi_mux_2>;
 				};
 
-				ipu2_di0_mipi: mipi-endpoint {
+				ipu2_di0_mipi: endpoint at 2 {
+					reg = <2>;
 					remote-endpoint = <&mipi_mux_2>;
 				};
 
-				ipu2_di0_lvds0: lvds0-endpoint {
+				ipu2_di0_lvds0: endpoint at 3 {
+					reg = <3>;
 					remote-endpoint = <&lvds0_mux_2>;
 				};
 
-				ipu2_di0_lvds1: lvds1-endpoint {
+				ipu2_di0_lvds1: endpoint at 4 {
+					reg = <4>;
 					remote-endpoint = <&lvds1_mux_2>;
 				};
 			};
@@ -179,33 +268,136 @@
 				#size-cells = <0>;
 				reg = <3>;
 
-				ipu2_di1_hdmi: hdmi-endpoint {
+				ipu2_di1_hdmi: endpoint at 1 {
+					reg = <1>;
 					remote-endpoint = <&hdmi_mux_3>;
 				};
 
-				ipu2_di1_mipi: mipi-endpoint {
+				ipu2_di1_mipi: endpoint at 2 {
+					reg = <2>;
 					remote-endpoint = <&mipi_mux_3>;
 				};
 
-				ipu2_di1_lvds0: lvds0-endpoint {
+				ipu2_di1_lvds0: endpoint at 3 {
+					reg = <3>;
 					remote-endpoint = <&lvds0_mux_3>;
 				};
 
-				ipu2_di1_lvds1: lvds1-endpoint {
+				ipu2_di1_lvds1: endpoint at 4 {
+					reg = <4>;
 					remote-endpoint = <&lvds1_mux_3>;
 				};
 			};
 		};
 	};
 
+	capture-subsystem {
+		compatible = "fsl,imx-capture-subsystem";
+		ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
+	};
+
 	display-subsystem {
 		compatible = "fsl,imx-display-subsystem";
 		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 	};
+};
+
+&gpio1 {
+	gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
+		      <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
+		      <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
+		      <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
+		      <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
+		      <&iomuxc 22 116 10>;
+};
+
+&gpio2 {
+	gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
+		      <&iomuxc 31  44  1>;
+};
+
+&gpio3 {
+	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
+};
+
+&gpio4 {
+	gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
+};
+
+&gpio5 {
+	gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
+		      <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
+};
+
+&gpio6 {
+	gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
+		      <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
+		      <&iomuxc 31  86 1>;
+};
+
+&gpio7 {
+	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
+};
+
+&gpr {
+	ipu1_csi0_mux {
+		compatible = "video-mux";
+		mux-controls = <&mux 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port at 0 {
+			reg = <0>;
+
+			ipu1_csi0_mux_from_mipi_vc0: endpoint {
+				remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+			};
+		};
+
+		port at 1 {
+			reg = <1>;
+
+			ipu1_csi0_mux_from_parallel_sensor: endpoint {
+			};
+		};
 
-	gpu-subsystem {
-		compatible = "fsl,imx-gpu-subsystem";
-		cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
+		port at 2 {
+			reg = <2>;
+
+			ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+				remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+			};
+		};
+	};
+
+	ipu2_csi1_mux {
+		compatible = "video-mux";
+		mux-controls = <&mux 1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port at 0 {
+			reg = <0>;
+
+			ipu2_csi1_mux_from_mipi_vc3: endpoint {
+				remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
+			};
+		};
+
+		port at 1 {
+			reg = <1>;
+
+			ipu2_csi1_mux_from_parallel_sensor: endpoint {
+			};
+		};
+
+		port at 2 {
+			reg = <2>;
+
+			ipu2_csi1_mux_to_ipu2_csi1: endpoint {
+				remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
+			};
+		};
 	};
 };
 
@@ -229,6 +421,12 @@
 	};
 };
 
+&ipu1_csi1 {
+	ipu1_csi1_from_mipi_vc1: endpoint {
+		remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
+	};
+};
+
 &ldb {
 	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -275,6 +473,40 @@
 	};
 };
 
+&mipi_csi {
+	port at 1 {
+		reg = <1>;
+
+		mipi_vc0_to_ipu1_csi0_mux: endpoint {
+			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+		};
+	};
+
+	port at 2 {
+		reg = <2>;
+
+		mipi_vc1_to_ipu1_csi1: endpoint {
+			remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
+		};
+	};
+
+	port at 3 {
+		reg = <3>;
+
+		mipi_vc2_to_ipu2_csi0: endpoint {
+			remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
+		};
+	};
+
+	port at 4 {
+		reg = <4>;
+
+		mipi_vc3_to_ipu2_csi1_mux: endpoint {
+			remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
+		};
+	};
+};
+
 &mipi_dsi {
 	ports {
 		port at 2 {
@@ -295,6 +527,16 @@
 	};
 };
 
+&mux {
+	mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
+			<0x04 0x00100000>, /* MIPI_IPU2_MUX */
+			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
+			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
+			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
+			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
+			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
+};
+
 &vpu {
 	compatible = "fsl,imx6q-vpu", "cnm,coda960";
 };
diff --git a/arch/arm/dts/imx6qdl-sabreauto.dtsi b/arch/arm/dts/imx6qdl-sabreauto.dtsi
new file mode 100644
index 0000000..a6dc5c4
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-sabreauto.dtsi
@@ -0,0 +1,810 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	chosen {
+		stdout-path = &uart4;
+	};
+
+	memory at 10000000 {
+		reg = <0x10000000 0x80000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		user {
+			label = "debug";
+			gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+
+		home {
+			label = "Home";
+			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_HOME>;
+			wakeup-source;
+		};
+
+		back {
+			label = "Back";
+			gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_BACK>;
+			wakeup-source;
+		};
+
+		program {
+			label = "Program";
+			gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_PROGRAM>;
+			wakeup-source;
+		};
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+			wakeup-source;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEDOWN>;
+			wakeup-source;
+		};
+	};
+
+	clocks {
+		codec_osc: anaclk2 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <24576000>;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_audio: regulator at 0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "cs42888_supply";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		reg_usb_h1_vbus: regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_h1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg_vbus: regulator at 2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "usb_otg_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+
+	sound-cs42888 {
+		compatible = "fsl,imx6-sabreauto-cs42888",
+			"fsl,imx-audio-cs42888";
+		model = "imx-cs42888";
+		audio-cpu = <&esai>;
+		audio-asrc = <&asrc>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"Line Out Jack", "AOUT1L",
+			"Line Out Jack", "AOUT1R",
+			"Line Out Jack", "AOUT2L",
+			"Line Out Jack", "AOUT2R",
+			"Line Out Jack", "AOUT3L",
+			"Line Out Jack", "AOUT3R",
+			"Line Out Jack", "AOUT4L",
+			"Line Out Jack", "AOUT4R",
+			"AIN1L", "Line In Jack",
+			"AIN1R", "Line In Jack",
+			"AIN2L", "Line In Jack",
+			"AIN2R", "Line In Jack";
+	};
+
+	sound-spdif {
+		compatible = "fsl,imx-audio-spdif",
+			   "fsl,imx-sabreauto-spdif";
+		model = "imx-spdif";
+		spdif-controller = <&spdif>;
+		spdif-in;
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm3 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+		status = "okay";
+	};
+
+	i2cmux {
+		compatible = "i2c-mux-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c3mux>;
+		mux-gpios = <&gpio5 4 0>;
+		i2c-parent = <&i2c3>;
+		idle-state = <0>;
+
+		i2c at 1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			adv7180: camera at 21 {
+				compatible = "adi,adv7180";
+				reg = <0x21>;
+				powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
+				interrupt-parent = <&gpio1>;
+				interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+
+				port {
+					adv7180_to_ipu1_csi0_mux: endpoint {
+						remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+						bus-width = <8>;
+					};
+				};
+			};
+
+			max7310_a: gpio at 30 {
+				compatible = "maxim,max7310";
+				reg = <0x30>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			max7310_b: gpio at 32 {
+				compatible = "maxim,max7310";
+				reg = <0x32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_max7310>;
+				reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+			};
+
+			max7310_c: gpio at 34 {
+				compatible = "maxim,max7310";
+				reg = <0x34>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			light-sensor at 44 {
+				compatible = "isil,isl29023";
+				reg = <0x44>;
+				interrupt-parent = <&gpio5>;
+				interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
+			};
+
+			magnetometer at e {
+				compatible = "fsl,mag3110";
+				reg = <0x0e>;
+				interrupt-parent = <&gpio2>;
+				interrupts = <29 IRQ_TYPE_EDGE_RISING>;
+			};
+
+			accelerometer at 1c {
+				compatible = "fsl,mma8451";
+				reg = <0x1c>;
+				interrupt-parent = <&gpio6>;
+				interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+			};
+		};
+	};
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+	bus-width = <8>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+	remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
+	bus-width = <8>;
+};
+
+&ipu1_csi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
+			  <&clks IMX6QDL_PLL4_BYPASS>,
+			  <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+			  <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
+				 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
+				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+	assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
+};
+
+&ecspi1 {
+	cs-gpios = <&gpio3 19 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+	status = "disabled"; /* pin conflict with WEIM NOR */
+
+	flash: m25p80 at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&esai {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esai>;
+	assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
+			  <&clks IMX6QDL_CLK_ESAI_EXTAL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <0>, <24576000>;
+	status = "okay";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+	fsl,err006687-workaround-present;
+	status = "okay";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	status = "okay";
+};
+
+&hdmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi_cec>;
+	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	pmic: pfuze100 at 8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	codec: cs42888 at 48 {
+		compatible = "cirrus,cs42888";
+		reg = <0x48>;
+		clocks = <&codec_osc>;
+		clock-names = "mclk";
+		VA-supply = <&reg_audio>;
+		VD-supply = <&reg_audio>;
+		VLS-supply = <&reg_audio>;
+		VLC-supply = <&reg_audio>;
+	};
+
+	touchscreen at 4 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_egalax_int>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+		wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx6qdl-sabreauto {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
+				MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
+			>;
+		};
+
+		pinctrl_ecspi1: ecspi1grp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
+				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
+				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
+			>;
+		};
+
+		pinctrl_ecspi1_cs: ecspi1cs {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
+			>;
+		};
+
+		pinctrl_egalax_int: egalax-intgrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_EB0__GPIO2_IO28		0xb0b1
+			>;
+		};
+
+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0
+				MX6QDL_PAD_KEY_COL2__ENET_MDC		0x1b0b0
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
+				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
+			>;
+		};
+
+		pinctrl_esai: esaigrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
+				MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
+				MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
+				MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
+				MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
+				MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
+				MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
+				MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
+				MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
+				MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
+			>;
+		};
+
+		pinctrl_gpio_keys: gpiokeysgrp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__GPIO1_IO11		0x1b0b0
+				MX6QDL_PAD_SD2_DAT3__GPIO1_IO12		0x1b0b0
+				MX6QDL_PAD_SD4_DAT4__GPIO2_IO12		0x1b0b0
+				MX6QDL_PAD_SD4_DAT7__GPIO2_IO15		0x1b0b0
+				MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x1b0b0
+			>;
+		};
+
+		pinctrl_gpio_leds: gpioledsgrp {
+			fsl,pins = <
+				MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15	0x80000000
+			>;
+		};
+
+		pinctrl_gpmi_nand: gpminandgrp {
+			fsl,pins = <
+				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
+				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
+				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
+				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
+				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
+				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
+				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
+				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
+				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
+				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
+				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
+				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
+				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
+				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
+				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
+				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
+				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
+			>;
+		};
+
+		pinctrl_hdmi_cec: hdmicecgrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE	0x1f8b0
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_EB2__I2C2_SCL	0x4001b8b1
+				MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
+				MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c3mux: i2c3muxgrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
+			>;
+		};
+
+		pinctrl_ipu1_csi0: ipu1csi0grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x1b0b0
+				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x1b0b0
+				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x1b0b0
+				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x1b0b0
+				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x1b0b0
+				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x1b0b0
+				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x1b0b0
+				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x1b0b0
+				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x1b0b0
+				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x1b0b0
+			>;
+		};
+
+		pinctrl_max7310: max7310grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
+			>;
+		};
+
+		pinctrl_pwm3: pwm1grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_gpt_input_capture0: gptinputcapture0grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1	0x1b0b0
+			>;
+		};
+
+		pinctrl_gpt_input_capture1: gptinputcapture1grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2	0x1b0b0
+			>;
+		};
+
+		pinctrl_spdif: spdifgrp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
+			>;
+		};
+
+		pinctrl_uart4: uart4grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
+				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
+			>;
+		};
+
+		pinctrl_usbotg: usbotggrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170b9
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170b9
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170b9
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170b9
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170f9
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170f9
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170f9
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170f9
+			>;
+		};
+
+		pinctrl_weim_cs0: weimcs0grp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_CS0__EIM_CS0_B		0xb0b1
+			>;
+		};
+
+		pinctrl_weim_nor: weimnorgrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0b1
+				MX6QDL_PAD_EIM_RW__EIM_RW		0xb0b1
+				MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B		0xb060
+				MX6QDL_PAD_EIM_D16__EIM_DATA16		0x1b0b0
+				MX6QDL_PAD_EIM_D17__EIM_DATA17		0x1b0b0
+				MX6QDL_PAD_EIM_D18__EIM_DATA18		0x1b0b0
+				MX6QDL_PAD_EIM_D19__EIM_DATA19		0x1b0b0
+				MX6QDL_PAD_EIM_D20__EIM_DATA20		0x1b0b0
+				MX6QDL_PAD_EIM_D21__EIM_DATA21		0x1b0b0
+				MX6QDL_PAD_EIM_D22__EIM_DATA22		0x1b0b0
+				MX6QDL_PAD_EIM_D23__EIM_DATA23		0x1b0b0
+				MX6QDL_PAD_EIM_D24__EIM_DATA24		0x1b0b0
+				MX6QDL_PAD_EIM_D25__EIM_DATA25		0x1b0b0
+				MX6QDL_PAD_EIM_D26__EIM_DATA26		0x1b0b0
+				MX6QDL_PAD_EIM_D27__EIM_DATA27		0x1b0b0
+				MX6QDL_PAD_EIM_D28__EIM_DATA28		0x1b0b0
+				MX6QDL_PAD_EIM_D29__EIM_DATA29		0x1b0b0
+				MX6QDL_PAD_EIM_D30__EIM_DATA30		0x1b0b0
+				MX6QDL_PAD_EIM_D31__EIM_DATA31		0x1b0b0
+				MX6QDL_PAD_EIM_A23__EIM_ADDR23		0xb0b1
+				MX6QDL_PAD_EIM_A22__EIM_ADDR22		0xb0b1
+				MX6QDL_PAD_EIM_A21__EIM_ADDR21		0xb0b1
+				MX6QDL_PAD_EIM_A20__EIM_ADDR20		0xb0b1
+				MX6QDL_PAD_EIM_A19__EIM_ADDR19		0xb0b1
+				MX6QDL_PAD_EIM_A18__EIM_ADDR18		0xb0b1
+				MX6QDL_PAD_EIM_A17__EIM_ADDR17		0xb0b1
+				MX6QDL_PAD_EIM_A16__EIM_ADDR16		0xb0b1
+				MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0b1
+				MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0b1
+				MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0b1
+				MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0b1
+				MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0b1
+				MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0b1
+				MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0b1
+				MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0b1
+				MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0b1
+				MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0b1
+				MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0b1
+				MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0b1
+				MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0b1
+				MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0b1
+				MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0b1
+				MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
+			>;
+		};
+	};
+};
+
+&ldb {
+	status = "okay";
+
+	lvds-channel at 0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				vactive = <768>;
+				hback-porch = <220>;
+				hfront-porch = <40>;
+				vback-porch = <21>;
+				vfront-porch = <7>;
+				hsync-len = <60>;
+				vsync-len = <10>;
+			};
+		};
+	};
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>;
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_usb_h1_vbus>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&weim {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
+	ranges = <0 0 0x08000000 0x08000000>;
+	status = "disabled"; /* pin conflict with SPI NOR */
+
+	nor at 0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x02000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+				0x0000c000 0x1404a38e 0x00000000>;
+	};
+};
diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi
new file mode 100644
index 0000000..2cd5a9f
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-sabresd.dtsi
@@ -0,0 +1,741 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	aliases {
+		mmc1 = &usdhc3;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory at 10000000 {
+		reg = <0x10000000 0x40000000>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg_vbus: regulator at 0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 22 0>;
+			enable-active-high;
+			vin-supply = <&swbst_reg>;
+		};
+
+		reg_usb_h1_vbus: regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_h1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 29 0>;
+			enable-active-high;
+			vin-supply = <&swbst_reg>;
+		};
+
+		reg_audio: regulator at 2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "wm8962-supply";
+			gpio = <&gpio4 10 0>;
+			enable-active-high;
+		};
+
+		reg_pcie: regulator at 3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_pcie_reg>;
+			regulator-name = "MPCIE_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio3 19 0>;
+			enable-active-high;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+
+		power {
+			label = "Power Button";
+			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+			linux,code = <KEY_POWER>;
+		};
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+			linux,code = <KEY_VOLUMEUP>;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+
+	sound {
+		compatible = "fsl,imx6q-sabresd-wm8962",
+			   "fsl,imx-audio-wm8962";
+		model = "wm8962-audio";
+		ssi-controller = <&ssi2>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"Ext Spk", "SPKOUTL",
+			"Ext Spk", "SPKOUTR",
+			"AMIC", "MICBIAS",
+			"IN3R", "AMIC";
+		mux-int-port = <2>;
+		mux-ext-port = <3>;
+	};
+
+	backlight_lvds: backlight-lvds {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+		status = "okay";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		red {
+			gpios = <&gpio1 2 0>;
+			default-state = "on";
+		};
+	};
+
+	panel {
+		compatible = "hannstar,hsd100pxn1";
+		backlight = <&backlight_lvds>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+	bus-width = <8>;
+	data-shift = <12>; /* Lines 19:12 used */
+	hsync-active = <1>;
+	vsync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+	remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
+&mipi_csi {
+	status = "okay";
+
+	port at 0 {
+		reg = <0>;
+
+		mipi_csi2_in: endpoint {
+			remote-endpoint = <&ov5640_to_mipi_csi2>;
+			clock-lanes = <0>;
+			data-lanes = <1 2>;
+		};
+	};
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux>;
+	status = "okay";
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&ecspi1 {
+	cs-gpios = <&gpio4 9 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "okay";
+
+	flash: m25p80 at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&hdmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi_cec>;
+	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	codec: wm8962 at 1a {
+		compatible = "wlf,wm8962";
+		reg = <0x1a>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
+		DCVDD-supply = <&reg_audio>;
+		DBVDD-supply = <&reg_audio>;
+		AVDD-supply = <&reg_audio>;
+		CPVDD-supply = <&reg_audio>;
+		MICVDD-supply = <&reg_audio>;
+		PLLVDD-supply = <&reg_audio>;
+		SPKVDD1-supply = <&reg_audio>;
+		SPKVDD2-supply = <&reg_audio>;
+		gpio-cfg = <
+			0x0000 /* 0:Default */
+			0x0000 /* 1:Default */
+			0x0013 /* 2:FN_DMICCLK */
+			0x0000 /* 3:Default */
+			0x8014 /* 4:FN_DMICCDAT */
+			0x0000 /* 5:Default */
+		>;
+	};
+
+	ov5642: camera at 3c {
+		compatible = "ovti,ov5642";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ov5642>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
+		clock-names = "xclk";
+		reg = <0x3c>;
+		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
+						rev B board is VGEN5 */
+		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
+		powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+		status = "disabled";
+
+		port {
+			ov5642_to_ipu1_csi0_mux: endpoint {
+				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+				bus-width = <8>;
+				hsync-active = <1>;
+				vsync-active = <1>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	ov5640: camera at 3c {
+		compatible = "ovti,ov5640";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ov5640>;
+		reg = <0x3c>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
+		clock-names = "xclk";
+		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
+						rev B board is VGEN5 */
+		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
+		powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+
+		port {
+			ov5640_to_mipi_csi2: endpoint {
+				remote-endpoint = <&mipi_csi2_in>;
+				clock-lanes = <0>;
+				data-lanes = <1 2>;
+			};
+		};
+	};
+
+	pmic: pfuze100 at 8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	egalax_ts at 4 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <7 2>;
+		wakeup-gpios = <&gpio6 7 0>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx6qdl-sabresd {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+				MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+				MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+				MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
+				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
+				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
+				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
+			>;
+		};
+
+		pinctrl_audmux: audmuxgrp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
+				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
+				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
+				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
+			>;
+		};
+
+		pinctrl_ecspi1: ecspi1grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
+				MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
+				MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
+				MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
+			>;
+		};
+
+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
+				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
+			>;
+		};
+
+		pinctrl_gpio_keys: gpio_keysgrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+				MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
+				MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
+			>;
+		};
+
+		pinctrl_hdmi_cec: hdmicecgrp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	0x1f8b0
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
+				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
+				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
+				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_ipu1_csi0: ipu1csi0grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
+				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
+				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
+				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
+			>;
+		};
+
+		pinctrl_ov5640: ov5640grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
+				MX6QDL_PAD_SD1_CLK__GPIO1_IO20  0x1b0b0
+			>;
+		};
+
+		pinctrl_ov5642: ov5642grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
+				MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
+			>;
+		};
+
+		pinctrl_pcie: pciegrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b0
+			>;
+		};
+
+		pinctrl_pcie_reg: pciereggrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x1b0b0
+			>;
+		};
+
+		pinctrl_pwm1: pwm1grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+			>;
+		};
+
+		pinctrl_usbotg: usbotggrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
+				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
+				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
+				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_usdhc4: usdhc4grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
+				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
+				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
+				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
+				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
+				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
+				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
+				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
+				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
+				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_1__WDOG2_B		0x1b0b0
+			>;
+		};
+	};
+
+	gpio_leds {
+		pinctrl_gpio_leds: gpioledsgrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+			>;
+		};
+	};
+};
+
+&ldb {
+	status = "okay";
+
+	lvds-channel at 1 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		status = "okay";
+
+		port at 4 {
+			reg = <4>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
+	vpcie-supply = <&reg_pcie>;
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&reg_arm {
+       vin-supply = <&sw1a_reg>;
+};
+
+&reg_pu {
+       vin-supply = <&sw1c_reg>;
+};
+
+&reg_soc {
+       vin-supply = <&sw1c_reg>;
+};
+
+&snvs_poweroff {
+	status = "okay";
+};
+
+&ssi2 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_usb_h1_vbus>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <8>;
+	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <8>;
+	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <8>;
+	non-removable;
+	no-1-8-v;
+	status = "okay";
+};
+
+&wdog1 {
+	status = "disabled";
+};
+
+&wdog2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index b13b0b2..e4daf15 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -1,21 +1,23 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2011 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
 
 #include <dt-bindings/clock/imx6qdl-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-#include "skeleton.dtsi"
-
 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	/*
+	 * The decompressor and also some bootloaders rely on a
+	 * pre-existing /chosen node to be available to insert the
+	 * command line and merge other ATAGS info.
+	 * Also for U-Boot there must be a pre-existing /memory node.
+	 */
+	chosen {};
+	memory { device_type = "memory"; };
+
 	aliases {
 		ethernet0 = &fec;
 		can0 = &can1;
@@ -49,9 +51,6 @@
 	};
 
 	clocks {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
 		ckil {
 			compatible = "fsl,imx-ckil", "fixed-clock";
 			#clock-cells = <0>;
@@ -71,6 +70,75 @@
 		};
 	};
 
+	tempmon: tempmon {
+		compatible = "fsl,imx6q-tempmon";
+		interrupt-parent = <&gpc>;
+		interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,tempmon = <&anatop>;
+		fsl,tempmon-data = <&ocotp>;
+		clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+	};
+
+	ldb: ldb {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
+		gpr = <&gpr>;
+		status = "disabled";
+
+		lvds-channel at 0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			status = "disabled";
+
+			port at 0 {
+				reg = <0>;
+
+				lvds0_mux_0: endpoint {
+					remote-endpoint = <&ipu1_di0_lvds0>;
+				};
+			};
+
+			port at 1 {
+				reg = <1>;
+
+				lvds0_mux_1: endpoint {
+					remote-endpoint = <&ipu1_di1_lvds0>;
+				};
+			};
+		};
+
+		lvds-channel at 1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			status = "disabled";
+
+			port at 0 {
+				reg = <0>;
+
+				lvds1_mux_0: endpoint {
+					remote-endpoint = <&ipu1_di0_lvds1>;
+				};
+			};
+
+			port at 1 {
+				reg = <1>;
+
+				lvds1_mux_1: endpoint {
+					remote-endpoint = <&ipu1_di1_lvds1>;
+				};
+			};
+		};
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupt-parent = <&gpc>;
+		interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -78,7 +146,7 @@
 		interrupt-parent = <&gpc>;
 		ranges;
 
-		dma_apbh: dma-apbh at 00110000 {
+		dma_apbh: dma-apbh at 110000 {
 			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 			reg = <0x00110000 0x2000>;
 			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
@@ -91,7 +159,7 @@
 			clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
 		};
 
-		gpmi: gpmi-nand at 00112000 {
+		gpmi: gpmi-nand at 112000 {
 			compatible = "fsl,imx6q-gpmi-nand";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -111,7 +179,7 @@
 			status = "disabled";
 		};
 
-		hdmi: hdmi at 0120000 {
+		hdmi: hdmi at 120000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x00120000 0x9000>;
@@ -139,7 +207,7 @@
 			};
 		};
 
-		gpu_3d: gpu at 00130000 {
+		gpu_3d: gpu at 130000 {
 			compatible = "vivante,gc";
 			reg = <0x00130000 0x4000>;
 			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
@@ -147,20 +215,20 @@
 				 <&clks IMX6QDL_CLK_GPU3D_CORE>,
 				 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
 			clock-names = "bus", "core", "shader";
-			power-domains = <&gpc 1>;
+			power-domains = <&pd_pu>;
 		};
 
-		gpu_2d: gpu at 00134000 {
+		gpu_2d: gpu at 134000 {
 			compatible = "vivante,gc";
 			reg = <0x00134000 0x4000>;
 			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
 				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
 			clock-names = "bus", "core";
-			power-domains = <&gpc 1>;
+			power-domains = <&pd_pu>;
 		};
 
-		timer at 00a00600 {
+		timer at a00600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0x00a00600 0x20>;
 			interrupts = <1 13 0xf01>;
@@ -168,7 +236,7 @@
 			clocks = <&clks IMX6QDL_CLK_TWD>;
 		};
 
-		intc: interrupt-controller at 00a01000 {
+		intc: interrupt-controller at a01000 {
 			compatible = "arm,cortex-a9-gic";
 			#interrupt-cells = <3>;
 			interrupt-controller;
@@ -177,7 +245,7 @@
 			interrupt-parent = <&intc>;
 		};
 
-		L2: l2-cache at 00a02000 {
+		L2: l2-cache at a02000 {
 			compatible = "arm,pl310-cache";
 			reg = <0x00a02000 0x1000>;
 			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -188,7 +256,7 @@
 			arm,shared-override;
 		};
 
-		pcie: pcie at 0x01000000 {
+		pcie: pcie at 1ffc000 {
 			compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 			reg = <0x01ffc000 0x04000>,
 			      <0x01f00000 0x80000>;
@@ -196,6 +264,7 @@
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
+			bus-range = <0x00 0xff>;
 			ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 				  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 			num-lanes = <1>;
@@ -204,9 +273,9 @@
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-			                <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
-			                <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-			                <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+					<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
 				 <&clks IMX6QDL_CLK_LVDS1_GATE>,
 				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
@@ -214,26 +283,21 @@
 			status = "disabled";
 		};
 
-		pmu {
-			compatible = "arm,cortex-a9-pmu";
-			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		aips-bus at 02000000 { /* AIPS1 */
+		aips-bus at 2000000 { /* AIPS1 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			reg = <0x02000000 0x100000>;
 			ranges;
 
-			spba-bus at 02000000 {
+			spba-bus at 2000000 {
 				compatible = "fsl,spba-bus", "simple-bus";
 				#address-cells = <1>;
 				#size-cells = <1>;
 				reg = <0x02000000 0x40000>;
 				ranges;
 
-				spdif: spdif at 02004000 {
+				spdif: spdif at 2004000 {
 					compatible = "fsl,imx35-spdif";
 					reg = <0x02004000 0x4000>;
 					interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
@@ -253,7 +317,7 @@
 					status = "disabled";
 				};
 
-				ecspi1: ecspi at 02008000 {
+				ecspi1: spi at 2008000 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -267,7 +331,7 @@
 					status = "disabled";
 				};
 
-				ecspi2: ecspi at 0200c000 {
+				ecspi2: spi at 200c000 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -281,7 +345,7 @@
 					status = "disabled";
 				};
 
-				ecspi3: ecspi at 02010000 {
+				ecspi3: spi at 2010000 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -295,7 +359,7 @@
 					status = "disabled";
 				};
 
-				ecspi4: ecspi at 02014000 {
+				ecspi4: spi at 2014000 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -309,7 +373,7 @@
 					status = "disabled";
 				};
 
-				uart1: serial at 02020000 {
+				uart1: serial at 2020000 {
 					compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 					reg = <0x02020000 0x4000>;
 					interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -321,7 +385,7 @@
 					status = "disabled";
 				};
 
-				esai: esai at 02024000 {
+				esai: esai at 2024000 {
 					#sound-dai-cells = <0>;
 					compatible = "fsl,imx35-esai";
 					reg = <0x02024000 0x4000>;
@@ -337,7 +401,7 @@
 					status = "disabled";
 				};
 
-				ssi1: ssi at 02028000 {
+				ssi1: ssi at 2028000 {
 					#sound-dai-cells = <0>;
 					compatible = "fsl,imx6q-ssi",
 							"fsl,imx51-ssi";
@@ -353,7 +417,7 @@
 					status = "disabled";
 				};
 
-				ssi2: ssi at 0202c000 {
+				ssi2: ssi at 202c000 {
 					#sound-dai-cells = <0>;
 					compatible = "fsl,imx6q-ssi",
 							"fsl,imx51-ssi";
@@ -369,7 +433,7 @@
 					status = "disabled";
 				};
 
-				ssi3: ssi at 02030000 {
+				ssi3: ssi at 2030000 {
 					#sound-dai-cells = <0>;
 					compatible = "fsl,imx6q-ssi",
 							"fsl,imx51-ssi";
@@ -385,7 +449,7 @@
 					status = "disabled";
 				};
 
-				asrc: asrc at 02034000 {
+				asrc: asrc at 2034000 {
 					compatible = "fsl,imx53-asrc";
 					reg = <0x02034000 0x4000>;
 					interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
@@ -410,12 +474,12 @@
 					status = "okay";
 				};
 
-				spba at 0203c000 {
+				spba at 203c000 {
 					reg = <0x0203c000 0x4000>;
 				};
 			};
 
-			vpu: vpu at 02040000 {
+			vpu: vpu at 2040000 {
 				compatible = "cnm,coda960";
 				reg = <0x02040000 0x3c000>;
 				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
@@ -424,16 +488,16 @@
 				clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
 					 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
 				clock-names = "per", "ahb";
-				power-domains = <&gpc 1>;
+				power-domains = <&pd_pu>;
 				resets = <&src 1>;
 				iram = <&ocram>;
 			};
 
-			aipstz at 0207c000 { /* AIPSTZ1 */
+			aipstz at 207c000 { /* AIPSTZ1 */
 				reg = <0x0207c000 0x4000>;
 			};
 
-			pwm1: pwm at 02080000 {
+			pwm1: pwm at 2080000 {
 				#pwm-cells = <2>;
 				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 				reg = <0x02080000 0x4000>;
@@ -444,7 +508,7 @@
 				status = "disabled";
 			};
 
-			pwm2: pwm at 02084000 {
+			pwm2: pwm at 2084000 {
 				#pwm-cells = <2>;
 				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 				reg = <0x02084000 0x4000>;
@@ -455,7 +519,7 @@
 				status = "disabled";
 			};
 
-			pwm3: pwm at 02088000 {
+			pwm3: pwm at 2088000 {
 				#pwm-cells = <2>;
 				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 				reg = <0x02088000 0x4000>;
@@ -466,7 +530,7 @@
 				status = "disabled";
 			};
 
-			pwm4: pwm at 0208c000 {
+			pwm4: pwm at 208c000 {
 				#pwm-cells = <2>;
 				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 				reg = <0x0208c000 0x4000>;
@@ -477,7 +541,7 @@
 				status = "disabled";
 			};
 
-			can1: flexcan at 02090000 {
+			can1: flexcan at 2090000 {
 				compatible = "fsl,imx6q-flexcan";
 				reg = <0x02090000 0x4000>;
 				interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
@@ -487,7 +551,7 @@
 				status = "disabled";
 			};
 
-			can2: flexcan at 02094000 {
+			can2: flexcan at 2094000 {
 				compatible = "fsl,imx6q-flexcan";
 				reg = <0x02094000 0x4000>;
 				interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
@@ -497,7 +561,7 @@
 				status = "disabled";
 			};
 
-			gpt: gpt at 02098000 {
+			gpt: gpt at 2098000 {
 				compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 				reg = <0x02098000 0x4000>;
 				interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -507,7 +571,7 @@
 				clock-names = "ipg", "per", "osc_per";
 			};
 
-			gpio1: gpio at 0209c000 {
+			gpio1: gpio at 209c000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 				reg = <0x0209c000 0x4000>;
 				interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
@@ -518,7 +582,7 @@
 				#interrupt-cells = <2>;
 			};
 
-			gpio2: gpio at 020a0000 {
+			gpio2: gpio at 20a0000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 				reg = <0x020a0000 0x4000>;
 				interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
@@ -529,7 +593,7 @@
 				#interrupt-cells = <2>;
 			};
 
-			gpio3: gpio at 020a4000 {
+			gpio3: gpio at 20a4000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 				reg = <0x020a4000 0x4000>;
 				interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
@@ -540,7 +604,7 @@
 				#interrupt-cells = <2>;
 			};
 
-			gpio4: gpio at 020a8000 {
+			gpio4: gpio at 20a8000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 				reg = <0x020a8000 0x4000>;
 				interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
@@ -551,7 +615,7 @@
 				#interrupt-cells = <2>;
 			};
 
-			gpio5: gpio at 020ac000 {
+			gpio5: gpio at 20ac000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 				reg = <0x020ac000 0x4000>;
 				interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
@@ -562,7 +626,7 @@
 				#interrupt-cells = <2>;
 			};
 
-			gpio6: gpio at 020b0000 {
+			gpio6: gpio at 20b0000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 				reg = <0x020b0000 0x4000>;
 				interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
@@ -573,7 +637,7 @@
 				#interrupt-cells = <2>;
 			};
 
-			gpio7: gpio at 020b4000 {
+			gpio7: gpio at 20b4000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 				reg = <0x020b4000 0x4000>;
 				interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
@@ -584,7 +648,7 @@
 				#interrupt-cells = <2>;
 			};
 
-			kpp: kpp at 020b8000 {
+			kpp: kpp at 20b8000 {
 				compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 				reg = <0x020b8000 0x4000>;
 				interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -592,14 +656,14 @@
 				status = "disabled";
 			};
 
-			wdog1: wdog at 020bc000 {
+			wdog1: wdog at 20bc000 {
 				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 				reg = <0x020bc000 0x4000>;
 				interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_DUMMY>;
 			};
 
-			wdog2: wdog at 020c0000 {
+			wdog2: wdog at 20c0000 {
 				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 				reg = <0x020c0000 0x4000>;
 				interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -607,7 +671,7 @@
 				status = "disabled";
 			};
 
-			clks: ccm at 020c4000 {
+			clks: ccm at 20c4000 {
 				compatible = "fsl,imx6q-ccm";
 				reg = <0x020c4000 0x4000>;
 				interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
@@ -615,7 +679,7 @@
 				#clock-cells = <1>;
 			};
 
-			anatop: anatop at 020c8000 {
+			anatop: anatop at 20c8000 {
 				compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 				reg = <0x020c8000 0x1000>;
 				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
@@ -625,8 +689,8 @@
 				regulator-1p1 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd1p1";
-					regulator-min-microvolt = <800000>;
-					regulator-max-microvolt = <1375000>;
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1200000>;
 					regulator-always-on;
 					anatop-reg-offset = <0x110>;
 					anatop-vol-bit-shift = <8>;
@@ -634,6 +698,7 @@
 					anatop-min-bit-val = <4>;
 					anatop-min-voltage = <800000>;
 					anatop-max-voltage = <1375000>;
+					anatop-enable-bit = <0>;
 				};
 
 				regulator-3p0 {
@@ -648,20 +713,22 @@
 					anatop-min-bit-val = <0>;
 					anatop-min-voltage = <2625000>;
 					anatop-max-voltage = <3400000>;
+					anatop-enable-bit = <0>;
 				};
 
 				regulator-2p5 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd2p5";
-					regulator-min-microvolt = <2000000>;
+					regulator-min-microvolt = <2250000>;
 					regulator-max-microvolt = <2750000>;
 					regulator-always-on;
 					anatop-reg-offset = <0x130>;
 					anatop-vol-bit-shift = <8>;
 					anatop-vol-bit-width = <5>;
 					anatop-min-bit-val = <0>;
-					anatop-min-voltage = <2000000>;
-					anatop-max-voltage = <2750000>;
+					anatop-min-voltage = <2100000>;
+					anatop-max-voltage = <2875000>;
+					anatop-enable-bit = <0>;
 				};
 
 				reg_arm: regulator-vddcore {
@@ -716,15 +783,7 @@
 				};
 			};
 
-			tempmon: tempmon {
-				compatible = "fsl,imx6q-tempmon";
-				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
-				fsl,tempmon = <&anatop>;
-				fsl,tempmon-data = <&ocotp>;
-				clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-			};
-
-			usbphy1: usbphy at 020c9000 {
+			usbphy1: usbphy at 20c9000 {
 				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 				reg = <0x020c9000 0x1000>;
 				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
@@ -732,7 +791,7 @@
 				fsl,anatop = <&anatop>;
 			};
 
-			usbphy2: usbphy at 020ca000 {
+			usbphy2: usbphy at 20ca000 {
 				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 				reg = <0x020ca000 0x1000>;
 				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -740,7 +799,7 @@
 				fsl,anatop = <&anatop>;
 			};
 
-			snvs: snvs at 020cc000 {
+			snvs: snvs at 20cc000 {
 				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 				reg = <0x020cc000 0x4000>;
 
@@ -756,22 +815,27 @@
 					compatible = "syscon-poweroff";
 					regmap = <&snvs>;
 					offset = <0x38>;
+					value = <0x60>;
 					mask = <0x60>;
 					status = "disabled";
 				};
+
+				snvs_lpgpr: snvs-lpgpr {
+					compatible = "fsl,imx6q-snvs-lpgpr";
+				};
 			};
 
-			epit1: epit at 020d0000 { /* EPIT1 */
+			epit1: epit at 20d0000 { /* EPIT1 */
 				reg = <0x020d0000 0x4000>;
 				interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			epit2: epit at 020d4000 { /* EPIT2 */
+			epit2: epit at 20d4000 { /* EPIT2 */
 				reg = <0x020d4000 0x4000>;
 				interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			src: src at 020d8000 {
+			src: src at 20d8000 {
 				compatible = "fsl,imx6q-src", "fsl,imx51-src";
 				reg = <0x020d8000 0x4000>;
 				interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -779,7 +843,7 @@
 				#reset-cells = <1>;
 			};
 
-			gpc: gpc at 020dc000 {
+			gpc: gpc at 20dc000 {
 				compatible = "fsl,imx6q-gpc";
 				reg = <0x020dc000 0x4000>;
 				interrupt-controller;
@@ -787,91 +851,57 @@
 				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 					     <0 90 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-parent = <&intc>;
-				pu-supply = <&reg_pu>;
-				clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
-					 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
-					 <&clks IMX6QDL_CLK_GPU2D_CORE>,
-					 <&clks IMX6QDL_CLK_GPU2D_AXI>,
-					 <&clks IMX6QDL_CLK_OPENVG_AXI>,
-					 <&clks IMX6QDL_CLK_VPU_AXI>;
-				#power-domain-cells = <1>;
-			};
-
-			gpr: iomuxc-gpr at 020e0000 {
-				compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
-				reg = <0x020e0000 0x38>;
-			};
-
-			iomuxc: iomuxc at 020e0000 {
-				compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
-				reg = <0x020e0000 0x4000>;
-			};
-
-			ldb: ldb at 020e0008 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
-				gpr = <&gpr>;
-				status = "disabled";
+				clocks = <&clks IMX6QDL_CLK_IPG>;
+				clock-names = "ipg";
 
-				lvds-channel at 0 {
+				pgc {
 					#address-cells = <1>;
 					#size-cells = <0>;
-					reg = <0>;
-					status = "disabled";
 
-					port at 0 {
+					power-domain at 0 {
 						reg = <0>;
-
-						lvds0_mux_0: endpoint {
-							remote-endpoint = <&ipu1_di0_lvds0>;
-						};
+						#power-domain-cells = <0>;
 					};
-
-					port at 1 {
+					pd_pu: power-domain at 1 {
 						reg = <1>;
-
-						lvds0_mux_1: endpoint {
-							remote-endpoint = <&ipu1_di1_lvds0>;
-						};
+						#power-domain-cells = <0>;
+						power-supply = <&reg_pu>;
+						clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+						         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+						         <&clks IMX6QDL_CLK_GPU2D_CORE>,
+						         <&clks IMX6QDL_CLK_GPU2D_AXI>,
+						         <&clks IMX6QDL_CLK_OPENVG_AXI>,
+						         <&clks IMX6QDL_CLK_VPU_AXI>;
 					};
 				};
+			};
 
-				lvds-channel at 1 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <1>;
-					status = "disabled";
-
-					port at 0 {
-						reg = <0>;
-
-						lvds1_mux_0: endpoint {
-							remote-endpoint = <&ipu1_di0_lvds1>;
-						};
-					};
+			gpr: iomuxc-gpr at 20e0000 {
+				compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
+				reg = <0x20e0000 0x38>;
 
-					port at 1 {
-						reg = <1>;
-
-						lvds1_mux_1: endpoint {
-							remote-endpoint = <&ipu1_di1_lvds1>;
-						};
-					};
+				mux: mux-controller {
+					compatible = "mmio-mux";
+					#mux-control-cells = <1>;
 				};
 			};
 
-			dcic1: dcic at 020e4000 {
+			iomuxc: iomuxc at 20e0000 {
+				compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
+				reg = <0x20e0000 0x4000>;
+			};
+
+			dcic1: dcic at 20e4000 {
 				reg = <0x020e4000 0x4000>;
 				interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			dcic2: dcic at 020e8000 {
+			dcic2: dcic at 20e8000 {
 				reg = <0x020e8000 0x4000>;
 				interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			sdma: sdma at 020ec000 {
+			sdma: sdma at 20ec000 {
 				compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 				reg = <0x020ec000 0x4000>;
 				interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -883,7 +913,7 @@
 			};
 		};
 
-		aips-bus at 02100000 { /* AIPS2 */
+		aips-bus at 2100000 { /* AIPS2 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -892,7 +922,6 @@
 
 			crypto: caam at 2100000 {
 				compatible = "fsl,sec-v4.0";
-				fsl,sec-era = <4>;
 				#address-cells = <1>;
 				#size-cells = <1>;
 				reg = <0x2100000 0x10000>;
@@ -916,11 +945,11 @@
 				};
 			};
 
-			aipstz at 0217c000 { /* AIPSTZ2 */
+			aipstz at 217c000 { /* AIPSTZ2 */
 				reg = <0x0217c000 0x4000>;
 			};
 
-			usbotg: usb at 02184000 {
+			usbotg: usb at 2184000 {
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184000 0x200>;
 				interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
@@ -933,7 +962,7 @@
 				status = "disabled";
 			};
 
-			usbh1: usb at 02184200 {
+			usbh1: usb at 2184200 {
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184200 0x200>;
 				interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
@@ -947,7 +976,7 @@
 				status = "disabled";
 			};
 
-			usbh2: usb at 02184400 {
+			usbh2: usb at 2184400 {
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184400 0x200>;
 				interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
@@ -960,7 +989,7 @@
 				status = "disabled";
 			};
 
-			usbh3: usb at 02184600 {
+			usbh3: usb at 2184600 {
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184600 0x200>;
 				interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
@@ -973,16 +1002,17 @@
 				status = "disabled";
 			};
 
-			usbmisc: usbmisc at 02184800 {
+			usbmisc: usbmisc at 2184800 {
 				#index-cells = <1>;
 				compatible = "fsl,imx6q-usbmisc";
 				reg = <0x02184800 0x200>;
 				clocks = <&clks IMX6QDL_CLK_USBOH3>;
 			};
 
-			fec: ethernet at 02188000 {
+			fec: ethernet at 2188000 {
 				compatible = "fsl,imx6q-fec";
 				reg = <0x02188000 0x4000>;
+				interrupt-names = "int0", "pps";
 				interrupts-extended =
 					<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 					<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
@@ -993,14 +1023,14 @@
 				status = "disabled";
 			};
 
-			mlb at 0218c000 {
+			mlb at 218c000 {
 				reg = <0x0218c000 0x4000>;
 				interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 					     <0 117 IRQ_TYPE_LEVEL_HIGH>,
 					     <0 126 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			usdhc1: usdhc at 02190000 {
+			usdhc1: usdhc at 2190000 {
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02190000 0x4000>;
 				interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -1012,7 +1042,7 @@
 				status = "disabled";
 			};
 
-			usdhc2: usdhc at 02194000 {
+			usdhc2: usdhc at 2194000 {
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02194000 0x4000>;
 				interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -1024,7 +1054,7 @@
 				status = "disabled";
 			};
 
-			usdhc3: usdhc at 02198000 {
+			usdhc3: usdhc at 2198000 {
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02198000 0x4000>;
 				interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -1036,7 +1066,7 @@
 				status = "disabled";
 			};
 
-			usdhc4: usdhc at 0219c000 {
+			usdhc4: usdhc at 219c000 {
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x0219c000 0x4000>;
 				interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -1048,7 +1078,7 @@
 				status = "disabled";
 			};
 
-			i2c1: i2c at 021a0000 {
+			i2c1: i2c at 21a0000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
@@ -1058,7 +1088,7 @@
 				status = "disabled";
 			};
 
-			i2c2: i2c at 021a4000 {
+			i2c2: i2c at 21a4000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
@@ -1068,7 +1098,7 @@
 				status = "disabled";
 			};
 
-			i2c3: i2c at 021a8000 {
+			i2c3: i2c at 21a8000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
@@ -1078,55 +1108,66 @@
 				status = "disabled";
 			};
 
-			romcp at 021ac000 {
+			romcp at 21ac000 {
 				reg = <0x021ac000 0x4000>;
 			};
 
-			mmdc0: mmdc at 021b0000 { /* MMDC0 */
+			mmdc0: mmdc at 21b0000 { /* MMDC0 */
 				compatible = "fsl,imx6q-mmdc";
 				reg = <0x021b0000 0x4000>;
 			};
 
-			mmdc1: mmdc at 021b4000 { /* MMDC1 */
+			mmdc1: mmdc at 21b4000 { /* MMDC1 */
 				reg = <0x021b4000 0x4000>;
 			};
 
-			weim: weim at 021b8000 {
+			weim: weim at 21b8000 {
+				#address-cells = <2>;
+				#size-cells = <1>;
 				compatible = "fsl,imx6q-weim";
 				reg = <0x021b8000 0x4000>;
 				interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
+				fsl,weim-cs-gpr = <&gpr>;
+				status = "disabled";
 			};
 
-			ocotp: ocotp at 021bc000 {
+			ocotp: ocotp at 21bc000 {
 				compatible = "fsl,imx6q-ocotp", "syscon";
 				reg = <0x021bc000 0x4000>;
 				clocks = <&clks IMX6QDL_CLK_IIM>;
 			};
 
-			tzasc at 021d0000 { /* TZASC1 */
+			tzasc at 21d0000 { /* TZASC1 */
 				reg = <0x021d0000 0x4000>;
 				interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			tzasc at 021d4000 { /* TZASC2 */
+			tzasc at 21d4000 { /* TZASC2 */
 				reg = <0x021d4000 0x4000>;
 				interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			audmux: audmux at 021d8000 {
+			audmux: audmux at 21d8000 {
 				compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 				reg = <0x021d8000 0x4000>;
 				status = "disabled";
 			};
 
-			mipi_csi: mipi at 021dc000 {
+			mipi_csi: mipi at 21dc000 {
+				compatible = "fsl,imx6-mipi-csi2";
 				reg = <0x021dc000 0x4000>;
-			};
-
-			mipi_dsi: mipi at 021e0000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
+				interrupts = <0 100 0x04>, <0 101 0x04>;
+				clocks = <&clks IMX6QDL_CLK_HSI_TX>,
+					 <&clks IMX6QDL_CLK_VIDEO_27M>,
+					 <&clks IMX6QDL_CLK_EIM_PODF>;
+				clock-names = "dphy", "ref", "pix";
+				status = "disabled";
+			};
+
+			mipi_dsi: mipi at 21e0000 {
 				reg = <0x021e0000 0x4000>;
 				status = "disabled";
 
@@ -1152,12 +1193,14 @@
 				};
 			};
 
-			vdoa at 021e4000 {
+			vdoa at 21e4000 {
+				compatible = "fsl,imx6q-vdoa";
 				reg = <0x021e4000 0x4000>;
 				interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6QDL_CLK_VDOA>;
 			};
 
-			uart2: serial at 021e8000 {
+			uart2: serial at 21e8000 {
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021e8000 0x4000>;
 				interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
@@ -1169,7 +1212,7 @@
 				status = "disabled";
 			};
 
-			uart3: serial at 021ec000 {
+			uart3: serial at 21ec000 {
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021ec000 0x4000>;
 				interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
@@ -1181,7 +1224,7 @@
 				status = "disabled";
 			};
 
-			uart4: serial at 021f0000 {
+			uart4: serial at 21f0000 {
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021f0000 0x4000>;
 				interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
@@ -1193,7 +1236,7 @@
 				status = "disabled";
 			};
 
-			uart5: serial at 021f4000 {
+			uart5: serial at 21f4000 {
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021f4000 0x4000>;
 				interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
@@ -1206,7 +1249,7 @@
 			};
 		};
 
-		ipu1: ipu at 02400000 {
+		ipu1: ipu at 2400000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "fsl,imx6q-ipu";
@@ -1221,6 +1264,10 @@
 
 			ipu1_csi0: port at 0 {
 				reg = <0>;
+
+				ipu1_csi0_from_ipu1_csi0_mux: endpoint {
+					remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
+				};
 			};
 
 			ipu1_csi1: port at 1 {
@@ -1232,22 +1279,27 @@
 				#size-cells = <0>;
 				reg = <2>;
 
-				ipu1_di0_disp0: disp0-endpoint {
+				ipu1_di0_disp0: endpoint at 0 {
+					reg = <0>;
 				};
 
-				ipu1_di0_hdmi: hdmi-endpoint {
+				ipu1_di0_hdmi: endpoint at 1 {
+					reg = <1>;
 					remote-endpoint = <&hdmi_mux_0>;
 				};
 
-				ipu1_di0_mipi: mipi-endpoint {
+				ipu1_di0_mipi: endpoint at 2 {
+					reg = <2>;
 					remote-endpoint = <&mipi_mux_0>;
 				};
 
-				ipu1_di0_lvds0: lvds0-endpoint {
+				ipu1_di0_lvds0: endpoint at 3 {
+					reg = <3>;
 					remote-endpoint = <&lvds0_mux_0>;
 				};
 
-				ipu1_di0_lvds1: lvds1-endpoint {
+				ipu1_di0_lvds1: endpoint at 4 {
+					reg = <4>;
 					remote-endpoint = <&lvds1_mux_0>;
 				};
 			};
@@ -1257,22 +1309,27 @@
 				#size-cells = <0>;
 				reg = <3>;
 
-				ipu1_di1_disp1: disp1-endpoint {
+				ipu1_di1_disp1: endpoint at 0 {
+					reg = <0>;
 				};
 
-				ipu1_di1_hdmi: hdmi-endpoint {
+				ipu1_di1_hdmi: endpoint at 1 {
+					reg = <1>;
 					remote-endpoint = <&hdmi_mux_1>;
 				};
 
-				ipu1_di1_mipi: mipi-endpoint {
+				ipu1_di1_mipi: endpoint at 2 {
+					reg = <2>;
 					remote-endpoint = <&mipi_mux_1>;
 				};
 
-				ipu1_di1_lvds0: lvds0-endpoint {
+				ipu1_di1_lvds0: endpoint at 3 {
+					reg = <3>;
 					remote-endpoint = <&lvds0_mux_1>;
 				};
 
-				ipu1_di1_lvds1: lvds1-endpoint {
+				ipu1_di1_lvds1: endpoint at 4 {
+					reg = <4>;
 					remote-endpoint = <&lvds1_mux_1>;
 				};
 			};
diff --git a/arch/arm/dts/imx6qp-sabreauto.dts b/arch/arm/dts/imx6qp-sabreauto.dts
new file mode 100644
index 0000000..d4caeeb
--- /dev/null
+++ b/arch/arm/dts/imx6qp-sabreauto.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2016 Freescale Semiconductor, Inc.
+
+/dts-v1/;
+
+#include "imx6qp.dtsi"
+#include "imx6qdl-sabreauto.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad Plus SABRE Automotive Board";
+	compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
+};
+
+&i2c2 {
+	max7322: gpio at 68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&iomuxc {
+	imx6qdl-sabreauto {
+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
+				MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b018
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b018
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b018
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b018
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b018
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b018
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b018
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b018
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b018
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b018
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b018
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b018
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
+			>;
+		};
+	};
+};
+
+&pcie {
+	status = "disabled";
+};
+
+&vgen3_reg {
+	regulator-always-on;
+};
diff --git a/arch/arm/dts/imx6qp-sabresd.dts b/arch/arm/dts/imx6qp-sabresd.dts
new file mode 100644
index 0000000..f1b9cb1
--- /dev/null
+++ b/arch/arm/dts/imx6qp-sabresd.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2016 Freescale Semiconductor, Inc.
+
+/dts-v1/;
+
+#include "imx6qp.dtsi"
+#include "imx6qdl-sabresd.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
+	compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
+};
+
+&reg_arm {
+	vin-supply = <&sw2_reg>;
+};
+
+&iomuxc {
+	imx6qdl-sabresd {
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10071
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
+				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
+				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
+				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10071
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+			>;
+		};
+	};
+};
+
+&pcie {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi
new file mode 100644
index 0000000..5f51f8e
--- /dev/null
+++ b/arch/arm/dts/imx6qp.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2016 Freescale Semiconductor, Inc.
+
+#include "imx6q.dtsi"
+
+/ {
+	soc {
+		ocram2: sram at 940000 {
+			compatible = "mmio-sram";
+			reg = <0x00940000 0x20000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
+		ocram3: sram at 960000 {
+			compatible = "mmio-sram";
+			reg = <0x00960000 0x20000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
+		aips-bus at 2100000 {
+			pre1: pre at 21c8000 {
+				compatible = "fsl,imx6qp-pre";
+				reg = <0x021c8000 0x1000>;
+				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clks IMX6QDL_CLK_PRE0>;
+				clock-names = "axi";
+				fsl,iram = <&ocram2>;
+			};
+
+			pre2: pre at 21c9000 {
+				compatible = "fsl,imx6qp-pre";
+				reg = <0x021c9000 0x1000>;
+				interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clks IMX6QDL_CLK_PRE1>;
+				clock-names = "axi";
+				fsl,iram = <&ocram2>;
+			};
+
+			pre3: pre at 21ca000 {
+				compatible = "fsl,imx6qp-pre";
+				reg = <0x021ca000 0x1000>;
+				interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clks IMX6QDL_CLK_PRE2>;
+				clock-names = "axi";
+				fsl,iram = <&ocram3>;
+			};
+
+			pre4: pre at 21cb000 {
+				compatible = "fsl,imx6qp-pre";
+				reg = <0x021cb000 0x1000>;
+				interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clks IMX6QDL_CLK_PRE3>;
+				clock-names = "axi";
+				fsl,iram = <&ocram3>;
+			};
+
+			prg1: prg at 21cc000 {
+				compatible = "fsl,imx6qp-prg";
+				reg = <0x021cc000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
+					 <&clks IMX6QDL_CLK_PRG0_AXI>;
+				clock-names = "ipg", "axi";
+				fsl,pres = <&pre1>, <&pre2>, <&pre3>;
+			};
+
+			prg2: prg at 21cd000 {
+				compatible = "fsl,imx6qp-prg";
+				reg = <0x021cd000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
+					 <&clks IMX6QDL_CLK_PRG1_AXI>;
+				clock-names = "ipg", "axi";
+				fsl,pres = <&pre4>, <&pre2>, <&pre3>;
+			};
+		};
+	};
+};
+
+&fec {
+	/delete-property/interrupts-extended;
+	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
+		     <0 119 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpc {
+	compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
+};
+
+&ipu1 {
+	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+	fsl,prg = <&prg1>;
+};
+
+&ipu2 {
+	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+	fsl,prg = <&prg2>;
+};
+
+&ldb {
+	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
+		 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
+	clock-names = "di0_pll", "di1_pll",
+		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
+		      "di0", "di1";
+};
+
+&mmdc0 {
+	compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
+};
+
+&pcie {
+	compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+};
-- 
2.7.4

[U-Boot] [PATCH v4 11/20] configs: mx6sabreauto: Add SPL FIT and DM support

[Abel Vesa]

Enable all the necessary configs for SPL DM and FIT support for
mx6sabreauto.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 configs/mx6sabreauto_defconfig | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 4bdcbb1..c3843ec 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -11,12 +11,18 @@ CONFIG_SPL=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_NXP_BOARD_REVISION=y
 CONFIG_NR_DRAM_BANKS=1
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT=y
+CONFIG_SPL_FIT_PRINT=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOUNCE_BUFFER=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
 CONFIG_SPL_EXT_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -40,8 +46,15 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
+CONFIG_OF_LIST="imx6dl-sabreauto imx6q-sabreauto imx6qp-sabreauto"
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_SF=y
 CONFIG_DM_MMC=y
@@ -68,4 +81,3 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
-- 
2.7.4

[U-Boot] [PATCH v4 12/20] configs: mx6sabresd: Add SPL FIT and DM support

[Abel Vesa]

Enable all the necessary configs for SPL DM and FIT support for
mx6sabresd.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 configs/mx6sabresd_defconfig | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 3babfd5..0e35d6c 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -10,12 +10,18 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT=y
+CONFIG_SPL_FIT_PRINT=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOUNCE_BUFFER=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
 CONFIG_SPL_EXT_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
@@ -47,23 +53,34 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_EFI_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
+CONFIG_OF_LIST="imx6q-sabresd imx6qp-sabresd imx6dl-sabresd"
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x12000000
 CONFIG_FASTBOOT_BUF_SIZE=0x10000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_DM_REGULATOR=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_USB=y
-CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
@@ -73,4 +90,3 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
-- 
2.7.4

[U-Boot] [PATCH v4 14/20] mx6sabresd: Add DM_GPIO support

[Abel Vesa]

Add the DM_GPIO related config for mx6sabresd.
Also add the gpio request calls.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/mx6sabresd/mx6sabresd.c | 5 +++++
 configs/mx6sabresd_defconfig            | 1 +
 2 files changed, 6 insertions(+)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 4688095..99002bd 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -96,6 +96,7 @@ static void setup_iomux_enet(void)
 	SETUP_IOMUX_PADS(enet_pads);
 
 	/* Reset AR8031 PHY */
+	gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset");
 	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
 	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
@@ -189,6 +190,7 @@ static iomux_v3_cfg_t const bl_pads[] = {
 static void enable_backlight(void)
 {
 	SETUP_IOMUX_PADS(bl_pads);
+	gpio_request(DISP0_PWR_EN, "Display Power Enable");
 	gpio_direction_output(DISP0_PWR_EN, 1);
 }
 
@@ -307,11 +309,13 @@ int board_mmc_init(bd_t *bis)
 		switch (i) {
 		case 0:
 			SETUP_IOMUX_PADS(usdhc2_pads);
+			gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");
 			gpio_direction_input(USDHC2_CD_GPIO);
 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 			break;
 		case 1:
 			SETUP_IOMUX_PADS(usdhc3_pads);
+			gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");
 			gpio_direction_input(USDHC3_CD_GPIO);
 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 			break;
@@ -729,6 +733,7 @@ int checkboard(void)
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
+	gpio_request(KEY_VOL_UP, "KEY Volume UP");
 	gpio_direction_input(KEY_VOL_UP);
 
 	/* Only enter in Falcon mode if KEY_VOL_UP is pressed */
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 0e35d6c..4b40dfe 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -68,6 +68,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12000000
 CONFIG_FASTBOOT_BUF_SIZE=0x10000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
-- 
2.7.4

[U-Boot] [PATCH v4 13/20] mx6sabreauto: Add DM_GPIO support

[Abel Vesa]

Add the DM_GPIO related config for mx6sabreauto.
Also add the gpio request calls.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/mx6sabreauto/mx6sabreauto.c | 3 +++
 configs/mx6sabreauto_defconfig              | 1 +
 2 files changed, 4 insertions(+)

diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
index c8f1263..c7e3e67 100644
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -501,6 +501,7 @@ iomux_v3_cfg_t const backlight_pads[] = {
 
 static void setup_iomux_backlight(void)
 {
+	gpio_request(IMX_GPIO_NR(2, 9), "backlight");
 	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
 	SETUP_IOMUX_PADS(backlight_pads);
 }
@@ -594,6 +595,7 @@ int board_init(void)
 	else
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 	/* I2C 3 Steer */
+	gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
 	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 	SETUP_IOMUX_PADS(i2c3_pads);
 #ifndef CONFIG_SYS_FLASH_CFI
@@ -602,6 +604,7 @@ int board_init(void)
 	else
 		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
 #endif
+	gpio_request(IMX_GPIO_NR(1, 15), "expander en");
 	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
 	SETUP_IOMUX_PADS(port_exp);
 
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index c3843ec..3b37766 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -57,6 +57,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_SF=y
+CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_NAND=y
-- 
2.7.4

[U-Boot] [PATCH v4 15/20] configs: mx6sabreauto: Add DM_SPI_FLASH necessary configs

[Abel Vesa]

Enable all neceassary configs to support DM_SPI_FLASH on mx6sabreauto.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 configs/mx6sabreauto_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 3b37766..bb466fe 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -62,12 +62,14 @@ CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_DM_REGULATOR=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-- 
2.7.4

[U-Boot] [PATCH v4 16/20] configs: mx6sabresd: Add DM_SPI_FLASH necessary configs

[Abel Vesa]

Enable all neceassary configs to support DM_SPI_FLASH on mx6sabresd.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 configs/mx6sabresd_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 4b40dfe..e8fd9b4 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -71,6 +71,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=2
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
@@ -78,6 +79,7 @@ CONFIG_MII=y
 CONFIG_PCI=y
 CONFIG_DM_REGULATOR=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-- 
2.7.4

[U-Boot] [PATCH v4 17/20] board: mx6sabreauto: Remove the non-DM code

[Abel Vesa]

Since the mx6sabreauto has DM support, remove the unused non-DM code
from mx6sabreauto board file.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 board/freescale/mx6sabreauto/mx6sabreauto.c | 70 -----------------------------
 1 file changed, 70 deletions(-)

diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
index c7e3e67..dd72de9 100644
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -159,44 +159,6 @@ static iomux_v3_cfg_t const port_exp[] = {
 	IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
-/*Define for building port exp gpio, pin starts from 0*/
-#define PORTEXP_IO_NR(chip, pin) \
-	((chip << 5) + pin)
-
-/*Get the chip addr from a ioexp gpio*/
-#define PORTEXP_IO_TO_CHIP(gpio_nr) \
-	(gpio_nr >> 5)
-
-/*Get the pin number from a ioexp gpio*/
-#define PORTEXP_IO_TO_PIN(gpio_nr) \
-	(gpio_nr & 0x1f)
-
-static int port_exp_direction_output(unsigned gpio, int value)
-{
-	int ret;
-
-	i2c_set_bus_num(2);
-	ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
-	if (ret)
-		return ret;
-
-	ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
-		(1 << PORTEXP_IO_TO_PIN(gpio)),
-		(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
-
-	if (ret)
-		return ret;
-
-	ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
-		(1 << PORTEXP_IO_TO_PIN(gpio)),
-		(value << PORTEXP_IO_TO_PIN(gpio)));
-
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
 #ifdef CONFIG_MTD_NOR_FLASH
 static iomux_v3_cfg_t const eimnor_pads[] = {
 	IOMUX_PADS(PAD_EIM_D16__EIM_DATA16	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
@@ -681,19 +643,10 @@ int checkboard(void)
 }
 
 #ifdef CONFIG_USB_EHCI_MX6
-#define USB_HOST1_PWR     PORTEXP_IO_NR(0x32, 7)
-#define USB_OTG_PWR       PORTEXP_IO_NR(0x34, 1)
-
-iomux_v3_cfg_t const usb_otg_pads[] = {
-	IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
 int board_ehci_hcd_init(int port)
 {
 	switch (port) {
 	case 0:
-		SETUP_IOMUX_PADS(usb_otg_pads);
-
 		/*
 		  * Set daisy chain for otg_pin_id on 6q.
 		 *  For 6dl, this bit is reserved.
@@ -708,29 +661,6 @@ int board_ehci_hcd_init(int port)
 	}
 	return 0;
 }
-
-int board_ehci_power(int port, int on)
-{
-	switch (port) {
-	case 0:
-		if (on)
-			port_exp_direction_output(USB_OTG_PWR, 1);
-		else
-			port_exp_direction_output(USB_OTG_PWR, 0);
-		break;
-	case 1:
-		if (on)
-			port_exp_direction_output(USB_HOST1_PWR, 1);
-		else
-			port_exp_direction_output(USB_HOST1_PWR, 0);
-		break;
-	default:
-		printf("MXC USB port %d not yet supported\n", port);
-		return -EINVAL;
-	}
-
-	return 0;
-}
 #endif
 
 #ifdef CONFIG_SPL_BUILD
-- 
2.7.4

[U-Boot] [PATCH v4 18/20] board: mx6sabresd: Remove non-DM code

[Abel Vesa]

Since the mx6sabreauto has DM support, remove the unused non-DM code
from mx6sabresd board file.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 board/freescale/mx6sabresd/mx6sabresd.c | 50 ---------------------------------
 1 file changed, 50 deletions(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 99002bd..0824a05 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -563,63 +563,13 @@ int board_eth_init(bd_t *bis)
 }
 
 #ifdef CONFIG_USB_EHCI_MX6
-#define USB_OTHERREGS_OFFSET	0x800
-#define UCTRL_PWR_POL		(1 << 9)
-
-static iomux_v3_cfg_t const usb_otg_pads[] = {
-	IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
-	IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usb_hc1_pads[] = {
-	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
 static void setup_usb(void)
 {
-	SETUP_IOMUX_PADS(usb_otg_pads);
-
 	/*
 	 * set daisy chain for otg_pin_id on 6q.
 	 * for 6dl, this bit is reserved
 	 */
 	imx_iomux_set_gpr_register(1, 13, 1, 0);
-
-	SETUP_IOMUX_PADS(usb_hc1_pads);
-}
-
-int board_ehci_hcd_init(int port)
-{
-	u32 *usbnc_usb_ctrl;
-
-	if (port > 1)
-		return -EINVAL;
-
-	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
-				 port * 4);
-
-	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
-
-	return 0;
-}
-
-int board_ehci_power(int port, int on)
-{
-	switch (port) {
-	case 0:
-		break;
-	case 1:
-		if (on)
-			gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
-		else
-			gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
-		break;
-	default:
-		printf("MXC USB port %d not yet supported\n", port);
-		return -EINVAL;
-	}
-
-	return 0;
 }
 #endif
 
-- 
2.7.4

[U-Boot] [PATCH v4 19/20] board: mx6sabresd: Remove the enet reset gpio handling

[Abel Vesa]

Rely on the phy-reset-gpios which is set in imx6qdl-sabresd dtsi
and get rid of the enet reset gpio handling from the board file.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 board/freescale/mx6sabresd/mx6sabresd.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 0824a05..385a18e 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -94,13 +94,6 @@ static iomux_v3_cfg_t const enet_pads[] = {
 static void setup_iomux_enet(void)
 {
 	SETUP_IOMUX_PADS(enet_pads);
-
-	/* Reset AR8031 PHY */
-	gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset");
-	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
-	mdelay(10);
-	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
-	udelay(100);
 }
 
 static iomux_v3_cfg_t const usdhc2_pads[] = {
-- 
2.7.4

[U-Boot] [PATCH v4 20/20] configs: mx6sabresd: Reduce SPL size by disabling DOS, EXT and EFI support

[Abel Vesa]

With DM and FIT enabled in SPL, there is an sram overflow. By disabling
CONFIG_SPL_DOS_PARTITION, CONFIG_SPL_EXT_SUPPORT and
CONFIG_SPL_EFI_PARTITION, we get to keep the 'one binary to fit all'
for imx6[q|qp|dl] on sabresd since the final SPL image is now under 64KB.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 configs/mx6sabresd_defconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index e8fd9b4..27ace02e 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -22,7 +22,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
-CONFIG_SPL_EXT_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_USB_HOST_SUPPORT=y
@@ -53,6 +52,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
-- 
2.7.4

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Fabio Estevam]

Hi Abel,

On Fri, Feb 1, 2019 at 2:43 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> The third version is here:
> https://lists.denx.de/pipermail/u-boot/2019-January/356903.html
>
> So, this time I hope I got it right. Before, I was stupidly trying
> to put a fit in another fit without a really good reason. To my
> excuse, that was working even with the spl_image->os set to 0,
> bug which I (hope) I fixed in the first patch (a new one)
> of this series.

Thanks for your work on this!

Just to confirm: with this series all sabresd variants (imx6q, imx6dl,
imx6qp) boot with the same binary, right?

Is there anything known to be not working that used to work before due
to missing driver model conversion?

Is Ethernet functional?

Thanks

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Abel Vesa]

On 19-02-01 15:13:32, Fabio Estevam wrote:
> Hi Abel,
> 
> On Fri, Feb 1, 2019 at 2:43 PM Abel Vesa <abel.vesa@nxp.com> wrote:
> >
> > The third version is here:
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.denx.de%2Fpipermail%2Fu-boot%2F2019-January%2F356903.html&amp;data=02%7C01%7Cabel.vesa%40nxp.com%7Cc7db2be273394c06098308d688689e41%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636846380248922351&amp;sdata=fhDqNxkE1dq0fGNroGRR%2F0OkmBPRlVBqCefS6GM8kns%3D&amp;reserved=0
> >
> > So, this time I hope I got it right. Before, I was stupidly trying
> > to put a fit in another fit without a really good reason. To my
> > excuse, that was working even with the spl_image->os set to 0,
> > bug which I (hope) I fixed in the first patch (a new one)
> > of this series.
> 
> Thanks for your work on this!
> 
> Just to confirm: with this series all sabresd variants (imx6q, imx6dl,
> imx6qp) boot with the same binary, right?
> 

That is correct.

For mx6sabresd_defconfig, all imx6q_sabresd, imx6qp_sabresd and imx6dl_sabresd
have been tested with the same binary.

And I've tested exactly the same the mx6sabreauto_defconfig with all three SoC
combinations.

> Is there anything known to be not working that used to work before due
> to missing driver model conversion?
> 

I don't know about anything that might not work. As specified in the cover
letter I had to get rid (disable) of EFI, EXT and DOS support in SPL.

> Is Ethernet functional?

I haven't tested the ethernet on all of them, just one of each (sabresd/sabreauto).

I'll test them all when I get back at the office tomorrow.

> 
> Thanks

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Fabio Estevam]

On Fri, Feb 1, 2019 at 3:59 PM Abel Vesa <abel.vesa@nxp.com> wrote:

> > Is Ethernet functional?
>
> I haven't tested the ethernet on all of them, just one of each (sabresd/sabreauto).
>
> I'll test them all when I get back at the office tomorrow.

Don't worry about that. If you tested in one of each then it is fine.

Thanks

[U-Boot] [PATCH v4 01/20] common: spl_fit: Fix the spl_fit_image_get_os for FIT_IMAGE_TINY

[Tom Rini]

On Fri, Feb 01, 2019 at 04:40:06PM +0000, Abel Vesa wrote:

> There is not really reducing codesize here since there is only
> a call. The function is always built in if CONFIG_$(SPL_TPL_)FIT is set.
> Plus, there was a change in behavior if CONFIG_SPL_OS_BOOT is defined.
> If CONFIG_FIT_IMAGE_TINY is defined, the spl_fit_image_get_os was
> returning -ENOTSUPP and then if CONFIG_SPL_OS_BOOT was also
> defined, the spl_image->os was left set to 0 which in turn
> was skipping the fdt appending resulting in boot-up failure.
> 
> Fixes: 337bbb6297775e spl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190201/3bdf82c3/attachment.sig>

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Tom Rini]

On Fri, Feb 01, 2019 at 04:40:05PM +0000, Abel Vesa wrote:

> The third version is here:
> https://lists.denx.de/pipermail/u-boot/2019-January/356903.html
> 
> So, this time I hope I got it right. Before, I was stupidly trying
> to put a fit in another fit without a really good reason. To my
> excuse, that was working even with the spl_image->os set to 0,
> bug which I (hope) I fixed in the first patch (a new one)
> of this series.
> 
> Changes since v3:
>  * Reduced the SPL size by disabling EXT_SUPPORT, otherwise the
>    6qp-sabresd wouldn't boot due to having its dtb last in the fit.
>    I forgot to mention in the last version that EFI and DOS SPL support
>    also had to be disabled to get the size right.
>  * Dropped the fit_spl.its file
>  * Dropped the (now) unnecessary updates to the README files. We're
>    sticking to the u-boot.img since it's exactly what is needed.
>  * Fixed a bug related to FIT_IMAGE_TINY when CONFIG_SPL_OS_BOOT
>    is enabled. The short story here is that spl_image->os was
>    remaining set to 0. (see first patch in the series for details)

Thanks for being persistent and figuring all of this out!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190201/4b7b2931/attachment.sig>

[U-Boot] [PATCH v4 01/20] common: spl_fit: Fix the spl_fit_image_get_os for FIT_IMAGE_TINY

[Lukasz Majewski]

Hi Abel,

> There is not really reducing codesize here since there is only
> a call.

Yes, I also haven't observed any change.

> The function is always built in if CONFIG_$(SPL_TPL_)FIT is
> set. Plus, there was a change in behavior if CONFIG_SPL_OS_BOOT is
> defined. If CONFIG_FIT_IMAGE_TINY is defined, the
> spl_fit_image_get_os was returning -ENOTSUPP and then if
> CONFIG_SPL_OS_BOOT was also defined, the spl_image->os was left set
> to 0 which in turn was skipping the fdt appending resulting in
> boot-up failure.
> 
> Fixes: 337bbb6297775e spl: fit: add SPL_FIT_IMAGE_TINY config to
> reduce code-size Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

However, this commit fixes the issue (the board didn't hang anymore
after SPL loading), hence

Tested-by: Lukasz Majewski <lukma@denx.de>

I've tested it on mccmon6 HW (imx6q).

Just to share - for me CONFIG_USE_TINY_PRINTF=y gave reduction of SPL
size from 38KiB to 34KiB.

Thanks for your commit.

> ---
>  common/spl/spl_fit.c | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index db43626..a87d02d 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -333,11 +333,7 @@ static int spl_fit_record_loadable(const void
> *fit, int images, int index, 
>  static int spl_fit_image_get_os(const void *fit, int noffset,
> uint8_t *os) {
> -#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
> -	return -ENOTSUPP;
> -#else
>  	return fit_image_get_os(fit, noffset, os);
> -#endif
>  }
>  
>  int spl_load_simple_fit(struct spl_image_info *spl_image,




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190201/20c3e8de/attachment.sig>

[U-Boot] [PATCH v4 01/20] common: spl_fit: Fix the spl_fit_image_get_os for FIT_IMAGE_TINY

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:50 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> There is not really reducing codesize here since there is only
> a call. The function is always built in if CONFIG_$(SPL_TPL_)FIT is set.
> Plus, there was a change in behavior if CONFIG_SPL_OS_BOOT is defined.
> If CONFIG_FIT_IMAGE_TINY is defined, the spl_fit_image_get_os was
> returning -ENOTSUPP and then if CONFIG_SPL_OS_BOOT was also
> defined, the spl_image->os was left set to 0 which in turn
> was skipping the fdt appending resulting in boot-up failure.
>
> Fixes: 337bbb6297775e spl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 02/20] usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGE

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:48 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in SPL,
> makes more sense to rename the SPL_USB_SUPPORT as SPL_USB_STORAGE.
> Everything that is not part of the usb storage support in SPL is now
> build under SPL_USB_HOST_SUPPORT.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 03/20] usb: ehci-mx6: Make regulator DM_REGULATOR dependent

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:47 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Do the regulator related work only if the build has the DM_REGULATOR.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 04/20] configs: imx6sabreauto: Add DM_MMC support

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:49 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Add DM_MMC config to imx6sabreauto defconfig.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 05/20] configs: imx6sabreauto: Add DM_USB support

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:47 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Add the DM support for USB. For that, DM_REGULATOR is needed.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 06/20] mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL builds

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:44 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Since the fsl_esdhc will also be used by SPL, make the
> preprocessor switches more generic to allow any kind of build.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 07/20] board: mx6sabresd: Add board_fit_config_name_match to support FIT in SPL

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:50 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> This matches one of the following three boards (or fails):
>  - imx6q-sabresd
>  - imx6qp-sabresd
>  - imx6dl-sabresd
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 08/20] board: mx6sabreauto: Add board_fit_config_name_match to support FIT in SPL

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:50 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> This matches one of the following three boards (or fails):
>  - imx6q-sabreauto
>  - imx6qp-sabreauto
>  - imx6dl-sabreauto
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 09/20] arm: dts: Add all the imx6[q|qp|dl] sabre[auto|sd] u-boot dts[i] files

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:46 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> This allows us to keep the basic dts[i] files up-to-date with
> the ones in kernel, but at the same time allowing the u-boot
> to add its own properties to the existing nodes.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 10/20] arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd]

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:45 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the ones
> from kernel v4.20 (commit 8fe28cb58bcb2).
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Acked-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 11/20] configs: mx6sabreauto: Add SPL FIT and DM support

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:48 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Enable all the necessary configs for SPL DM and FIT support for
> mx6sabreauto.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 12/20] configs: mx6sabresd: Add SPL FIT and DM support

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:47 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Enable all the necessary configs for SPL DM and FIT support for
> mx6sabresd.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 13/20] mx6sabreauto: Add DM_GPIO support

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:49 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Add the DM_GPIO related config for mx6sabreauto.
> Also add the gpio request calls.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 14/20] mx6sabresd: Add DM_GPIO support

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:46 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Add the DM_GPIO related config for mx6sabresd.
> Also add the gpio request calls.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 15/20] configs: mx6sabreauto: Add DM_SPI_FLASH necessary configs

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:48 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Enable all neceassary configs to support DM_SPI_FLASH on mx6sabreauto.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 16/20] configs: mx6sabresd: Add DM_SPI_FLASH necessary configs

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:48 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Enable all neceassary configs to support DM_SPI_FLASH on mx6sabresd.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 17/20] board: mx6sabreauto: Remove the non-DM code

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:50 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Since the mx6sabreauto has DM support, remove the unused non-DM code
> from mx6sabreauto board file.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 18/20] board: mx6sabresd: Remove non-DM code

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:51 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Since the mx6sabreauto has DM support, remove the unused non-DM code
> from mx6sabresd board file.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 19/20] board: mx6sabresd: Remove the enet reset gpio handling

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:53 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> Rely on the phy-reset-gpios which is set in imx6qdl-sabresd dtsi
> and get rid of the enet reset gpio handling from the board file.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 20/20] configs: mx6sabresd: Reduce SPL size by disabling DOS, EXT and EFI support

[Fabio Estevam]

On Fri, Feb 1, 2019 at 2:50 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> With DM and FIT enabled in SPL, there is an sram overflow. By disabling
> CONFIG_SPL_DOS_PARTITION, CONFIG_SPL_EXT_SUPPORT and
> CONFIG_SPL_EFI_PARTITION, we get to keep the 'one binary to fit all'
> for imx6[q|qp|dl] on sabresd since the final SPL image is now under 64KB.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Fabio Estevam]

Hi Abel,

On Fri, Feb 1, 2019 at 2:43 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> The third version is here:
> https://lists.denx.de/pipermail/u-boot/2019-January/356903.html
>
> So, this time I hope I got it right. Before, I was stupidly trying
> to put a fit in another fit without a really good reason. To my
> excuse, that was working even with the spl_image->os set to 0,
> bug which I (hope) I fixed in the first patch (a new one)
> of this series.

I am happy with the entire series.

One more question: do we get build error when the SPL gets larger than 64kB?

[U-Boot] [PATCH v4 02/20] usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGE

[Lukasz Majewski]

On Fri, 1 Feb 2019 16:40:07 +0000
Abel Vesa <abel.vesa@nxp.com> wrote:

> Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in
> SPL, makes more sense to rename the SPL_USB_SUPPORT as
> SPL_USB_STORAGE. Everything that is not part of the usb storage
> support in SPL is now build under SPL_USB_HOST_SUPPORT.
> 

Reviewed-by: Lukasz Majewski <lukma@denx.de>

> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
> ---
>  arch/arm/include/asm/arch-am33xx/spl.h    | 2 +-
>  arch/arm/mach-omap2/boot-common.c         | 2 +-
>  common/Makefile                           | 5 +++--
>  common/spl/Kconfig                        | 4 ++--
>  common/spl/Makefile                       | 2 +-
>  common/spl/spl_usb.c                      | 4 ----
>  configs/am43xx_evm_usbhost_boot_defconfig | 2 +-
>  configs/am43xx_hs_evm_defconfig           | 2 +-
>  8 files changed, 10 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-am33xx/spl.h
> b/arch/arm/include/asm/arch-am33xx/spl.h index 0bf8c17..f3910c2 100644
> --- a/arch/arm/include/asm/arch-am33xx/spl.h
> +++ b/arch/arm/include/asm/arch-am33xx/spl.h
> @@ -62,7 +62,7 @@
>  #define BOOT_DEVICE_CPGMAC	0x47
>  
>  #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
> -#ifdef CONFIG_SPL_USB_SUPPORT
> +#ifdef CONFIG_SPL_USB_STORAGE
>  #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_USB
>  #else
>  #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2
> diff --git a/arch/arm/mach-omap2/boot-common.c
> b/arch/arm/mach-omap2/boot-common.c index 2db1922..c8b8ac6 100644
> --- a/arch/arm/mach-omap2/boot-common.c
> +++ b/arch/arm/mach-omap2/boot-common.c
> @@ -93,7 +93,7 @@ void save_omap_boot_params(void)
>  			sys_boot_device = 1;
>  			break;
>  #endif
> -#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_SUPPORT)
> +#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_STORAGE)
>  		case BOOT_DEVICE_USB:
>  			sys_boot_device = 1;
>  			break;
> diff --git a/common/Makefile b/common/Makefile
> index ad390d0..8c92feb 100644
> --- a/common/Makefile
> +++ b/common/Makefile
> @@ -75,8 +75,9 @@ obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
>  obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
>  
>  ifdef CONFIG_SPL_USB_HOST_SUPPORT
> -obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o
> -obj-$(CONFIG_USB_STORAGE) += usb_storage.o
> +obj-y += usb.o
> +obj-y += usb_hub.o
> +obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o
>  else
>  obj-$(CONFIG_USB_MUSB_HOST) += usb.o
>  endif
> diff --git a/common/spl/Kconfig b/common/spl/Kconfig
> index 54b0dc3..8b0627e 100644
> --- a/common/spl/Kconfig
> +++ b/common/spl/Kconfig
> @@ -766,9 +766,9 @@ config SPL_USB_HOST_SUPPORT
>  	  device can be attached. This option enables the drivers in
>  	  drivers/usb/host as part of an SPL build.
>  
> -config SPL_USB_SUPPORT
> +config SPL_USB_STORAGE
>  	bool "Support loading from USB"
> -	depends on SPL_USB_HOST_SUPPORT
> +	depends on SPL_USB_HOST_SUPPORT && !(BLK && !DM_USB)
>  	help
>  	  Enable support for USB devices in SPL. This allows use of
> USB devices such as hard drives and flash drivers for loading U-Boot.
> diff --git a/common/spl/Makefile b/common/spl/Makefile
> index 6f8d759..a3980ce 100644
> --- a/common/spl/Makefile
> +++ b/common/spl/Makefile
> @@ -22,7 +22,7 @@ obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
>  obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
>  obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
>  obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
> -obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
> +obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
>  obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o
>  obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o
>  obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o
> diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
> index c8d8231..e29d579 100644
> --- a/common/spl/spl_usb.c
> +++ b/common/spl/spl_usb.c
> @@ -15,9 +15,7 @@
>  #include <usb.h>
>  #include <fat.h>
>  
> -#ifdef CONFIG_USB_STORAGE
>  static int usb_stor_curr_dev = -1; /* current device */
> -#endif
>  
>  static int spl_usb_load_image(struct spl_image_info *spl_image,
>  			      struct spl_boot_device *bootdev)
> @@ -34,13 +32,11 @@ static int spl_usb_load_image(struct
> spl_image_info *spl_image, return err;
>  	}
>  
> -#ifdef CONFIG_USB_STORAGE
>  	/* try to recognize storage devices immediately */
>  	usb_stor_curr_dev = usb_stor_scan(1);
>  	stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
> usb_stor_curr_dev); if (!stor_dev)
>  		return -ENODEV;
> -#endif
>  
>  	debug("boot mode - FAT\n");
>  
> diff --git a/configs/am43xx_evm_usbhost_boot_defconfig
> b/configs/am43xx_evm_usbhost_boot_defconfig index 5131f19..5bd919b
> 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig
> +++ b/configs/am43xx_evm_usbhost_boot_defconfig
> @@ -14,7 +14,7 @@ CONFIG_VERSION_VARIABLE=y
>  CONFIG_SPL_MTD_SUPPORT=y
>  CONFIG_SPL_OS_BOOT=y
>  CONFIG_SPL_USB_HOST_SUPPORT=y
> -CONFIG_SPL_USB_SUPPORT=y
> +CONFIG_SPL_USB_STORAGE=y
>  CONFIG_CMD_SPL=y
>  CONFIG_CMD_SPL_NAND_OFS=0x00100000
>  CONFIG_CMD_SPL_WRITE_SIZE=0x40000
> diff --git a/configs/am43xx_hs_evm_defconfig
> b/configs/am43xx_hs_evm_defconfig index 99e4ccb..c01fda9 100644
> --- a/configs/am43xx_hs_evm_defconfig
> +++ b/configs/am43xx_hs_evm_defconfig
> @@ -24,7 +24,7 @@ CONFIG_SPL_MTD_SUPPORT=y
>  CONFIG_SPL_NET_SUPPORT=y
>  CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
>  CONFIG_SPL_USB_HOST_SUPPORT=y
> -CONFIG_SPL_USB_SUPPORT=y
> +CONFIG_SPL_USB_STORAGE=y
>  CONFIG_SPL_USB_GADGET=y
>  CONFIG_SPL_USB_ETHER=y
>  # CONFIG_CMD_FLASH is not set




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190202/0cda1f22/attachment.sig>

[U-Boot] [PATCH v4 03/20] usb: ehci-mx6: Make regulator DM_REGULATOR dependent

[Lukasz Majewski]

On Fri, 1 Feb 2019 16:40:08 +0000
Abel Vesa <abel.vesa@nxp.com> wrote:

> Do the regulator related work only if the build has the DM_REGULATOR.
> 

Yes, this part was missing for IMX6Q - especially SPL can get away with
enabling SPL_DM_REGULATOR if needed.

Reviewed-by: Lukasz Majewski <lukma@denx.de>

> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/usb/host/ehci-mx6.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
> index 1acf08d..9483947 100644
> --- a/drivers/usb/host/ehci-mx6.c
> +++ b/drivers/usb/host/ehci-mx6.c
> @@ -404,6 +404,7 @@ static int mx6_init_after_reset(struct ehci_ctrl
> *dev) if (ret)
>  		return ret;
>  
> +#if CONFIG_IS_ENABLED(DM_REGULATOR)
>  	if (priv->vbus_supply) {
>  		ret = regulator_set_enable(priv->vbus_supply,
>  					   (type ==
> USB_INIT_DEVICE) ? @@ -413,6 +414,7 @@ static int
> mx6_init_after_reset(struct ehci_ctrl *dev) return ret;
>  		}
>  	}
> +#endif
>  
>  	if (type == USB_INIT_DEVICE)
>  		return 0;
> @@ -514,15 +516,17 @@ static int ehci_usb_probe(struct udevice *dev)
>  	priv->portnr = dev->seq;
>  	priv->init_type = type;
>  
> +#if CONFIG_IS_ENABLED(DM_REGULATOR)
>  	ret = device_get_supply_regulator(dev, "vbus-supply",
>  					  &priv->vbus_supply);
>  	if (ret)
>  		debug("%s: No vbus supply\n", dev->name);
> -
> +#endif
>  	ret = ehci_mx6_common_init(ehci, priv->portnr);
>  	if (ret)
>  		return ret;
>  
> +#if CONFIG_IS_ENABLED(DM_REGULATOR)
>  	if (priv->vbus_supply) {
>  		ret = regulator_set_enable(priv->vbus_supply,
>  					   (type ==
> USB_INIT_DEVICE) ? @@ -532,6 +536,7 @@ static int
> ehci_usb_probe(struct udevice *dev) return ret;
>  		}
>  	}
> +#endif
>  
>  	if (priv->init_type == USB_INIT_HOST) {
>  		setbits_le32(&ehci->usbmode, CM_HOST);




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190202/586863e1/attachment.sig>

[U-Boot] [PATCH v4 06/20] mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL builds

[Lukasz Majewski]

On Fri, 1 Feb 2019 16:40:11 +0000
Abel Vesa <abel.vesa@nxp.com> wrote:

> Since the fsl_esdhc will also be used by SPL, make the
> preprocessor switches more generic to allow any kind of build.
> 

The same here - as with ehci-mx6.
Thanks Abel for this patch.

Reviewed-by: Lukasz Majewski <lukma@denx.de>

> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  drivers/mmc/fsl_esdhc.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 21fa2ab..9e34557 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -804,7 +804,7 @@ static int esdhc_set_voltage(struct mmc *mmc)
>  	case MMC_SIGNAL_VOLTAGE_330:
>  		if (priv->vs18_enable)
>  			return -EIO;
> -#ifdef CONFIG_DM_REGULATOR
> +#if CONFIG_IS_ENABLED(DM_REGULATOR)
>  		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
>  			ret = regulator_set_value(priv->vqmmc_dev,
> 3300000); if (ret) {
> @@ -823,7 +823,7 @@ static int esdhc_set_voltage(struct mmc *mmc)
>  
>  		return -EAGAIN;
>  	case MMC_SIGNAL_VOLTAGE_180:
> -#ifdef CONFIG_DM_REGULATOR
> +#if CONFIG_IS_ENABLED(DM_REGULATOR)
>  		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
>  			ret = regulator_set_value(priv->vqmmc_dev,
> 1800000); if (ret) {
> @@ -1442,7 +1442,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
>  	int node = dev_of_offset(dev);
>  	struct esdhc_soc_data *data =
>  		(struct esdhc_soc_data *)dev_get_driver_data(dev);
> -#ifdef CONFIG_DM_REGULATOR
> +#if CONFIG_IS_ENABLED(DM_REGULATOR)
>  	struct udevice *vqmmc_dev;
>  #endif
>  	fdt_addr_t addr;
> @@ -1500,7 +1500,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
>  
>  	priv->vs18_enable = 0;
>  
> -#ifdef CONFIG_DM_REGULATOR
> +#if CONFIG_IS_ENABLED(DM_REGULATOR)
>  	/*
>  	 * If emmc I/O has a fixed voltage at 1.8V, this must be
> provided,
>  	 * otherwise, emmc will work abnormally.




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190202/df6e5e61/attachment.sig>

[U-Boot] [PATCH v4 07/20] board: mx6sabresd: Add board_fit_config_name_match to support FIT in SPL

[Lukasz Majewski]

On Fri, 1 Feb 2019 16:40:12 +0000
Abel Vesa <abel.vesa@nxp.com> wrote:

> This matches one of the following three boards (or fails):
>  - imx6q-sabresd
>  - imx6qp-sabresd
>  - imx6dl-sabresd
> 

Reviewed-by: Lukasz Majewski <lukma@denx.de>

> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> ---
>  board/freescale/mx6sabresd/mx6sabresd.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
> b/board/freescale/mx6sabresd/mx6sabresd.c index 0183ede..4688095
> 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c
> +++ b/board/freescale/mx6sabresd/mx6sabresd.c
> @@ -1062,3 +1062,21 @@ void board_init_f(ulong dummy)
>  	board_init_r(NULL, 0);
>  }
>  #endif
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +	if (is_mx6dq()) {
> +		if (!strcmp(name, "imx6q-sabresd"))
> +			return 0;
> +	} else if (is_mx6dqp()) {
> +		if (!strcmp(name, "imx6qp-sabresd"))
> +			return 0;
> +	} else if (is_mx6dl()) {
> +		if (!strcmp(name, "imx6dl-sabresd"))
> +			return 0;
> +	}
> +
> +	return -1;
> +}
> +#endif




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190202/3f12a3e0/attachment.sig>

[U-Boot] [PATCH v4 08/20] board: mx6sabreauto: Add board_fit_config_name_match to support FIT in SPL

[Lukasz Majewski]

On Fri, 1 Feb 2019 16:40:13 +0000
Abel Vesa <abel.vesa@nxp.com> wrote:

> This matches one of the following three boards (or fails):
>  - imx6q-sabreauto
>  - imx6qp-sabreauto
>  - imx6dl-sabreauto
> 

Reviewed-by: Lukasz Majewski <lukma@denx.de>

> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> ---
>  board/freescale/mx6sabreauto/mx6sabreauto.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c
> b/board/freescale/mx6sabreauto/mx6sabreauto.c index c1bef85..c8f1263
> 100644 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c
> +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
> @@ -1097,3 +1097,21 @@ void board_init_f(ulong dummy)
>  	board_init_r(NULL, 0);
>  }
>  #endif
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +	if (is_mx6dq()) {
> +		if (!strcmp(name, "imx6q-sabreauto"))
> +			return 0;
> +	} else if (is_mx6dqp()) {
> +		if (!strcmp(name, "imx6qp-sabreauto"))
> +			return 0;
> +	} else if (is_mx6dl()) {
> +		if (!strcmp(name, "imx6dl-sabreauto"))
> +			return 0;
> +	}
> +
> +	return -1;
> +}
> +#endif




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190202/45c8c1dd/attachment.sig>

[U-Boot] [PATCH v4 09/20] arm: dts: Add all the imx6[q|qp|dl] sabre[auto|sd] u-boot dts[i] files

[Lukasz Majewski]

On Fri, 1 Feb 2019 16:40:14 +0000
Abel Vesa <abel.vesa@nxp.com> wrote:

> This allows us to keep the basic dts[i] files up-to-date with
> the ones in kernel, but at the same time allowing the u-boot
> to add its own properties to the existing nodes.
> 

Reviewed-by: Lukasz Majewski <lukma@denx.de>

> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi  |  6 ++++++
>  arch/arm/dts/imx6dl-sabresd-u-boot.dtsi    |  6 ++++++
>  arch/arm/dts/imx6q-sabreauto-u-boot.dtsi   |  6 ++++++
>  arch/arm/dts/imx6q-sabresd-u-boot.dtsi     |  6 ++++++
>  arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi | 21 +++++++++++++++++++++
>  arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi   | 14 ++++++++++++++
>  arch/arm/dts/imx6qdl-u-boot.dtsi           |  4 ++--
>  arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi  |  6 ++++++
>  arch/arm/dts/imx6qp-sabresd-u-boot.dtsi    |  6 ++++++
>  9 files changed, 73 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi
>  create mode 100644 arch/arm/dts/imx6dl-sabresd-u-boot.dtsi
>  create mode 100644 arch/arm/dts/imx6q-sabreauto-u-boot.dtsi
>  create mode 100644 arch/arm/dts/imx6q-sabresd-u-boot.dtsi
>  create mode 100644 arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi
>  create mode 100644 arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi
>  create mode 100644 arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi
>  create mode 100644 arch/arm/dts/imx6qp-sabresd-u-boot.dtsi
> 
> diff --git a/arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi
> b/arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi new file mode 100644
> index 0000000..d75fcc1
> --- /dev/null
> +++ b/arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 NXP
> + */
> +
> +#include "imx6qdl-sabreauto-u-boot.dtsi"
> diff --git a/arch/arm/dts/imx6dl-sabresd-u-boot.dtsi
> b/arch/arm/dts/imx6dl-sabresd-u-boot.dtsi new file mode 100644
> index 0000000..e4d7d28
> --- /dev/null
> +++ b/arch/arm/dts/imx6dl-sabresd-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 NXP
> + */
> +
> +#include "imx6qdl-sabresd-u-boot.dtsi"
> diff --git a/arch/arm/dts/imx6q-sabreauto-u-boot.dtsi
> b/arch/arm/dts/imx6q-sabreauto-u-boot.dtsi new file mode 100644
> index 0000000..d75fcc1
> --- /dev/null
> +++ b/arch/arm/dts/imx6q-sabreauto-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 NXP
> + */
> +
> +#include "imx6qdl-sabreauto-u-boot.dtsi"
> diff --git a/arch/arm/dts/imx6q-sabresd-u-boot.dtsi
> b/arch/arm/dts/imx6q-sabresd-u-boot.dtsi new file mode 100644
> index 0000000..e4d7d28
> --- /dev/null
> +++ b/arch/arm/dts/imx6q-sabresd-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 NXP
> + */
> +
> +#include "imx6qdl-sabresd-u-boot.dtsi"
> diff --git a/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi
> b/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi new file mode 100644
> index 0000000..ea90f40
> --- /dev/null
> +++ b/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 NXP
> + */
> +
> +#include "imx6qdl-u-boot.dtsi"
> +
> +/ {
> +	aliases {
> +		mmc0 = &usdhc3;
> +	};
> +};
> +
> +&usdhc3 {
> +	no-1-8-v;
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc3 {
> +	u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi
> b/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi new file mode 100644
> index 0000000..45f02b1
> --- /dev/null
> +++ b/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 NXP
> + */
> +
> +#include "imx6qdl-u-boot.dtsi"
> +
> +&usdhc3 {
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc3 {
> +	u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/imx6qdl-u-boot.dtsi
> b/arch/arm/dts/imx6qdl-u-boot.dtsi index dffc21b..45ae2fa 100644
> --- a/arch/arm/dts/imx6qdl-u-boot.dtsi
> +++ b/arch/arm/dts/imx6qdl-u-boot.dtsi
> @@ -7,11 +7,11 @@
>  	soc {
>  		u-boot,dm-spl;
>  
> -		aips-bus at 02000000 {
> +		aips-bus at 2000000 {
>  			u-boot,dm-spl;
>  		};
>  
> -		aips-bus at 02100000 {
> +		aips-bus at 2100000 {
>  			u-boot,dm-spl;
>  		};
>  	};
> diff --git a/arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi
> b/arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi new file mode 100644
> index 0000000..d75fcc1
> --- /dev/null
> +++ b/arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 NXP
> + */
> +
> +#include "imx6qdl-sabreauto-u-boot.dtsi"
> diff --git a/arch/arm/dts/imx6qp-sabresd-u-boot.dtsi
> b/arch/arm/dts/imx6qp-sabresd-u-boot.dtsi new file mode 100644
> index 0000000..e4d7d28
> --- /dev/null
> +++ b/arch/arm/dts/imx6qp-sabresd-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 NXP
> + */
> +
> +#include "imx6qdl-sabresd-u-boot.dtsi"




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190202/96e447d7/attachment.sig>

[U-Boot] [PATCH v4 10/20] arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd]

[Lukasz Majewski]

On Fri, 1 Feb 2019 16:40:16 +0000
Abel Vesa <abel.vesa@nxp.com> wrote:

> Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the
> ones from kernel v4.20 (commit 8fe28cb58bcb2).
> 

Reviewed-by: Lukasz Majewski <lukma@denx.de>

> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Acked-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/dts/Makefile               |   8 +-
>  arch/arm/dts/imx6dl-sabreauto.dts   |  13 +
>  arch/arm/dts/imx6dl-sabresd.dts     |  18 +
>  arch/arm/dts/imx6dl.dtsi            | 306 ++++++++++++--
>  arch/arm/dts/imx6q-sabreauto.dts    |  18 +
>  arch/arm/dts/imx6q-sabresd.dts      |  23 +
>  arch/arm/dts/imx6q.dtsi             | 310 ++++++++++++--
>  arch/arm/dts/imx6qdl-sabreauto.dtsi | 810
> ++++++++++++++++++++++++++++++++++++
> arch/arm/dts/imx6qdl-sabresd.dtsi   | 741
> +++++++++++++++++++++++++++++++++ arch/arm/dts/imx6qdl.dtsi
> | 455 +++++++++++--------- arch/arm/dts/imx6qp-sabreauto.dts   |  55
> +++ arch/arm/dts/imx6qp-sabresd.dts     |  55 +++
> arch/arm/dts/imx6qp.dtsi            | 115 +++++ 13 files changed,
> 2669 insertions(+), 258 deletions(-) create mode 100644
> arch/arm/dts/imx6dl-sabreauto.dts create mode 100644
> arch/arm/dts/imx6dl-sabresd.dts create mode 100644
> arch/arm/dts/imx6q-sabreauto.dts create mode 100644
> arch/arm/dts/imx6q-sabresd.dts create mode 100644
> arch/arm/dts/imx6qdl-sabreauto.dtsi create mode 100644
> arch/arm/dts/imx6qdl-sabresd.dtsi create mode 100644
> arch/arm/dts/imx6qp-sabreauto.dts create mode 100644
> arch/arm/dts/imx6qp-sabresd.dts create mode 100644
> arch/arm/dts/imx6qp.dtsi
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 46f1d69..e8512af 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -443,7 +443,13 @@ dtb-$(CONFIG_MX6QDL) += \
>  	imx6q-icore.dtb \
>  	imx6q-icore-mipi.dtb \
>  	imx6q-icore-rqs.dtb \
> -	imx6q-logicpd.dtb
> +	imx6q-logicpd.dtb \
> +	imx6q-sabreauto.dtb \
> +	imx6q-sabresd.dtb \
> +	imx6dl-sabreauto.dtb \
> +	imx6dl-sabresd.dtb \
> +	imx6qp-sabreauto.dtb \
> +	imx6qp-sabresd.dtb
>  
>  dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
>  
> diff --git a/arch/arm/dts/imx6dl-sabreauto.dts
> b/arch/arm/dts/imx6dl-sabreauto.dts new file mode 100644
> index 0000000..660d52a
> --- /dev/null
> +++ b/arch/arm/dts/imx6dl-sabreauto.dts
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (C) 2013 Freescale Semiconductor, Inc.
> +
> +/dts-v1/;
> +
> +#include "imx6dl.dtsi"
> +#include "imx6qdl-sabreauto.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 DualLite/Solo SABRE Automotive
> Board";
> +	compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
> +};
> diff --git a/arch/arm/dts/imx6dl-sabresd.dts
> b/arch/arm/dts/imx6dl-sabresd.dts new file mode 100644
> index 0000000..cd6bbf2
> --- /dev/null
> +++ b/arch/arm/dts/imx6dl-sabresd.dts
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (C) 2013 Freescale Semiconductor, Inc.
> +
> +/dts-v1/;
> +
> +#include "imx6dl.dtsi"
> +#include "imx6qdl-sabresd.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
> +	compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
> +};
> +
> +&ipu1_csi1_from_ipu1_csi1_mux {
> +	clock-lanes = <0>;
> +	data-lanes = <1 2>;
> +};
> diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
> index 9a4c22c..f0607eb 100644
> --- a/arch/arm/dts/imx6dl.dtsi
> +++ b/arch/arm/dts/imx6dl.dtsi
> @@ -1,12 +1,6 @@
> -
> -/*
> - * Copyright 2013 Freescale Semiconductor, Inc.
> - *
> - * This program is free software; you can redistribute it and/or
> modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - *
> - */
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright 2013 Freescale Semiconductor, Inc.
>  
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include "imx6dl-pinfunc.h"
> @@ -39,6 +33,7 @@
>  				396000	1175000
>  			>;  
>  			clock-latency = <61036>; /* two CLK32
> periods */
> +			#cooling-cells = <2>;
>  			clocks = <&clks IMX6QDL_CLK_ARM>,
>  				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
>  				 <&clks IMX6QDL_CLK_STEP>,
> @@ -56,39 +51,57 @@
>  			device_type = "cpu";
>  			reg = <1>;
>  			next-level-cache = <&L2>;
> +			operating-points = <
> +				/* kHz    uV */
> +				996000  1250000
> +				792000  1175000
> +				396000  1150000
> +			>;
> +			fsl,soc-operating-points = <
> +				/* ARM kHz  SOC-PU uV */
> +				996000	1175000
> +				792000	1175000
> +				396000	1175000
> +			>;
> +			clock-latency = <61036>; /* two CLK32
> periods */
> +			clocks = <&clks IMX6QDL_CLK_ARM>,
> +				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
> +				 <&clks IMX6QDL_CLK_STEP>,
> +				 <&clks IMX6QDL_CLK_PLL1_SW>,
> +				 <&clks IMX6QDL_CLK_PLL1_SYS>;
> +			clock-names = "arm", "pll2_pfd2_396m",
> "step",
> +				      "pll1_sw", "pll1_sys";
> +			arm-supply = <&reg_arm>;
> +			pu-supply = <&reg_pu>;
> +			soc-supply = <&reg_soc>;
>  		};
>  	};
>  
>  	soc {
> -		ocram: sram at 00900000 {
> +		ocram: sram at 900000 {
>  			compatible = "mmio-sram";
>  			reg = <0x00900000 0x20000>;
>  			clocks = <&clks IMX6QDL_CLK_OCRAM>;
>  		};
>  
> -		aips1: aips-bus at 02000000 {
> -			iomuxc: iomuxc at 020e0000 {
> +		aips1: aips-bus at 2000000 {
> +			iomuxc: iomuxc at 20e0000 {
>  				compatible = "fsl,imx6dl-iomuxc";
>  			};
>  
> -			pxp: pxp at 020f0000 {
> +			pxp: pxp at 20f0000 {
>  				reg = <0x020f0000 0x4000>;
>  				interrupts = <0 98
> IRQ_TYPE_LEVEL_HIGH>; };
>  
> -			epdc: epdc at 020f4000 {
> +			epdc: epdc at 20f4000 {
>  				reg = <0x020f4000 0x4000>;
>  				interrupts = <0 97
> IRQ_TYPE_LEVEL_HIGH>; };
> -
> -			lcdif: lcdif at 020f8000 {
> -				reg = <0x020f8000 0x4000>;
> -				interrupts = <0 39
> IRQ_TYPE_LEVEL_HIGH>;
> -			};
>  		};
>  
> -		aips2: aips-bus at 02100000 {
> -			i2c4: i2c at 021f8000 {
> +		aips2: aips-bus at 2100000 {
> +			i2c4: i2c at 21f8000 {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
>  				compatible = "fsl,imx6q-i2c",
> "fsl,imx21-i2c"; @@ -100,14 +113,177 @@
>  		};
>  	};
>  
> +	capture-subsystem {
> +		compatible = "fsl,imx-capture-subsystem";
> +		ports = <&ipu1_csi0>, <&ipu1_csi1>;
> +	};
> +
>  	display-subsystem {
>  		compatible = "fsl,imx-display-subsystem";
>  		ports = <&ipu1_di0>, <&ipu1_di1>;
>  	};
> +};
> +
> +&gpio1 {
> +	gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>,
> <&iomuxc 10 189 2>,
> +		      <&iomuxc 12 194 1>, <&iomuxc 13 193 1>,
> <&iomuxc 14 192 1>,
> +		      <&iomuxc 15 191 1>, <&iomuxc 16 185 2>,
> <&iomuxc 18 184 1>,
> +		      <&iomuxc 19 187 1>, <&iomuxc 20 183 1>,
> <&iomuxc 21 188 1>,
> +		      <&iomuxc 22 123 3>, <&iomuxc 25 121 1>,
> <&iomuxc 26 127 1>,
> +		      <&iomuxc 27 126 1>, <&iomuxc 28 128 1>,
> <&iomuxc 29 130 1>,
> +		      <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
> +};
> +
> +&gpio2 {
> +	gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>,
> <&iomuxc 16  74 1>,
> +		      <&iomuxc 17  73 1>, <&iomuxc 18  72 1>,
> <&iomuxc 19  71 1>,
> +		      <&iomuxc 20  70 1>, <&iomuxc 21  69 1>,
> <&iomuxc 22  68 1>,
> +		      <&iomuxc 23  79 2>, <&iomuxc 25 118 2>,
> <&iomuxc 27 117 1>,
> +		      <&iomuxc 28 113 4>;
> +};
> +
> +&gpio3 {
> +	gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>,
> <&iomuxc 10 99 6>,
> +		      <&iomuxc 16 81 16>;
> +};
> +
> +&gpio4 {
> +	gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>,
> <&iomuxc  7 150 1>,
> +		      <&iomuxc  8 146 1>, <&iomuxc  9 151 1>,
> <&iomuxc 10 147 1>,
> +		      <&iomuxc 11 152 1>, <&iomuxc 12 148 1>,
> <&iomuxc 13 153 1>,
> +		      <&iomuxc 14 149 1>, <&iomuxc 15 154 1>,
> <&iomuxc 16  39 7>,
> +		      <&iomuxc 23  56 1>, <&iomuxc 24  61 7>,
> <&iomuxc 31  46 1>; +};
>  
> -	gpu-subsystem {
> -		compatible = "fsl,imx-gpu-subsystem";
> -		cores = <&gpu_2d>, <&gpu_3d>;
> +&gpio5 {
> +	gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>,
> <&iomuxc  4 76 1>,
> +		      <&iomuxc  5  47 9>, <&iomuxc 14 57 4>,
> <&iomuxc 18 37 1>,
> +		      <&iomuxc 19  36 1>, <&iomuxc 20 35 1>,
> <&iomuxc 21 38 1>,
> +		      <&iomuxc 22  29 6>, <&iomuxc 28 19 4>;
> +};
> +
> +&gpio6 {
> +	gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>,
> <&iomuxc  7 156 1>,
> +		      <&iomuxc  8 155 1>, <&iomuxc  9 170 1>,
> <&iomuxc 10 169 1>,
> +		      <&iomuxc 11 157 1>, <&iomuxc 14 158 3>,
> <&iomuxc 17 204 1>,
> +		      <&iomuxc 18 203 1>, <&iomuxc 19 182 1>,
> <&iomuxc 20 177 4>,
> +		      <&iomuxc 24 175 1>, <&iomuxc 25 171 1>,
> <&iomuxc 26 181 1>,
> +		      <&iomuxc 27 172 3>, <&iomuxc 30 176 1>,
> <&iomuxc 31  78 1>; +};
> +
> +&gpio7 {
> +	gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>,
> <&iomuxc  2 196 1>,
> +		      <&iomuxc 3 195 1>, <&iomuxc  4 197 4>,
> <&iomuxc  8 205 1>,
> +		      <&iomuxc 9 207 1>, <&iomuxc 10 206 1>,
> <&iomuxc 11 133 3>; +};
> +
> +&gpr {
> +	ipu1_csi0_mux {
> +		compatible = "video-mux";
> +		mux-controls = <&mux 0>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port at 0 {
> +			reg = <0>;
> +
> +			ipu1_csi0_mux_from_mipi_vc0: endpoint {
> +				remote-endpoint =
> <&mipi_vc0_to_ipu1_csi0_mux>;
> +			};
> +		};
> +
> +		port at 1 {
> +			reg = <1>;
> +
> +			ipu1_csi0_mux_from_mipi_vc1: endpoint {
> +				remote-endpoint =
> <&mipi_vc1_to_ipu1_csi0_mux>;
> +			};
> +		};
> +
> +		port at 2 {
> +			reg = <2>;
> +
> +			ipu1_csi0_mux_from_mipi_vc2: endpoint {
> +				remote-endpoint =
> <&mipi_vc2_to_ipu1_csi0_mux>;
> +			};
> +		};
> +
> +		port at 3 {
> +			reg = <3>;
> +
> +			ipu1_csi0_mux_from_mipi_vc3: endpoint {
> +				remote-endpoint =
> <&mipi_vc3_to_ipu1_csi0_mux>;
> +			};
> +		};
> +
> +		port at 4 {
> +			reg = <4>;
> +
> +			ipu1_csi0_mux_from_parallel_sensor: endpoint
> {
> +			};
> +		};
> +
> +		port at 5 {
> +			reg = <5>;
> +
> +			ipu1_csi0_mux_to_ipu1_csi0: endpoint {
> +				remote-endpoint =
> <&ipu1_csi0_from_ipu1_csi0_mux>;
> +			};
> +		};
> +	};
> +
> +	ipu1_csi1_mux {
> +		compatible = "video-mux";
> +		mux-controls = <&mux 1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port at 0 {
> +			reg = <0>;
> +
> +			ipu1_csi1_mux_from_mipi_vc0: endpoint {
> +				remote-endpoint =
> <&mipi_vc0_to_ipu1_csi1_mux>;
> +			};
> +		};
> +
> +		port at 1 {
> +			reg = <1>;
> +
> +			ipu1_csi1_mux_from_mipi_vc1: endpoint {
> +				remote-endpoint =
> <&mipi_vc1_to_ipu1_csi1_mux>;
> +			};
> +		};
> +
> +		port at 2 {
> +			reg = <2>;
> +
> +			ipu1_csi1_mux_from_mipi_vc2: endpoint {
> +				remote-endpoint =
> <&mipi_vc2_to_ipu1_csi1_mux>;
> +			};
> +		};
> +
> +		port at 3 {
> +			reg = <3>;
> +
> +			ipu1_csi1_mux_from_mipi_vc3: endpoint {
> +				remote-endpoint =
> <&mipi_vc3_to_ipu1_csi1_mux>;
> +			};
> +		};
> +
> +		port at 4 {
> +			reg = <4>;
> +
> +			ipu1_csi1_mux_from_parallel_sensor: endpoint
> {
> +			};
> +		};
> +
> +		port at 5 {
> +			reg = <5>;
> +
> +			ipu1_csi1_mux_to_ipu1_csi1: endpoint {
> +				remote-endpoint =
> <&ipu1_csi1_from_ipu1_csi1_mux>;
> +			};
> +		};
>  	};
>  };
>  
> @@ -119,6 +295,12 @@
>  	compatible = "fsl,imx6dl-hdmi";
>  };
>  
> +&ipu1_csi1 {
> +	ipu1_csi1_from_ipu1_csi1_mux: endpoint {
> +		remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
> +	};
> +};
> +
>  &ldb {
>  	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks
> IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks
> IMX6QDL_CLK_IPU1_DI1_SEL>, @@ -128,6 +310,82 @@
>  		      "di0", "di1";
>  };
>  
> +&mipi_csi {
> +	port at 1 {
> +		reg = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		mipi_vc0_to_ipu1_csi0_mux: endpoint at 0 {
> +			reg = <0>;
> +			remote-endpoint =
> <&ipu1_csi0_mux_from_mipi_vc0>;
> +		};
> +
> +		mipi_vc0_to_ipu1_csi1_mux: endpoint at 1 {
> +			reg = <1>;
> +			remote-endpoint =
> <&ipu1_csi1_mux_from_mipi_vc0>;
> +		};
> +	};
> +
> +	port at 2 {
> +		reg = <2>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		mipi_vc1_to_ipu1_csi0_mux: endpoint at 0 {
> +			reg = <0>;
> +			remote-endpoint =
> <&ipu1_csi0_mux_from_mipi_vc1>;
> +		};
> +
> +		mipi_vc1_to_ipu1_csi1_mux: endpoint at 1 {
> +			reg = <1>;
> +			remote-endpoint =
> <&ipu1_csi1_mux_from_mipi_vc1>;
> +		};
> +	};
> +
> +	port at 3 {
> +		reg = <3>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		mipi_vc2_to_ipu1_csi0_mux: endpoint at 0 {
> +			reg = <0>;
> +			remote-endpoint =
> <&ipu1_csi0_mux_from_mipi_vc2>;
> +		};
> +
> +		mipi_vc2_to_ipu1_csi1_mux: endpoint at 1 {
> +			reg = <1>;
> +			remote-endpoint =
> <&ipu1_csi1_mux_from_mipi_vc2>;
> +		};
> +	};
> +
> +	port at 4 {
> +		reg = <4>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		mipi_vc3_to_ipu1_csi0_mux: endpoint at 0 {
> +			reg = <0>;
> +			remote-endpoint =
> <&ipu1_csi0_mux_from_mipi_vc3>;
> +		};
> +
> +		mipi_vc3_to_ipu1_csi1_mux: endpoint at 1 {
> +			reg = <1>;
> +			remote-endpoint =
> <&ipu1_csi1_mux_from_mipi_vc3>;
> +		};
> +	};
> +};
> +
> +&mux {
> +	mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
> +			<0x34 0x00000038>, /* IPU_CSI1_MUX */
> +			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
> +			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
> +			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
> +			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
> +			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
> +};
> +
>  &vpu {
>  	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
>  };
> diff --git a/arch/arm/dts/imx6q-sabreauto.dts
> b/arch/arm/dts/imx6q-sabreauto.dts new file mode 100644
> index 0000000..6e981a3
> --- /dev/null
> +++ b/arch/arm/dts/imx6q-sabreauto.dts
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2012 Freescale Semiconductor, Inc.
> +// Copyright 2011 Linaro Ltd.
> +
> +/dts-v1/;
> +
> +#include "imx6q.dtsi"
> +#include "imx6qdl-sabreauto.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 Quad SABRE Automotive Board";
> +	compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
> +};
> +
> +&sata {
> +	status = "okay";
> +};
> diff --git a/arch/arm/dts/imx6q-sabresd.dts
> b/arch/arm/dts/imx6q-sabresd.dts new file mode 100644
> index 0000000..eec9446
> --- /dev/null
> +++ b/arch/arm/dts/imx6q-sabresd.dts
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2012 Freescale Semiconductor, Inc.
> +// Copyright 2011 Linaro Ltd.
> +
> +/dts-v1/;
> +
> +#include "imx6q.dtsi"
> +#include "imx6qdl-sabresd.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 Quad SABRE Smart Device Board";
> +	compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
> +};
> +
> +&sata {
> +	status = "okay";
> +};
> +
> +&ipu1_csi1_from_mipi_vc1 {
> +	clock-lanes = <0>;
> +	data-lanes = <1 2>;
> +};
> diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
> index c30c836..8381d24 100644
> --- a/arch/arm/dts/imx6q.dtsi
> +++ b/arch/arm/dts/imx6q.dtsi
> @@ -1,12 +1,6 @@
> -
> -/*
> - * Copyright 2013 Freescale Semiconductor, Inc.
> - *
> - * This program is free software; you can redistribute it and/or
> modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - *
> - */
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright 2013 Freescale Semiconductor, Inc.
>  
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include "imx6q-pinfunc.h"
> @@ -44,6 +38,7 @@
>  				396000	1175000
>  			>;  
>  			clock-latency = <61036>; /* two CLK32
> periods */
> +			#cooling-cells = <2>;
>  			clocks = <&clks IMX6QDL_CLK_ARM>,
>  				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
>  				 <&clks IMX6QDL_CLK_STEP>,
> @@ -56,38 +51,119 @@
>  			soc-supply = <&reg_soc>;
>  		};
>  
> -		cpu at 1 {
> +		cpu1: cpu at 1 {
>  			compatible = "arm,cortex-a9";
>  			device_type = "cpu";
>  			reg = <1>;
>  			next-level-cache = <&L2>;
> +			operating-points = <
> +				/* kHz    uV */
> +				1200000 1275000
> +				996000  1250000
> +				852000  1250000
> +				792000  1175000
> +				396000  975000
> +			>;
> +			fsl,soc-operating-points = <
> +				/* ARM kHz  SOC-PU uV */
> +				1200000 1275000
> +				996000	1250000
> +				852000	1250000
> +				792000	1175000
> +				396000	1175000
> +			>;
> +			clock-latency = <61036>; /* two CLK32
> periods */
> +			clocks = <&clks IMX6QDL_CLK_ARM>,
> +				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
> +				 <&clks IMX6QDL_CLK_STEP>,
> +				 <&clks IMX6QDL_CLK_PLL1_SW>,
> +				 <&clks IMX6QDL_CLK_PLL1_SYS>;
> +			clock-names = "arm", "pll2_pfd2_396m",
> "step",
> +				      "pll1_sw", "pll1_sys";
> +			arm-supply = <&reg_arm>;
> +			pu-supply = <&reg_pu>;
> +			soc-supply = <&reg_soc>;
>  		};
>  
> -		cpu at 2 {
> +		cpu2: cpu at 2 {
>  			compatible = "arm,cortex-a9";
>  			device_type = "cpu";
>  			reg = <2>;
>  			next-level-cache = <&L2>;
> +			operating-points = <
> +				/* kHz    uV */
> +				1200000 1275000
> +				996000  1250000
> +				852000  1250000
> +				792000  1175000
> +				396000  975000
> +			>;
> +			fsl,soc-operating-points = <
> +				/* ARM kHz  SOC-PU uV */
> +				1200000 1275000
> +				996000	1250000
> +				852000	1250000
> +				792000	1175000
> +				396000	1175000
> +			>;
> +			clock-latency = <61036>; /* two CLK32
> periods */
> +			clocks = <&clks IMX6QDL_CLK_ARM>,
> +				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
> +				 <&clks IMX6QDL_CLK_STEP>,
> +				 <&clks IMX6QDL_CLK_PLL1_SW>,
> +				 <&clks IMX6QDL_CLK_PLL1_SYS>;
> +			clock-names = "arm", "pll2_pfd2_396m",
> "step",
> +				      "pll1_sw", "pll1_sys";
> +			arm-supply = <&reg_arm>;
> +			pu-supply = <&reg_pu>;
> +			soc-supply = <&reg_soc>;
>  		};
>  
> -		cpu at 3 {
> +		cpu3: cpu at 3 {
>  			compatible = "arm,cortex-a9";
>  			device_type = "cpu";
>  			reg = <3>;
>  			next-level-cache = <&L2>;
> +			operating-points = <
> +				/* kHz    uV */
> +				1200000 1275000
> +				996000  1250000
> +				852000  1250000
> +				792000  1175000
> +				396000  975000
> +			>;
> +			fsl,soc-operating-points = <
> +				/* ARM kHz  SOC-PU uV */
> +				1200000 1275000
> +				996000	1250000
> +				852000	1250000
> +				792000	1175000
> +				396000	1175000
> +			>;
> +			clock-latency = <61036>; /* two CLK32
> periods */
> +			clocks = <&clks IMX6QDL_CLK_ARM>,
> +				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
> +				 <&clks IMX6QDL_CLK_STEP>,
> +				 <&clks IMX6QDL_CLK_PLL1_SW>,
> +				 <&clks IMX6QDL_CLK_PLL1_SYS>;
> +			clock-names = "arm", "pll2_pfd2_396m",
> "step",
> +				      "pll1_sw", "pll1_sys";
> +			arm-supply = <&reg_arm>;
> +			pu-supply = <&reg_pu>;
> +			soc-supply = <&reg_soc>;
>  		};
>  	};
>  
>  	soc {
> -		ocram: sram at 00900000 {
> +		ocram: sram at 900000 {
>  			compatible = "mmio-sram";
>  			reg = <0x00900000 0x40000>;
>  			clocks = <&clks IMX6QDL_CLK_OCRAM>;
>  		};
>  
> -		aips-bus at 02000000 { /* AIPS1 */
> -			spba-bus at 02000000 {
> -				ecspi5: ecspi at 02018000 {
> +		aips-bus at 2000000 { /* AIPS1 */
> +			spba-bus at 2000000 {
> +				ecspi5: spi at 2018000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  					compatible =
> "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -96,18 +172,18 @@
>  					clocks = <&clks
> IMX6Q_CLK_ECSPI5>, <&clks IMX6Q_CLK_ECSPI5>;
>  					clock-names = "ipg", "per";
> -					dmas = <&sdma 11 7 1>,
> <&sdma 12 7 2>;
> +					dmas = <&sdma 11 8 1>,
> <&sdma 12 8 2>; dma-names = "rx", "tx";
>  					status = "disabled";
>  				};
>  			};
>  
> -			iomuxc: iomuxc at 020e0000 {
> +			iomuxc: iomuxc at 20e0000 {
>  				compatible = "fsl,imx6q-iomuxc";
>  			};
>  		};
>  
> -		sata: sata at 02200000 {
> +		sata: sata at 2200000 {
>  			compatible = "fsl,imx6q-ahci";
>  			reg = <0x02200000 0x4000>;
>  			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
> @@ -118,17 +194,17 @@
>  			status = "disabled";
>  		};
>  
> -		gpu_vg: gpu at 02204000 {
> +		gpu_vg: gpu at 2204000 {
>  			compatible = "vivante,gc";
>  			reg = <0x02204000 0x4000>;
>  			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
>  				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
>  			clock-names = "bus", "core";
> -			power-domains = <&gpc 1>;
> +			power-domains = <&pd_pu>;
>  		};
>  
> -		ipu2: ipu at 02800000 {
> +		ipu2: ipu at 2800000 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			compatible = "fsl,imx6q-ipu";
> @@ -143,10 +219,18 @@
>  
>  			ipu2_csi0: port at 0 {
>  				reg = <0>;
> +
> +				ipu2_csi0_from_mipi_vc2: endpoint {
> +					remote-endpoint =
> <&mipi_vc2_to_ipu2_csi0>;
> +				};
>  			};
>  
>  			ipu2_csi1: port at 1 {
>  				reg = <1>;
> +
> +				ipu2_csi1_from_ipu2_csi1_mux:
> endpoint {
> +					remote-endpoint =
> <&ipu2_csi1_mux_to_ipu2_csi1>;
> +				};
>  			};
>  
>  			ipu2_di0: port at 2 {
> @@ -154,22 +238,27 @@
>  				#size-cells = <0>;
>  				reg = <2>;
>  
> -				ipu2_di0_disp0: disp0-endpoint {
> +				ipu2_di0_disp0: endpoint at 0 {
> +					reg = <0>;
>  				};
>  
> -				ipu2_di0_hdmi: hdmi-endpoint {
> +				ipu2_di0_hdmi: endpoint at 1 {
> +					reg = <1>;
>  					remote-endpoint =
> <&hdmi_mux_2>; };
>  
> -				ipu2_di0_mipi: mipi-endpoint {
> +				ipu2_di0_mipi: endpoint at 2 {
> +					reg = <2>;
>  					remote-endpoint =
> <&mipi_mux_2>; };
>  
> -				ipu2_di0_lvds0: lvds0-endpoint {
> +				ipu2_di0_lvds0: endpoint at 3 {
> +					reg = <3>;
>  					remote-endpoint =
> <&lvds0_mux_2>; };
>  
> -				ipu2_di0_lvds1: lvds1-endpoint {
> +				ipu2_di0_lvds1: endpoint at 4 {
> +					reg = <4>;
>  					remote-endpoint =
> <&lvds1_mux_2>; };
>  			};
> @@ -179,33 +268,136 @@
>  				#size-cells = <0>;
>  				reg = <3>;
>  
> -				ipu2_di1_hdmi: hdmi-endpoint {
> +				ipu2_di1_hdmi: endpoint at 1 {
> +					reg = <1>;
>  					remote-endpoint =
> <&hdmi_mux_3>; };
>  
> -				ipu2_di1_mipi: mipi-endpoint {
> +				ipu2_di1_mipi: endpoint at 2 {
> +					reg = <2>;
>  					remote-endpoint =
> <&mipi_mux_3>; };
>  
> -				ipu2_di1_lvds0: lvds0-endpoint {
> +				ipu2_di1_lvds0: endpoint at 3 {
> +					reg = <3>;
>  					remote-endpoint =
> <&lvds0_mux_3>; };
>  
> -				ipu2_di1_lvds1: lvds1-endpoint {
> +				ipu2_di1_lvds1: endpoint at 4 {
> +					reg = <4>;
>  					remote-endpoint =
> <&lvds1_mux_3>; };
>  			};
>  		};
>  	};
>  
> +	capture-subsystem {
> +		compatible = "fsl,imx-capture-subsystem";
> +		ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>,
> <&ipu2_csi1>;
> +	};
> +
>  	display-subsystem {
>  		compatible = "fsl,imx-display-subsystem";
>  		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>,
> <&ipu2_di1>; };
> +};
> +
> +&gpio1 {
> +	gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>,
> <&iomuxc  3 139 1>,
> +		      <&iomuxc  4 142  2>, <&iomuxc  6 140 1>,
> <&iomuxc  7 144 2>,
> +		      <&iomuxc  9 138  1>, <&iomuxc 10 213 3>,
> <&iomuxc 13  20 1>,
> +		      <&iomuxc 14  19  1>, <&iomuxc 15  21 1>,
> <&iomuxc 16 208 1>,
> +		      <&iomuxc 17 207  1>, <&iomuxc 18 210 3>,
> <&iomuxc 21 209 1>,
> +		      <&iomuxc 22 116 10>;
> +};
> +
> +&gpio2 {
> +	gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>,
> <&iomuxc 30 35 1>,
> +		      <&iomuxc 31  44  1>;
> +};
> +
> +&gpio3 {
> +	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc
> 24 45 8>; +};
> +
> +&gpio4 {
> +	gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>,
> <&iomuxc 16 87 16>; +};
> +
> +&gpio5 {
> +	gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>,
> <&iomuxc 4 53 1>,
> +		      <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
> +};
> +
> +&gpio6 {
> +	gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>,
> <&iomuxc  7 181  5>,
> +		      <&iomuxc 14 186 3>, <&iomuxc 17 170 2>,
> <&iomuxc 19  22 12>,
> +		      <&iomuxc 31  86 1>;
> +};
> +
> +&gpio7 {
> +	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc
> 11 146 3>; +};
> +
> +&gpr {
> +	ipu1_csi0_mux {
> +		compatible = "video-mux";
> +		mux-controls = <&mux 0>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port at 0 {
> +			reg = <0>;
> +
> +			ipu1_csi0_mux_from_mipi_vc0: endpoint {
> +				remote-endpoint =
> <&mipi_vc0_to_ipu1_csi0_mux>;
> +			};
> +		};
> +
> +		port at 1 {
> +			reg = <1>;
> +
> +			ipu1_csi0_mux_from_parallel_sensor: endpoint
> {
> +			};
> +		};
>  
> -	gpu-subsystem {
> -		compatible = "fsl,imx-gpu-subsystem";
> -		cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
> +		port at 2 {
> +			reg = <2>;
> +
> +			ipu1_csi0_mux_to_ipu1_csi0: endpoint {
> +				remote-endpoint =
> <&ipu1_csi0_from_ipu1_csi0_mux>;
> +			};
> +		};
> +	};
> +
> +	ipu2_csi1_mux {
> +		compatible = "video-mux";
> +		mux-controls = <&mux 1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port at 0 {
> +			reg = <0>;
> +
> +			ipu2_csi1_mux_from_mipi_vc3: endpoint {
> +				remote-endpoint =
> <&mipi_vc3_to_ipu2_csi1_mux>;
> +			};
> +		};
> +
> +		port at 1 {
> +			reg = <1>;
> +
> +			ipu2_csi1_mux_from_parallel_sensor: endpoint
> {
> +			};
> +		};
> +
> +		port at 2 {
> +			reg = <2>;
> +
> +			ipu2_csi1_mux_to_ipu2_csi1: endpoint {
> +				remote-endpoint =
> <&ipu2_csi1_from_ipu2_csi1_mux>;
> +			};
> +		};
>  	};
>  };
>  
> @@ -229,6 +421,12 @@
>  	};
>  };
>  
> +&ipu1_csi1 {
> +	ipu1_csi1_from_mipi_vc1: endpoint {
> +		remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
> +	};
> +};
> +
>  &ldb {
>  	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks
> IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks
> IMX6QDL_CLK_IPU1_DI1_SEL>, @@ -275,6 +473,40 @@
>  	};
>  };
>  
> +&mipi_csi {
> +	port at 1 {
> +		reg = <1>;
> +
> +		mipi_vc0_to_ipu1_csi0_mux: endpoint {
> +			remote-endpoint =
> <&ipu1_csi0_mux_from_mipi_vc0>;
> +		};
> +	};
> +
> +	port at 2 {
> +		reg = <2>;
> +
> +		mipi_vc1_to_ipu1_csi1: endpoint {
> +			remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
> +		};
> +	};
> +
> +	port at 3 {
> +		reg = <3>;
> +
> +		mipi_vc2_to_ipu2_csi0: endpoint {
> +			remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
> +		};
> +	};
> +
> +	port at 4 {
> +		reg = <4>;
> +
> +		mipi_vc3_to_ipu2_csi1_mux: endpoint {
> +			remote-endpoint =
> <&ipu2_csi1_mux_from_mipi_vc3>;
> +		};
> +	};
> +};
> +
>  &mipi_dsi {
>  	ports {
>  		port at 2 {
> @@ -295,6 +527,16 @@
>  	};
>  };
>  
> +&mux {
> +	mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
> +			<0x04 0x00100000>, /* MIPI_IPU2_MUX */
> +			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
> +			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
> +			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
> +			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
> +			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
> +};
> +
>  &vpu {
>  	compatible = "fsl,imx6q-vpu", "cnm,coda960";
>  };
> diff --git a/arch/arm/dts/imx6qdl-sabreauto.dtsi
> b/arch/arm/dts/imx6qdl-sabreauto.dtsi new file mode 100644
> index 0000000..a6dc5c4
> --- /dev/null
> +++ b/arch/arm/dts/imx6qdl-sabreauto.dtsi
> @@ -0,0 +1,810 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2012 Freescale Semiconductor, Inc.
> +// Copyright 2011 Linaro Ltd.
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +	chosen {
> +		stdout-path = &uart4;
> +	};
> +
> +	memory at 10000000 {
> +		reg = <0x10000000 0x80000000>;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_gpio_leds>;
> +
> +		user {
> +			label = "debug";
> +			gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_gpio_keys>;
> +
> +		home {
> +			label = "Home";
> +			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_HOME>;
> +			wakeup-source;
> +		};
> +
> +		back {
> +			label = "Back";
> +			gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_BACK>;
> +			wakeup-source;
> +		};
> +
> +		program {
> +			label = "Program";
> +			gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_PROGRAM>;
> +			wakeup-source;
> +		};
> +
> +		volume-up {
> +			label = "Volume Up";
> +			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_VOLUMEUP>;
> +			wakeup-source;
> +		};
> +
> +		volume-down {
> +			label = "Volume Down";
> +			gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_VOLUMEDOWN>;
> +			wakeup-source;
> +		};
> +	};
> +
> +	clocks {
> +		codec_osc: anaclk2 {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <24576000>;
> +		};
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		reg_audio: regulator at 0 {
> +			compatible = "regulator-fixed";
> +			reg = <0>;
> +			regulator-name = "cs42888_supply";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +		};
> +
> +		reg_usb_h1_vbus: regulator at 1 {
> +			compatible = "regulator-fixed";
> +			reg = <1>;
> +			regulator-name = "usb_h1_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +		};
> +
> +		reg_usb_otg_vbus: regulator at 2 {
> +			compatible = "regulator-fixed";
> +			reg = <2>;
> +			regulator-name = "usb_otg_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +		};
> +	};
> +
> +	sound-cs42888 {
> +		compatible = "fsl,imx6-sabreauto-cs42888",
> +			"fsl,imx-audio-cs42888";
> +		model = "imx-cs42888";
> +		audio-cpu = <&esai>;
> +		audio-asrc = <&asrc>;
> +		audio-codec = <&codec>;
> +		audio-routing =
> +			"Line Out Jack", "AOUT1L",
> +			"Line Out Jack", "AOUT1R",
> +			"Line Out Jack", "AOUT2L",
> +			"Line Out Jack", "AOUT2R",
> +			"Line Out Jack", "AOUT3L",
> +			"Line Out Jack", "AOUT3R",
> +			"Line Out Jack", "AOUT4L",
> +			"Line Out Jack", "AOUT4R",
> +			"AIN1L", "Line In Jack",
> +			"AIN1R", "Line In Jack",
> +			"AIN2L", "Line In Jack",
> +			"AIN2R", "Line In Jack";
> +	};
> +
> +	sound-spdif {
> +		compatible = "fsl,imx-audio-spdif",
> +			   "fsl,imx-sabreauto-spdif";
> +		model = "imx-spdif";
> +		spdif-controller = <&spdif>;
> +		spdif-in;
> +	};
> +
> +	backlight {
> +		compatible = "pwm-backlight";
> +		pwms = <&pwm3 0 5000000>;
> +		brightness-levels = <0 4 8 16 32 64 128 255>;
> +		default-brightness-level = <7>;
> +		status = "okay";
> +	};
> +
> +	i2cmux {
> +		compatible = "i2c-mux-gpio";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_i2c3mux>;
> +		mux-gpios = <&gpio5 4 0>;
> +		i2c-parent = <&i2c3>;
> +		idle-state = <0>;
> +
> +		i2c at 1 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <1>;
> +
> +			adv7180: camera at 21 {
> +				compatible = "adi,adv7180";
> +				reg = <0x21>;
> +				powerdown-gpios = <&max7310_b 2
> GPIO_ACTIVE_LOW>;
> +				interrupt-parent = <&gpio1>;
> +				interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
> +
> +				port {
> +					adv7180_to_ipu1_csi0_mux:
> endpoint {
> +						remote-endpoint =
> <&ipu1_csi0_mux_from_parallel_sensor>;
> +						bus-width = <8>;
> +					};
> +				};
> +			};
> +
> +			max7310_a: gpio at 30 {
> +				compatible = "maxim,max7310";
> +				reg = <0x30>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +			};
> +
> +			max7310_b: gpio at 32 {
> +				compatible = "maxim,max7310";
> +				reg = <0x32>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_max7310>;
> +				reset-gpios = <&gpio1 15
> GPIO_ACTIVE_LOW>;
> +			};
> +
> +			max7310_c: gpio at 34 {
> +				compatible = "maxim,max7310";
> +				reg = <0x34>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +			};
> +
> +			light-sensor at 44 {
> +				compatible = "isil,isl29023";
> +				reg = <0x44>;
> +				interrupt-parent = <&gpio5>;
> +				interrupts = <17
> IRQ_TYPE_EDGE_FALLING>;
> +			};
> +
> +			magnetometer at e {
> +				compatible = "fsl,mag3110";
> +				reg = <0x0e>;
> +				interrupt-parent = <&gpio2>;
> +				interrupts = <29
> IRQ_TYPE_EDGE_RISING>;
> +			};
> +
> +			accelerometer at 1c {
> +				compatible = "fsl,mma8451";
> +				reg = <0x1c>;
> +				interrupt-parent = <&gpio6>;
> +				interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
> +			};
> +		};
> +	};
> +};
> +
> +&ipu1_csi0_from_ipu1_csi0_mux {
> +	bus-width = <8>;
> +};
> +
> +&ipu1_csi0_mux_from_parallel_sensor {
> +	remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
> +	bus-width = <8>;
> +};
> +
> +&ipu1_csi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ipu1_csi0>;
> +};
> +
> +&clks {
> +	assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
> +			  <&clks IMX6QDL_PLL4_BYPASS>,
> +			  <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
> +			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
> +			  <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
> +	assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
> +				 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
> +				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
> +				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> +	assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
> +};
> +
> +&ecspi1 {
> +	cs-gpios = <&gpio3 19 0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
> +	status = "disabled"; /* pin conflict with WEIM NOR */
> +
> +	flash: m25p80 at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "st,m25p32", "jedec,spi-nor";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +	};
> +};
> +
> +&esai {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_esai>;
> +	assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
> +			  <&clks IMX6QDL_CLK_ESAI_EXTAL>;
> +	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
> +	assigned-clock-rates = <0>, <24576000>;
> +	status = "okay";
> +};
> +
> +&fec {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_enet>;
> +	phy-mode = "rgmii";
> +	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
> +			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
> +	fsl,err006687-workaround-present;
> +	status = "okay";
> +};
> +
> +&gpmi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_gpmi_nand>;
> +	status = "okay";
> +};
> +
> +&hdmi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hdmi_cec>;
> +	ddc-i2c-bus = <&i2c2>;
> +	status = "okay";
> +};
> +
> +&i2c2 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c2>;
> +	status = "okay";
> +
> +	pmic: pfuze100 at 8 {
> +		compatible = "fsl,pfuze100";
> +		reg = <0x08>;
> +
> +		regulators {
> +			sw1a_reg: sw1ab {
> +				regulator-min-microvolt = <300000>;
> +				regulator-max-microvolt = <1875000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <6250>;
> +			};
> +
> +			sw1c_reg: sw1c {
> +				regulator-min-microvolt = <300000>;
> +				regulator-max-microvolt = <1875000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <6250>;
> +			};
> +
> +			sw2_reg: sw2 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sw3a_reg: sw3a {
> +				regulator-min-microvolt = <400000>;
> +				regulator-max-microvolt = <1975000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sw3b_reg: sw3b {
> +				regulator-min-microvolt = <400000>;
> +				regulator-max-microvolt = <1975000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sw4_reg: sw4 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +
> +			swbst_reg: swbst {
> +				regulator-min-microvolt = <5000000>;
> +				regulator-max-microvolt = <5150000>;
> +			};
> +
> +			snvs_reg: vsnvs {
> +				regulator-min-microvolt = <1000000>;
> +				regulator-max-microvolt = <3000000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			vref_reg: vrefddr {
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			vgen1_reg: vgen1 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1550000>;
> +			};
> +
> +			vgen2_reg: vgen2 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1550000>;
> +			};
> +
> +			vgen3_reg: vgen3 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +
> +			vgen4_reg: vgen4 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +
> +			vgen5_reg: vgen5 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +
> +			vgen6_reg: vgen6 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +
> +	codec: cs42888 at 48 {
> +		compatible = "cirrus,cs42888";
> +		reg = <0x48>;
> +		clocks = <&codec_osc>;
> +		clock-names = "mclk";
> +		VA-supply = <&reg_audio>;
> +		VD-supply = <&reg_audio>;
> +		VLS-supply = <&reg_audio>;
> +		VLC-supply = <&reg_audio>;
> +	};
> +
> +	touchscreen at 4 {
> +		compatible = "eeti,egalax_ts";
> +		reg = <0x04>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_egalax_int>;
> +		interrupt-parent = <&gpio2>;
> +		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
> +		wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
> +	};
> +};
> +
> +&i2c3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c3>;
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog>;
> +
> +	imx6qdl-sabreauto {
> +		pinctrl_hog: hoggrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15
> 0x80000000
> +				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13
> 0x80000000
> +				MX6QDL_PAD_GPIO_18__SD3_VSELECT
> 0x17059
> +			>;
> +		};
> +
> +		pinctrl_ecspi1: ecspi1grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
> +
> MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
> +
> MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
> +			>;
> +		};
> +
> +		pinctrl_ecspi1_cs: ecspi1cs {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_D19__GPIO3_IO19
> 0x80000000
> +			>;
> +		};
> +
> +		pinctrl_egalax_int: egalax-intgrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_EIM_EB0__GPIO2_IO28		0xb0b1
> +			>;
> +		};
> +
> +		pinctrl_enet: enetgrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0
> +
> MX6QDL_PAD_KEY_COL2__ENET_MDC		0x1b0b0
> +
> MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
> +
> MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
> +
> MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
> +
> MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
> +
> MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
> +
> MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
> +
> MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
> +
> MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
> +
> MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
> +
> MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
> +
> MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
> +
> MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
> +
> MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
> +
> MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
> +			>;
> +		};
> +
> +		pinctrl_esai: esaigrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK
> 0x1b030
> +				MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS
> 0x1b030
> +				MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2
> 0x1b030
> +				MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3
> 0x1b030
> +				MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1
> 0x1b030
> +				MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0
> 0x1b030
> +				MX6QDL_PAD_GPIO_17__ESAI_TX0
> 0x1b030
> +				MX6QDL_PAD_NANDF_CS3__ESAI_TX1
> 0x1b030
> +				MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK
> 0x1b030
> +				MX6QDL_PAD_GPIO_9__ESAI_RX_FS
> 0x1b030
> +			>;
> +		};
> +
> +		pinctrl_gpio_keys: gpiokeysgrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD2_CMD__GPIO1_IO11		0x1b0b0
> +
> MX6QDL_PAD_SD2_DAT3__GPIO1_IO12		0x1b0b0
> +
> MX6QDL_PAD_SD4_DAT4__GPIO2_IO12		0x1b0b0
> +
> MX6QDL_PAD_SD4_DAT7__GPIO2_IO15		0x1b0b0
> +
> MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_gpio_leds: gpioledsgrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15	0x80000000
> +			>;
> +		};
> +
> +		pinctrl_gpmi_nand: gpminandgrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
> +
> MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
> +
> MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
> +
> MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
> +
> MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
> +
> MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
> +
> MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
> +
> MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
> +
> MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
> +
> MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
> +
> MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
> +
> MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
> +
> MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
> +
> MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
> +
> MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
> +
> MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
> +
> MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
> +			>;
> +		};
> +
> +		pinctrl_hdmi_cec: hdmicecgrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE	0x1f8b0
> +			>;
> +		};
> +
> +		pinctrl_i2c2: i2c2grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_EB2__I2C2_SCL
> 0x4001b8b1
> +				MX6QDL_PAD_KEY_ROW3__I2C2_SDA
> 0x4001b8b1
> +			>;
> +		};
> +
> +		pinctrl_i2c3: i2c3grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_GPIO_3__I2C3_SCL
> 0x4001b8b1
> +				MX6QDL_PAD_EIM_D18__I2C3_SDA
> 0x4001b8b1
> +			>;
> +		};
> +
> +		pinctrl_i2c3mux: i2c3muxgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_A24__GPIO5_IO04
> 0x0b0b1
> +			>;
> +		};
> +
> +		pinctrl_ipu1_csi0: ipu1csi0grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x1b0b0
> +
> MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
> +
> MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x1b0b0
> +
> MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_max7310: max7310grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD2_DAT0__GPIO1_IO15
> 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_pwm3: pwm1grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
> +			>;
> +		};
> +
> +		pinctrl_gpt_input_capture0: gptinputcapture0grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1	0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_gpt_input_capture1: gptinputcapture1grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2	0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_spdif: spdifgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_uart4: uart4grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
> +
> MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
> +			>;
> +		};
> +
> +		pinctrl_usbotg: usbotggrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID
> 0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc3: usdhc3grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
> +
> MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
> +
> MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
> +
> MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
> +
> MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
> +
> MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
> +
> MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
> +
> MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
> +
> MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
> +
> MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
> +
> MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
> +
> MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
> +
> MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
> +
> MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
> +
> MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
> +
> MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170b9
> +
> MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170b9
> +
> MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170b9
> +
> MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170b9
> +			>;
> +		};
> +
> +		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
> +
> MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
> +
> MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
> +
> MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
> +
> MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
> +
> MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
> +
> MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170f9
> +
> MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170f9
> +
> MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170f9
> +
> MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170f9
> +			>;
> +		};
> +
> +		pinctrl_weim_cs0: weimcs0grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_EIM_CS0__EIM_CS0_B		0xb0b1
> +			>;
> +		};
> +
> +		pinctrl_weim_nor: weimnorgrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0b1
> +
> MX6QDL_PAD_EIM_RW__EIM_RW		0xb0b1
> +
> MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B		0xb060
> +
> MX6QDL_PAD_EIM_D16__EIM_DATA16		0x1b0b0
> +
> MX6QDL_PAD_EIM_D17__EIM_DATA17		0x1b0b0
> +
> MX6QDL_PAD_EIM_D18__EIM_DATA18		0x1b0b0
> +
> MX6QDL_PAD_EIM_D19__EIM_DATA19		0x1b0b0
> +
> MX6QDL_PAD_EIM_D20__EIM_DATA20		0x1b0b0
> +
> MX6QDL_PAD_EIM_D21__EIM_DATA21		0x1b0b0
> +
> MX6QDL_PAD_EIM_D22__EIM_DATA22		0x1b0b0
> +
> MX6QDL_PAD_EIM_D23__EIM_DATA23		0x1b0b0
> +
> MX6QDL_PAD_EIM_D24__EIM_DATA24		0x1b0b0
> +
> MX6QDL_PAD_EIM_D25__EIM_DATA25		0x1b0b0
> +
> MX6QDL_PAD_EIM_D26__EIM_DATA26		0x1b0b0
> +
> MX6QDL_PAD_EIM_D27__EIM_DATA27		0x1b0b0
> +
> MX6QDL_PAD_EIM_D28__EIM_DATA28		0x1b0b0
> +
> MX6QDL_PAD_EIM_D29__EIM_DATA29		0x1b0b0
> +
> MX6QDL_PAD_EIM_D30__EIM_DATA30		0x1b0b0
> +
> MX6QDL_PAD_EIM_D31__EIM_DATA31		0x1b0b0
> +
> MX6QDL_PAD_EIM_A23__EIM_ADDR23		0xb0b1
> +
> MX6QDL_PAD_EIM_A22__EIM_ADDR22		0xb0b1
> +
> MX6QDL_PAD_EIM_A21__EIM_ADDR21		0xb0b1
> +
> MX6QDL_PAD_EIM_A20__EIM_ADDR20		0xb0b1
> +
> MX6QDL_PAD_EIM_A19__EIM_ADDR19		0xb0b1
> +
> MX6QDL_PAD_EIM_A18__EIM_ADDR18		0xb0b1
> +
> MX6QDL_PAD_EIM_A17__EIM_ADDR17		0xb0b1
> +
> MX6QDL_PAD_EIM_A16__EIM_ADDR16		0xb0b1
> +
> MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0b1
> +
> MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0b1
> +
> MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0b1
> +
> MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0b1
> +
> MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0b1
> +
> MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0b1
> +
> MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0b1
> +
> MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0b1
> +
> MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0b1
> +
> MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0b1
> +
> MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0b1
> +
> MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0b1
> +
> MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0b1
> +
> MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0b1
> +
> MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0b1
> +
> MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
> +			>;
> +		};
> +	};
> +};
> +
> +&ldb {
> +	status = "okay";
> +
> +	lvds-channel at 0 {
> +		fsl,data-mapping = "spwg";
> +		fsl,data-width = <18>;
> +		status = "okay";
> +
> +		display-timings {
> +			native-mode = <&timing0>;
> +			timing0: hsd100pxn1 {
> +				clock-frequency = <65000000>;
> +				hactive = <1024>;
> +				vactive = <768>;
> +				hback-porch = <220>;
> +				hfront-porch = <40>;
> +				vback-porch = <21>;
> +				vfront-porch = <7>;
> +				hsync-len = <60>;
> +				vsync-len = <10>;
> +			};
> +		};
> +	};
> +};
> +
> +&pwm3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pwm3>;
> +	status = "okay";
> +};
> +
> +&spdif {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_spdif>;
> +	status = "okay";
> +};
> +
> +&uart4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart4>;
> +	status = "okay";
> +};
> +
> +&usbh1 {
> +	vbus-supply = <&reg_usb_h1_vbus>;
> +	status = "okay";
> +};
> +
> +&usbotg {
> +	vbus-supply = <&reg_usb_otg_vbus>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usbotg>;
> +	status = "okay";
> +};
> +
> +&usdhc3 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc3>;
> +	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> +	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> +	cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
> +	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&weim {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
> +	ranges = <0 0 0x08000000 0x08000000>;
> +	status = "disabled"; /* pin conflict with SPI NOR */
> +
> +	nor at 0,0 {
> +		compatible = "cfi-flash";
> +		reg = <0 0 0x02000000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		bank-width = <2>;
> +		fsl,weim-cs-timing = <0x00620081 0x00000001
> 0x1c022000
> +				0x0000c000 0x1404a38e 0x00000000>;
> +	};
> +};
> diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi
> b/arch/arm/dts/imx6qdl-sabresd.dtsi new file mode 100644
> index 0000000..2cd5a9f
> --- /dev/null
> +++ b/arch/arm/dts/imx6qdl-sabresd.dtsi
> @@ -0,0 +1,741 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2012 Freescale Semiconductor, Inc.
> +// Copyright 2011 Linaro Ltd.
> +
> +#include <dt-bindings/clock/imx6qdl-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +	aliases {
> +		mmc1 = &usdhc3;
> +	};
> +
> +	chosen {
> +		stdout-path = &uart1;
> +	};
> +
> +	memory at 10000000 {
> +		reg = <0x10000000 0x40000000>;
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		reg_usb_otg_vbus: regulator at 0 {
> +			compatible = "regulator-fixed";
> +			reg = <0>;
> +			regulator-name = "usb_otg_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio3 22 0>;
> +			enable-active-high;
> +			vin-supply = <&swbst_reg>;
> +		};
> +
> +		reg_usb_h1_vbus: regulator at 1 {
> +			compatible = "regulator-fixed";
> +			reg = <1>;
> +			regulator-name = "usb_h1_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio1 29 0>;
> +			enable-active-high;
> +			vin-supply = <&swbst_reg>;
> +		};
> +
> +		reg_audio: regulator at 2 {
> +			compatible = "regulator-fixed";
> +			reg = <2>;
> +			regulator-name = "wm8962-supply";
> +			gpio = <&gpio4 10 0>;
> +			enable-active-high;
> +		};
> +
> +		reg_pcie: regulator at 3 {
> +			compatible = "regulator-fixed";
> +			reg = <3>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&pinctrl_pcie_reg>;
> +			regulator-name = "MPCIE_3V3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			gpio = <&gpio3 19 0>;
> +			enable-active-high;
> +		};
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_gpio_keys>;
> +
> +		power {
> +			label = "Power Button";
> +			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +			linux,code = <KEY_POWER>;
> +		};
> +
> +		volume-up {
> +			label = "Volume Up";
> +			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +			linux,code = <KEY_VOLUMEUP>;
> +		};
> +
> +		volume-down {
> +			label = "Volume Down";
> +			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +			linux,code = <KEY_VOLUMEDOWN>;
> +		};
> +	};
> +
> +	sound {
> +		compatible = "fsl,imx6q-sabresd-wm8962",
> +			   "fsl,imx-audio-wm8962";
> +		model = "wm8962-audio";
> +		ssi-controller = <&ssi2>;
> +		audio-codec = <&codec>;
> +		audio-routing =
> +			"Headphone Jack", "HPOUTL",
> +			"Headphone Jack", "HPOUTR",
> +			"Ext Spk", "SPKOUTL",
> +			"Ext Spk", "SPKOUTR",
> +			"AMIC", "MICBIAS",
> +			"IN3R", "AMIC";
> +		mux-int-port = <2>;
> +		mux-ext-port = <3>;
> +	};
> +
> +	backlight_lvds: backlight-lvds {
> +		compatible = "pwm-backlight";
> +		pwms = <&pwm1 0 5000000>;
> +		brightness-levels = <0 4 8 16 32 64 128 255>;
> +		default-brightness-level = <7>;
> +		status = "okay";
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_gpio_leds>;
> +
> +		red {
> +			gpios = <&gpio1 2 0>;
> +			default-state = "on";
> +		};
> +	};
> +
> +	panel {
> +		compatible = "hannstar,hsd100pxn1";
> +		backlight = <&backlight_lvds>;
> +
> +		port {
> +			panel_in: endpoint {
> +				remote-endpoint = <&lvds0_out>;
> +			};
> +		};
> +	};
> +};
> +
> +&ipu1_csi0_from_ipu1_csi0_mux {
> +	bus-width = <8>;
> +	data-shift = <12>; /* Lines 19:12 used */
> +	hsync-active = <1>;
> +	vsync-active = <1>;
> +};
> +
> +&ipu1_csi0_mux_from_parallel_sensor {
> +	remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
> +};
> +
> +&ipu1_csi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ipu1_csi0>;
> +};
> +
> +&mipi_csi {
> +	status = "okay";
> +
> +	port at 0 {
> +		reg = <0>;
> +
> +		mipi_csi2_in: endpoint {
> +			remote-endpoint = <&ov5640_to_mipi_csi2>;
> +			clock-lanes = <0>;
> +			data-lanes = <1 2>;
> +		};
> +	};
> +};
> +
> +&audmux {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_audmux>;
> +	status = "okay";
> +};
> +
> +&clks {
> +	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
> +			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
> +	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
> +				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> +};
> +
> +&ecspi1 {
> +	cs-gpios = <&gpio4 9 0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ecspi1>;
> +	status = "okay";
> +
> +	flash: m25p80 at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "st,m25p32", "jedec,spi-nor";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +	};
> +};
> +
> +&fec {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_enet>;
> +	phy-mode = "rgmii";
> +	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
> +	status = "okay";
> +};
> +
> +&hdmi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hdmi_cec>;
> +	ddc-i2c-bus = <&i2c2>;
> +	status = "okay";
> +};
> +
> +&i2c1 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c1>;
> +	status = "okay";
> +
> +	codec: wm8962 at 1a {
> +		compatible = "wlf,wm8962";
> +		reg = <0x1a>;
> +		clocks = <&clks IMX6QDL_CLK_CKO>;
> +		DCVDD-supply = <&reg_audio>;
> +		DBVDD-supply = <&reg_audio>;
> +		AVDD-supply = <&reg_audio>;
> +		CPVDD-supply = <&reg_audio>;
> +		MICVDD-supply = <&reg_audio>;
> +		PLLVDD-supply = <&reg_audio>;
> +		SPKVDD1-supply = <&reg_audio>;
> +		SPKVDD2-supply = <&reg_audio>;
> +		gpio-cfg = <
> +			0x0000 /* 0:Default */
> +			0x0000 /* 1:Default */
> +			0x0013 /* 2:FN_DMICCLK */
> +			0x0000 /* 3:Default */
> +			0x8014 /* 4:FN_DMICCDAT */
> +			0x0000 /* 5:Default */
> +		>;
> +	};
> +
> +	ov5642: camera at 3c {
> +		compatible = "ovti,ov5642";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_ov5642>;
> +		clocks = <&clks IMX6QDL_CLK_CKO>;
> +		clock-names = "xclk";
> +		reg = <0x3c>;
> +		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
> +		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is
> VGEN3
> +						rev B board is VGEN5
> */
> +		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
> +		powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
> +		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
> +		status = "disabled";
> +
> +		port {
> +			ov5642_to_ipu1_csi0_mux: endpoint {
> +				remote-endpoint =
> <&ipu1_csi0_mux_from_parallel_sensor>;
> +				bus-width = <8>;
> +				hsync-active = <1>;
> +				vsync-active = <1>;
> +			};
> +		};
> +	};
> +};
> +
> +&i2c2 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c2>;
> +	status = "okay";
> +
> +	ov5640: camera at 3c {
> +		compatible = "ovti,ov5640";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_ov5640>;
> +		reg = <0x3c>;
> +		clocks = <&clks IMX6QDL_CLK_CKO>;
> +		clock-names = "xclk";
> +		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
> +		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is
> VGEN3
> +						rev B board is VGEN5
> */
> +		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
> +		powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
> +		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
> +
> +		port {
> +			ov5640_to_mipi_csi2: endpoint {
> +				remote-endpoint = <&mipi_csi2_in>;
> +				clock-lanes = <0>;
> +				data-lanes = <1 2>;
> +			};
> +		};
> +	};
> +
> +	pmic: pfuze100 at 8 {
> +		compatible = "fsl,pfuze100";
> +		reg = <0x08>;
> +
> +		regulators {
> +			sw1a_reg: sw1ab {
> +				regulator-min-microvolt = <300000>;
> +				regulator-max-microvolt = <1875000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <6250>;
> +			};
> +
> +			sw1c_reg: sw1c {
> +				regulator-min-microvolt = <300000>;
> +				regulator-max-microvolt = <1875000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <6250>;
> +			};
> +
> +			sw2_reg: sw2 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <6250>;
> +			};
> +
> +			sw3a_reg: sw3a {
> +				regulator-min-microvolt = <400000>;
> +				regulator-max-microvolt = <1975000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sw3b_reg: sw3b {
> +				regulator-min-microvolt = <400000>;
> +				regulator-max-microvolt = <1975000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sw4_reg: sw4 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +
> +			swbst_reg: swbst {
> +				regulator-min-microvolt = <5000000>;
> +				regulator-max-microvolt = <5150000>;
> +			};
> +
> +			snvs_reg: vsnvs {
> +				regulator-min-microvolt = <1000000>;
> +				regulator-max-microvolt = <3000000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			vref_reg: vrefddr {
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			vgen1_reg: vgen1 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1550000>;
> +			};
> +
> +			vgen2_reg: vgen2 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1550000>;
> +			};
> +
> +			vgen3_reg: vgen3 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +
> +			vgen4_reg: vgen4 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +
> +			vgen5_reg: vgen5 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +
> +			vgen6_reg: vgen6 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +};
> +
> +&i2c3 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c3>;
> +	status = "okay";
> +
> +	egalax_ts at 4 {
> +		compatible = "eeti,egalax_ts";
> +		reg = <0x04>;
> +		interrupt-parent = <&gpio6>;
> +		interrupts = <7 2>;
> +		wakeup-gpios = <&gpio6 7 0>;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog>;
> +
> +	imx6qdl-sabresd {
> +		pinctrl_hog: hoggrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_NANDF_D0__GPIO2_IO00
> 0x1b0b0
> +				MX6QDL_PAD_NANDF_D1__GPIO2_IO01
> 0x1b0b0
> +				MX6QDL_PAD_NANDF_D2__GPIO2_IO02
> 0x1b0b0
> +				MX6QDL_PAD_NANDF_D3__GPIO2_IO03
> 0x1b0b0
> +				MX6QDL_PAD_GPIO_0__CCM_CLKO1
> 0x130b0
> +				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07
> 0x1b0b0
> +				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29
> 0x1b0b0
> +				MX6QDL_PAD_EIM_D22__GPIO3_IO22
> 0x1b0b0
> +				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25
> 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_audmux: audmuxgrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
> +
> MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
> +
> MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
> +
> MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
> +			>;
> +		};
> +
> +		pinctrl_ecspi1: ecspi1grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
> +
> MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
> +
> MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
> +
> MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_enet: enetgrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
> +
> MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
> +
> MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
> +
> MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
> +
> MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
> +
> MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
> +
> MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
> +
> MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
> +
> MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
> +
> MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
> +
> MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
> +
> MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
> +
> MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
> +
> MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
> +
> MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
> +
> MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
> +			>;
> +		};
> +
> +		pinctrl_gpio_keys: gpio_keysgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_D29__GPIO3_IO29
> 0x1b0b0
> +				MX6QDL_PAD_GPIO_4__GPIO1_IO04
> 0x1b0b0
> +				MX6QDL_PAD_GPIO_5__GPIO1_IO05
> 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_hdmi_cec: hdmicecgrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	0x1f8b0
> +			>;
> +		};
> +
> +		pinctrl_i2c1: i2c1grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
> +
> MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
> +			>;
> +		};
> +
> +		pinctrl_i2c2: i2c2grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
> +
> MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
> +			>;
> +		};
> +
> +		pinctrl_i2c3: i2c3grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
> +
> MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
> +			>;
> +		};
> +
> +		pinctrl_ipu1_csi0: ipu1csi0grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
> +
> MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
> +
> MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
> +
> MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
> +
> MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_ov5640: ov5640grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD1_DAT2__GPIO1_IO19
> 0x1b0b0
> +				MX6QDL_PAD_SD1_CLK__GPIO1_IO20
> 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_ov5642: ov5642grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16
> 0x1b0b0
> +				MX6QDL_PAD_SD1_DAT1__GPIO1_IO17
> 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_pcie: pciegrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_pcie_reg: pciereggrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_pwm1: pwm1grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
> +			>;
> +		};
> +
> +		pinctrl_uart1: uart1grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
> +
> MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
> +			>;
> +		};
> +
> +		pinctrl_usbotg: usbotggrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc2: usdhc2grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
> +
> MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
> +
> MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
> +
> MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
> +
> MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
> +
> MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
> +
> MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
> +
> MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
> +
> MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
> +
> MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc3: usdhc3grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
> +
> MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
> +
> MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
> +
> MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
> +
> MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
> +
> MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
> +
> MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
> +
> MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
> +
> MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
> +
> MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc4: usdhc4grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
> +
> MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
> +
> MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
> +
> MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
> +
> MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
> +
> MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
> +
> MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
> +
> MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
> +
> MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
> +
> MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
> +			>;
> +		};
> +
> +		pinctrl_wdog: wdoggrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_GPIO_1__WDOG2_B		0x1b0b0
> +			>;
> +		};
> +	};
> +
> +	gpio_leds {
> +		pinctrl_gpio_leds: gpioledsgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
> +			>;
> +		};
> +	};
> +};
> +
> +&ldb {
> +	status = "okay";
> +
> +	lvds-channel at 1 {
> +		fsl,data-mapping = "spwg";
> +		fsl,data-width = <18>;
> +		status = "okay";
> +
> +		port at 4 {
> +			reg = <4>;
> +
> +			lvds0_out: endpoint {
> +				remote-endpoint = <&panel_in>;
> +			};
> +		};
> +	};
> +};
> +
> +&pcie {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pcie>;
> +	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
> +	vpcie-supply = <&reg_pcie>;
> +	status = "okay";
> +};
> +
> +&pwm1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pwm1>;
> +	status = "okay";
> +};
> +
> +&reg_arm {
> +       vin-supply = <&sw1a_reg>;
> +};
> +
> +&reg_pu {
> +       vin-supply = <&sw1c_reg>;
> +};
> +
> +&reg_soc {
> +       vin-supply = <&sw1c_reg>;
> +};
> +
> +&snvs_poweroff {
> +	status = "okay";
> +};
> +
> +&ssi2 {
> +	status = "okay";
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	status = "okay";
> +};
> +
> +&usbh1 {
> +	vbus-supply = <&reg_usb_h1_vbus>;
> +	status = "okay";
> +};
> +
> +&usbotg {
> +	vbus-supply = <&reg_usb_otg_vbus>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usbotg>;
> +	disable-over-current;
> +	status = "okay";
> +};
> +
> +&usdhc2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc2>;
> +	bus-width = <8>;
> +	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
> +	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&usdhc3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc3>;
> +	bus-width = <8>;
> +	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
> +	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&usdhc4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc4>;
> +	bus-width = <8>;
> +	non-removable;
> +	no-1-8-v;
> +	status = "okay";
> +};
> +
> +&wdog1 {
> +	status = "disabled";
> +};
> +
> +&wdog2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_wdog>;
> +	fsl,ext-reset-output;
> +	status = "okay";
> +};
> diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
> index b13b0b2..e4daf15 100644
> --- a/arch/arm/dts/imx6qdl.dtsi
> +++ b/arch/arm/dts/imx6qdl.dtsi
> @@ -1,21 +1,23 @@
> -/*
> - * Copyright 2011 Freescale Semiconductor, Inc.
> - * Copyright 2011 Linaro Ltd.
> - *
> - * The code contained herein is licensed under the GNU General Public
> - * License. You may obtain a copy of the GNU General Public License
> - * Version 2 or later at the following locations:
> - *
> - * http://www.opensource.org/licenses/gpl-license.html
> - * http://www.gnu.org/copyleft/gpl.html
> - */
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2011 Freescale Semiconductor, Inc.
> +// Copyright 2011 Linaro Ltd.
>  
>  #include <dt-bindings/clock/imx6qdl-clock.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  
> -#include "skeleton.dtsi"
> -
>  / {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	/*
> +	 * The decompressor and also some bootloaders rely on a
> +	 * pre-existing /chosen node to be available to insert the
> +	 * command line and merge other ATAGS info.
> +	 * Also for U-Boot there must be a pre-existing /memory node.
> +	 */
> +	chosen {};
> +	memory { device_type = "memory"; };
> +
>  	aliases {
>  		ethernet0 = &fec;
>  		can0 = &can1;
> @@ -49,9 +51,6 @@
>  	};
>  
>  	clocks {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
>  		ckil {
>  			compatible = "fsl,imx-ckil", "fixed-clock";
>  			#clock-cells = <0>;
> @@ -71,6 +70,75 @@
>  		};
>  	};
>  
> +	tempmon: tempmon {
> +		compatible = "fsl,imx6q-tempmon";
> +		interrupt-parent = <&gpc>;
> +		interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
> +		fsl,tempmon = <&anatop>;
> +		fsl,tempmon-data = <&ocotp>;
> +		clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> +	};
> +
> +	ldb: ldb {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
> +		gpr = <&gpr>;
> +		status = "disabled";
> +
> +		lvds-channel at 0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0>;
> +			status = "disabled";
> +
> +			port at 0 {
> +				reg = <0>;
> +
> +				lvds0_mux_0: endpoint {
> +					remote-endpoint =
> <&ipu1_di0_lvds0>;
> +				};
> +			};
> +
> +			port at 1 {
> +				reg = <1>;
> +
> +				lvds0_mux_1: endpoint {
> +					remote-endpoint =
> <&ipu1_di1_lvds0>;
> +				};
> +			};
> +		};
> +
> +		lvds-channel at 1 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <1>;
> +			status = "disabled";
> +
> +			port at 0 {
> +				reg = <0>;
> +
> +				lvds1_mux_0: endpoint {
> +					remote-endpoint =
> <&ipu1_di0_lvds1>;
> +				};
> +			};
> +
> +			port at 1 {
> +				reg = <1>;
> +
> +				lvds1_mux_1: endpoint {
> +					remote-endpoint =
> <&ipu1_di1_lvds1>;
> +				};
> +			};
> +		};
> +	};
> +
> +	pmu: pmu {
> +		compatible = "arm,cortex-a9-pmu";
> +		interrupt-parent = <&gpc>;
> +		interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
>  	soc {
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> @@ -78,7 +146,7 @@
>  		interrupt-parent = <&gpc>;
>  		ranges;
>  
> -		dma_apbh: dma-apbh at 00110000 {
> +		dma_apbh: dma-apbh at 110000 {
>  			compatible = "fsl,imx6q-dma-apbh",
> "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>;
>  			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
> @@ -91,7 +159,7 @@
>  			clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
>  		};
>  
> -		gpmi: gpmi-nand at 00112000 {
> +		gpmi: gpmi-nand at 112000 {
>  			compatible = "fsl,imx6q-gpmi-nand";
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> @@ -111,7 +179,7 @@
>  			status = "disabled";
>  		};
>  
> -		hdmi: hdmi at 0120000 {
> +		hdmi: hdmi at 120000 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			reg = <0x00120000 0x9000>;
> @@ -139,7 +207,7 @@
>  			};
>  		};
>  
> -		gpu_3d: gpu at 00130000 {
> +		gpu_3d: gpu at 130000 {
>  			compatible = "vivante,gc";
>  			reg = <0x00130000 0x4000>;
>  			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
> @@ -147,20 +215,20 @@
>  				 <&clks IMX6QDL_CLK_GPU3D_CORE>,
>  				 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
>  			clock-names = "bus", "core", "shader";
> -			power-domains = <&gpc 1>;
> +			power-domains = <&pd_pu>;
>  		};
>  
> -		gpu_2d: gpu at 00134000 {
> +		gpu_2d: gpu at 134000 {
>  			compatible = "vivante,gc";
>  			reg = <0x00134000 0x4000>;
>  			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
>  				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
>  			clock-names = "bus", "core";
> -			power-domains = <&gpc 1>;
> +			power-domains = <&pd_pu>;
>  		};
>  
> -		timer at 00a00600 {
> +		timer at a00600 {
>  			compatible = "arm,cortex-a9-twd-timer";
>  			reg = <0x00a00600 0x20>;
>  			interrupts = <1 13 0xf01>;
> @@ -168,7 +236,7 @@
>  			clocks = <&clks IMX6QDL_CLK_TWD>;
>  		};
>  
> -		intc: interrupt-controller at 00a01000 {
> +		intc: interrupt-controller at a01000 {
>  			compatible = "arm,cortex-a9-gic";
>  			#interrupt-cells = <3>;
>  			interrupt-controller;
> @@ -177,7 +245,7 @@
>  			interrupt-parent = <&intc>;
>  		};
>  
> -		L2: l2-cache at 00a02000 {
> +		L2: l2-cache at a02000 {
>  			compatible = "arm,pl310-cache";
>  			reg = <0x00a02000 0x1000>;
>  			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
> @@ -188,7 +256,7 @@
>  			arm,shared-override;
>  		};
>  
> -		pcie: pcie at 0x01000000 {
> +		pcie: pcie at 1ffc000 {
>  			compatible = "fsl,imx6q-pcie",
> "snps,dw-pcie"; reg = <0x01ffc000 0x04000>,
>  			      <0x01f00000 0x80000>;
> @@ -196,6 +264,7 @@
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> +			bus-range = <0x00 0xff>;
>  			ranges = <0x81000000 0 0          0x01f80000
> 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000
> 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>;
> @@ -204,9 +273,9 @@
>  			#interrupt-cells = <1>;
>  			interrupt-map-mask = <0 0 0 0x7>;
>  			interrupt-map = <0 0 0 1 &gpc GIC_SPI 123
> IRQ_TYPE_LEVEL_HIGH>,
> -			                <0 0 0 2 &gpc GIC_SPI 122
> IRQ_TYPE_LEVEL_HIGH>,
> -			                <0 0 0 3 &gpc GIC_SPI 121
> IRQ_TYPE_LEVEL_HIGH>,
> -			                <0 0 0 4 &gpc GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> +					<0 0 0 2 &gpc GIC_SPI 122
> IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &gpc GIC_SPI 121
> IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &gpc GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
>  				 <&clks IMX6QDL_CLK_LVDS1_GATE>,
>  				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
> @@ -214,26 +283,21 @@
>  			status = "disabled";
>  		};
>  
> -		pmu {
> -			compatible = "arm,cortex-a9-pmu";
> -			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
> -		};
> -
> -		aips-bus at 02000000 { /* AIPS1 */
> +		aips-bus at 2000000 { /* AIPS1 */
>  			compatible = "fsl,aips-bus", "simple-bus";
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			reg = <0x02000000 0x100000>;
>  			ranges;
>  
> -			spba-bus at 02000000 {
> +			spba-bus at 2000000 {
>  				compatible = "fsl,spba-bus",
> "simple-bus"; #address-cells = <1>;
>  				#size-cells = <1>;
>  				reg = <0x02000000 0x40000>;
>  				ranges;
>  
> -				spdif: spdif at 02004000 {
> +				spdif: spdif at 2004000 {
>  					compatible =
> "fsl,imx35-spdif"; reg = <0x02004000 0x4000>;
>  					interrupts = <0 52
> IRQ_TYPE_LEVEL_HIGH>; @@ -253,7 +317,7 @@
>  					status = "disabled";
>  				};
>  
> -				ecspi1: ecspi at 02008000 {
> +				ecspi1: spi at 2008000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  					compatible =
> "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -267,7 +331,7 @@
>  					status = "disabled";
>  				};
>  
> -				ecspi2: ecspi at 0200c000 {
> +				ecspi2: spi at 200c000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  					compatible =
> "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -281,7 +345,7 @@
>  					status = "disabled";
>  				};
>  
> -				ecspi3: ecspi at 02010000 {
> +				ecspi3: spi at 2010000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  					compatible =
> "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -295,7 +359,7 @@
>  					status = "disabled";
>  				};
>  
> -				ecspi4: ecspi at 02014000 {
> +				ecspi4: spi at 2014000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  					compatible =
> "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -309,7 +373,7 @@
>  					status = "disabled";
>  				};
>  
> -				uart1: serial at 02020000 {
> +				uart1: serial at 2020000 {
>  					compatible =
> "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>;
>  					interrupts = <0 26
> IRQ_TYPE_LEVEL_HIGH>; @@ -321,7 +385,7 @@
>  					status = "disabled";
>  				};
>  
> -				esai: esai at 02024000 {
> +				esai: esai at 2024000 {
>  					#sound-dai-cells = <0>;
>  					compatible =
> "fsl,imx35-esai"; reg = <0x02024000 0x4000>;
> @@ -337,7 +401,7 @@
>  					status = "disabled";
>  				};
>  
> -				ssi1: ssi at 02028000 {
> +				ssi1: ssi at 2028000 {
>  					#sound-dai-cells = <0>;
>  					compatible = "fsl,imx6q-ssi",
>  							"fsl,imx51-ssi";
> @@ -353,7 +417,7 @@
>  					status = "disabled";
>  				};
>  
> -				ssi2: ssi at 0202c000 {
> +				ssi2: ssi at 202c000 {
>  					#sound-dai-cells = <0>;
>  					compatible = "fsl,imx6q-ssi",
>  							"fsl,imx51-ssi";
> @@ -369,7 +433,7 @@
>  					status = "disabled";
>  				};
>  
> -				ssi3: ssi at 02030000 {
> +				ssi3: ssi at 2030000 {
>  					#sound-dai-cells = <0>;
>  					compatible = "fsl,imx6q-ssi",
>  							"fsl,imx51-ssi";
> @@ -385,7 +449,7 @@
>  					status = "disabled";
>  				};
>  
> -				asrc: asrc at 02034000 {
> +				asrc: asrc at 2034000 {
>  					compatible =
> "fsl,imx53-asrc"; reg = <0x02034000 0x4000>;
>  					interrupts = <0 50
> IRQ_TYPE_LEVEL_HIGH>; @@ -410,12 +474,12 @@
>  					status = "okay";
>  				};
>  
> -				spba at 0203c000 {
> +				spba at 203c000 {
>  					reg = <0x0203c000 0x4000>;
>  				};
>  			};
>  
> -			vpu: vpu at 02040000 {
> +			vpu: vpu at 2040000 {
>  				compatible = "cnm,coda960";
>  				reg = <0x02040000 0x3c000>;
>  				interrupts = <0 12
> IRQ_TYPE_LEVEL_HIGH>, @@ -424,16 +488,16 @@
>  				clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
>  					 <&clks
> IMX6QDL_CLK_MMDC_CH0_AXI>; clock-names = "per", "ahb";
> -				power-domains = <&gpc 1>;
> +				power-domains = <&pd_pu>;
>  				resets = <&src 1>;
>  				iram = <&ocram>;
>  			};
>  
> -			aipstz at 0207c000 { /* AIPSTZ1 */
> +			aipstz at 207c000 { /* AIPSTZ1 */
>  				reg = <0x0207c000 0x4000>;
>  			};
>  
> -			pwm1: pwm at 02080000 {
> +			pwm1: pwm at 2080000 {
>  				#pwm-cells = <2>;
>  				compatible = "fsl,imx6q-pwm",
> "fsl,imx27-pwm"; reg = <0x02080000 0x4000>;
> @@ -444,7 +508,7 @@
>  				status = "disabled";
>  			};
>  
> -			pwm2: pwm at 02084000 {
> +			pwm2: pwm at 2084000 {
>  				#pwm-cells = <2>;
>  				compatible = "fsl,imx6q-pwm",
> "fsl,imx27-pwm"; reg = <0x02084000 0x4000>;
> @@ -455,7 +519,7 @@
>  				status = "disabled";
>  			};
>  
> -			pwm3: pwm at 02088000 {
> +			pwm3: pwm at 2088000 {
>  				#pwm-cells = <2>;
>  				compatible = "fsl,imx6q-pwm",
> "fsl,imx27-pwm"; reg = <0x02088000 0x4000>;
> @@ -466,7 +530,7 @@
>  				status = "disabled";
>  			};
>  
> -			pwm4: pwm at 0208c000 {
> +			pwm4: pwm at 208c000 {
>  				#pwm-cells = <2>;
>  				compatible = "fsl,imx6q-pwm",
> "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>;
> @@ -477,7 +541,7 @@
>  				status = "disabled";
>  			};
>  
> -			can1: flexcan at 02090000 {
> +			can1: flexcan at 2090000 {
>  				compatible = "fsl,imx6q-flexcan";
>  				reg = <0x02090000 0x4000>;
>  				interrupts = <0 110
> IRQ_TYPE_LEVEL_HIGH>; @@ -487,7 +551,7 @@
>  				status = "disabled";
>  			};
>  
> -			can2: flexcan at 02094000 {
> +			can2: flexcan at 2094000 {
>  				compatible = "fsl,imx6q-flexcan";
>  				reg = <0x02094000 0x4000>;
>  				interrupts = <0 111
> IRQ_TYPE_LEVEL_HIGH>; @@ -497,7 +561,7 @@
>  				status = "disabled";
>  			};
>  
> -			gpt: gpt at 02098000 {
> +			gpt: gpt at 2098000 {
>  				compatible = "fsl,imx6q-gpt",
> "fsl,imx31-gpt"; reg = <0x02098000 0x4000>;
>  				interrupts = <0 55
> IRQ_TYPE_LEVEL_HIGH>; @@ -507,7 +571,7 @@
>  				clock-names = "ipg", "per",
> "osc_per"; };
>  
> -			gpio1: gpio at 0209c000 {
> +			gpio1: gpio at 209c000 {
>  				compatible = "fsl,imx6q-gpio",
> "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>;
>  				interrupts = <0 66
> IRQ_TYPE_LEVEL_HIGH>, @@ -518,7 +582,7 @@
>  				#interrupt-cells = <2>;
>  			};
>  
> -			gpio2: gpio at 020a0000 {
> +			gpio2: gpio at 20a0000 {
>  				compatible = "fsl,imx6q-gpio",
> "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>;
>  				interrupts = <0 68
> IRQ_TYPE_LEVEL_HIGH>, @@ -529,7 +593,7 @@
>  				#interrupt-cells = <2>;
>  			};
>  
> -			gpio3: gpio at 020a4000 {
> +			gpio3: gpio at 20a4000 {
>  				compatible = "fsl,imx6q-gpio",
> "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>;
>  				interrupts = <0 70
> IRQ_TYPE_LEVEL_HIGH>, @@ -540,7 +604,7 @@
>  				#interrupt-cells = <2>;
>  			};
>  
> -			gpio4: gpio at 020a8000 {
> +			gpio4: gpio at 20a8000 {
>  				compatible = "fsl,imx6q-gpio",
> "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>;
>  				interrupts = <0 72
> IRQ_TYPE_LEVEL_HIGH>, @@ -551,7 +615,7 @@
>  				#interrupt-cells = <2>;
>  			};
>  
> -			gpio5: gpio at 020ac000 {
> +			gpio5: gpio at 20ac000 {
>  				compatible = "fsl,imx6q-gpio",
> "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>;
>  				interrupts = <0 74
> IRQ_TYPE_LEVEL_HIGH>, @@ -562,7 +626,7 @@
>  				#interrupt-cells = <2>;
>  			};
>  
> -			gpio6: gpio at 020b0000 {
> +			gpio6: gpio at 20b0000 {
>  				compatible = "fsl,imx6q-gpio",
> "fsl,imx35-gpio"; reg = <0x020b0000 0x4000>;
>  				interrupts = <0 76
> IRQ_TYPE_LEVEL_HIGH>, @@ -573,7 +637,7 @@
>  				#interrupt-cells = <2>;
>  			};
>  
> -			gpio7: gpio at 020b4000 {
> +			gpio7: gpio at 20b4000 {
>  				compatible = "fsl,imx6q-gpio",
> "fsl,imx35-gpio"; reg = <0x020b4000 0x4000>;
>  				interrupts = <0 78
> IRQ_TYPE_LEVEL_HIGH>, @@ -584,7 +648,7 @@
>  				#interrupt-cells = <2>;
>  			};
>  
> -			kpp: kpp at 020b8000 {
> +			kpp: kpp at 20b8000 {
>  				compatible = "fsl,imx6q-kpp",
> "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>;
>  				interrupts = <0 82
> IRQ_TYPE_LEVEL_HIGH>; @@ -592,14 +656,14 @@
>  				status = "disabled";
>  			};
>  
> -			wdog1: wdog at 020bc000 {
> +			wdog1: wdog at 20bc000 {
>  				compatible = "fsl,imx6q-wdt",
> "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>;
>  				interrupts = <0 80
> IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_DUMMY>;
>  			};
>  
> -			wdog2: wdog at 020c0000 {
> +			wdog2: wdog at 20c0000 {
>  				compatible = "fsl,imx6q-wdt",
> "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>;
>  				interrupts = <0 81
> IRQ_TYPE_LEVEL_HIGH>; @@ -607,7 +671,7 @@
>  				status = "disabled";
>  			};
>  
> -			clks: ccm at 020c4000 {
> +			clks: ccm at 20c4000 {
>  				compatible = "fsl,imx6q-ccm";
>  				reg = <0x020c4000 0x4000>;
>  				interrupts = <0 87
> IRQ_TYPE_LEVEL_HIGH>, @@ -615,7 +679,7 @@
>  				#clock-cells = <1>;
>  			};
>  
> -			anatop: anatop at 020c8000 {
> +			anatop: anatop at 20c8000 {
>  				compatible = "fsl,imx6q-anatop",
> "syscon", "simple-bus"; reg = <0x020c8000 0x1000>;
>  				interrupts = <0 49
> IRQ_TYPE_LEVEL_HIGH>, @@ -625,8 +689,8 @@
>  				regulator-1p1 {
>  					compatible =
> "fsl,anatop-regulator"; regulator-name = "vdd1p1";
> -					regulator-min-microvolt =
> <800000>;
> -					regulator-max-microvolt =
> <1375000>;
> +					regulator-min-microvolt =
> <1000000>;
> +					regulator-max-microvolt =
> <1200000>; regulator-always-on;
>  					anatop-reg-offset = <0x110>;
>  					anatop-vol-bit-shift = <8>;
> @@ -634,6 +698,7 @@
>  					anatop-min-bit-val = <4>;
>  					anatop-min-voltage =
> <800000>; anatop-max-voltage = <1375000>;
> +					anatop-enable-bit = <0>;
>  				};
>  
>  				regulator-3p0 {
> @@ -648,20 +713,22 @@
>  					anatop-min-bit-val = <0>;
>  					anatop-min-voltage =
> <2625000>; anatop-max-voltage = <3400000>;
> +					anatop-enable-bit = <0>;
>  				};
>  
>  				regulator-2p5 {
>  					compatible =
> "fsl,anatop-regulator"; regulator-name = "vdd2p5";
> -					regulator-min-microvolt =
> <2000000>;
> +					regulator-min-microvolt =
> <2250000>; regulator-max-microvolt = <2750000>;
>  					regulator-always-on;
>  					anatop-reg-offset = <0x130>;
>  					anatop-vol-bit-shift = <8>;
>  					anatop-vol-bit-width = <5>;
>  					anatop-min-bit-val = <0>;
> -					anatop-min-voltage =
> <2000000>;
> -					anatop-max-voltage =
> <2750000>;
> +					anatop-min-voltage =
> <2100000>;
> +					anatop-max-voltage =
> <2875000>;
> +					anatop-enable-bit = <0>;
>  				};
>  
>  				reg_arm: regulator-vddcore {
> @@ -716,15 +783,7 @@
>  				};
>  			};
>  
> -			tempmon: tempmon {
> -				compatible = "fsl,imx6q-tempmon";
> -				interrupts = <0 49
> IRQ_TYPE_LEVEL_HIGH>;
> -				fsl,tempmon = <&anatop>;
> -				fsl,tempmon-data = <&ocotp>;
> -				clocks = <&clks
> IMX6QDL_CLK_PLL3_USB_OTG>;
> -			};
> -
> -			usbphy1: usbphy at 020c9000 {
> +			usbphy1: usbphy at 20c9000 {
>  				compatible = "fsl,imx6q-usbphy",
> "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>;
>  				interrupts = <0 44
> IRQ_TYPE_LEVEL_HIGH>; @@ -732,7 +791,7 @@
>  				fsl,anatop = <&anatop>;
>  			};
>  
> -			usbphy2: usbphy at 020ca000 {
> +			usbphy2: usbphy at 20ca000 {
>  				compatible = "fsl,imx6q-usbphy",
> "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>;
>  				interrupts = <0 45
> IRQ_TYPE_LEVEL_HIGH>; @@ -740,7 +799,7 @@
>  				fsl,anatop = <&anatop>;
>  			};
>  
> -			snvs: snvs at 020cc000 {
> +			snvs: snvs at 20cc000 {
>  				compatible = "fsl,sec-v4.0-mon",
> "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>;
>  
> @@ -756,22 +815,27 @@
>  					compatible =
> "syscon-poweroff"; regmap = <&snvs>;
>  					offset = <0x38>;
> +					value = <0x60>;
>  					mask = <0x60>;
>  					status = "disabled";
>  				};
> +
> +				snvs_lpgpr: snvs-lpgpr {
> +					compatible =
> "fsl,imx6q-snvs-lpgpr";
> +				};
>  			};
>  
> -			epit1: epit at 020d0000 { /* EPIT1 */
> +			epit1: epit at 20d0000 { /* EPIT1 */
>  				reg = <0x020d0000 0x4000>;
>  				interrupts = <0 56
> IRQ_TYPE_LEVEL_HIGH>; };
>  
> -			epit2: epit at 020d4000 { /* EPIT2 */
> +			epit2: epit at 20d4000 { /* EPIT2 */
>  				reg = <0x020d4000 0x4000>;
>  				interrupts = <0 57
> IRQ_TYPE_LEVEL_HIGH>; };
>  
> -			src: src at 020d8000 {
> +			src: src at 20d8000 {
>  				compatible = "fsl,imx6q-src",
> "fsl,imx51-src"; reg = <0x020d8000 0x4000>;
>  				interrupts = <0 91
> IRQ_TYPE_LEVEL_HIGH>, @@ -779,7 +843,7 @@
>  				#reset-cells = <1>;
>  			};
>  
> -			gpc: gpc at 020dc000 {
> +			gpc: gpc at 20dc000 {
>  				compatible = "fsl,imx6q-gpc";
>  				reg = <0x020dc000 0x4000>;
>  				interrupt-controller;
> @@ -787,91 +851,57 @@
>  				interrupts = <0 89
> IRQ_TYPE_LEVEL_HIGH>, <0 90 IRQ_TYPE_LEVEL_HIGH>;
>  				interrupt-parent = <&intc>;
> -				pu-supply = <&reg_pu>;
> -				clocks = <&clks
> IMX6QDL_CLK_GPU3D_CORE>,
> -					 <&clks
> IMX6QDL_CLK_GPU3D_SHADER>,
> -					 <&clks
> IMX6QDL_CLK_GPU2D_CORE>,
> -					 <&clks
> IMX6QDL_CLK_GPU2D_AXI>,
> -					 <&clks
> IMX6QDL_CLK_OPENVG_AXI>,
> -					 <&clks IMX6QDL_CLK_VPU_AXI>;
> -				#power-domain-cells = <1>;
> -			};
> -
> -			gpr: iomuxc-gpr at 020e0000 {
> -				compatible = "fsl,imx6q-iomuxc-gpr",
> "syscon";
> -				reg = <0x020e0000 0x38>;
> -			};
> -
> -			iomuxc: iomuxc at 020e0000 {
> -				compatible = "fsl,imx6dl-iomuxc",
> "fsl,imx6q-iomuxc";
> -				reg = <0x020e0000 0x4000>;
> -			};
> -
> -			ldb: ldb at 020e0008 {
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -				compatible = "fsl,imx6q-ldb",
> "fsl,imx53-ldb";
> -				gpr = <&gpr>;
> -				status = "disabled";
> +				clocks = <&clks IMX6QDL_CLK_IPG>;
> +				clock-names = "ipg";
>  
> -				lvds-channel at 0 {
> +				pgc {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
> -					reg = <0>;
> -					status = "disabled";
>  
> -					port at 0 {
> +					power-domain at 0 {
>  						reg = <0>;
> -
> -						lvds0_mux_0:
> endpoint {
> -
> remote-endpoint = <&ipu1_di0_lvds0>;
> -						};
> +						#power-domain-cells
> = <0>; };
> -
> -					port at 1 {
> +					pd_pu: power-domain at 1 {
>  						reg = <1>;
> -
> -						lvds0_mux_1:
> endpoint {
> -
> remote-endpoint = <&ipu1_di1_lvds0>;
> -						};
> +						#power-domain-cells
> = <0>;
> +						power-supply =
> <&reg_pu>;
> +						clocks = <&clks
> IMX6QDL_CLK_GPU3D_CORE>,
> +						         <&clks
> IMX6QDL_CLK_GPU3D_SHADER>,
> +						         <&clks
> IMX6QDL_CLK_GPU2D_CORE>,
> +						         <&clks
> IMX6QDL_CLK_GPU2D_AXI>,
> +						         <&clks
> IMX6QDL_CLK_OPENVG_AXI>,
> +						         <&clks
> IMX6QDL_CLK_VPU_AXI>; };
>  				};
> +			};
>  
> -				lvds-channel at 1 {
> -					#address-cells = <1>;
> -					#size-cells = <0>;
> -					reg = <1>;
> -					status = "disabled";
> -
> -					port at 0 {
> -						reg = <0>;
> -
> -						lvds1_mux_0:
> endpoint {
> -
> remote-endpoint = <&ipu1_di0_lvds1>;
> -						};
> -					};
> +			gpr: iomuxc-gpr at 20e0000 {
> +				compatible = "fsl,imx6q-iomuxc-gpr",
> "syscon", "simple-mfd";
> +				reg = <0x20e0000 0x38>;
>  
> -					port at 1 {
> -						reg = <1>;
> -
> -						lvds1_mux_1:
> endpoint {
> -
> remote-endpoint = <&ipu1_di1_lvds1>;
> -						};
> -					};
> +				mux: mux-controller {
> +					compatible = "mmio-mux";
> +					#mux-control-cells = <1>;
>  				};
>  			};
>  
> -			dcic1: dcic at 020e4000 {
> +			iomuxc: iomuxc at 20e0000 {
> +				compatible = "fsl,imx6dl-iomuxc",
> "fsl,imx6q-iomuxc";
> +				reg = <0x20e0000 0x4000>;
> +			};
> +
> +			dcic1: dcic at 20e4000 {
>  				reg = <0x020e4000 0x4000>;
>  				interrupts = <0 124
> IRQ_TYPE_LEVEL_HIGH>; };
>  
> -			dcic2: dcic at 020e8000 {
> +			dcic2: dcic at 20e8000 {
>  				reg = <0x020e8000 0x4000>;
>  				interrupts = <0 125
> IRQ_TYPE_LEVEL_HIGH>; };
>  
> -			sdma: sdma at 020ec000 {
> +			sdma: sdma at 20ec000 {
>  				compatible = "fsl,imx6q-sdma",
> "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>;
>  				interrupts = <0 2
> IRQ_TYPE_LEVEL_HIGH>; @@ -883,7 +913,7 @@
>  			};
>  		};
>  
> -		aips-bus at 02100000 { /* AIPS2 */
> +		aips-bus at 2100000 { /* AIPS2 */
>  			compatible = "fsl,aips-bus", "simple-bus";
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> @@ -892,7 +922,6 @@
>  
>  			crypto: caam at 2100000 {
>  				compatible = "fsl,sec-v4.0";
> -				fsl,sec-era = <4>;
>  				#address-cells = <1>;
>  				#size-cells = <1>;
>  				reg = <0x2100000 0x10000>;
> @@ -916,11 +945,11 @@
>  				};
>  			};
>  
> -			aipstz at 0217c000 { /* AIPSTZ2 */
> +			aipstz at 217c000 { /* AIPSTZ2 */
>  				reg = <0x0217c000 0x4000>;
>  			};
>  
> -			usbotg: usb at 02184000 {
> +			usbotg: usb at 2184000 {
>  				compatible = "fsl,imx6q-usb",
> "fsl,imx27-usb"; reg = <0x02184000 0x200>;
>  				interrupts = <0 43
> IRQ_TYPE_LEVEL_HIGH>; @@ -933,7 +962,7 @@
>  				status = "disabled";
>  			};
>  
> -			usbh1: usb at 02184200 {
> +			usbh1: usb at 2184200 {
>  				compatible = "fsl,imx6q-usb",
> "fsl,imx27-usb"; reg = <0x02184200 0x200>;
>  				interrupts = <0 40
> IRQ_TYPE_LEVEL_HIGH>; @@ -947,7 +976,7 @@
>  				status = "disabled";
>  			};
>  
> -			usbh2: usb at 02184400 {
> +			usbh2: usb at 2184400 {
>  				compatible = "fsl,imx6q-usb",
> "fsl,imx27-usb"; reg = <0x02184400 0x200>;
>  				interrupts = <0 41
> IRQ_TYPE_LEVEL_HIGH>; @@ -960,7 +989,7 @@
>  				status = "disabled";
>  			};
>  
> -			usbh3: usb at 02184600 {
> +			usbh3: usb at 2184600 {
>  				compatible = "fsl,imx6q-usb",
> "fsl,imx27-usb"; reg = <0x02184600 0x200>;
>  				interrupts = <0 42
> IRQ_TYPE_LEVEL_HIGH>; @@ -973,16 +1002,17 @@
>  				status = "disabled";
>  			};
>  
> -			usbmisc: usbmisc at 02184800 {
> +			usbmisc: usbmisc at 2184800 {
>  				#index-cells = <1>;
>  				compatible = "fsl,imx6q-usbmisc";
>  				reg = <0x02184800 0x200>;
>  				clocks = <&clks IMX6QDL_CLK_USBOH3>;
>  			};
>  
> -			fec: ethernet at 02188000 {
> +			fec: ethernet at 2188000 {
>  				compatible = "fsl,imx6q-fec";
>  				reg = <0x02188000 0x4000>;
> +				interrupt-names = "int0", "pps";
>  				interrupts-extended =
>  					<&intc 0 118
> IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
> @@ -993,14 +1023,14 @@
>  				status = "disabled";
>  			};
>  
> -			mlb at 0218c000 {
> +			mlb at 218c000 {
>  				reg = <0x0218c000 0x4000>;
>  				interrupts = <0 53
> IRQ_TYPE_LEVEL_HIGH>, <0 117 IRQ_TYPE_LEVEL_HIGH>,
>  					     <0 126
> IRQ_TYPE_LEVEL_HIGH>; };
>  
> -			usdhc1: usdhc at 02190000 {
> +			usdhc1: usdhc at 2190000 {
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x02190000 0x4000>;
>  				interrupts = <0 22
> IRQ_TYPE_LEVEL_HIGH>; @@ -1012,7 +1042,7 @@
>  				status = "disabled";
>  			};
>  
> -			usdhc2: usdhc at 02194000 {
> +			usdhc2: usdhc at 2194000 {
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x02194000 0x4000>;
>  				interrupts = <0 23
> IRQ_TYPE_LEVEL_HIGH>; @@ -1024,7 +1054,7 @@
>  				status = "disabled";
>  			};
>  
> -			usdhc3: usdhc at 02198000 {
> +			usdhc3: usdhc at 2198000 {
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x02198000 0x4000>;
>  				interrupts = <0 24
> IRQ_TYPE_LEVEL_HIGH>; @@ -1036,7 +1066,7 @@
>  				status = "disabled";
>  			};
>  
> -			usdhc4: usdhc at 0219c000 {
> +			usdhc4: usdhc at 219c000 {
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x0219c000 0x4000>;
>  				interrupts = <0 25
> IRQ_TYPE_LEVEL_HIGH>; @@ -1048,7 +1078,7 @@
>  				status = "disabled";
>  			};
>  
> -			i2c1: i2c at 021a0000 {
> +			i2c1: i2c at 21a0000 {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
>  				compatible = "fsl,imx6q-i2c",
> "fsl,imx21-i2c"; @@ -1058,7 +1088,7 @@
>  				status = "disabled";
>  			};
>  
> -			i2c2: i2c at 021a4000 {
> +			i2c2: i2c at 21a4000 {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
>  				compatible = "fsl,imx6q-i2c",
> "fsl,imx21-i2c"; @@ -1068,7 +1098,7 @@
>  				status = "disabled";
>  			};
>  
> -			i2c3: i2c at 021a8000 {
> +			i2c3: i2c at 21a8000 {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
>  				compatible = "fsl,imx6q-i2c",
> "fsl,imx21-i2c"; @@ -1078,55 +1108,66 @@
>  				status = "disabled";
>  			};
>  
> -			romcp at 021ac000 {
> +			romcp at 21ac000 {
>  				reg = <0x021ac000 0x4000>;
>  			};
>  
> -			mmdc0: mmdc at 021b0000 { /* MMDC0 */
> +			mmdc0: mmdc at 21b0000 { /* MMDC0 */
>  				compatible = "fsl,imx6q-mmdc";
>  				reg = <0x021b0000 0x4000>;
>  			};
>  
> -			mmdc1: mmdc at 021b4000 { /* MMDC1 */
> +			mmdc1: mmdc at 21b4000 { /* MMDC1 */
>  				reg = <0x021b4000 0x4000>;
>  			};
>  
> -			weim: weim at 021b8000 {
> +			weim: weim at 21b8000 {
> +				#address-cells = <2>;
> +				#size-cells = <1>;
>  				compatible = "fsl,imx6q-weim";
>  				reg = <0x021b8000 0x4000>;
>  				interrupts = <0 14
> IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
> +				fsl,weim-cs-gpr = <&gpr>;
> +				status = "disabled";
>  			};
>  
> -			ocotp: ocotp at 021bc000 {
> +			ocotp: ocotp at 21bc000 {
>  				compatible = "fsl,imx6q-ocotp",
> "syscon"; reg = <0x021bc000 0x4000>;
>  				clocks = <&clks IMX6QDL_CLK_IIM>;
>  			};
>  
> -			tzasc at 021d0000 { /* TZASC1 */
> +			tzasc at 21d0000 { /* TZASC1 */
>  				reg = <0x021d0000 0x4000>;
>  				interrupts = <0 108
> IRQ_TYPE_LEVEL_HIGH>; };
>  
> -			tzasc at 021d4000 { /* TZASC2 */
> +			tzasc at 21d4000 { /* TZASC2 */
>  				reg = <0x021d4000 0x4000>;
>  				interrupts = <0 109
> IRQ_TYPE_LEVEL_HIGH>; };
>  
> -			audmux: audmux at 021d8000 {
> +			audmux: audmux at 21d8000 {
>  				compatible = "fsl,imx6q-audmux",
> "fsl,imx31-audmux"; reg = <0x021d8000 0x4000>;
>  				status = "disabled";
>  			};
>  
> -			mipi_csi: mipi at 021dc000 {
> +			mipi_csi: mipi at 21dc000 {
> +				compatible = "fsl,imx6-mipi-csi2";
>  				reg = <0x021dc000 0x4000>;
> -			};
> -
> -			mipi_dsi: mipi at 021e0000 {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
> +				interrupts = <0 100 0x04>, <0 101
> 0x04>;
> +				clocks = <&clks IMX6QDL_CLK_HSI_TX>,
> +					 <&clks
> IMX6QDL_CLK_VIDEO_27M>,
> +					 <&clks
> IMX6QDL_CLK_EIM_PODF>;
> +				clock-names = "dphy", "ref", "pix";
> +				status = "disabled";
> +			};
> +
> +			mipi_dsi: mipi at 21e0000 {
>  				reg = <0x021e0000 0x4000>;
>  				status = "disabled";
>  
> @@ -1152,12 +1193,14 @@
>  				};
>  			};
>  
> -			vdoa at 021e4000 {
> +			vdoa at 21e4000 {
> +				compatible = "fsl,imx6q-vdoa";
>  				reg = <0x021e4000 0x4000>;
>  				interrupts = <0 18
> IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clks IMX6QDL_CLK_VDOA>;
>  			};
>  
> -			uart2: serial at 021e8000 {
> +			uart2: serial at 21e8000 {
>  				compatible = "fsl,imx6q-uart",
> "fsl,imx21-uart"; reg = <0x021e8000 0x4000>;
>  				interrupts = <0 27
> IRQ_TYPE_LEVEL_HIGH>; @@ -1169,7 +1212,7 @@
>  				status = "disabled";
>  			};
>  
> -			uart3: serial at 021ec000 {
> +			uart3: serial at 21ec000 {
>  				compatible = "fsl,imx6q-uart",
> "fsl,imx21-uart"; reg = <0x021ec000 0x4000>;
>  				interrupts = <0 28
> IRQ_TYPE_LEVEL_HIGH>; @@ -1181,7 +1224,7 @@
>  				status = "disabled";
>  			};
>  
> -			uart4: serial at 021f0000 {
> +			uart4: serial at 21f0000 {
>  				compatible = "fsl,imx6q-uart",
> "fsl,imx21-uart"; reg = <0x021f0000 0x4000>;
>  				interrupts = <0 29
> IRQ_TYPE_LEVEL_HIGH>; @@ -1193,7 +1236,7 @@
>  				status = "disabled";
>  			};
>  
> -			uart5: serial at 021f4000 {
> +			uart5: serial at 21f4000 {
>  				compatible = "fsl,imx6q-uart",
> "fsl,imx21-uart"; reg = <0x021f4000 0x4000>;
>  				interrupts = <0 30
> IRQ_TYPE_LEVEL_HIGH>; @@ -1206,7 +1249,7 @@
>  			};
>  		};
>  
> -		ipu1: ipu at 02400000 {
> +		ipu1: ipu at 2400000 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			compatible = "fsl,imx6q-ipu";
> @@ -1221,6 +1264,10 @@
>  
>  			ipu1_csi0: port at 0 {
>  				reg = <0>;
> +
> +				ipu1_csi0_from_ipu1_csi0_mux:
> endpoint {
> +					remote-endpoint =
> <&ipu1_csi0_mux_to_ipu1_csi0>;
> +				};
>  			};
>  
>  			ipu1_csi1: port at 1 {
> @@ -1232,22 +1279,27 @@
>  				#size-cells = <0>;
>  				reg = <2>;
>  
> -				ipu1_di0_disp0: disp0-endpoint {
> +				ipu1_di0_disp0: endpoint at 0 {
> +					reg = <0>;
>  				};
>  
> -				ipu1_di0_hdmi: hdmi-endpoint {
> +				ipu1_di0_hdmi: endpoint at 1 {
> +					reg = <1>;
>  					remote-endpoint =
> <&hdmi_mux_0>; };
>  
> -				ipu1_di0_mipi: mipi-endpoint {
> +				ipu1_di0_mipi: endpoint at 2 {
> +					reg = <2>;
>  					remote-endpoint =
> <&mipi_mux_0>; };
>  
> -				ipu1_di0_lvds0: lvds0-endpoint {
> +				ipu1_di0_lvds0: endpoint at 3 {
> +					reg = <3>;
>  					remote-endpoint =
> <&lvds0_mux_0>; };
>  
> -				ipu1_di0_lvds1: lvds1-endpoint {
> +				ipu1_di0_lvds1: endpoint at 4 {
> +					reg = <4>;
>  					remote-endpoint =
> <&lvds1_mux_0>; };
>  			};
> @@ -1257,22 +1309,27 @@
>  				#size-cells = <0>;
>  				reg = <3>;
>  
> -				ipu1_di1_disp1: disp1-endpoint {
> +				ipu1_di1_disp1: endpoint at 0 {
> +					reg = <0>;
>  				};
>  
> -				ipu1_di1_hdmi: hdmi-endpoint {
> +				ipu1_di1_hdmi: endpoint at 1 {
> +					reg = <1>;
>  					remote-endpoint =
> <&hdmi_mux_1>; };
>  
> -				ipu1_di1_mipi: mipi-endpoint {
> +				ipu1_di1_mipi: endpoint at 2 {
> +					reg = <2>;
>  					remote-endpoint =
> <&mipi_mux_1>; };
>  
> -				ipu1_di1_lvds0: lvds0-endpoint {
> +				ipu1_di1_lvds0: endpoint at 3 {
> +					reg = <3>;
>  					remote-endpoint =
> <&lvds0_mux_1>; };
>  
> -				ipu1_di1_lvds1: lvds1-endpoint {
> +				ipu1_di1_lvds1: endpoint at 4 {
> +					reg = <4>;
>  					remote-endpoint =
> <&lvds1_mux_1>; };
>  			};
> diff --git a/arch/arm/dts/imx6qp-sabreauto.dts
> b/arch/arm/dts/imx6qp-sabreauto.dts new file mode 100644
> index 0000000..d4caeeb
> --- /dev/null
> +++ b/arch/arm/dts/imx6qp-sabreauto.dts
> @@ -0,0 +1,55 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +//
> +// Copyright 2016 Freescale Semiconductor, Inc.
> +
> +/dts-v1/;
> +
> +#include "imx6qp.dtsi"
> +#include "imx6qdl-sabreauto.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 Quad Plus SABRE Automotive Board";
> +	compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
> +};
> +
> +&i2c2 {
> +	max7322: gpio at 68 {
> +		compatible = "maxim,max7322";
> +		reg = <0x68>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +	};
> +};
> +
> +&iomuxc {
> +	imx6qdl-sabreauto {
> +		pinctrl_enet: enetgrp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
> +
> MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
> +
> MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b018
> +
> MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b018
> +
> MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b018
> +
> MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b018
> +
> MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b018
> +
> MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b018
> +
> MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b018
> +
> MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b018
> +
> MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b018
> +
> MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b018
> +
> MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b018
> +
> MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b018
> +
> MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
> +
> MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
> +			>;
> +		};
> +	};
> +};
> +
> +&pcie {
> +	status = "disabled";
> +};
> +
> +&vgen3_reg {
> +	regulator-always-on;
> +};
> diff --git a/arch/arm/dts/imx6qp-sabresd.dts
> b/arch/arm/dts/imx6qp-sabresd.dts new file mode 100644
> index 0000000..f1b9cb1
> --- /dev/null
> +++ b/arch/arm/dts/imx6qp-sabresd.dts
> @@ -0,0 +1,55 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +//
> +// Copyright 2016 Freescale Semiconductor, Inc.
> +
> +/dts-v1/;
> +
> +#include "imx6qp.dtsi"
> +#include "imx6qdl-sabresd.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
> +	compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
> +};
> +
> +&reg_arm {
> +	vin-supply = <&sw2_reg>;
> +};
> +
> +&iomuxc {
> +	imx6qdl-sabresd {
> +		pinctrl_usdhc2: usdhc2grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
> +
> MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10071
> +
> MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
> +
> MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
> +
> MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
> +
> MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
> +
> MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
> +
> MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
> +
> MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
> +
> MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc3: usdhc3grp {
> +			fsl,pins = <
> +
> MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
> +
> MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10071
> +
> MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
> +
> MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
> +
> MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
> +
> MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
> +
> MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
> +
> MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
> +
> MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
> +
> MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
> +			>;
> +		};
> +	};
> +};
> +
> +&pcie {
> +	status = "disabled";
> +};
> diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi
> new file mode 100644
> index 0000000..5f51f8e
> --- /dev/null
> +++ b/arch/arm/dts/imx6qp.dtsi
> @@ -0,0 +1,115 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +//
> +// Copyright 2016 Freescale Semiconductor, Inc.
> +
> +#include "imx6q.dtsi"
> +
> +/ {
> +	soc {
> +		ocram2: sram at 940000 {
> +			compatible = "mmio-sram";
> +			reg = <0x00940000 0x20000>;
> +			clocks = <&clks IMX6QDL_CLK_OCRAM>;
> +		};
> +
> +		ocram3: sram at 960000 {
> +			compatible = "mmio-sram";
> +			reg = <0x00960000 0x20000>;
> +			clocks = <&clks IMX6QDL_CLK_OCRAM>;
> +		};
> +
> +		aips-bus at 2100000 {
> +			pre1: pre at 21c8000 {
> +				compatible = "fsl,imx6qp-pre";
> +				reg = <0x021c8000 0x1000>;
> +				interrupts = <GIC_SPI 90
> IRQ_TYPE_EDGE_RISING>;
> +				clocks = <&clks IMX6QDL_CLK_PRE0>;
> +				clock-names = "axi";
> +				fsl,iram = <&ocram2>;
> +			};
> +
> +			pre2: pre at 21c9000 {
> +				compatible = "fsl,imx6qp-pre";
> +				reg = <0x021c9000 0x1000>;
> +				interrupts = <GIC_SPI 97
> IRQ_TYPE_EDGE_RISING>;
> +				clocks = <&clks IMX6QDL_CLK_PRE1>;
> +				clock-names = "axi";
> +				fsl,iram = <&ocram2>;
> +			};
> +
> +			pre3: pre at 21ca000 {
> +				compatible = "fsl,imx6qp-pre";
> +				reg = <0x021ca000 0x1000>;
> +				interrupts = <GIC_SPI 98
> IRQ_TYPE_EDGE_RISING>;
> +				clocks = <&clks IMX6QDL_CLK_PRE2>;
> +				clock-names = "axi";
> +				fsl,iram = <&ocram3>;
> +			};
> +
> +			pre4: pre at 21cb000 {
> +				compatible = "fsl,imx6qp-pre";
> +				reg = <0x021cb000 0x1000>;
> +				interrupts = <GIC_SPI 99
> IRQ_TYPE_EDGE_RISING>;
> +				clocks = <&clks IMX6QDL_CLK_PRE3>;
> +				clock-names = "axi";
> +				fsl,iram = <&ocram3>;
> +			};
> +
> +			prg1: prg at 21cc000 {
> +				compatible = "fsl,imx6qp-prg";
> +				reg = <0x021cc000 0x1000>;
> +				clocks = <&clks
> IMX6QDL_CLK_PRG0_APB>,
> +					 <&clks
> IMX6QDL_CLK_PRG0_AXI>;
> +				clock-names = "ipg", "axi";
> +				fsl,pres = <&pre1>, <&pre2>, <&pre3>;
> +			};
> +
> +			prg2: prg at 21cd000 {
> +				compatible = "fsl,imx6qp-prg";
> +				reg = <0x021cd000 0x1000>;
> +				clocks = <&clks
> IMX6QDL_CLK_PRG1_APB>,
> +					 <&clks
> IMX6QDL_CLK_PRG1_AXI>;
> +				clock-names = "ipg", "axi";
> +				fsl,pres = <&pre4>, <&pre2>, <&pre3>;
> +			};
> +		};
> +	};
> +};
> +
> +&fec {
> +	/delete-property/interrupts-extended;
> +	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
> +		     <0 119 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&gpc {
> +	compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
> +};
> +
> +&ipu1 {
> +	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
> +	fsl,prg = <&prg1>;
> +};
> +
> +&ipu2 {
> +	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
> +	fsl,prg = <&prg2>;
> +};
> +
> +&ldb {
> +	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks
> IMX6QDL_CLK_LDB_DI1_SEL>,
> +		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks
> IMX6QDL_CLK_IPU1_DI1_SEL>,
> +		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks
> IMX6QDL_CLK_IPU2_DI1_SEL>,
> +		 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks
> IMX6QDL_CLK_LDB_DI1_PODF>;
> +	clock-names = "di0_pll", "di1_pll",
> +		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
> +		      "di0", "di1";
> +};
> +
> +&mmdc0 {
> +	compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
> +};
> +
> +&pcie {
> +	compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
> +};




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190202/88467f01/attachment.sig>

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Abel Vesa]

On 19-02-02 07:50:28, Fabio Estevam wrote:
> Hi Abel,
> 
> On Fri, Feb 1, 2019 at 2:43 PM Abel Vesa <abel.vesa@nxp.com> wrote:
> >
> > The third version is here:
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.denx.de%2Fpipermail%2Fu-boot%2F2019-January%2F356903.html&amp;data=02%7C01%7Cabel.vesa%40nxp.com%7Ca93c33315b5b492ca15308d688f3e275%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636846978387908349&amp;sdata=wQrrLoMyouM5vdUlfXI325wqZYt4tTa5WTRJsgwMEz0%3D&amp;reserved=0
> >
> > So, this time I hope I got it right. Before, I was stupidly trying
> > to put a fit in another fit without a really good reason. To my
> > excuse, that was working even with the spl_image->os set to 0,
> > bug which I (hope) I fixed in the first patch (a new one)
> > of this series.
> 
> I am happy with the entire series.
> 
> One more question: do we get build error when the SPL gets larger than 64kB?

If the SPL size (without the dtb appended) is larger then yes, the build fails.
Trouble is if the SPL (without the dtb appended) is, lets say, 63kB and
then the dtb is larger than 1kB. Then there is no mechanism in place to check that
and it will just fail to boot without giving any clues why. But this is a totally
unrelated problem from this patchset's point of view and I think it impacts all
the platforms that support SPL with DM.

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Fabio Estevam]

On Mon, Feb 4, 2019 at 7:55 AM Abel Vesa <abel.vesa@nxp.com> wrote:

> If the SPL size (without the dtb appended) is larger then yes, the build fails.
> Trouble is if the SPL (without the dtb appended) is, lets say, 63kB and
> then the dtb is larger than 1kB. Then there is no mechanism in place to check that
> and it will just fail to boot without giving any clues why. But this is a totally
> unrelated problem from this patchset's point of view and I think it impacts all
> the platforms that support SPL with DM.

Yes, it is unrelated to this series and should be treated separately.

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Tom Rini]

On Mon, Feb 04, 2019 at 09:03:43AM -0200, Fabio Estevam wrote:
> On Mon, Feb 4, 2019 at 7:55 AM Abel Vesa <abel.vesa@nxp.com> wrote:
> 
> > If the SPL size (without the dtb appended) is larger then yes, the build fails.
> > Trouble is if the SPL (without the dtb appended) is, lets say, 63kB and
> > then the dtb is larger than 1kB. Then there is no mechanism in place to check that
> > and it will just fail to boot without giving any clues why. But this is a totally
> > unrelated problem from this patchset's point of view and I think it impacts all
> > the platforms that support SPL with DM.
> 
> Yes, it is unrelated to this series and should be treated separately.

I also agree.  But, don't we have a mechanism for that?  It sounds like
some additional targets need to call $(BOARD_SIZE_CHECK) at the end.  Or
am I missing something?

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190204/5baa9361/attachment.sig>

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Abel Vesa]

On 19-02-04 08:19:23, Tom Rini wrote:
> On Mon, Feb 04, 2019 at 09:03:43AM -0200, Fabio Estevam wrote:
> > On Mon, Feb 4, 2019 at 7:55 AM Abel Vesa <abel.vesa@nxp.com> wrote:
> > 
> > > If the SPL size (without the dtb appended) is larger then yes, the build fails.
> > > Trouble is if the SPL (without the dtb appended) is, lets say, 63kB and
> > > then the dtb is larger than 1kB. Then there is no mechanism in place to check that
> > > and it will just fail to boot without giving any clues why. But this is a totally
> > > unrelated problem from this patchset's point of view and I think it impacts all
> > > the platforms that support SPL with DM.
> > 
> > Yes, it is unrelated to this series and should be treated separately.
> 
> I also agree.  But, don't we have a mechanism for that?  It sounds like
> some additional targets need to call $(BOARD_SIZE_CHECK) at the end.  Or
> am I missing something?
> 

Hmm, I believe that is true. I haven't looked deeper into it but it seems
that's the thing the SPL is missing.

> -- 
> Tom

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Simon Goldschmidt]

Am Mo., 4. Feb. 2019, 16:16 hat Abel Vesa <abel.vesa@nxp.com> geschrieben:

> On 19-02-04 08:19:23, Tom Rini wrote:
> > On Mon, Feb 04, 2019 at 09:03:43AM -0200, Fabio Estevam wrote:
> > > On Mon, Feb 4, 2019 at 7:55 AM Abel Vesa <abel.vesa@nxp.com> wrote:
> > >
> > > > If the SPL size (without the dtb appended) is larger then yes, the
> build fails.
> > > > Trouble is if the SPL (without the dtb appended) is, lets say, 63kB
> and
> > > > then the dtb is larger than 1kB. Then there is no mechanism in place
> to check that
> > > > and it will just fail to boot without giving any clues why. But this
> is a totally
> > > > unrelated problem from this patchset's point of view and I think it
> impacts all
> > > > the platforms that support SPL with DM.
> > >
> > > Yes, it is unrelated to this series and should be treated separately.
> >
> > I also agree.  But, don't we have a mechanism for that?  It sounds like
> > some additional targets need to call $(BOARD_SIZE_CHECK) at the end.  Or
> > am I missing something?
> >
>
> Hmm, I believe that is true. I haven't looked deeper into it but it seems
> that's the thing the SPL is missing.


Haven't we talked about that just some days or weeks ago? That's exactly
what I am missing for socfpga. I keep getting broken SPL images when adding
functionality. And you don't even get an error message because the dtb is
broken and cannot provide the serial output mode...

Regards,
Simon

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Tom Rini]

On Mon, Feb 04, 2019 at 04:21:37PM +0100, Simon Goldschmidt wrote:
> Am Mo., 4. Feb. 2019, 16:16 hat Abel Vesa <abel.vesa@nxp.com> geschrieben:
> 
> > On 19-02-04 08:19:23, Tom Rini wrote:
> > > On Mon, Feb 04, 2019 at 09:03:43AM -0200, Fabio Estevam wrote:
> > > > On Mon, Feb 4, 2019 at 7:55 AM Abel Vesa <abel.vesa@nxp.com> wrote:
> > > >
> > > > > If the SPL size (without the dtb appended) is larger then yes, the
> > build fails.
> > > > > Trouble is if the SPL (without the dtb appended) is, lets say, 63kB
> > and
> > > > > then the dtb is larger than 1kB. Then there is no mechanism in place
> > to check that
> > > > > and it will just fail to boot without giving any clues why. But this
> > is a totally
> > > > > unrelated problem from this patchset's point of view and I think it
> > impacts all
> > > > > the platforms that support SPL with DM.
> > > >
> > > > Yes, it is unrelated to this series and should be treated separately.
> > >
> > > I also agree.  But, don't we have a mechanism for that?  It sounds like
> > > some additional targets need to call $(BOARD_SIZE_CHECK) at the end.  Or
> > > am I missing something?
> > >
> >
> > Hmm, I believe that is true. I haven't looked deeper into it but it seems
> > that's the thing the SPL is missing.
> 
> 
> Haven't we talked about that just some days or weeks ago? That's exactly
> what I am missing for socfpga. I keep getting broken SPL images when adding
> functionality. And you don't even get an error message because the dtb is
> broken and cannot provide the serial output mode...

Yes, I believe it is.  I guess what I'm waiting / hoping for is someone
to patch the top-level Makefile to call $(BOARD_SIZE_CHECK) on a number
of make targets that look reasonable, throw it at travis and see what if
anything fails (and if stuff fails, ask for help to see if it's right or
investigate a bit more).  More or less, if it's a final target for
U-Boot, we should probably give BOARD_SIZE_CHECK a try.  Most of the
rules start with u-boot, but I bet the %.imx target should also do it,
and then we can drop all of that from arch/arm/mach-imx/Makefile.

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190204/e880d7c4/attachment.sig>

[U-Boot] [PATCH v2 00/23] apalis imx6 fixes, device tree enablement and driver model conversion

[Marcel Ziswiler]

This series addresses some shortcomings, enables/introduces device tree
support and converts all except video to using the driver model. This is
fully tested both running our latest downstream BSP as well as the
mainline Linux kernel.

Changes in v2:
- Remove spurious mentioning of DFU MMC both in subject as well as
  description.
- Use GPL-2.0+ OR X11 instead of GPL-2.0 OR MIT to be more consistent
  with all our other device trees.
- Further comments and white-space clean-up.
- Also add SION bit for Apalis, backlight, eMMC reset and Ethernet PHY
  reset GPIOs.
- Also request MMC/SD CD and USB power GPIOs.
- Clean-up and re-order includes.
- White-space clean-up.
- Also update copyright year in PMIC header file.
- And drop compiler.h include.
- Remove Colibri iMX6 change which inadvertently slipped in here.
- Also fix device tree naming for MMC DFU.

Gerard Salvatella (1):
  board: apalis_imx6: check for and report ecc errors in fuses

Marcel Ziswiler (16):
  apalis_imx6: get rid of obsolete nospl configurations
  apalis_imx6: use distro defaults
  apalis_imx6: move console in env from header file to defconfig
  apalis_imx6: enable fit image, gpt, imx thermal, efi loader support
  apalis_imx6: remove obsolete USB_GADGET_MASS_STORAGE configuration
  apalis_imx6: migrate to using device tree
  apalis_imx6: clean-up and migrate gpios to using driver model
  apalis_imx6: enable pin control driver
  apalis_imx6: migrate i2c to using driver model
  apalis_imx6: migrate pmic and regulator to using driver model
  apalis_imx6: migrate mmc and sata to using driver model
  apalis_imx6: migrate usb to using driver model
  apalis_imx6: drop CONFIG_OF_SYSTEM_SETUP
  apalis_imx6: add distroboot support
  apalis_imx6: pf0100: reorder and cleanup message printing
  apalis_imx6: switch to zimage

Max Krummenacher (4):
  apalis_imx6: use both sd/mmc interfaces for setsdupdate
  apalis_imx6: unify sd/mmc drive strength with linux kernel settings
  apalis_imx6: disable ri and dcd irq in uarts
  apalis_imx6: revert fuse value set in mfgr_fuse

Sanchayan Maity (1):
  configs: apalis_imx6: Use ext4 file system by default

Stefan Agner (1):
  apalis_imx6: use SDP if USB serial downloader has been used

 arch/arm/dts/imx6-apalis.dts                  | 730 ++++++++++++++++++
 .../toradex/apalis_imx6/1066mhz_4x128mx16.cfg |  47 --
 .../toradex/apalis_imx6/1066mhz_4x256mx16.cfg |  47 --
 board/toradex/apalis_imx6/MAINTAINERS         |   4 +-
 board/toradex/apalis_imx6/apalis_imx6.c       | 341 ++++----
 board/toradex/apalis_imx6/apalis_imx6q.cfg    |  33 -
 board/toradex/apalis_imx6/clocks.cfg          |  41 -
 board/toradex/apalis_imx6/ddr-setup.cfg       |  96 ---
 board/toradex/apalis_imx6/do_fuse.c           |   2 +-
 board/toradex/apalis_imx6/pf0100.c            | 206 +++--
 board/toradex/apalis_imx6/pf0100.h            |  59 +-
 configs/apalis_imx6_defconfig                 |  35 +-
 configs/apalis_imx6_nospl_com_defconfig       |  65 --
 configs/apalis_imx6_nospl_it_defconfig        |  65 --
 include/configs/apalis_imx6.h                 |  83 +-
 15 files changed, 1119 insertions(+), 735 deletions(-)
 create mode 100644 arch/arm/dts/imx6-apalis.dts
 delete mode 100644 board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
 delete mode 100644 board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
 delete mode 100644 board/toradex/apalis_imx6/apalis_imx6q.cfg
 delete mode 100644 board/toradex/apalis_imx6/clocks.cfg
 delete mode 100644 board/toradex/apalis_imx6/ddr-setup.cfg
 delete mode 100644 configs/apalis_imx6_nospl_com_defconfig
 delete mode 100644 configs/apalis_imx6_nospl_it_defconfig

-- 
2.20.1

[U-Boot] [PATCH v2 01/23] apalis_imx6: get rid of obsolete nospl configurations

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Now with SPL long since being in place even for recovery using SDP
finally get rid of those nospl configurations.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 .../toradex/apalis_imx6/1066mhz_4x128mx16.cfg | 47 ---------
 .../toradex/apalis_imx6/1066mhz_4x256mx16.cfg | 47 ---------
 board/toradex/apalis_imx6/MAINTAINERS         |  2 -
 board/toradex/apalis_imx6/apalis_imx6q.cfg    | 33 -------
 board/toradex/apalis_imx6/clocks.cfg          | 41 --------
 board/toradex/apalis_imx6/ddr-setup.cfg       | 96 -------------------
 configs/apalis_imx6_nospl_com_defconfig       | 65 -------------
 configs/apalis_imx6_nospl_it_defconfig        | 65 -------------
 8 files changed, 396 deletions(-)
 delete mode 100644 board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
 delete mode 100644 board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
 delete mode 100644 board/toradex/apalis_imx6/apalis_imx6q.cfg
 delete mode 100644 board/toradex/apalis_imx6/clocks.cfg
 delete mode 100644 board/toradex/apalis_imx6/ddr-setup.cfg
 delete mode 100644 configs/apalis_imx6_nospl_com_defconfig
 delete mode 100644 configs/apalis_imx6_nospl_it_defconfig

diff --git a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
deleted file mode 100644
index 29d1c3126c..0000000000
--- a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016 Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7954
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB328F64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09555050
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
-DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x432A0338
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03260324
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43340344
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x031E027C
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37
-
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4336453F
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
deleted file mode 100644
index 02e90dd5e6..0000000000
--- a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016 Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E78f5
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xff328f64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
-DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x02888032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03300338
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03240324
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x03440350
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x032C0308
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46
-
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x403E463E
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS
index 2c70ab4fbd..a5d2c84956 100644
--- a/board/toradex/apalis_imx6/MAINTAINERS
+++ b/board/toradex/apalis_imx6/MAINTAINERS
@@ -5,5 +5,3 @@ S:	Maintained
 F:	board/toradex/apalis_imx6/
 F:	include/configs/apalis_imx6.h
 F:	configs/apalis_imx6_defconfig
-F:	configs/apalis_imx6_nospl_com_defconfig
-F:	configs/apalis_imx6_nospl_it_defconfig
diff --git a/board/toradex/apalis_imx6/apalis_imx6q.cfg b/board/toradex/apalis_imx6/apalis_imx6q.cfg
deleted file mode 100644
index 739b1b7061..0000000000
--- a/board/toradex/apalis_imx6/apalis_imx6q.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM      sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-#include "ddr-setup.cfg"
-#if CONFIG_DDR_MB == 2048
-#include "1066mhz_4x256mx16.cfg"
-#else
-#include "1066mhz_4x128mx16.cfg"
-#endif
-#include "clocks.cfg"
diff --git a/board/toradex/apalis_imx6/clocks.cfg b/board/toradex/apalis_imx6/clocks.cfg
deleted file mode 100644
index 1bcbc4fa38..0000000000
--- a/board/toradex/apalis_imx6/clocks.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/apalis_imx6/ddr-setup.cfg b/board/toradex/apalis_imx6/ddr-setup.cfg
deleted file mode 100644
index e42e3ce438..0000000000
--- a/board/toradex/apalis_imx6/ddr-setup.cfg
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/*
- * DDR3 settings
- * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 32 bits	x16/x32
- */
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
-
-/* (differential input) */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-/* (differential input) */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-/* disable ddr pullups */
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-
-/* Read data DQ Byte0-3 delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
-
-/*
- * MDSCR	con_req
- */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig
deleted file mode 100644
index b6ab5285c2..0000000000
--- a/configs/apalis_imx6_nospl_com_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_APALIS_IMX6=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DWC_AHSATA=y
-CONFIG_DFU_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4020
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig
deleted file mode 100644
index c972b11eb5..0000000000
--- a/configs/apalis_imx6_nospl_it_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_APALIS_IMX6=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=2048"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DWC_AHSATA=y
-CONFIG_DFU_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4020
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
-- 
2.20.1

[U-Boot] [PATCH v2 02/23] apalis_imx6: use distro defaults

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Use distro defaults and minimise default configuration again using
savedefconfig.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 configs/apalis_imx6_defconfig | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 86dabd3736..f7fb7a5f8a 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -9,12 +9,11 @@ CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_MISC_INIT_R=y
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -26,9 +25,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_USB_HOST_SUPPORT=y
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
@@ -43,14 +40,8 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DWC_AHSATA=y
@@ -61,7 +52,6 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_MII=y
 CONFIG_USB=y
-CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-- 
2.20.1

[U-Boot] [PATCH v2 03/23] apalis_imx6: move console in env from header file to defconfig

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Move console in env from header file to defconfig.

While at it also update copyright year and remove spurious comments and
new lines.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2:
- Remove spurious mentioning of DFU MMC both in subject as well as
  description.

 configs/apalis_imx6_defconfig | 1 +
 include/configs/apalis_imx6.h | 4 +---
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index f7fb7a5f8a..098d791a62 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -14,6 +14,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_MISC_INIT_R=y
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index ba4e96da50..a1ba16fc79 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2013-2015 Toradex, Inc.
+ * Copyright 2013-2019 Toradex, Inc.
  *
  * Configuration settings for the Toradex Apalis iMX6
  */
@@ -86,7 +86,6 @@
 
 /* Framebuffer and LCD */
 #define CONFIG_VIDEO_IPUV3
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
@@ -255,7 +254,6 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /* environment organization */
-
 #define CONFIG_ENV_SIZE			(8 * 1024)
 
 #if defined(CONFIG_ENV_IS_IN_MMC)
-- 
2.20.1

[U-Boot] [PATCH v2 04/23] apalis_imx6: enable fit image, gpt, imx thermal, efi loader support

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Enbale FIT image, GPT command, i.MX thermal and EFI loader support.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 configs/apalis_imx6_defconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 098d791a62..b262bb88b9 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -11,6 +11,7 @@ CONFIG_SPL=y
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
@@ -36,6 +37,7 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -52,6 +54,7 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_MII=y
+CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
@@ -65,4 +68,3 @@ CONFIG_VIDEO=y
 CONFIG_FAT_WRITE=y
 CONFIG_OF_LIBFDT=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-# CONFIG_EFI_LOADER is not set
-- 
2.20.1

[U-Boot] [PATCH v2 05/23] apalis_imx6: remove obsolete USB_GADGET_MASS_STORAGE configuration

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Remove obsolete USB_GADGET_MASS_STORAGE configuration.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 include/configs/apalis_imx6.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index a1ba16fc79..7222285ab3 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -82,8 +82,6 @@
 /* Client */
 #define CONFIG_USBD_HS
 
-#define CONFIG_USB_GADGET_MASS_STORAGE
-
 /* Framebuffer and LCD */
 #define CONFIG_VIDEO_IPUV3
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-- 
2.20.1

[U-Boot] [PATCH v2 06/23] apalis_imx6: migrate to using device tree

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate to using device tree required for further driver model
integration.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2:
- Use GPL-2.0+ OR X11 instead of GPL-2.0 OR MIT to be more consistent
  with all our other device trees.
- Further comments and white-space clean-up.

 arch/arm/dts/imx6-apalis.dts          | 730 ++++++++++++++++++++++++++
 board/toradex/apalis_imx6/MAINTAINERS |   2 +
 configs/apalis_imx6_defconfig         |   3 +-
 3 files changed, 734 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx6-apalis.dts

diff --git a/arch/arm/dts/imx6-apalis.dts b/arch/arm/dts/imx6-apalis.dts
new file mode 100644
index 0000000000..b2fdfa1af4
--- /dev/null
+++ b/arch/arm/dts/imx6-apalis.dts
@@ -0,0 +1,730 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6q.dtsi"
+
+/ {
+	model = "Toradex Apalis iMX6Q/D";
+	compatible = "toradex,apalis_imx6q", "fsl,imx6q";
+
+	/* Will be filled by the bootloader */
+	memory at 10000000 {
+		device_type = "memory";
+		reg = <0x10000000 0>;
+	};
+
+	aliases {
+		mmc0 = &usdhc3;
+		mmc1 = &usdhc1;
+		mmc2 = &usdhc2;
+		usb0 = &usbotg; /* required for ums */
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	reg_module_3v3: regulator-module-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "+V3.3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* USBO1_EN */
+		enable-active-high;
+	};
+
+	/* on-module USB hub */
+	reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
+		regulator-name = "usb_host_vbus_hub";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <2000>;
+		enable-active-high;
+	};
+
+	reg_usb_host_vbus: regulator-usb-host-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
+		regulator-name = "usb_host_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* USBH_EN */
+		enable-active-high;
+		vin-supply = <&reg_usb_host_vbus_hub>;
+	};
+};
+
+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	pmic: pfuze100 at 8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+/*
+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
+ * board)
+ */
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_recovery>;
+	scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+/* Apalis Serial ATA */
+&sata {
+	status = "okay";
+};
+
+/* Apalis UART1 */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
+	fsl,dte-mode;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+/* Apalis UART2 */
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_dte>;
+	fsl,dte-mode;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+/* Apalis UART3 */
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4_dte>;
+	fsl,dte-mode;
+	status = "okay";
+};
+
+/* Apalis UART4 */
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5_dte>;
+	fsl,dte-mode;
+	status = "okay";
+};
+
+/* Apalis USBH[2|3|4] */
+&usbh1 {
+	dr_mode = "host";
+	vbus-supply = <&reg_usb_host_vbus>;
+	status = "okay";
+};
+
+/* Apalis USBO1 */
+&usbotg {
+	dr_mode = "host";
+	vbus-supply = <&reg_usb_otg_vbus>;
+	status = "okay";
+};
+
+/* Apalis MMC1 */
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
+	cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; /* MMC1_CD */
+	disable-wp;
+	no-1-8-v;
+	status = "okay";
+};
+
+/* Apalis SD1 */
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;	/* SD1_CD */
+	disable-wp;
+	no-1-8-v;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	vqmmc-supply = <&reg_module_3v3>;
+	bus-width = <8>;
+	no-1-8-v;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_apalis_gpio1: gpio2io04grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D4__GPIO2_IO04	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio2: gpio2io05grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D5__GPIO2_IO05	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio3: gpio2io06grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D6__GPIO2_IO06	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio4: gpio2io07grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D7__GPIO2_IO07	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio5: gpio6io10grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_RB0__GPIO6_IO10	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio6: gpio6io09grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio7: gpio1io02grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio8: gpio1io06grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_6__GPIO1_IO06	0x130b0
+		>;
+	};
+
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT20__AUD4_TXC	0x130b0
+			MX6QDL_PAD_DISP0_DAT21__AUD4_TXD	0x130b0
+			MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS	0x130b0
+			MX6QDL_PAD_DISP0_DAT23__AUD4_RXD	0x130b0
+			/* SGTL5000 sys_mclk */
+			MX6QDL_PAD_GPIO_5__CCM_CLKO1		0x130b0
+		>;
+	};
+
+	pinctrl_cam_mclk: cammclkgrp {
+		fsl,pins = <
+			/* CAM sys_mclk */
+			MX6QDL_PAD_NANDF_CS2__CCM_CLKO2	0x00b0
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO	0x100b1
+			MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI	0x100b1
+			MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK	0x100b1
+			/* SPI1 cs */
+			MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25	0x000b1
+		>;
+	};
+
+	pinctrl_ecspi2: ecspi2grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_OE__ECSPI2_MISO	0x100b1
+			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI	0x100b1
+			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK	0x100b1
+			/* SPI2 cs */
+			MX6QDL_PAD_EIM_RW__GPIO2_IO26	0x000b1
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			/* Ethernet PHY reset */
+			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x000b0
+			/* Ethernet PHY interrupt */
+			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x000b1
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX	0x1b0b0
+			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX	0x1b0b0
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x1b0b0
+			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x1b0b0
+		>;
+	};
+
+	pinctrl_gpio_bl_on: gpioblon {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
+		>;
+	};
+
+	pinctrl_gpio_keys: gpio1io04grp {
+		fsl,pins = <
+			/* Power button */
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+		>;
+	};
+
+	pinctrl_hdmi_cec: hdmicecgrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+		>;
+	};
+
+	pinctrl_hdmi_ddc: hdmiddcgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL	0x4001b8b1
+			MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA	0x4001b8b1
+			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL	0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__I2C3_SCL	0x4001b8b1
+			MX6QDL_PAD_EIM_D18__I2C3_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3_recovery: i2c3recoverygrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__GPIO3_IO17	0x4001b8b1
+			MX6QDL_PAD_EIM_D18__GPIO3_IO18	0x4001b8b1
+		>;
+	};
+
+	pinctrl_ipu1_lcdif: ipu1lcdifgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK	0x61
+			/* DE */
+			MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15	0x61
+			/* HSync */
+			MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02	0x61
+			/* VSync */
+			MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03	0x61
+			MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00	0x61
+			MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01	0x61
+			MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02	0x61
+			MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03	0x61
+			MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04	0x61
+			MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05	0x61
+			MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06	0x61
+			MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07	0x61
+			MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08	0x61
+			MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09	0x61
+			MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10	0x61
+			MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11	0x61
+			MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12	0x61
+			MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13	0x61
+			MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14	0x61
+			MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15	0x61
+			MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16	0x61
+			MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17	0x61
+			MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18	0x61
+			MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19	0x61
+			MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20	0x61
+			MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21	0x61
+			MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22	0x61
+			MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23	0x61
+		>;
+	};
+
+	pinctrl_ipu2_vdac: ipu2vdacgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK	0xd1
+			MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15		0xd1
+			MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02		0xd1
+			MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03		0xd1
+			MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00	0xf9
+			MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01	0xf9
+			MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02	0xf9
+			MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03	0xf9
+			MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04	0xf9
+			MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05	0xf9
+			MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06	0xf9
+			MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07	0xf9
+			MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08	0xf9
+			MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09	0xf9
+			MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10	0xf9
+			MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11	0xf9
+			MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12	0xf9
+			MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13	0xf9
+			MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14	0xf9
+			MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15	0xf9
+		>;
+	};
+
+	pinctrl_mmc_cd: gpiommccdgrp {
+		fsl,pins = <
+			 /* MMC1 CD */
+			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20	0x000b0
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_9__PWM1_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__PWM2_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm3: pwm3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT1__PWM3_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm4: pwm4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT2__PWM4_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
+		fsl,pins = <
+			/* USBH_EN */
+			MX6QDL_PAD_GPIO_0__GPIO1_IO00	0x0f058
+		>;
+	};
+
+	pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
+		fsl,pins = <
+			/* USBH_HUB_EN */
+			MX6QDL_PAD_EIM_D28__GPIO3_IO28	0x0f058
+		>;
+	};
+
+	pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
+		fsl,pins = <
+			/* USBO1 power en */
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22	0x0f058
+		>;
+	};
+
+	pinctrl_reset_moci: gpioresetmocigrp {
+		fsl,pins = <
+			/* RESET_MOCI control */
+			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x0f058
+		>;
+	};
+
+	pinctrl_sd_cd: gpiosdcdgrp {
+		fsl,pins = <
+			/* SD1 CD */
+			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x000b0
+		>;
+	};
+
+	pinctrl_spdif: spdifgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_16__SPDIF_IN	0x1b0b0
+			MX6QDL_PAD_GPIO_17__SPDIF_OUT	0x1b0b0
+		>;
+	};
+
+	pinctrl_touch_int: gpiotouchintgrp {
+		fsl,pins = <
+			/* STMPE811 interrupt */
+			MX6QDL_PAD_KEY_COL2__GPIO4_IO10	0x1b0b0
+		>;
+	};
+
+	pinctrl_uart1_dce: uart1dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart1_dte: uart1dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D19__UART1_RTS_B		0x1b0b1
+			MX6QDL_PAD_EIM_D20__UART1_CTS_B		0x1b0b1
+		>;
+	};
+
+	/* Additional DTR, DSR, DCD */
+	pinctrl_uart1_ctrl: uart1ctrlgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D23__UART1_DCD_B	0x1b0b0
+			MX6QDL_PAD_EIM_D24__UART1_DTR_B	0x1b0b0
+			MX6QDL_PAD_EIM_D25__UART1_DSR_B	0x1b0b0
+		>;
+	};
+
+	pinctrl_uart2_dce: uart2dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart2_dte: uart2dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT6__UART2_RTS_B	0x1b0b1
+			MX6QDL_PAD_SD4_DAT5__UART2_CTS_B	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart4_dce: uart4dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart4_dte: uart4dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__UART4_RX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart5_dce: uart5dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart5_dte: uart5dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL1__UART5_RX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
+		>;
+	};
+
+	pinctrl_usdhc1_4bit: usdhc1grp_4bit {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17071
+			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10071
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17071
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17071
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17071
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17071
+		>;
+	};
+
+	pinctrl_usdhc1_8bit: usdhc1grp_8bit {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D0__SD1_DATA4	0x17071
+			MX6QDL_PAD_NANDF_D1__SD1_DATA5	0x17071
+			MX6QDL_PAD_NANDF_D2__SD1_DATA6	0x17071
+			MX6QDL_PAD_NANDF_D3__SD1_DATA7	0x17071
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD	0x17071
+			MX6QDL_PAD_SD2_CLK__SD2_CLK	0x10071
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0	0x17071
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1	0x17071
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2	0x17071
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3	0x17071
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
+			/* eMMC reset */
+			MX6QDL_PAD_SD3_RST__SD3_RESET	0x17059
+		>;
+	};
+};
diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS
index a5d2c84956..7efe816a78 100644
--- a/board/toradex/apalis_imx6/MAINTAINERS
+++ b/board/toradex/apalis_imx6/MAINTAINERS
@@ -1,7 +1,9 @@
 Apalis iMX6
 M:	Max Krummenacher <max.krummenacher@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
+W:      https://www.toradex.com/community
 S:	Maintained
 F:	board/toradex/apalis_imx6/
 F:	include/configs/apalis_imx6.h
 F:	configs/apalis_imx6_defconfig
+F:	arch/arm/dts/imx6-apalis.dts
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index b262bb88b9..985d8554b8 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -45,6 +45,8 @@ CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6-apalis"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DWC_AHSATA=y
@@ -66,5 +68,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_VIDEO=y
 CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-- 
2.20.1

[U-Boot] [PATCH v2 07/23] apalis_imx6: clean-up and migrate gpios to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate GPIOs to using driver model, properly request backlight,
Ethernet PHY reset, MMC/SD card detect and USB power GPIOs and also
enable SION bit in pin muxing for Apalis, backlight, eMMC reset,
Ethernet PHY reset and USB power enable GPIOs.

While at it also update copyright year, clean-up/re-order includes,
add some comments clarifying ifdef scope and do some White-space
clean-up.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2:
- Also add SION bit for Apalis, backlight, eMMC reset and Ethernet PHY
  reset GPIOs.
- Also request MMC/SD CD and USB power GPIOs.
- Clean-up and re-order includes.
- White-space clean-up.

 board/toradex/apalis_imx6/apalis_imx6.c | 90 ++++++++++++++-----------
 configs/apalis_imx6_defconfig           |  1 +
 2 files changed, 53 insertions(+), 38 deletions(-)

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 368db9c488..0a60b36447 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -2,38 +2,32 @@
 /*
  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  * copied from nitrogen6x
  */
 
 #include <common.h>
 #include <dm.h>
-#include <environment.h>
+
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
-#include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mx6-pins.h>
 #include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/bootm.h>
 #include <asm/gpio.h>
-#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/sata.h>
-#include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/video.h>
 #include <dm/platform_data/serial_mxc.h>
-#include <dm/platdata.h>
+#include <environment.h>
 #include <fsl_esdhc.h>
 #include <i2c.h>
-#include <input.h>
 #include <imx_thermal.h>
-#include <linux/errno.h>
-#include <malloc.h>
-#include <mmc.h>
 #include <micrel.h>
 #include <miiphy.h>
 #include <netdev.h>
@@ -200,7 +194,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
 	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 };
 
 int mx6_rgmii_rework(struct phy_device *phydev)
@@ -241,7 +235,8 @@ iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	/* KSZ9031 PHY Reset */
-	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL) |
+						  MUX_MODE_SION,
 #	define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 };
 
@@ -253,6 +248,7 @@ static void setup_iomux_enet(void)
 static int reset_enet_phy(struct mii_dev *bus)
 {
 	/* Reset KSZ9031 PHY */
+	gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#");
 	gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
 	mdelay(10);
 	gpio_set_value(GPIO_ENET_PHY_RESET, 1);
@@ -263,15 +259,24 @@ static int reset_enet_phy(struct mii_dev *bus)
 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 iomux_v3_cfg_t const gpio_pads[] = {
 	/* Apalis GPIO1 - GPIO8 */
-	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D5__GPIO2_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D7__GPIO2_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLDOWN),
-	MX6_PAD_GPIO_6__GPIO1_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D5__GPIO2_IO05	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D7__GPIO2_IO07	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLDOWN) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_6__GPIO1_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 };
 
 static void setup_iomux_gpio(void)
@@ -281,7 +286,7 @@ static void setup_iomux_gpio(void)
 
 iomux_v3_cfg_t const usb_pads[] = {
 	/* USBH_EN */
-	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 #	define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 	/* USB_VBUS_DET */
 	MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -289,7 +294,7 @@ iomux_v3_cfg_t const usb_pads[] = {
 	/* USBO1_ID */
 	MX6_PAD_ENET_RX_ER__USB_OTG_ID	| MUX_PAD_CTRL(WEAK_PULLUP),
 	/* USBO1_EN */
-	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 #	define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 };
 
@@ -321,7 +326,6 @@ static void setup_iomux_dte_uart(void)
 	imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 					 ARRAY_SIZE(uart1_pads_dte));
 }
-
 static void setup_iomux_dce_uart(void)
 {
 	setup_dcemode_uart();
@@ -360,7 +364,7 @@ int board_ehci_power(int port, int on)
 #endif
 
 #ifdef CONFIG_FSL_ESDHC
-/* use the following sequence: eMMC, MMC, SD */
+/* use the following sequence: eMMC, MMC1, SD1 */
 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 	{USDHC3_BASE_ADDR},
 	{USDHC1_BASE_ADDR},
@@ -374,10 +378,12 @@ int board_mmc_getcd(struct mmc *mmc)
 
 	switch (cfg->esdhc_base) {
 	case USDHC1_BASE_ADDR:
+		gpio_request(GPIO_MMC_CD, "MMC_CD");
 		gpio_direction_input(GPIO_MMC_CD);
 		ret = !gpio_get_value(GPIO_MMC_CD);
 		break;
 	case USDHC2_BASE_ADDR:
+		gpio_request(GPIO_MMC_CD, "SD_CD");
 		gpio_direction_input(GPIO_SD_CD);
 		ret = !gpio_get_value(GPIO_SD_CD);
 		break;
@@ -424,7 +430,7 @@ int board_mmc_init(bd_t *bis)
 	}
 
 	return status;
-#else
+#else /* CONFIG_SPL_BUILD */
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
 	unsigned reg = readl(&psrc->sbmr1) >> 11;
 	/*
@@ -463,9 +469,9 @@ int board_mmc_init(bd_t *bis)
 	}
 
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
+#endif /* CONFIG_SPL_BUILD */
 }
-#endif
+#endif /* CONFIG_FSL_ESDHC */
 
 int board_phy_config(struct phy_device *phydev)
 {
@@ -489,6 +495,7 @@ int board_eth_init(bd_t *bis)
 	bus = fec_get_miibus(base, -1);
 	if (!bus)
 		return 0;
+
 	bus->reset = reset_enet_phy;
 	/* scan PHY 4,5,6,7 */
 	phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
@@ -497,6 +504,7 @@ int board_eth_init(bd_t *bis)
 		puts("no PHY found\n");
 		return 0;
 	}
+
 	printf("using PHY@%d\n", phydev->addr);
 	ret = fec_probe(bis, -1, base, bus, phydev);
 	if (ret) {
@@ -504,7 +512,8 @@ int board_eth_init(bd_t *bis)
 		free(phydev);
 		free(bus);
 	}
-#endif
+#endif /* CONFIG_FEC_MXC */
+
 	return 0;
 }
 
@@ -520,18 +529,21 @@ static iomux_v3_cfg_t const pwr_intb_pads[] = {
 
 static iomux_v3_cfg_t const backlight_pads[] = {
 	/* Backlight on RGB connector: J15 */
-	MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 	/* additional CPU pin on BKL_PWM, keep in tristate */
 	MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 	/* Backlight PWM, used as GPIO in U-Boot */
-	MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 	/* buffer output enable 0: buffer enabled */
-	MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 	/* PSAVE# integrated VDAC */
-	MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 };
 
@@ -741,6 +753,9 @@ static void setup_display(void)
 	imx_iomux_v3_setup_multiple_pads(backlight_pads,
 					 ARRAY_SIZE(backlight_pads));
 	/* use 0 for EDT 7", use 1 for LG fullHD panel */
+	gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
+	gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
+	gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 	gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
@@ -1134,7 +1149,6 @@ MX6_MMDC_P0_MDSCR, 0x00000000,
 MX6_MMDC_P0_MAPSR, 0x00011006,
 };
 
-
 static void ccgr_init(void)
 {
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -1223,7 +1237,7 @@ void reset_cpu(ulong addr)
 {
 }
 
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 static struct mxc_serial_platdata mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART1_BASE,
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 985d8554b8..0f6119bef5 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -51,6 +51,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DWC_AHSATA=y
 CONFIG_DFU_MMC=y
+CONFIG_DM_GPIO=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
-- 
2.20.1

[U-Boot] [PATCH v2 08/23] apalis_imx6: enable pin control driver

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Enable pin control driver as required for further driver model
migration.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 configs/apalis_imx6_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 0f6119bef5..0763b1d986 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -57,6 +57,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
-- 
2.20.1

[U-Boot] [PATCH v2 09/23] apalis_imx6: migrate i2c to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate I2C to using driver model.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2:
- Also update copyright year in PMIC header file.
- And drop compiler.h include.

 board/toradex/apalis_imx6/apalis_imx6.c | 88 +------------------------
 board/toradex/apalis_imx6/pf0100.c      | 59 ++++++++---------
 board/toradex/apalis_imx6/pf0100.h      |  2 +-
 configs/apalis_imx6_defconfig           |  1 +
 include/configs/apalis_imx6.h           |  8 +--
 5 files changed, 36 insertions(+), 122 deletions(-)

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 0a60b36447..2c16c31021 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -20,13 +20,11 @@
 #include <asm/gpio.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/video.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <environment.h>
 #include <fsl_esdhc.h>
-#include <i2c.h>
 #include <imx_thermal.h>
 #include <micrel.h>
 #include <miiphy.h>
@@ -50,32 +48,16 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
 #define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_SRE_SLOW)
 
-#define NO_PULLUP	(					\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_SRE_SLOW)
-
 #define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 
 #define TRISTATE	(PAD_CTL_HYS | PAD_CTL_SPEED_MED)
 
-#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
-
 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
 
 int dram_init(void)
@@ -97,63 +79,6 @@ iomux_v3_cfg_t const uart1_pads_dte[] = {
 	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* Apalis I2C1 */
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
-		.gp = IMX_GPIO_NR(5, 26)
-	}
-};
-
-/* Apalis local, PMIC, SGTL5000, STMPE811 */
-struct i2c_pads_info i2c_pad_info_loc = {
-	.scl = {
-		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-/* Apalis I2C3 / CAM */
-struct i2c_pads_info i2c_pad_info3 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
-		.gp = IMX_GPIO_NR(3, 17)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
-		.gp = IMX_GPIO_NR(3, 18)
-	}
-};
-
-/* Apalis I2C2 / DDC */
-struct i2c_pads_info i2c_pad_info_ddc = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
-		.gp = IMX_GPIO_NR(2, 30)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
-		.gp = IMX_GPIO_NR(3, 16)
-	}
-};
-
 /* Apalis MMC1 */
 iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -583,12 +508,6 @@ static void do_enable_hdmi(struct display_info_t const *dev)
 	imx_enable_hdmi_phy();
 }
 
-static int detect_i2c(struct display_info_t const *dev)
-{
-	return (0 == i2c_set_bus_num(dev->bus)) &&
-	       (0 == i2c_probe(dev->addr));
-}
-
 static void enable_lvds(struct display_info_t const *dev)
 {
 	struct iomuxc *iomux = (struct iomuxc *)
@@ -682,7 +601,6 @@ struct display_info_t const displays[] = {{
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_LVDS666,
-	.detect	= detect_i2c,
 	.enable	= enable_lvds,
 	.mode	= {
 		.name           = "wsvga-lvds",
@@ -788,10 +706,6 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_display();
 #endif
@@ -1209,7 +1123,7 @@ void board_init_f(ulong dummy)
 	ccgr_init();
 	gpr_init();
 
-	/* iomux and setup of i2c */
+	/* iomux */
 	board_early_init_f();
 
 	/* setup GP timer */
diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c
index 7334e92f2e..3a944b3699 100644
--- a/board/toradex/apalis_imx6/pf0100.c
+++ b/board/toradex/apalis_imx6/pf0100.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  */
 
 /*
@@ -9,7 +9,6 @@
 
 #include <common.h>
 #include <i2c.h>
-#include <linux/compiler.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
@@ -30,22 +29,25 @@ static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
 
 unsigned pmic_init(void)
 {
+	int rc;
+	struct udevice *dev = NULL;
 	unsigned programmed = 0;
 	uchar bus = 1;
 	uchar devid, revid, val;
 
 	puts("PMIC: ");
-	if (!((0 == i2c_set_bus_num(bus)) &&
-	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
-		puts("i2c bus failed\n");
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC at address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
 		return 0;
 	}
 	/* get device ident */
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) {
 		puts("i2c pmic devid read failed\n");
 		return 0;
 	}
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) {
 		puts("i2c pmic revid read failed\n");
 		return 0;
 	}
@@ -60,7 +62,7 @@ unsigned pmic_init(void)
 		for (j = 0; j < 0x80; ) {
 			printf("\n%2x", j);
 			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				dm_i2c_read(dev, j + i, &val, 1);
 				printf("\t%2x", val);
 			}
 			j += 0x10;
@@ -68,8 +70,7 @@ unsigned pmic_init(void)
 		printf("\nEXT Page 1");
 
 		val = PFUZE100_PAGE_REGISTER_PAGE1;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
-			      &val, 1)) {
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
 			puts("i2c write failed\n");
 			return 0;
 		}
@@ -77,7 +78,7 @@ unsigned pmic_init(void)
 		for (j = 0x80; j < 0x100; ) {
 			printf("\n%2x", j);
 			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				dm_i2c_read(dev, j + i, &val, 1);
 				printf("\t%2x", val);
 			}
 			j += 0x10;
@@ -85,8 +86,7 @@ unsigned pmic_init(void)
 		printf("\nEXT Page 2");
 
 		val = PFUZE100_PAGE_REGISTER_PAGE2;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
-			      &val, 1)) {
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
 			puts("i2c write failed\n");
 			return 0;
 		}
@@ -94,35 +94,35 @@ unsigned pmic_init(void)
 		for (j = 0x80; j < 0x100; ) {
 			printf("\n%2x", j);
 			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				dm_i2c_read(dev, j + i, &val, 1);
 				printf("\t%2x", val);
 			}
 			j += 0x10;
 		}
 		printf("\n");
 	}
-#endif
+#endif /* DEBUG */
 	/* get device programmed state */
 	val = PFUZE100_PAGE_REGISTER_PAGE1;
-	if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) {
+	if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
 		puts("i2c write failed\n");
 		return 0;
 	}
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return 0;
 	}
 	if (val & PFUZE100_FUSE_POR_M)
 		programmed++;
 
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return programmed;
 	}
 	if (val & PFUZE100_FUSE_POR_M)
 		programmed++;
 
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return programmed;
 	}
@@ -145,18 +145,15 @@ unsigned pmic_init(void)
 	if (programmed != 3) {
 		/* set VGEN1 to 1.2V */
 		val = PFUZE100_VGEN1_VAL;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_VGEN1CTL, 1,
-			      &val, 1)) {
+		if (dm_i2c_write(dev, PFUZE100_VGEN1CTL, &val, 1)) {
 			puts("i2c write failed\n");
 			return programmed;
 		}
 
 		/* set SWBST to 5.0V */
 		val = PFUZE100_SWBST_VAL;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_SWBSTCTL, 1,
-			      &val, 1)) {
+		if (dm_i2c_write(dev, PFUZE100_SWBSTCTL, &val, 1))
 			puts("i2c write failed\n");
-		}
 	}
 	return programmed;
 }
@@ -164,6 +161,8 @@ unsigned pmic_init(void)
 #ifndef CONFIG_SPL_BUILD
 static int pf0100_prog(void)
 {
+	int rc;
+	struct udevice *dev = NULL;
 	unsigned char bus = 1;
 	unsigned char val;
 	unsigned int i;
@@ -177,9 +176,10 @@ static int pf0100_prog(void)
 					 ARRAY_SIZE(pmic_prog_pads));
 	gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
 
-	if (!((0 == i2c_set_bus_num(bus)) &&
-	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
-		puts("i2c bus failed\n");
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC@address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
 		return CMD_RET_FAILURE;
 	}
 
@@ -187,8 +187,7 @@ static int pf0100_prog(void)
 		switch (pmic_otp_prog[i].cmd) {
 		case pmic_i2c:
 			val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
-			if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
-				      1, &val, 1)) {
+			if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) {
 				printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
 				       pmic_otp_prog[i].reg, val);
 				return CMD_RET_FAILURE;
@@ -227,4 +226,4 @@ U_BOOT_CMD(
 	"Program the OTP fuses on the PMIC PF0100",
 	""
 );
-#endif
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/toradex/apalis_imx6/pf0100.h b/board/toradex/apalis_imx6/pf0100.h
index c0efb79bbc..b854fe8c54 100644
--- a/board/toradex/apalis_imx6/pf0100.h
+++ b/board/toradex/apalis_imx6/pf0100.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  */
 
 /*
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 0763b1d986..60c4d9720d 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -52,6 +52,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DWC_AHSATA=y
 CONFIG_DFU_MMC=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 7222285ab3..5ab009c8f3 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -34,12 +34,12 @@
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 /* I2C Configs */
-#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_MXC_I2C3_SPEED	400000
 
 /* OCOTP Configs */
 #ifdef CONFIG_CMD_FUSE
-- 
2.20.1

[U-Boot] [PATCH v2 10/23] apalis_imx6: migrate pmic and regulator to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate PMIC and regulator to using driver model.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 configs/apalis_imx6_defconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 60c4d9720d..7e973ded74 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -45,6 +45,8 @@ CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6-apalis"
 CONFIG_ENV_IS_IN_MMC=y
@@ -60,6 +62,11 @@ CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
-- 
2.20.1

[U-Boot] [PATCH v2 11/23] apalis_imx6: migrate mmc and sata to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate MMC and SATA to using driver model.

While at it also enable SCSI driver model.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/apalis_imx6/apalis_imx6.c | 98 +++++++++++++++----------
 configs/apalis_imx6_defconfig           |  3 +
 include/configs/apalis_imx6.h           |  3 -
 3 files changed, 61 insertions(+), 43 deletions(-)

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 2c16c31021..db06c4e064 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <dm.h>
 
+#include <ahci.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/imx-regs.h>
@@ -22,7 +23,9 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/video.h>
+#include <dm/device-internal.h>
 #include <dm/platform_data/serial_mxc.h>
+#include <dwc_ahsata.h>
 #include <environment.h>
 #include <fsl_esdhc.h>
 #include <imx_thermal.h>
@@ -60,6 +63,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
 
+#define APALIS_IMX6_SATA_INIT_RETRIES	10
+
 int dram_init(void)
 {
 	/* use the DDR controllers configured size */
@@ -79,6 +84,7 @@ iomux_v3_cfg_t const uart1_pads_dte[] = {
 	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 /* Apalis MMC1 */
 iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -121,6 +127,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
 	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 };
+#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 
 int mx6_rgmii_rework(struct phy_device *phydev)
 {
@@ -288,7 +295,7 @@ int board_ehci_power(int port, int on)
 }
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
+#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 /* use the following sequence: eMMC, MMC1, SD1 */
 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 	{USDHC3_BASE_ADDR},
@@ -319,43 +326,6 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_init(bd_t *bis)
 {
-#ifndef CONFIG_SPL_BUILD
-	s32 status = 0;
-	u32 index = 0;
-
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
-	usdhc_cfg[0].max_bus_width = 8;
-	usdhc_cfg[1].max_bus_width = 8;
-	usdhc_cfg[2].max_bus_width = 4;
-
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-		switch (index) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-			break;
-		case 2:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
-			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return status;
-		}
-
-		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-	}
-
-	return status;
-#else /* CONFIG_SPL_BUILD */
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
 	unsigned reg = readl(&psrc->sbmr1) >> 11;
 	/*
@@ -394,9 +364,8 @@ int board_mmc_init(bd_t *bis)
 	}
 
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif /* CONFIG_SPL_BUILD */
 }
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 
 int board_phy_config(struct phy_device *phydev)
 {
@@ -1162,3 +1131,52 @@ U_BOOT_DEVICE(mxc_serial) = {
 	.name = "serial_mxc",
 	.platdata = &mxc_serial_plat,
 };
+
+#if CONFIG_IS_ENABLED(AHCI)
+static int sata_imx_probe(struct udevice *dev)
+{
+	int i, err;
+
+	for (i = 0; i < APALIS_IMX6_SATA_INIT_RETRIES; i++) {
+		err = setup_sata();
+		if (err) {
+			printf("SATA setup failed: %d\n", err);
+			return err;
+		}
+
+		udelay(100);
+
+		err = dwc_ahsata_probe(dev);
+		if (!err)
+			break;
+
+		/* There is no device on the SATA port */
+		if (sata_dm_port_status(0, 0) == 0)
+			break;
+
+		/* There's a device, but link not established. Retry */
+		device_remove(dev, DM_REMOVE_NORMAL);
+	}
+
+	return 0;
+}
+
+struct ahci_ops sata_imx_ops = {
+	.port_status = dwc_ahsata_port_status,
+	.reset	= dwc_ahsata_bus_reset,
+	.scan	= dwc_ahsata_scan,
+};
+
+static const struct udevice_id sata_imx_ids[] = {
+	{ .compatible = "fsl,imx6q-ahci" },
+	{ }
+};
+
+U_BOOT_DRIVER(sata_imx) = {
+	.name		= "dwc_ahci",
+	.id		= UCLASS_AHCI,
+	.of_match	= sata_imx_ids,
+	.ops		= &sata_imx_ops,
+	.probe		= sata_imx_probe,
+};
+#endif /* AHCI */
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 7e973ded74..510161ad32 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -9,6 +9,7 @@ CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_CMD_HDMIDETECT=y
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
@@ -55,6 +56,7 @@ CONFIG_DWC_AHSATA=y
 CONFIG_DFU_MMC=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
@@ -67,6 +69,7 @@ CONFIG_DM_PMIC_PFUZE100=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_SCSI=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 5ab009c8f3..6b20d1e104 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -57,9 +57,6 @@
  * SATA Configs
  */
 #ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE	1
-#define CONFIG_DWC_AHSATA_PORT_ID	0
-#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
 #define CONFIG_LBA48
 #endif
 
-- 
2.20.1

[U-Boot] [PATCH v2 12/23] apalis_imx6: migrate usb to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate USB to using driver model.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/apalis_imx6/apalis_imx6.c | 22 ----------------------
 configs/apalis_imx6_defconfig           |  1 +
 2 files changed, 1 insertion(+), 22 deletions(-)

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index db06c4e064..1faa94f99d 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -271,28 +271,6 @@ int board_ehci_hcd_init(int port)
 	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 	return 0;
 }
-
-int board_ehci_power(int port, int on)
-{
-	switch (port) {
-	case 0:
-		/* control OTG power */
-		gpio_direction_output(GPIO_USBO_EN, on);
-		mdelay(100);
-		break;
-	case 1:
-		/* Control MXM USBH */
-		gpio_direction_output(GPIO_USBH_EN, on);
-		mdelay(2);
-		/* Control onboard USB Hub VBUS */
-		gpio_direction_output(GPIO_USB_VBUS_DET, on);
-		mdelay(100);
-		break;
-	default:
-		break;
-	}
-	return 0;
-}
 #endif
 
 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 510161ad32..1ab5edc966 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -72,6 +72,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_SCSI=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-- 
2.20.1

[U-Boot] [PATCH v2 13/23] apalis_imx6: drop CONFIG_OF_SYSTEM_SETUP

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

This doesn't do anything anymore, probably never did.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/apalis_imx6/apalis_imx6.c | 7 -------
 include/configs/apalis_imx6.h           | 2 --
 2 files changed, 9 deletions(-)

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 1faa94f99d..254fa4ddfb 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -706,13 +706,6 @@ int board_late_init(void)
 }
 #endif /* CONFIG_BOARD_LATE_INIT */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
-int ft_system_setup(void *blob, bd_t *bd)
-{
-	return 0;
-}
-#endif
-
 int checkboard(void)
 {
 	char it[] = " IT";
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 6b20d1e104..382048d2ef 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -259,8 +259,6 @@
 #define CONFIG_SYS_MMC_ENV_PART		1
 #endif
 
-#define CONFIG_OF_SYSTEM_SETUP
-
 #define CONFIG_CMD_TIME
 
 #endif	/* __CONFIG_H */
-- 
2.20.1

[U-Boot] [PATCH v2 14/23] apalis_imx6: add distroboot support

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Add support for distro boot. This is especially helpful for external
devices. There is a global boot command which scans a predefined
list of boot targets:
  run distro_bootcmd

As well as direct boot commands such as:
  run bootcmd_mmc1
  run bootcmd_mmc2
  run bootcmd_usb
  run bootcmd_dhcp
  ...

Refer to doc/README.distro for details.

While at it, remove the CONFIG_DRIVE_TYPES define which has not
been used and was meant to be used for multi device boot support
which is now provided by distroboot.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 include/configs/apalis_imx6.h | 30 ++++++++++++++++--------------
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 382048d2ef..5f865e1f08 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -109,20 +109,19 @@
 
 #define CONFIG_LOADADDR			0x12000000
 
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_DRIVE_SATA "sata "
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
 #else
-#define CONFIG_DRIVE_SATA
+#define BOOTENV
 #endif
 
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_DRIVE_MMC "mmc "
-#else
-#define CONFIG_DRIVE_MMC
-#endif
-
-#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
-
 #define DFU_ALT_EMMC_INFO \
 	"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
 	"boot part 0 1;" \
@@ -149,7 +148,9 @@
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"kernel_addr_r=0x11000000\0" \
-	"ramdisk_addr_r=0x12100000\0"
+	"pxefile_addr_r=0x17100000\0" \
+	"ramdisk_addr_r=0x12100000\0" \
+	"scriptaddr=0x17000000\0"
 
 #define NFS_BOOTCMD \
 	"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
@@ -191,9 +192,10 @@
 #define FDT_FILE "imx6q-apalis_v1_0-eval.dtb"
 #endif
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
 	"bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
-		"run nfsboot ; echo ; echo nfsboot failed ; " \
-		"usb start ;" \
+		"run distro_bootcmd ; " \
+		"usb start ; " \
 		"setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
 	"boot_file=uImage\0" \
 	"console=ttymxc0\0" \
-- 
2.20.1

[U-Boot] [PATCH v2 15/23] apalis_imx6: use both sd/mmc interfaces for setsdupdate

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

During porting to 2016.11 the check of a SD (mmc2) interface
was dropped, this was unintended.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 include/configs/apalis_imx6.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 5f865e1f08..7df32feb0d 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -210,8 +210,10 @@
 	"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
 		"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
 		"flash_eth.img && source ${loadaddr}\0" \
-	"setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \
-		"${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+	"setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \
+		"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \
+		"|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1" \
+		" ${loadaddr} flash_blk.img && " \
 		"source ${loadaddr}\0" \
 	"setup=setenv setupargs fec_mac=${ethaddr} " \
 		"consoleblank=0 no_console_suspend=1 console=tty1 " \
-- 
2.20.1

[U-Boot] [PATCH v2 16/23] apalis_imx6: unify sd/mmc drive strength with linux kernel settings

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

In the Linux device tree we use 40Ohm drive strength. So use the same
value in U-Boot.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/apalis_imx6/apalis_imx6.c | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 254fa4ddfb..cfdadda939 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -45,6 +45,10 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |		\
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
@@ -115,16 +119,16 @@ iomux_v3_cfg_t const usdhc2_pads[] = {
 
 /* eMMC */
 iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 };
 #endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
-- 
2.20.1

[U-Boot] [PATCH v2 17/23] apalis_imx6: pf0100: reorder and cleanup message printing

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Keep debug code at the end of the function.
Use a one line informational message for the PMIC only.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/apalis_imx6/pf0100.c | 110 +++++++++++++++--------------
 1 file changed, 56 insertions(+), 54 deletions(-)

diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c
index 3a944b3699..8106abf89a 100644
--- a/board/toradex/apalis_imx6/pf0100.c
+++ b/board/toradex/apalis_imx6/pf0100.c
@@ -35,7 +35,7 @@ unsigned pmic_init(void)
 	uchar bus = 1;
 	uchar devid, revid, val;
 
-	puts("PMIC: ");
+	puts("PMIC:  ");
 	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
 	if (rc) {
 		printf("failed to get device for PMIC at address 0x%x\n",
@@ -51,57 +51,8 @@ unsigned pmic_init(void)
 		puts("i2c pmic revid read failed\n");
 		return 0;
 	}
-	printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
+	printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid);
 
-#ifdef DEBUG
-	{
-		unsigned i, j;
-
-		for (i = 0; i < 16; i++)
-			printf("\t%x", i);
-		for (j = 0; j < 0x80; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				dm_i2c_read(dev, j + i, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\nEXT Page 1");
-
-		val = PFUZE100_PAGE_REGISTER_PAGE1;
-		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
-			puts("i2c write failed\n");
-			return 0;
-		}
-
-		for (j = 0x80; j < 0x100; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				dm_i2c_read(dev, j + i, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\nEXT Page 2");
-
-		val = PFUZE100_PAGE_REGISTER_PAGE2;
-		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
-			puts("i2c write failed\n");
-			return 0;
-		}
-
-		for (j = 0x80; j < 0x100; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				dm_i2c_read(dev, j + i, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\n");
-	}
-#endif /* DEBUG */
 	/* get device programmed state */
 	val = PFUZE100_PAGE_REGISTER_PAGE1;
 	if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
@@ -131,13 +82,13 @@ unsigned pmic_init(void)
 
 	switch (programmed) {
 	case 0:
-		printf("PMIC: not programmed\n");
+		puts("not programmed\n");
 		break;
 	case 3:
-		printf("PMIC: programmed\n");
+		puts("programmed\n");
 		break;
 	default:
-		printf("PMIC: undefined programming state\n");
+		puts("undefined programming state\n");
 		break;
 	}
 
@@ -155,6 +106,57 @@ unsigned pmic_init(void)
 		if (dm_i2c_write(dev, PFUZE100_SWBSTCTL, &val, 1))
 			puts("i2c write failed\n");
 	}
+
+#ifdef DEBUG
+	{
+		unsigned int i, j;
+
+		for (i = 0; i < 16; i++)
+			printf("\t%x", i);
+		for (j = 0; j < 0x80; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 1");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE1;
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 2");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE2;
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\n");
+	}
+#endif /* DEBUG */
+
 	return programmed;
 }
 
-- 
2.20.1

[U-Boot] [PATCH v2 18/23] apalis_imx6: disable ri and dcd irq in uarts

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

If the UART is used in DTE mode the RI and DCD bits in UCR3 become
irq enable bits. Both are set to enabled after reset and both likely
are pending.

Disable the bits also on UARTs not used in the boot loader to prevent
an interrupt storm when Linux enables the UART interrupts.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/apalis_imx6/apalis_imx6.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index cfdadda939..2c90a40042 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -238,8 +238,11 @@ iomux_v3_cfg_t const usb_pads[] = {
  * UARTs are used in DTE mode, switch the mode on all UARTs before
  * any pinmuxing connects a (DCE) output to a transceiver output.
  */
+#define UCR3		0x88	/* FIFO Control Register */
+#define UCR3_RI		BIT(8)	/* RIDELT DTE mode */
+#define UCR3_DCD	BIT(9)	/* DCDDELT DTE mode */
 #define UFCR		0x90	/* FIFO Control Register */
-#define UFCR_DCEDTE	(1<<6)	/* DCE=0 */
+#define UFCR_DCEDTE	BIT(6)	/* DCE=0 */
 
 static void setup_dtemode_uart(void)
 {
@@ -247,6 +250,11 @@ static void setup_dtemode_uart(void)
 	setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 	setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 	setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
+
+	clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
 }
 static void setup_dcemode_uart(void)
 {
-- 
2.20.1

[U-Boot] [PATCH v2 19/23] apalis_imx6: revert fuse value set in mfgr_fuse

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

We have two commands to change the bootmode fuses:
mfgr_fuse which set fuse 0/5 and 0/6
and
updt_fuse which burns bit 4 of 0/5.

Before BSP 2.6 we fused in mfgr_fuse 0x5062, which boots
from the user partition of the eMMC.
To workaround certain hangs we moved to fastboot mode and
using the first bootpartition of the eMMC requiring a fuse
value of 0x5072 which could be achieved by the then added
updt_fuse command. At the same time the mfgr_fuse command
was changed to also fuse 0x5072, revert that second change
so that one can fuse both values, one with just mfgr_fuse
and the later with mfgr_fuse;updt_fuse.

Note that the mfgr_fuse command is only needed at module
production time, a customer might need to use updt_fuse
when upgrading an older module to be compatible with a
newer image. The command is integrated into the image
update scripts.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2:
- Remove Colibri iMX6 change which inadvertently slipped in here.

 board/toradex/apalis_imx6/do_fuse.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c
index e6793e366a..22d191f52a 100644
--- a/board/toradex/apalis_imx6/do_fuse.c
+++ b/board/toradex/apalis_imx6/do_fuse.c
@@ -29,7 +29,7 @@ static int mfgr_fuse(void)
 		return CMD_RET_FAILURE;
 	}
 	/* boot cfg */
-	fuse_prog(0, 5, 0x00005072);
+	fuse_prog(0, 5, 0x00005062);
 	/* BT_FUSE_SEL */
 	fuse_prog(0, 6, 0x00000010);
 	return CMD_RET_SUCCESS;
-- 
2.20.1

[U-Boot] [PATCH v2 20/23] configs: apalis_imx6: Use ext4 file system by default

[Marcel Ziswiler]

From: Sanchayan Maity <maitysanchayan@gmail.com>

Use ext4 file system by default.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 include/configs/apalis_imx6.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 7df32feb0d..a49b08ba45 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -131,7 +131,7 @@
 	"imx6q-colibri-cam-eval-v3.dtb fat 0 1"
 
 #define EMMC_BOOTCMD \
-	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
+	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"emmcboot=run setup; " \
 		"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
@@ -163,7 +163,7 @@
 		"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
 #define SD_BOOTCMD						\
-	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
+	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"sdboot=run setup; " \
 		"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
@@ -175,7 +175,7 @@
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
 #define USB_BOOTCMD \
-	"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
+	"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
 		"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
-- 
2.20.1

[U-Boot] [PATCH v2 21/23] apalis_imx6: use SDP if USB serial downloader has been used

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

In case USB serial downloader has been used to load U-Boot start the
serial download protocol (SDP) emulation. This allows to download
complete images such as Toradex Easy Installer over USB SDP as well.
This code uses the boot ROM provided boot information to reliably
detect USB serial downloader.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/apalis_imx6/apalis_imx6.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 2c90a40042..ce54638c4c 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -714,6 +714,14 @@ int board_late_init(void)
 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 #endif /* CONFIG_REVISION_TAG */
 
+#ifdef CONFIG_CMD_USB_SDP
+	if (is_boot_from_usb()) {
+		printf("Serial Downloader recovery mode, using sdp command\n");
+		env_set("bootdelay", "0");
+		env_set("bootcmd", "sdp 0");
+	}
+#endif /* CONFIG_CMD_USB_SDP */
+
 	return 0;
 }
 #endif /* CONFIG_BOARD_LATE_INIT */
-- 
2.20.1

[U-Boot] [PATCH v2 22/23] apalis_imx6: switch to zimage

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Switch to the generic compressed Kernel image type (zImage) instead of
the U-Boot specific uImage format.

While at it also fix device tree naming for MMC DFU.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2:
- Also fix device tree naming for MMC DFU.

 include/configs/apalis_imx6.h | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index a49b08ba45..c8aa1bdddf 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -118,17 +118,17 @@
 #include <config_distro_bootcmd.h>
 #undef BOOTENV_RUN_NET_USB_START
 #define BOOTENV_RUN_NET_USB_START ""
-#else
+#else /* CONFIG_SPL_BUILD */
 #define BOOTENV
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 #define DFU_ALT_EMMC_INFO \
 	"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
 	"boot part 0 1;" \
 	"rootfs part 0 2;" \
-	"uImage fat 0 1;" \
-	"imx6q-colibri-eval-v3.dtb fat 0 1;" \
-	"imx6q-colibri-cam-eval-v3.dtb fat 0 1"
+	"zImage fat 0 1;" \
+	"imx6q-apalis-eval.dtb fat 0 1;" \
+	"imx6q-apalis-cam-eval.dtb fat 0 1"
 
 #define EMMC_BOOTCMD \
 	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \
@@ -138,7 +138,7 @@
 		"${vidargs}; echo Booting from internal eMMC chip...; "	\
 		"run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
@@ -158,11 +158,11 @@
 		"setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
 		"${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
 		"run nfsdtbload; dhcp ${kernel_addr_r} " \
-		"&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
 		"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
-#define SD_BOOTCMD						\
+#define SD_BOOTCMD \
 	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"sdboot=run setup; " \
@@ -170,7 +170,7 @@
 		"${vidargs}; echo Booting from SD card; " \
 		"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
@@ -181,7 +181,7 @@
 		"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
 		"usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
@@ -197,7 +197,7 @@
 		"run distro_bootcmd ; " \
 		"usb start ; " \
 		"setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
-	"boot_file=uImage\0" \
+	"boot_file=zImage\0" \
 	"console=ttymxc0\0" \
 	"defargs=enable_wait_mode=off vmalloc=400M\0" \
 	"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
-- 
2.20.1

[U-Boot] [PATCH v2 23/23] board: apalis_imx6: check for and report ecc errors in fuses

[Marcel Ziswiler]

From: Gerard Salvatella <gerard.salvatella@toradex.com>

The PMIC on Apalis iMX6 may have ECC errors in fuses that will prevent
correct settings. Up to one bit error per fuse bank may be reported and
corrected by the ECC logic. Two bit errors can only be reported.

Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/apalis_imx6/pf0100.c | 51 ++++++++++++++++++++++++++
 board/toradex/apalis_imx6/pf0100.h | 57 +++++++++++++++++++++++++++++-
 2 files changed, 107 insertions(+), 1 deletion(-)

diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c
index 8106abf89a..ebd6418fd4 100644
--- a/board/toradex/apalis_imx6/pf0100.c
+++ b/board/toradex/apalis_imx6/pf0100.c
@@ -21,6 +21,8 @@
 /* define for PMIC register dump */
 /*#define DEBUG */
 
+#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n"
+
 /* use Apalis GPIO1 to switch on VPGM, ON: 1 */
 static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
 	MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -42,6 +44,55 @@ unsigned pmic_init(void)
 		       PFUZE100_I2C_ADDR);
 		return 0;
 	}
+
+	/* check for errors in PMIC fuses */
+	if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) {
+		puts("i2c pmic INTSTAT3 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BIT_OTP_ECCI) {
+		puts("\n" WARNBAR);
+		puts("WARNING: ecc errors found in pmic fuse banks\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE1 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE1) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 1 to 5\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE2 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE2) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 6 to 10\n"
+		    );
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE1) {
+		puts(WARNBAR);
+		puts("ERROR: banks 1 to 5 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE2) {
+		puts(WARNBAR);
+		puts("ERROR: banks 6 to 10 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+
 	/* get device ident */
 	if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) {
 		puts("i2c pmic devid read failed\n");
diff --git a/board/toradex/apalis_imx6/pf0100.h b/board/toradex/apalis_imx6/pf0100.h
index b854fe8c54..9257620511 100644
--- a/board/toradex/apalis_imx6/pf0100.h
+++ b/board/toradex/apalis_imx6/pf0100.h
@@ -10,11 +10,23 @@
 #ifndef PF0100_H_
 #define PF0100_H_
 
+/* bit definitions */
+#define PFUZE100_BIT_0			(0x01 << 0)
+#define PFUZE100_BIT_1			(0x01 << 1)
+#define PFUZE100_BIT_2			(0x01 << 2)
+#define PFUZE100_BIT_3			(0x01 << 3)
+#define PFUZE100_BIT_4			(0x01 << 4)
+#define PFUZE100_BIT_5			(0x01 << 5)
+#define PFUZE100_BIT_6			(0x01 << 6)
+#define PFUZE100_BIT_7			(0x01 << 7)
+
 /* 7-bit I2C bus slave address */
 #define PFUZE100_I2C_ADDR		(0x08)
 /* Register Addresses */
 #define PFUZE100_DEVICEID		(0x0)
 #define PFUZE100_REVID			(0x3)
+#define PFUZE100_INTSTAT3		(0xe)
+#define PFUZE100_BIT_OTP_ECCI		PFUZE100_BIT_7
 #define PFUZE100_SW1AMODE		(0x23)
 #define PFUZE100_SW1ACON		36
 #define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
@@ -39,12 +51,55 @@
 #define PFUZE100_PAGE_REGISTER_PAGE2	(0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
 
 /* extended page 1 */
+#define PFUZE100_OTP_ECC_SE1		0x8a
+#define PFUZE100_BIT_ECC1_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE1		((PFUZE100_BIT_ECC1_SE) | \
+					(PFUZE100_BIT_ECC2_SE) | \
+					(PFUZE100_BIT_ECC3_SE) | \
+					(PFUZE100_BIT_ECC4_SE) | \
+					(PFUZE100_BIT_ECC5_SE))
+#define PFUZE100_OTP_ECC_SE2		0x8b
+#define PFUZE100_BIT_ECC6_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE2		((PFUZE100_BIT_ECC6_SE) | \
+					(PFUZE100_BIT_ECC7_SE) | \
+					(PFUZE100_BIT_ECC8_SE) | \
+					(PFUZE100_BIT_ECC9_SE) | \
+					(PFUZE100_BIT_ECC10_SE))
+#define PFUZE100_OTP_ECC_DE1		0x8c
+#define PFUZE100_BIT_ECC1_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE1		((PFUZE100_BIT_ECC1_DE) | \
+					(PFUZE100_BIT_ECC2_DE) | \
+					(PFUZE100_BIT_ECC3_DE) | \
+					(PFUZE100_BIT_ECC4_DE) | \
+					(PFUZE100_BIT_ECC5_DE))
+#define PFUZE100_OTP_ECC_DE2		0x8d
+#define PFUZE100_BIT_ECC6_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE2		((PFUZE100_BIT_ECC6_DE) | \
+					(PFUZE100_BIT_ECC7_DE) | \
+					(PFUZE100_BIT_ECC8_DE) | \
+					(PFUZE100_BIT_ECC9_DE) | \
+					(PFUZE100_BIT_ECC10_DE))
 #define PFUZE100_FUSE_POR1		0xe4
 #define PFUZE100_FUSE_POR2		0xe5
 #define PFUZE100_FUSE_POR3		0xe6
 #define PFUZE100_FUSE_POR_M		(0x1 << 1)
 
-
 /* output some informational messages, return the number FUSE_POR=1 */
 /* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
 unsigned pmic_init(void);
-- 
2.20.1

[U-Boot] [PATCH v1 00/26] colibri imx6 fixes, device tree enablement and driver model conversion

[Marcel Ziswiler]

This series addresses some shortcomings, enables/introduces device tree
support and converts all except video to using the driver model. This is
fully tested both running our latest downstream BSP as well as the
mainline Linux kernel.


Bhuvanchandra DV (2):
  toradex: colibri_imx6: overwrite CMA memory set in device tree
  colibri_imx6: switch to zimage

Gerard Salvatella (2):
  colibri_imx6: added nreset gpio on reboot
  board: colibri_imx6: check for and report ecc errors in fuses

Marcel Ziswiler (12):
  colibri_imx6: get rid of obsolete nospl configurations
  colibri_imx6: use distro defaults
  colibri_imx6: move console in env from header file to defconfig
  colibri_imx6: enable fit image, gpt, imx thermal, efi loader support
  colibri_imx6: remove obsolete USB_GADGET_MASS_STORAGE configuration
  colibri_imx6: migrate to using device tree
  colibri_imx6: clean-up and migrate gpios to using driver model
  colibri_imx6: enable pin control driver
  colibri_imx6: migrate i2c to using driver model
  colibri_imx6: migrate pmic and regulator to using driver model
  colibri_imx6: migrate mmc to using driver model
  colibri_imx6: migrate usb to using driver model

Max Krummenacher (7):
  colibri_imx6: drop CONFIG_OF_SYSTEM_SETUP
  colibri_imx6: print also 64-bit IT
  colibri_imx6: unify sd/mmc drive strenght with linux kernel settings
  colibri imx6: pf0100: reorder and cleanup message printing
  colibri imx6: disable ri and dcd irq in uarts
  colibri_imx6: change pmic fusing according to hw 1.1 requirements
  colibri_imx6: revert fuse value set in mfgr_fuse

Sanchayan Maity (1):
  configs: colibri_imx6: Use ext4 file system by default

Stefan Agner (2):
  colibri_imx6: add distroboot support
  colibri_imx6: use SDP if USB serial downloader has been used

 arch/arm/dts/imx6-colibri.dts                 | 411 ++++++++++++++++++
 .../toradex/colibri_imx6/800mhz_2x64mx16.cfg  |  58 ---
 .../toradex/colibri_imx6/800mhz_4x64mx16.cfg  |  58 ---
 board/toradex/colibri_imx6/MAINTAINERS        |   3 +-
 board/toradex/colibri_imx6/clocks.cfg         |  41 --
 board/toradex/colibri_imx6/colibri_imx6.c     | 395 +++++++++--------
 board/toradex/colibri_imx6/colibri_imx6.cfg   |  37 --
 board/toradex/colibri_imx6/ddr-setup.cfg      |  97 -----
 board/toradex/colibri_imx6/do_fuse.c          |   2 +-
 board/toradex/colibri_imx6/pf0100.c           | 177 +++++---
 board/toradex/colibri_imx6/pf0100.h           |  59 ++-
 board/toradex/colibri_imx6/pf0100_otp.inc     |  16 +-
 configs/colibri_imx6_defconfig                |  33 +-
 configs/colibri_imx6_nospl_defconfig          |  63 ---
 include/configs/colibri_imx6.h                |  66 +--
 15 files changed, 853 insertions(+), 663 deletions(-)
 create mode 100644 arch/arm/dts/imx6-colibri.dts
 delete mode 100644 board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
 delete mode 100644 board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
 delete mode 100644 board/toradex/colibri_imx6/clocks.cfg
 delete mode 100644 board/toradex/colibri_imx6/colibri_imx6.cfg
 delete mode 100644 board/toradex/colibri_imx6/ddr-setup.cfg
 delete mode 100644 configs/colibri_imx6_nospl_defconfig

-- 
2.20.1

[U-Boot] [PATCH v1 01/26] colibri_imx6: get rid of obsolete nospl configurations

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Now with SPL long since being in place even for recovery using SDP
finally get rid of those nospl configurations.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 .../toradex/colibri_imx6/800mhz_2x64mx16.cfg  | 58 -----------
 .../toradex/colibri_imx6/800mhz_4x64mx16.cfg  | 58 -----------
 board/toradex/colibri_imx6/MAINTAINERS        |  1 -
 board/toradex/colibri_imx6/clocks.cfg         | 41 --------
 board/toradex/colibri_imx6/colibri_imx6.cfg   | 37 -------
 board/toradex/colibri_imx6/ddr-setup.cfg      | 97 -------------------
 configs/colibri_imx6_nospl_defconfig          | 63 ------------
 7 files changed, 355 deletions(-)
 delete mode 100644 board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
 delete mode 100644 board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
 delete mode 100644 board/toradex/colibri_imx6/clocks.cfg
 delete mode 100644 board/toradex/colibri_imx6/colibri_imx6.cfg
 delete mode 100644 board/toradex/colibri_imx6/ddr-setup.cfg
 delete mode 100644 configs/colibri_imx6_nospl_defconfig

diff --git a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
deleted file mode 100644
index c9407143d2..0000000000
--- a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
-/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
-/* DDR3 DATA BUS SIZE: 64BIT */
-/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */
-/* DDR3 DATA BUS SIZE: 32BIT */
-DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000
-
-/* Write commands to DDR */
-/* Load Mode Registers */
-/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
-/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
-/* ZQ calibration */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
deleted file mode 100644
index c319d2a729..0000000000
--- a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
-/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
-/* DDR3 DATA BUS SIZE: 64BIT */
-DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000
-/* DDR3 DATA BUS SIZE: 32BIT */
-/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */
-
-/* Write commands to DDR */
-/* Load Mode Registers */
-/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
-/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
-/* ZQ calibration */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS
index 1cc7ef2e71..49999d8cf5 100644
--- a/board/toradex/colibri_imx6/MAINTAINERS
+++ b/board/toradex/colibri_imx6/MAINTAINERS
@@ -5,4 +5,3 @@ S:	Maintained
 F:	board/toradex/colibri_imx6/
 F:	include/configs/colibri_imx6.h
 F:	configs/colibri_imx6_defconfig
-F:	configs/colibri_imx6_nospl_defconfig
diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg
deleted file mode 100644
index 1bcbc4fa38..0000000000
--- a/board/toradex/colibri_imx6/clocks.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/colibri_imx6/colibri_imx6.cfg b/board/toradex/colibri_imx6/colibri_imx6.cfg
deleted file mode 100644
index 517c5eb107..0000000000
--- a/board/toradex/colibri_imx6/colibri_imx6.cfg
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014 Toradex AG
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM      sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-#include "ddr-setup.cfg"
-
-#if CONFIG_DDR_MB == 256
-#include "800mhz_2x64mx16.cfg"
-#elif CONFIG_DDR_MB == 512
-#include "800mhz_4x64mx16.cfg"
-#else
-#error "unknown DDR size"
-#endif
-
-#include "clocks.cfg"
diff --git a/board/toradex/colibri_imx6/ddr-setup.cfg b/board/toradex/colibri_imx6/ddr-setup.cfg
deleted file mode 100644
index a943fd228c..0000000000
--- a/board/toradex/colibri_imx6/ddr-setup.cfg
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/*
- * DDR3 settings
- * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 32 bits	x16/x32
- */
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
-
-/* (differential input) */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-/* (differential input) */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-/* disable ddr pullups */
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-
-/* Read data DQ Byte0-3 delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-/* TODO: check what the RALAT field does */
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
-
-/*
- * MDSCR	con_req
- */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/configs/colibri_imx6_nospl_defconfig b/configs/colibri_imx6_nospl_defconfig
deleted file mode 100644
index 5e9490bc42..0000000000
--- a/configs/colibri_imx6_nospl_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_COLIBRI_IMX6=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Colibri iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DFU_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
-- 
2.20.1

[U-Boot] [PATCH v1 02/26] colibri_imx6: use distro defaults

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Use distro defaults and minimise default configuration again using
savedefconfig.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 configs/colibri_imx6_defconfig | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 2072281354..699eb70088 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -9,12 +9,11 @@ CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_MISC_INIT_R=y
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -26,9 +25,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_USB_HOST_SUPPORT=y
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri iMX6 # "
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
@@ -43,14 +40,8 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DFU_MMC=y
@@ -59,7 +50,6 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_MII=y
 CONFIG_USB=y
-CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-- 
2.20.1

[U-Boot] [PATCH v1 03/26] colibri_imx6: move console in env from header file to defconfig

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Move console in env from header file to defconfig.

While at it also update copyright year.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 configs/colibri_imx6_defconfig | 1 +
 include/configs/colibri_imx6.h | 3 +--
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 699eb70088..0b31a46cc9 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -14,6 +14,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_MISC_INIT_R=y
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 2d40ceb24e..9e45d63245 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2013-2015 Toradex, Inc.
+ * Copyright 2013-2019 Toradex, Inc.
  *
  * Configuration settings for the Toradex Colibri iMX6
  */
@@ -74,7 +74,6 @@
 
 /* Framebuffer and LCD */
 #define CONFIG_VIDEO_IPUV3
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
-- 
2.20.1

[U-Boot] [PATCH v1 04/26] colibri_imx6: enable fit image, gpt, imx thermal, efi loader support

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Enbale FIT image, GPT command, i.MX thermal and EFI loader support.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 configs/colibri_imx6_defconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 0b31a46cc9..84fa427c8c 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -11,6 +11,7 @@ CONFIG_SPL=y
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
@@ -36,6 +37,7 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -50,6 +52,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_MII=y
+CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
@@ -63,4 +66,3 @@ CONFIG_VIDEO=y
 CONFIG_FAT_WRITE=y
 CONFIG_OF_LIBFDT=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-# CONFIG_EFI_LOADER is not set
-- 
2.20.1

[U-Boot] [PATCH v1 05/26] colibri_imx6: remove obsolete USB_GADGET_MASS_STORAGE configuration

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Remove obsolete USB_GADGET_MASS_STORAGE configuration.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 include/configs/colibri_imx6.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 9e45d63245..f029a885d2 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -70,8 +70,6 @@
 /* Client */
 #define CONFIG_USBD_HS
 
-#define CONFIG_USB_GADGET_MASS_STORAGE
-
 /* Framebuffer and LCD */
 #define CONFIG_VIDEO_IPUV3
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-- 
2.20.1

[U-Boot] [PATCH v1 06/26] colibri_imx6: migrate to using device tree

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate to using device tree required for further driver model
integration.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 arch/arm/dts/imx6-colibri.dts          | 411 +++++++++++++++++++++++++
 board/toradex/colibri_imx6/MAINTAINERS |   2 +
 configs/colibri_imx6_defconfig         |   3 +-
 3 files changed, 415 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx6-colibri.dts

diff --git a/arch/arm/dts/imx6-colibri.dts b/arch/arm/dts/imx6-colibri.dts
new file mode 100644
index 0000000000..5c9f1f0d2b
--- /dev/null
+++ b/arch/arm/dts/imx6-colibri.dts
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6dl.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX6DL/S";
+	compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
+
+	/* Will be filled by the bootloader */
+	memory at 10000000 {
+		device_type = "memory";
+		reg = <0x10000000 0>;
+	};
+
+	aliases {
+		mmc0 = &usdhc3;
+		mmc1 = &usdhc1;
+		usb0 = &usbotg; /* required for ums */
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	reg_module_3v3: regulator-module-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "+V3.3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_usb_host_vbus: regulator-usb-host-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
+		regulator-name = "usb_host_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* USBH_PEN */
+	};
+};
+
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	pmic: pfuze100 at 8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* vgen1: unused */
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* vgen3: unused */
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+/*
+ * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_recovery>;
+	scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+/* Colibri UART_A */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
+	fsl,dte-mode;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+/* Colibri UART_B */
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_dte>;
+	fsl,dte-mode;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+/* Colibri UART_C */
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3_dte>;
+	fsl,dte-mode;
+	status = "okay";
+};
+
+/* Colibri USBH */
+&usbh1 {
+	dr_mode = "host";
+	vbus-supply = <&reg_usb_host_vbus>;
+	status = "okay";
+};
+
+/* Colibri USBC */
+&usbotg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
+	cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
+	disable-wp;
+	vqmmc-supply = <&reg_module_3v3>;
+	bus-width = <4>;
+	no-1-8-v;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	vqmmc-supply = <&reg_module_3v3>;
+	bus-width = <8>;
+	no-1-8-v;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_ecspi4: ecspi4grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D22__ECSPI4_MISO	0x100b1
+			MX6QDL_PAD_EIM_D28__ECSPI4_MOSI	0x100b1
+			MX6QDL_PAD_EIM_D21__ECSPI4_SCLK	0x100b1
+			/* SPI CS */
+			MX6QDL_PAD_EIM_A25__GPIO5_IO02	0x000b1
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
+			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
+			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK     ((1<<30) | 0x1b0b0)
+		>;
+	};
+
+	pinctrl_gpio_bl_on: gpioblon {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D26__GPIO3_IO26	0x1b0b0
+		>;
+	};
+
+	pinctrl_hdmi_ddc: hdmiddcgrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL	0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_EB2__I2C2_SCL	0x4001b8b1
+			MX6QDL_PAD_EIM_D16__I2C2_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL	0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3_recovery: i2c3recoverygrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__GPIO1_IO03	0x4001b8b1
+			MX6QDL_PAD_GPIO_6__GPIO1_IO06	0x4001b8b1
+		>;
+	};
+
+	pinctrl_ipu1_lcdif: ipu1lcdifgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0xa1
+			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0xa1
+			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0xa1
+			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0xa1
+			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0xa1
+			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0xa1
+			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0xa1
+			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0xa1
+			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0xa1
+			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0xa1
+			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0xa1
+			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0xa1
+			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0xa1
+			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0xa1
+			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0xa1
+			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0xa1
+			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0xa1
+			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0xa1
+			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0xa1
+			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0xa1
+			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0xa1
+			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0xa1
+		>;
+	};
+
+	pinctrl_mmc_cd: gpiommccd {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D5__GPIO2_IO05	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_9__PWM1_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__PWM2_OUT	0x1b0b1
+			MX6QDL_PAD_EIM_A21__GPIO2_IO17	0x00040
+		>;
+	};
+
+	pinctrl_pwm3: pwm3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT1__PWM3_OUT	0x1b0b1
+			MX6QDL_PAD_EIM_A22__GPIO2_IO16	0x00040
+		>;
+	};
+
+	pinctrl_pwm4: pwm4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT2__PWM4_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
+		fsl,pins = <
+			/* SODIMM 129 USBH_PEN */
+			MX6QDL_PAD_EIM_D31__GPIO3_IO31	0x0f058
+		>;
+	};
+
+	pinctrl_uart1_dce: uart1dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart1_dte: uart1dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D19__UART1_RTS_B		0x1b0b1
+			MX6QDL_PAD_EIM_D20__UART1_CTS_B		0x1b0b1
+		>;
+	};
+
+	/* Additional DTR, DSR, DCD */
+	pinctrl_uart1_ctrl: uart1ctrlgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D23__UART1_DCD_B	0x1b0b0
+			MX6QDL_PAD_EIM_D24__UART1_DTR_B	0x1b0b0
+			MX6QDL_PAD_EIM_D25__UART1_DSR_B	0x1b0b0
+		>;
+	};
+
+	pinctrl_uart2_dte: uart2dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT6__UART2_RTS_B	0x1b0b1
+			MX6QDL_PAD_SD4_DAT5__UART2_CTS_B	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart3_dte: uart3dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CLK__UART3_TX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_CMD__UART3_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17071
+			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10071
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17071
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17071
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17071
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17071
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
+			/* eMMC reset */
+			MX6QDL_PAD_SD3_RST__SD3_RESET	0x17059
+		>;
+	};
+};
diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS
index 49999d8cf5..e25c07306c 100644
--- a/board/toradex/colibri_imx6/MAINTAINERS
+++ b/board/toradex/colibri_imx6/MAINTAINERS
@@ -1,7 +1,9 @@
 Colibri iMX6
 M:	Max Krummenacher <max.krummenacher@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
+W:      https://www.toradex.com/community
 S:	Maintained
 F:	board/toradex/colibri_imx6/
 F:	include/configs/colibri_imx6.h
 F:	configs/colibri_imx6_defconfig
+F:	arch/arm/dts/imx6-colibri.dts
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 84fa427c8c..47e05b0b26 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -45,6 +45,8 @@ CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DFU_MMC=y
@@ -64,5 +66,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_VIDEO=y
 CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-- 
2.20.1

[U-Boot] [PATCH v1 07/26] colibri_imx6: clean-up and migrate gpios to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate GPIOs to using driver model, properly request backlight, MMC/SD
card detect and USB power enable GPIOs and also enable SION bit in pin
muxing for auxiliary, backlight and USB power enable GPIOs.

While at it also update copyright year, clean-up/re-order includes, add
some comments clarifying ifdef scope and do some white-space clean-up.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/colibri_imx6.c | 209 ++++++++++++++--------
 configs/colibri_imx6_defconfig            |   1 +
 2 files changed, 135 insertions(+), 75 deletions(-)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 68c0c02a8a..1f5de2f5f6 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -2,39 +2,34 @@
 /*
  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  * copied from nitrogen6x
  */
 
 #include <common.h>
 #include <dm.h>
+
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
 #include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/bootm.h>
 #include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/sata.h>
-#include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/video.h>
-#include <asm/io.h>
 #include <dm/platform_data/serial_mxc.h>
-#include <dm/platdata.h>
+#include <environment.h>
 #include <fsl_esdhc.h>
 #include <i2c.h>
-#include <input.h>
 #include <imx_thermal.h>
-#include <linux/errno.h>
-#include <malloc.h>
 #include <micrel.h>
 #include <miiphy.h>
-#include <mmc.h>
 #include <netdev.h>
 
 #include "../common/tdx-cfg-block.h"
@@ -173,68 +168,123 @@ static void setup_iomux_enet(void)
 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
 iomux_v3_cfg_t const gpio_pads[] = {
 	/* ADDRESS[17:18] [25] used as GPIO */
-	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_KEY_COL2__GPIO4_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D1__GPIO2_IO01	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_KEY_COL2__GPIO4_IO10	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D1__GPIO2_IO01	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* ADDRESS[19:24] used as GPIO */
-	MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* DATA[16:29] [31]	 used as GPIO */
-	MX6_PAD_EIM_LBA__GPIO2_IO27	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_CS3__GPIO6_IO16	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_CS1__GPIO6_IO14	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_ALE__GPIO6_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_CS0__GPIO6_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_CLE__GPIO6_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_19__GPIO4_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_CSI0_MCLK__GPIO5_IO19	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_5__GPIO1_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_LBA__GPIO2_IO27	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS3__GPIO6_IO16	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS1__GPIO6_IO14	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_ALE__GPIO6_IO08	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS0__GPIO6_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CLE__GPIO6_IO07	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_19__GPIO4_IO05	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_CSI0_MCLK__GPIO5_IO19	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_5__GPIO1_IO05	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* DQM[0:3]	 used as GPIO */
-	MX6_PAD_EIM_EB0__GPIO2_IO28	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_EB1__GPIO2_IO29	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_SD2_DAT2__GPIO1_IO13	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D0__GPIO2_IO00	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_EB0__GPIO2_IO28	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_EB1__GPIO2_IO29	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD2_DAT2__GPIO1_IO13	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D0__GPIO2_IO00	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* RDY	used as GPIO */
-	MX6_PAD_EIM_WAIT__GPIO5_IO00	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_WAIT__GPIO5_IO00	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* ADDRESS[16] DATA[30]	 used as GPIO */
-	MX6_PAD_KEY_ROW4__GPIO4_IO15	| MUX_PAD_CTRL(WEAK_PULLDOWN),
-	MX6_PAD_KEY_COL4__GPIO4_IO14	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_KEY_ROW4__GPIO4_IO15	| MUX_PAD_CTRL(WEAK_PULLDOWN) |
+					  MUX_MODE_SION,
+	MX6_PAD_KEY_COL4__GPIO4_IO14	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* CSI pins used as GPIO */
-	MX6_PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_SD2_CMD__GPIO1_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_D18__GPIO3_IO18	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_A19__GPIO2_IO19	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_D29__GPIO3_IO29	| MUX_PAD_CTRL(WEAK_PULLDOWN),
-	MX6_PAD_EIM_A23__GPIO6_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_A20__GPIO2_IO18	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_A18__GPIO2_IO20	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_EB3__GPIO2_IO31	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_D17__GPIO3_IO17	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD2_CMD__GPIO1_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D18__GPIO3_IO18	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A19__GPIO2_IO19	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D29__GPIO3_IO29	| MUX_PAD_CTRL(WEAK_PULLDOWN) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A23__GPIO6_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A20__GPIO2_IO18	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A18__GPIO2_IO20	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_EB3__GPIO2_IO31	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D17__GPIO3_IO17	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* GPIO */
-	MX6_PAD_EIM_D26__GPIO3_IO26	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_D27__GPIO3_IO27	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D3__GPIO2_IO03	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DI0_PIN4__GPIO4_IO20	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_SD4_DAT3__GPIO2_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_SD4_DAT0__GPIO2_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_7__GPIO1_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_8__GPIO1_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_D26__GPIO3_IO26	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D27__GPIO3_IO27	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D3__GPIO2_IO03	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DI0_PIN4__GPIO4_IO20	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD4_DAT3__GPIO2_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD4_DAT0__GPIO2_IO08	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_7__GPIO1_IO07	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_8__GPIO1_IO08	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* USBH_OC */
 	MX6_PAD_EIM_D30__GPIO3_IO30	| MUX_PAD_CTRL(WEAK_PULLUP),
 	/* USBC_ID */
@@ -249,8 +299,8 @@ static void setup_iomux_gpio(void)
 }
 
 iomux_v3_cfg_t const usb_pads[] = {
-	/* USB_PE */
-	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* USBH_PEN */
+	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 #	define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
 };
 
@@ -292,6 +342,7 @@ int board_ehci_power(int port, int on)
 	case 1:
 		/* Control MXM USBH */
 		/* Set MXM USBH power enable, '0' means on */
+		gpio_request(GPIO_USBH_EN, "USBH_EN");
 		gpio_direction_output(GPIO_USBH_EN, !on);
 		mdelay(100);
 		break;
@@ -300,7 +351,7 @@ int board_ehci_power(int port, int on)
 	}
 	return 0;
 }
-#endif
+#endif /* CONFIG_USB_EHCI_MX6 */
 
 #ifdef CONFIG_FSL_ESDHC
 /* use the following sequence: eMMC, MMC */
@@ -316,6 +367,7 @@ int board_mmc_getcd(struct mmc *mmc)
 
 	switch (cfg->esdhc_base) {
 	case USDHC1_BASE_ADDR:
+		gpio_request(GPIO_MMC_CD, "MMC_CD");
 		gpio_direction_input(GPIO_MMC_CD);
 		ret = !gpio_get_value(GPIO_MMC_CD);
 		break;
@@ -356,7 +408,7 @@ int board_mmc_init(bd_t *bis)
 	}
 
 	return status;
-#else
+#else /* !CONFIG_SPL_BUILD */
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
 	unsigned reg = readl(&psrc->sbmr1) >> 11;
 	/*
@@ -388,9 +440,9 @@ int board_mmc_init(bd_t *bis)
 	}
 
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
+#endif /* !CONFIG_SPL_BUILD */
 }
-#endif
+#endif /* CONFIG_FSL_ESDHC */
 
 int board_phy_config(struct phy_device *phydev)
 {
@@ -412,6 +464,7 @@ int board_eth_init(bd_t *bis)
 	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 	if (ret)
 		return ret;
+
 	/* set gpr1[ENET_CLK_SEL] */
 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 
@@ -421,6 +474,7 @@ int board_eth_init(bd_t *bis)
 	bus = fec_get_miibus(base, -1);
 	if (!bus)
 		return 0;
+
 	/* scan PHY 1..7 */
 	phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
 	if (!phydev) {
@@ -428,6 +482,7 @@ int board_eth_init(bd_t *bis)
 		puts("no PHY found\n");
 		return 0;
 	}
+
 	phy_reset(phydev);
 	printf("using PHY at %d\n", phydev->addr);
 	ret = fec_probe(bis, -1, base, bus, phydev);
@@ -436,7 +491,8 @@ int board_eth_init(bd_t *bis)
 		free(phydev);
 		free(bus);
 	}
-#endif
+#endif /* CONFIG_FEC_MXC */
+
 	return 0;
 }
 
@@ -452,11 +508,12 @@ static iomux_v3_cfg_t const pwr_intb_pads[] = {
 
 static iomux_v3_cfg_t const backlight_pads[] = {
 	/* Backlight On */
-	MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
 	/* Backlight PWM, used as GPIO in U-Boot */
 	MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
-	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
 };
 
@@ -619,6 +676,8 @@ static void setup_display(void)
 	imx_iomux_v3_setup_multiple_pads(backlight_pads,
 					 ARRAY_SIZE(backlight_pads));
 	/* use 0 for EDT 7", use 1 for LG fullHD panel */
+	gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
+	gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
 	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 }
@@ -1108,7 +1167,7 @@ void reset_cpu(ulong addr)
 {
 }
 
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 static struct mxc_serial_platdata mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART1_BASE,
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 47e05b0b26..27b85c61dc 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -50,6 +50,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DFU_MMC=y
+CONFIG_DM_GPIO=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
-- 
2.20.1

[U-Boot] [PATCH v1 08/26] colibri_imx6: enable pin control driver

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Enable pin control driver as required for further driver model
migration.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 configs/colibri_imx6_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 27b85c61dc..481d65329f 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -55,6 +55,8 @@ CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
-- 
2.20.1

[U-Boot] [PATCH v1 09/26] colibri_imx6: migrate i2c to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate I2C to using driver model.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/colibri_imx6.c | 50 +--------------------
 board/toradex/colibri_imx6/pf0100.c       | 54 ++++++++++++-----------
 configs/colibri_imx6_defconfig            |  1 +
 include/configs/colibri_imx6.h            |  8 ++--
 4 files changed, 36 insertions(+), 77 deletions(-)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 1f5de2f5f6..f5cfeb30bc 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -20,13 +20,11 @@
 #include <asm/gpio.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/video.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <environment.h>
 #include <fsl_esdhc.h>
-#include <i2c.h>
 #include <imx_thermal.h>
 #include <micrel.h>
 #include <miiphy.h>
@@ -50,16 +48,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
 #define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_SRE_SLOW)
@@ -72,8 +60,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 
-#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
-
 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
 
 int dram_init(void)
@@ -91,36 +77,7 @@ iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* Colibri I2C */
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
-		.gp = IMX_GPIO_NR(1, 6)
-	}
-};
-
-/* Colibri local, PMIC, SGTL5000, STMPE811 */
-struct i2c_pads_info i2c_pad_info_loc = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
-		.gp = IMX_GPIO_NR(2, 30)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
-		.gp = IMX_GPIO_NR(3, 16)
-	}
-};
-
-/* Apalis MMC */
+/* Colibri MMC */
 iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -706,9 +663,6 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
-
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_display();
 #endif
@@ -1141,7 +1095,7 @@ void board_init_f(ulong dummy)
 	ccgr_init();
 	gpr_init();
 
-	/* iomux and setup of i2c */
+	/* iomux */
 	board_early_init_f();
 
 	/* setup GP timer */
diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c
index fa63865670..5e411f1743 100644
--- a/board/toradex/colibri_imx6/pf0100.c
+++ b/board/toradex/colibri_imx6/pf0100.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  */
 
 /*
@@ -29,22 +29,25 @@ static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
 
 unsigned pmic_init(void)
 {
+	int rc;
+	struct udevice *dev = NULL;
 	unsigned programmed = 0;
 	uchar bus = 1;
 	uchar devid, revid, val;
 
 	puts("PMIC: ");
-	if (!((0 == i2c_set_bus_num(bus)) &&
-	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
-		puts("i2c bus failed\n");
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC at address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
 		return 0;
 	}
 	/* get device ident */
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) {
 		puts("i2c pmic devid read failed\n");
 		return 0;
 	}
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) {
 		puts("i2c pmic revid read failed\n");
 		return 0;
 	}
@@ -52,14 +55,14 @@ unsigned pmic_init(void)
 
 #ifdef DEBUG
 	{
-		unsigned i, j;
+		unsigned int i, j;
 
 		for (i = 0; i < 16; i++)
 			printf("\t%x", i);
 		for (j = 0; j < 0x80; ) {
 			printf("\n%2x", j);
 			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				dm_i2c_read(dev, j + i, &val, 1);
 				printf("\t%2x", val);
 			}
 			j += 0x10;
@@ -67,8 +70,7 @@ unsigned pmic_init(void)
 		printf("\nEXT Page 1");
 
 		val = PFUZE100_PAGE_REGISTER_PAGE1;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
-			      &val, 1)) {
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
 			puts("i2c write failed\n");
 			return 0;
 		}
@@ -76,7 +78,7 @@ unsigned pmic_init(void)
 		for (j = 0x80; j < 0x100; ) {
 			printf("\n%2x", j);
 			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				dm_i2c_read(dev, j + i, &val, 1);
 				printf("\t%2x", val);
 			}
 			j += 0x10;
@@ -84,8 +86,7 @@ unsigned pmic_init(void)
 		printf("\nEXT Page 2");
 
 		val = PFUZE100_PAGE_REGISTER_PAGE2;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
-			      &val, 1)) {
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
 			puts("i2c write failed\n");
 			return 0;
 		}
@@ -93,35 +94,36 @@ unsigned pmic_init(void)
 		for (j = 0x80; j < 0x100; ) {
 			printf("\n%2x", j);
 			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				dm_i2c_read(dev, j + i, &val, 1);
 				printf("\t%2x", val);
 			}
 			j += 0x10;
 		}
 		printf("\n");
 	}
-#endif
+#endif /* DEBUG */
+
 	/* get device programmed state */
 	val = PFUZE100_PAGE_REGISTER_PAGE1;
-	if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) {
+	if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
 		puts("i2c write failed\n");
 		return 0;
 	}
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return 0;
 	}
 	if (val & PFUZE100_FUSE_POR_M)
 		programmed++;
 
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return programmed;
 	}
 	if (val & PFUZE100_FUSE_POR_M)
 		programmed++;
 
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return programmed;
 	}
@@ -146,6 +148,8 @@ unsigned pmic_init(void)
 #ifndef CONFIG_SPL_BUILD
 static int pf0100_prog(void)
 {
+	int rc;
+	struct udevice *dev = NULL;
 	unsigned char bus = 1;
 	unsigned char val;
 	unsigned int i;
@@ -159,9 +163,10 @@ static int pf0100_prog(void)
 					 ARRAY_SIZE(pmic_prog_pads));
 	gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
 
-	if (!((0 == i2c_set_bus_num(bus)) &&
-	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
-		puts("i2c bus failed\n");
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC@address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
 		return CMD_RET_FAILURE;
 	}
 
@@ -169,8 +174,7 @@ static int pf0100_prog(void)
 		switch (pmic_otp_prog[i].cmd) {
 		case pmic_i2c:
 			val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
-			if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
-				      1, &val, 1)) {
+			if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) {
 				printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
 				       pmic_otp_prog[i].reg, val);
 				return CMD_RET_FAILURE;
@@ -209,4 +213,4 @@ U_BOOT_CMD(
 	"Program the OTP fuses on the PMIC PF0100",
 	""
 );
-#endif
+#endif /* CONFIG_SPL_BUILD */
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 481d65329f..dea6ca6270 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -51,6 +51,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DFU_MMC=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index f029a885d2..e51ec8516f 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -32,12 +32,12 @@
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 /* I2C Configs */
-#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_MXC_I2C3_SPEED	400000
 
 /* OCOTP Configs */
 #ifdef CONFIG_CMD_FUSE
-- 
2.20.1

[U-Boot] [PATCH v1 10/26] colibri_imx6: migrate pmic and regulator to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate PMIC and regulator to using driver model.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 configs/colibri_imx6_defconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index dea6ca6270..6fd050a99f 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -45,6 +45,8 @@ CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri"
 CONFIG_ENV_IS_IN_MMC=y
@@ -58,6 +60,11 @@ CONFIG_PHY_MICREL=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
-- 
2.20.1

[U-Boot] [PATCH v1 11/26] colibri_imx6: migrate mmc to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate MMC to using driver model.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/colibri_imx6.c | 38 +++--------------------
 configs/colibri_imx6_defconfig            |  1 +
 2 files changed, 5 insertions(+), 34 deletions(-)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index f5cfeb30bc..ef4dd0c87c 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -77,6 +77,7 @@ iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 /* Colibri MMC */
 iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -103,6 +104,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
 	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
+#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 
 iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -310,7 +312,7 @@ int board_ehci_power(int port, int on)
 }
 #endif /* CONFIG_USB_EHCI_MX6 */
 
-#ifdef CONFIG_FSL_ESDHC
+#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 /* use the following sequence: eMMC, MMC */
 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 	{USDHC3_BASE_ADDR},
@@ -335,37 +337,6 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_init(bd_t *bis)
 {
-#ifndef CONFIG_SPL_BUILD
-	s32 status = 0;
-	u32 index = 0;
-
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-	usdhc_cfg[0].max_bus_width = 8;
-	usdhc_cfg[1].max_bus_width = 4;
-
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-		switch (index) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
-			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return status;
-		}
-
-		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-	}
-
-	return status;
-#else /* !CONFIG_SPL_BUILD */
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
 	unsigned reg = readl(&psrc->sbmr1) >> 11;
 	/*
@@ -397,9 +368,8 @@ int board_mmc_init(bd_t *bis)
 	}
 
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif /* !CONFIG_SPL_BUILD */
 }
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 
 int board_phy_config(struct phy_device *phydev)
 {
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 6fd050a99f..2ab7db44a8 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -54,6 +54,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DFU_MMC=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
-- 
2.20.1

[U-Boot] [PATCH v1 12/26] colibri_imx6: migrate usb to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate USB to using driver model.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/colibri_imx6.c | 23 +----------------------
 configs/colibri_imx6_defconfig            |  1 +
 2 files changed, 2 insertions(+), 22 deletions(-)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index ef4dd0c87c..adb5a3df4c 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -289,28 +289,7 @@ int board_ehci_hcd_init(int port)
 	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 	return 0;
 }
-
-int board_ehci_power(int port, int on)
-{
-	switch (port) {
-	case 0:
-		/* control OTG power */
-		/* No special PE for USBC, always on when ID pin signals
-		   host mode */
-		break;
-	case 1:
-		/* Control MXM USBH */
-		/* Set MXM USBH power enable, '0' means on */
-		gpio_request(GPIO_USBH_EN, "USBH_EN");
-		gpio_direction_output(GPIO_USBH_EN, !on);
-		mdelay(100);
-		break;
-	default:
-		break;
-	}
-	return 0;
-}
-#endif /* CONFIG_USB_EHCI_MX6 */
+#endif
 
 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 /* use the following sequence: eMMC, MMC */
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 2ab7db44a8..df5a7be39f 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -68,6 +68,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-- 
2.20.1

[U-Boot] [PATCH v1 13/26] colibri_imx6: drop CONFIG_OF_SYSTEM_SETUP

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

This doesn't do anything anymore, probably never did.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/colibri_imx6.c | 7 -------
 include/configs/colibri_imx6.h            | 2 --
 2 files changed, 9 deletions(-)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index adb5a3df4c..83ecd20b3d 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -646,13 +646,6 @@ int board_late_init(void)
 }
 #endif /* CONFIG_BOARD_LATE_INIT */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
-int ft_system_setup(void *blob, bd_t *bd)
-{
-	return 0;
-}
-#endif
-
 int checkboard(void)
 {
 	char it[] = " IT";
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index e51ec8516f..c782b2924c 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -237,8 +237,6 @@
 #define CONFIG_SYS_MMC_ENV_PART		1
 #endif
 
-#define CONFIG_OF_SYSTEM_SETUP
-
 #define CONFIG_CMD_TIME
 
 #endif	/* __CONFIG_H */
-- 
2.20.1

[U-Boot] [PATCH v1 14/26] colibri_imx6: print also 64-bit IT

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

Print also for Colibri iMX6 512MB IT with 64-bit RAM bus.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/colibri_imx6.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 83ecd20b3d..439d38bc29 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -1019,6 +1019,7 @@ static void spl_dram_init(void)
 	case TEMP_AUTOMOTIVE:
 	default:
 		if (is_cpu_type(MXC_CPU_MX6DL)) {
+			puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
 			ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
 		} else {
 			puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
-- 
2.20.1

[U-Boot] [PATCH v1 15/26] colibri_imx6: add distroboot support

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Add support for distro boot. This is especially helpful for external
devices. There is a global boot command which scans a predefined
list of boot targets:
  run distro_bootcmd

As well as direct boot commands such as:
  run bootcmd_mmc1
  run bootcmd_usb
  run bootcmd_dhcp
  ...

Refer to doc/README.distro fo details.

While at it, remove the CONFIG_DRIVE_TYPES define which has not
been used and was meant to be used for multi device boot support
which is now provided by distroboot.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 include/configs/colibri_imx6.h | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index c782b2924c..77f884f341 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -100,14 +100,18 @@
 
 #define CONFIG_LOADADDR			0x12000000
 
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_DRIVE_MMC "mmc "
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
 #else
-#define CONFIG_DRIVE_MMC
+#define BOOTENV
 #endif
 
-#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC
-
 #define DFU_ALT_EMMC_INFO \
 	"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
 	"boot part 0 1;" \
@@ -134,7 +138,9 @@
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"kernel_addr_r=0x11000000\0" \
-	"ramdisk_addr_r=0x12100000\0"
+	"pxefile_addr_r=0x17100000\0" \
+	"ramdisk_addr_r=0x12100000\0" \
+	"scriptaddr=0x17000000\0"
 
 #define NFS_BOOTCMD \
 	"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
@@ -171,9 +177,10 @@
 
 #define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
 	"bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
-		"run nfsboot ; echo ; echo nfsboot failed ; " \
-		"usb start ;" \
+		"run distro_bootcmd ; " \
+		"usb start ; " \
 		"setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
 	"boot_file=uImage\0" \
 	"console=ttymxc0\0" \
-- 
2.20.1

[U-Boot] [PATCH v1 16/26] colibri_imx6: unify sd/mmc drive strenght with linux kernel settings

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

In the linux device tree we use 40Ohm drive strenght. So use the same
value in U-Boot.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/colibri_imx6.c | 24 +++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 439d38bc29..3d72a315b4 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -42,6 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |		\
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
@@ -92,16 +96,16 @@ iomux_v3_cfg_t const usdhc1_pads[] = {
 
 /* eMMC */
 iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 	MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 #endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
-- 
2.20.1

[U-Boot] [PATCH v1 17/26] colibri imx6: pf0100: reorder and cleanup message printing

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

Keep debug code at the end of the function.
Use a one line informational message for the PMIC only.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/pf0100.c | 82 ++++++++++++++---------------
 1 file changed, 41 insertions(+), 41 deletions(-)

diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c
index 5e411f1743..09c3cc950a 100644
--- a/board/toradex/colibri_imx6/pf0100.c
+++ b/board/toradex/colibri_imx6/pf0100.c
@@ -35,7 +35,7 @@ unsigned pmic_init(void)
 	uchar bus = 1;
 	uchar devid, revid, val;
 
-	puts("PMIC: ");
+	puts("PMIC:  ");
 	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
 	if (rc) {
 		printf("failed to get device for PMIC at address 0x%x\n",
@@ -51,7 +51,46 @@ unsigned pmic_init(void)
 		puts("i2c pmic revid read failed\n");
 		return 0;
 	}
-	printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
+	printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid);
+
+	/* get device programmed state */
+	val = PFUZE100_PAGE_REGISTER_PAGE1;
+	if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+		puts("i2c write failed\n");
+		return 0;
+	}
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	switch (programmed) {
+	case 0:
+		puts("not programmed\n");
+		break;
+	case 3:
+		puts("programmed\n");
+		break;
+	default:
+		puts("undefined programming state\n");
+		break;
+	}
 
 #ifdef DEBUG
 	{
@@ -103,45 +142,6 @@ unsigned pmic_init(void)
 	}
 #endif /* DEBUG */
 
-	/* get device programmed state */
-	val = PFUZE100_PAGE_REGISTER_PAGE1;
-	if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
-		puts("i2c write failed\n");
-		return 0;
-	}
-	if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) {
-		puts("i2c fuse_por read failed\n");
-		return 0;
-	}
-	if (val & PFUZE100_FUSE_POR_M)
-		programmed++;
-
-	if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) {
-		puts("i2c fuse_por read failed\n");
-		return programmed;
-	}
-	if (val & PFUZE100_FUSE_POR_M)
-		programmed++;
-
-	if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) {
-		puts("i2c fuse_por read failed\n");
-		return programmed;
-	}
-	if (val & PFUZE100_FUSE_POR_M)
-		programmed++;
-
-	switch (programmed) {
-	case 0:
-		printf("PMIC: not programmed\n");
-		break;
-	case 3:
-		printf("PMIC: programmed\n");
-		break;
-	default:
-		printf("PMIC: undefined programming state\n");
-		break;
-	}
-
 	return programmed;
 }
 
-- 
2.20.1

[U-Boot] [PATCH v1 18/26] colibri imx6: disable ri and dcd irq in uarts

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

If the UART is used in DTE mode the RI and DCD bits in UCR3 become
irq enable bits. Both are set to enabled after reset and both likely
are pending.

Disable the bits also on UARTs not used in the boot loader to prevent
an interrupt storm when Linux enables the UART interrupts.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/colibri_imx6.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 3d72a315b4..76b776e17e 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -271,14 +271,21 @@ iomux_v3_cfg_t const usb_pads[] = {
  * UARTs are used in DTE mode, switch the mode on all UARTs before
  * any pinmuxing connects a (DCE) output to a transceiver output.
  */
+#define UCR3		0x88	/* FIFO Control Register */
+#define UCR3_RI		BIT(8)	/* RIDELT DTE mode */
+#define UCR3_DCD	BIT(9)	/* DCDDELT DTE mode */
 #define UFCR		0x90	/* FIFO Control Register */
-#define UFCR_DCEDTE	(1<<6)	/* DCE=0 */
+#define UFCR_DCEDTE	BIT(6)	/* DCE=0 */
 
 static void setup_dtemode_uart(void)
 {
 	setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 	setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 	setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
+
+	clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
 }
 
 static void setup_iomux_uart(void)
-- 
2.20.1

[U-Boot] [PATCH v1 19/26] colibri_imx6: change pmic fusing according to hw 1.1 requirements

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

Colibri iMX6 V1.1 HW can use the PMIC GEN3 to power the NVCC_SD1.
Change the settings fused into the PMIC's OTP to powerup with
GEN3 set to output 3.3V.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/pf0100_otp.inc | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/board/toradex/colibri_imx6/pf0100_otp.inc b/board/toradex/colibri_imx6/pf0100_otp.inc
index ce29b95ae2..c3b1f67f81 100644
--- a/board/toradex/colibri_imx6/pf0100_otp.inc
+++ b/board/toradex/colibri_imx6/pf0100_otp.inc
@@ -5,16 +5,17 @@
 
 // Register Output for PF0100 programmer
 // Customer: Toradex AG
-// Program: Colibri iMX6
+// Program: Colibri iMX6 V1.1
 // Sample marking:
-// Date: 24.07.2015
-// Time: 10:52:58
+// Date: 01.05.2017
+// Time: 16:22:32
 // Generated from Spreadsheet Revision: P1.8
 
-/* sed commands to get from programmer script to struct */
+/* sed commands to get from programmer script to struct content */
 /* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc
    sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
-   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
+   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc
+*/
 
 enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
 struct pmic_otp_prog_t{
@@ -47,7 +48,8 @@ struct pmic_otp_prog_t pmic_otp_prog[] = {
 {pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
 {pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
 {pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
-{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
+{pmic_i2c, 0xD0, 0x0F}, // Auto gen from Row142
+{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
 {pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
 {pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
 {pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
@@ -185,4 +187,4 @@ struct pmic_otp_prog_t pmic_otp_prog[] = {
 {pmic_delay, 0, 500},
 {pmic_pwr, 0, 1},
 #endif
-};
\ No newline at end of file
+};
-- 
2.20.1

[U-Boot] [PATCH v1 20/26] colibri_imx6: revert fuse value set in mfgr_fuse

[Marcel Ziswiler]

From: Max Krummenacher <max.krummenacher@toradex.com>

We have two commands to change the bootmode fuses:
mfgr_fuse which set fuse 0/5 and 0/6
and
updt_fuse which burns bit 4 of 0/5.

Before Image 2.6 we fused in mfgr_fuse 0x5062, which boots
from the user partition of the eMMC.
To workaround certain hangs we moved to fastboot mode and
using the first bootpartition of the eMMC requiring a fuse
value of 0x5072 which could be achived by the then added
updt_fuse command. At the same time the mfgr_fuse command
was changed to also fuse 0x5072, revert that second change
so that one can fuse both values, one with just mfgr_fuse
and the later with mfgr_fuse;updt_fuse.

Note that the mfgr_fuse command is only needed at module
production time, a customer might need to use updt_fuse
when upgrading an older module to be compatible with a
newer image. The command is integrated into the image
update scripts.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/do_fuse.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c
index e6793e366a..22d191f52a 100644
--- a/board/toradex/colibri_imx6/do_fuse.c
+++ b/board/toradex/colibri_imx6/do_fuse.c
@@ -29,7 +29,7 @@ static int mfgr_fuse(void)
 		return CMD_RET_FAILURE;
 	}
 	/* boot cfg */
-	fuse_prog(0, 5, 0x00005072);
+	fuse_prog(0, 5, 0x00005062);
 	/* BT_FUSE_SEL */
 	fuse_prog(0, 6, 0x00000010);
 	return CMD_RET_SUCCESS;
-- 
2.20.1

[U-Boot] [PATCH v1 21/26] toradex: colibri_imx6: overwrite CMA memory set in device tree

[Marcel Ziswiler]

From: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>

Make sure CMA memory is not greater than 50% of available physical
memory.

Allow user to change the CMA memory via 'cma-size' U-Boot environment
variable.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/colibri_imx6.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 76b776e17e..fd988bd2b0 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -22,6 +22,7 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/video.h>
+#include <cpu.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <environment.h>
 #include <fsl_esdhc.h>
@@ -679,7 +680,18 @@ int checkboard(void)
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, bd_t *bd)
 {
-	return ft_common_board_setup(blob, bd);
+	u32 cma_size;
+
+	ft_common_board_setup(blob, bd);
+
+	cma_size = getenv_ulong("cma-size", 10, 320 * 1024 * 1024);
+	cma_size = min((u32)(gd->ram_size >> 1), cma_size);
+
+	fdt_setprop_u32(blob,
+			fdt_path_offset(blob, "/reserved-memory/linux,cma"),
+			"size",
+			cma_size);
+	return 0;
 }
 #endif
 
-- 
2.20.1

[U-Boot] [PATCH v1 22/26] configs: colibri_imx6: Use ext4 file system by default

[Marcel Ziswiler]

From: Sanchayan Maity <maitysanchayan@gmail.com>

Use ext4 file system by default.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 include/configs/colibri_imx6.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 77f884f341..6e056aab31 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -121,7 +121,7 @@
 	"imx6q-colibri-cam-eval-v3.dtb fat 0 1"
 
 #define EMMC_BOOTCMD \
-	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
+	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"emmcboot=run setup; " \
 		"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
@@ -153,7 +153,7 @@
 		"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
 #define SD_BOOTCMD						\
-	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
+	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"sdboot=run setup; " \
 		"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
@@ -165,7 +165,7 @@
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
 #define USB_BOOTCMD \
-	"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
+	"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
 		"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
-- 
2.20.1

[U-Boot] [PATCH v1 23/26] colibri_imx6: use SDP if USB serial downloader has been used

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

In case USB serial downloader has been used to load U-Boot start the
serial download protocol (SDP) emulation. This allows to download
complete images such as Toradex Easy Installer over USB SDP as well.
This code uses the boot ROM provided boot information to reliably
detect USB serial downloader.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/colibri_imx6.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index fd988bd2b0..4d9032419a 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -654,6 +654,14 @@ int board_late_init(void)
 	env_set("board_rev", env_str);
 #endif
 
+#ifdef CONFIG_CMD_USB_SDP
+	if (is_boot_from_usb()) {
+		printf("Serial Downloader recovery mode, using sdp command\n");
+		env_set("bootdelay", "0");
+		env_set("bootcmd", "sdp 0");
+	}
+#endif /* CONFIG_CMD_USB_SDP */
+
 	return 0;
 }
 #endif /* CONFIG_BOARD_LATE_INIT */
@@ -684,7 +692,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	ft_common_board_setup(blob, bd);
 
-	cma_size = getenv_ulong("cma-size", 10, 320 * 1024 * 1024);
+	cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
 	cma_size = min((u32)(gd->ram_size >> 1), cma_size);
 
 	fdt_setprop_u32(blob,
-- 
2.20.1

[U-Boot] [PATCH v1 24/26] colibri_imx6: switch to zimage

[Marcel Ziswiler]

From: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>

Switch to the generic compressed Kernel image type (zImage) instead of
the U-Boot specific uImage format.

While at it also fix device tree naming for MMC DFU.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 include/configs/colibri_imx6.h | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 6e056aab31..a6a823ee1f 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -108,17 +108,17 @@
 #include <config_distro_bootcmd.h>
 #undef BOOTENV_RUN_NET_USB_START
 #define BOOTENV_RUN_NET_USB_START ""
-#else
+#else /* CONFIG_SPL_BUILD */
 #define BOOTENV
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 #define DFU_ALT_EMMC_INFO \
 	"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
 	"boot part 0 1;" \
 	"rootfs part 0 2;" \
-	"uImage fat 0 1;" \
-	"imx6q-colibri-eval-v3.dtb fat 0 1;" \
-	"imx6q-colibri-cam-eval-v3.dtb fat 0 1"
+	"zImage fat 0 1;" \
+	"imx6dl-colibri-eval-v3.dtb fat 0 1;" \
+	"imx6dl-colibri-cam-eval-v3.dtb fat 0 1"
 
 #define EMMC_BOOTCMD \
 	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \
@@ -128,7 +128,7 @@
 		"${vidargs}; echo Booting from internal eMMC chip...; "	\
 		"run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
@@ -148,11 +148,11 @@
 		"setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
 		"${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
 		"run nfsdtbload; dhcp ${kernel_addr_r} " \
-		"&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
 		"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
-#define SD_BOOTCMD						\
+#define SD_BOOTCMD \
 	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"sdboot=run setup; " \
@@ -160,7 +160,7 @@
 		"${vidargs}; echo Booting from SD card; " \
 		"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
@@ -171,7 +171,7 @@
 		"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
 		"usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
@@ -182,7 +182,7 @@
 		"run distro_bootcmd ; " \
 		"usb start ; " \
 		"setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
-	"boot_file=uImage\0" \
+	"boot_file=zImage\0" \
 	"console=ttymxc0\0" \
 	"defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \
 	"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
-- 
2.20.1

[U-Boot] [PATCH v1 25/26] colibri_imx6: added nreset gpio on reboot

[Marcel Ziswiler]

From: Gerard Salvatella <gerard.salvatella@toradex.com>

RGMII_RD1 pin (active high, GPIO6_IO27) is triggered on reboot during
the SPL phase. This asserts (active low) nReset_Out from the PMIC.
Only V1.1 and later Colibri iMX6 modules implement this in hw. Previous
versions do not use this pin, so it is safe to leave it enabled at all
times.

Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/colibri_imx6.c | 24 +++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 4d9032419a..98ad87af19 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -30,6 +30,7 @@
 #include <micrel.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <cpu.h>
 
 #include "../common/tdx-cfg-block.h"
 #ifdef CONFIG_TDX_CMD_IMX_MFGR
@@ -1061,6 +1062,26 @@ static void spl_dram_init(void)
 	udelay(100);
 }
 
+static iomux_v3_cfg_t const gpio_reset_pad[] = {
+	MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+					MUX_MODE_SION
+#define GPIO_NRESET IMX_GPIO_NR(6, 27)
+};
+
+#define IMX_RESET_CAUSE_POR 0x00011
+static void nreset_out(void)
+{
+	int reset_cause = get_imx_reset_cause();
+
+	if (reset_cause != IMX_RESET_CAUSE_POR) {
+		imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
+						 ARRAY_SIZE(gpio_reset_pad));
+		gpio_direction_output(GPIO_NRESET, 1);
+		udelay(100);
+		gpio_direction_output(GPIO_NRESET, 0);
+	}
+}
+
 void board_init_f(ulong dummy)
 {
 	/* setup AIPS and disable watchdog */
@@ -1087,6 +1108,9 @@ void board_init_f(ulong dummy)
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
+	/* Assert nReset_Out */
+	nreset_out();
+
 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }
-- 
2.20.1

[U-Boot] [PATCH v1 26/26] board: colibri_imx6: check for and report ecc errors in fuses

[Marcel Ziswiler]

From: Gerard Salvatella <gerard.salvatella@toradex.com>

The PMIC on the Colibri iMX6 may have ECC errors in fuses that will
prevent correct settings. Up to one bit error per fuse bank can be
reported and corrected by the ECC logic. Two bit errors can only be
reported.

Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_imx6/pf0100.c | 51 +++++++++++++++++++++++++
 board/toradex/colibri_imx6/pf0100.h | 59 ++++++++++++++++++++++++++++-
 2 files changed, 108 insertions(+), 2 deletions(-)

diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c
index 09c3cc950a..e744243297 100644
--- a/board/toradex/colibri_imx6/pf0100.c
+++ b/board/toradex/colibri_imx6/pf0100.c
@@ -21,6 +21,8 @@
 /* define for PMIC register dump */
 /*#define DEBUG */
 
+#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n"
+
 /* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */
 static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
 	MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -42,6 +44,55 @@ unsigned pmic_init(void)
 		       PFUZE100_I2C_ADDR);
 		return 0;
 	}
+
+	/* check for errors in PMIC fuses */
+	if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) {
+		puts("i2c pmic INTSTAT3 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BIT_OTP_ECCI) {
+		puts("\n" WARNBAR);
+		puts("WARNING: ecc errors found in pmic fuse banks\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE1 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE1) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 1 to 5\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE2 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE2) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 6 to 10\n"
+		    );
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE1) {
+		puts(WARNBAR);
+		puts("ERROR: banks 1 to 5 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE2) {
+		puts(WARNBAR);
+		puts("ERROR: banks 6 to 10 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+
 	/* get device ident */
 	if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) {
 		puts("i2c pmic devid read failed\n");
diff --git a/board/toradex/colibri_imx6/pf0100.h b/board/toradex/colibri_imx6/pf0100.h
index c0efb79bbc..9257620511 100644
--- a/board/toradex/colibri_imx6/pf0100.h
+++ b/board/toradex/colibri_imx6/pf0100.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  */
 
 /*
@@ -10,11 +10,23 @@
 #ifndef PF0100_H_
 #define PF0100_H_
 
+/* bit definitions */
+#define PFUZE100_BIT_0			(0x01 << 0)
+#define PFUZE100_BIT_1			(0x01 << 1)
+#define PFUZE100_BIT_2			(0x01 << 2)
+#define PFUZE100_BIT_3			(0x01 << 3)
+#define PFUZE100_BIT_4			(0x01 << 4)
+#define PFUZE100_BIT_5			(0x01 << 5)
+#define PFUZE100_BIT_6			(0x01 << 6)
+#define PFUZE100_BIT_7			(0x01 << 7)
+
 /* 7-bit I2C bus slave address */
 #define PFUZE100_I2C_ADDR		(0x08)
 /* Register Addresses */
 #define PFUZE100_DEVICEID		(0x0)
 #define PFUZE100_REVID			(0x3)
+#define PFUZE100_INTSTAT3		(0xe)
+#define PFUZE100_BIT_OTP_ECCI		PFUZE100_BIT_7
 #define PFUZE100_SW1AMODE		(0x23)
 #define PFUZE100_SW1ACON		36
 #define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
@@ -39,12 +51,55 @@
 #define PFUZE100_PAGE_REGISTER_PAGE2	(0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
 
 /* extended page 1 */
+#define PFUZE100_OTP_ECC_SE1		0x8a
+#define PFUZE100_BIT_ECC1_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE1		((PFUZE100_BIT_ECC1_SE) | \
+					(PFUZE100_BIT_ECC2_SE) | \
+					(PFUZE100_BIT_ECC3_SE) | \
+					(PFUZE100_BIT_ECC4_SE) | \
+					(PFUZE100_BIT_ECC5_SE))
+#define PFUZE100_OTP_ECC_SE2		0x8b
+#define PFUZE100_BIT_ECC6_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE2		((PFUZE100_BIT_ECC6_SE) | \
+					(PFUZE100_BIT_ECC7_SE) | \
+					(PFUZE100_BIT_ECC8_SE) | \
+					(PFUZE100_BIT_ECC9_SE) | \
+					(PFUZE100_BIT_ECC10_SE))
+#define PFUZE100_OTP_ECC_DE1		0x8c
+#define PFUZE100_BIT_ECC1_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE1		((PFUZE100_BIT_ECC1_DE) | \
+					(PFUZE100_BIT_ECC2_DE) | \
+					(PFUZE100_BIT_ECC3_DE) | \
+					(PFUZE100_BIT_ECC4_DE) | \
+					(PFUZE100_BIT_ECC5_DE))
+#define PFUZE100_OTP_ECC_DE2		0x8d
+#define PFUZE100_BIT_ECC6_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE2		((PFUZE100_BIT_ECC6_DE) | \
+					(PFUZE100_BIT_ECC7_DE) | \
+					(PFUZE100_BIT_ECC8_DE) | \
+					(PFUZE100_BIT_ECC9_DE) | \
+					(PFUZE100_BIT_ECC10_DE))
 #define PFUZE100_FUSE_POR1		0xe4
 #define PFUZE100_FUSE_POR2		0xe5
 #define PFUZE100_FUSE_POR3		0xe6
 #define PFUZE100_FUSE_POR_M		(0x1 << 1)
 
-
 /* output some informational messages, return the number FUSE_POR=1 */
 /* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
 unsigned pmic_init(void);
-- 
2.20.1

[U-Boot] [PATCH v1 24/26] colibri_imx6: switch to zimage

[Lukasz Majewski]

Hi Marcel,

> From: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> 
> Switch to the generic compressed Kernel image type (zImage) instead of
> the U-Boot specific uImage format.
> 

I would recommend switching to use fitImage instead of zImage.

You can look on display5 board for a reference.

> While at it also fix device tree naming for MMC DFU.
> 
> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> ---
> 
>  include/configs/colibri_imx6.h | 22 +++++++++++-----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/include/configs/colibri_imx6.h
> b/include/configs/colibri_imx6.h index 6e056aab31..a6a823ee1f 100644
> --- a/include/configs/colibri_imx6.h
> +++ b/include/configs/colibri_imx6.h
> @@ -108,17 +108,17 @@
>  #include <config_distro_bootcmd.h>
>  #undef BOOTENV_RUN_NET_USB_START
>  #define BOOTENV_RUN_NET_USB_START ""
> -#else
> +#else /* CONFIG_SPL_BUILD */
>  #define BOOTENV
> -#endif
> +#endif /* CONFIG_SPL_BUILD */
>  
>  #define DFU_ALT_EMMC_INFO \
>  	"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
>  	"boot part 0 1;" \
>  	"rootfs part 0 2;" \
> -	"uImage fat 0 1;" \
> -	"imx6q-colibri-eval-v3.dtb fat 0 1;" \
> -	"imx6q-colibri-cam-eval-v3.dtb fat 0 1"
> +	"zImage fat 0 1;" \
> +	"imx6dl-colibri-eval-v3.dtb fat 0 1;" \
> +	"imx6dl-colibri-cam-eval-v3.dtb fat 0 1"
>  
>  #define EMMC_BOOTCMD \
>  	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime
> rootfstype=ext4 " \ @@ -128,7 +128,7 @@
>  		"${vidargs}; echo Booting from internal eMMC
> chip...; "	\ "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} "
> \ "${boot_file} && run fdt_fixup && " \
> -		"bootm ${kernel_addr_r} ${dtbparam}\0" \
> +		"bootz ${kernel_addr_r} ${dtbparam}\0" \
>  	"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
>  		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\"
> && true\0" 
> @@ -148,11 +148,11 @@
>  		"setenv bootargs ${defargs} ${nfsargs} ${setupargs}
> " \ "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
>  		"run nfsdtbload; dhcp ${kernel_addr_r} " \
> -		"&& run fdt_fixup && bootm ${kernel_addr_r}
> ${dtbparam}\0" \
> +		"&& run fdt_fixup && bootz ${kernel_addr_r}
> ${dtbparam}\0" \ "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r}
> ${fdt_file} " \ "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
>  
> -#define SD_BOOTCMD						\
> +#define SD_BOOTCMD \
>  	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime
> rootfstype=ext4 " \ "rootwait\0" \
>  	"sdboot=run setup; " \
> @@ -160,7 +160,7 @@
>  		"${vidargs}; echo Booting from SD card; " \
>  		"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
>  		"${boot_file} && run fdt_fixup && " \
> -		"bootm ${kernel_addr_r} ${dtbparam}\0" \
> +		"bootz ${kernel_addr_r} ${dtbparam}\0" \
>  	"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
>  		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\"
> && true\0" 
> @@ -171,7 +171,7 @@
>  		"${usbargs} ${vidargs}; echo Booting from USB
> stick...; " \ "usb start && run usbdtbload; load usb 0:1
> ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \
> -		"bootm ${kernel_addr_r} ${dtbparam}\0" \
> +		"bootz ${kernel_addr_r} ${dtbparam}\0" \
>  	"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
>  		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\"
> && true\0" 
> @@ -182,7 +182,7 @@
>  		"run distro_bootcmd ; " \
>  		"usb start ; " \
>  		"setenv stdout serial,vga ; setenv stdin
> serial,usbkbd\0" \
> -	"boot_file=uImage\0" \
> +	"boot_file=zImage\0" \
>  	"console=ttymxc0\0" \
>  	"defargs=enable_wait_mode=off
> galcore.contiguousSize=50331648\0" \ "dfu_alt_info="
> DFU_ALT_EMMC_INFO "\0" \




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190208/41e58ba6/attachment.sig>

[U-Boot] [PATCH v1 24/26] colibri_imx6: switch to zimage

[Marcel Ziswiler]

Hi Lukasz

On Fri, 2019-02-08 at 22:42 +0100, Lukasz Majewski wrote:
> Hi Marcel,
> 
> > From: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> > 
> > Switch to the generic compressed Kernel image type (zImage) instead
> > of
> > the U-Boot specific uImage format.
> > 
> 
> I would recommend switching to use fitImage instead of zImage.

Thanks, we are, of course, aware of fitImage and we do use it e.g. for
the Toradex Easy Installer. However, while our former BSPs still booted
from uImage our current BSPs now boot from zImage. In the future, we
plan to fully integrate distroboot which basically makes this choice
here obsolete anyway.

> You can look on display5 board for a reference.
> 
> > While at it also fix device tree naming for MMC DFU.
> > 
> > Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> > Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > 
> > ---
> > 
> >  include/configs/colibri_imx6.h | 22 +++++++++++-----------
> >  1 file changed, 11 insertions(+), 11 deletions(-)
> > 
> > diff --git a/include/configs/colibri_imx6.h
> > b/include/configs/colibri_imx6.h index 6e056aab31..a6a823ee1f
> > 100644
> > --- a/include/configs/colibri_imx6.h
> > +++ b/include/configs/colibri_imx6.h
> > @@ -108,17 +108,17 @@
> >  #include <config_distro_bootcmd.h>
> >  #undef BOOTENV_RUN_NET_USB_START
> >  #define BOOTENV_RUN_NET_USB_START ""
> > -#else
> > +#else /* CONFIG_SPL_BUILD */
> >  #define BOOTENV
> > -#endif
> > +#endif /* CONFIG_SPL_BUILD */
> >  
> >  #define DFU_ALT_EMMC_INFO \
> >  	"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
> >  	"boot part 0 1;" \
> >  	"rootfs part 0 2;" \
> > -	"uImage fat 0 1;" \
> > -	"imx6q-colibri-eval-v3.dtb fat 0 1;" \
> > -	"imx6q-colibri-cam-eval-v3.dtb fat 0 1"
> > +	"zImage fat 0 1;" \
> > +	"imx6dl-colibri-eval-v3.dtb fat 0 1;" \
> > +	"imx6dl-colibri-cam-eval-v3.dtb fat 0 1"
> >  
> >  #define EMMC_BOOTCMD \
> >  	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime
> > rootfstype=ext4 " \ @@ -128,7 +128,7 @@
> >  		"${vidargs}; echo Booting from internal eMMC
> > chip...; "	\ "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} "
> > \ "${boot_file} && run fdt_fixup && " \
> > -		"bootm ${kernel_addr_r} ${dtbparam}\0" \
> > +		"bootz ${kernel_addr_r} ${dtbparam}\0" \
> >  	"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
> >  		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\"
> > && true\0" 
> > @@ -148,11 +148,11 @@
> >  		"setenv bootargs ${defargs} ${nfsargs} ${setupargs}
> > " \ "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
> >  		"run nfsdtbload; dhcp ${kernel_addr_r} " \
> > -		"&& run fdt_fixup && bootm ${kernel_addr_r}
> > ${dtbparam}\0" \
> > +		"&& run fdt_fixup && bootz ${kernel_addr_r}
> > ${dtbparam}\0" \ "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r}
> > ${fdt_file} " \ "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
> >  
> > -#define SD_BOOTCMD						\
> > +#define SD_BOOTCMD \
> >  	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime
> > rootfstype=ext4 " \ "rootwait\0" \
> >  	"sdboot=run setup; " \
> > @@ -160,7 +160,7 @@
> >  		"${vidargs}; echo Booting from SD card; " \
> >  		"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
> >  		"${boot_file} && run fdt_fixup && " \
> > -		"bootm ${kernel_addr_r} ${dtbparam}\0" \
> > +		"bootz ${kernel_addr_r} ${dtbparam}\0" \
> >  	"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
> >  		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\"
> > && true\0" 
> > @@ -171,7 +171,7 @@
> >  		"${usbargs} ${vidargs}; echo Booting from USB
> > stick...; " \ "usb start && run usbdtbload; load usb 0:1
> > ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \
> > -		"bootm ${kernel_addr_r} ${dtbparam}\0" \
> > +		"bootz ${kernel_addr_r} ${dtbparam}\0" \
> >  	"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
> >  		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\"
> > && true\0" 
> > @@ -182,7 +182,7 @@
> >  		"run distro_bootcmd ; " \
> >  		"usb start ; " \
> >  		"setenv stdout serial,vga ; setenv stdin
> > serial,usbkbd\0" \
> > -	"boot_file=uImage\0" \
> > +	"boot_file=zImage\0" \
> >  	"console=ttymxc0\0" \
> >  	"defargs=enable_wait_mode=off
> > galcore.contiguousSize=50331648\0" \ "dfu_alt_info="
> > DFU_ALT_EMMC_INFO "\0" \
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: 
> lukma at denx.de
 
Best regards - Mit freundlichen Grüssen - Meilleures salutations

Marcel Ziswiler
Platform Manager Embedded Linux

Toradex AG
Altsagenstrasse 5 | 6048 Horw/Luzern | Switzerland | T: +41 41 500 48 00
(main line) | Direct: +41 41 500 48 10

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Abel Vesa]

On 19-02-04 08:19:23, Tom Rini wrote:
> On Mon, Feb 04, 2019 at 09:03:43AM -0200, Fabio Estevam wrote:
> > On Mon, Feb 4, 2019 at 7:55 AM Abel Vesa <abel.vesa@nxp.com> wrote:
> > 
> > > If the SPL size (without the dtb appended) is larger then yes, the build fails.
> > > Trouble is if the SPL (without the dtb appended) is, lets say, 63kB and
> > > then the dtb is larger than 1kB. Then there is no mechanism in place to check that
> > > and it will just fail to boot without giving any clues why. But this is a totally
> > > unrelated problem from this patchset's point of view and I think it impacts all
> > > the platforms that support SPL with DM.
> > 
> > Yes, it is unrelated to this series and should be treated separately.
> 
> I also agree.  But, don't we have a mechanism for that?  It sounds like
> some additional targets need to call $(BOARD_SIZE_CHECK) at the end.  Or
> am I missing something?
> 

So, do I need to resend this with all the R-bs ?
> -- 
> Tom

[U-Boot] [PATCH v4 00/20] mx6sabre: Add DM and SPL FIT support

[Fabio Estevam]

On Sat, Feb 9, 2019 at 8:48 PM Abel Vesa <abel.vesa@nxp.com> wrote:

> So, do I need to resend this with all the R-bs ?

Just realized that you missed to Cc Stefano Babic <sbabic@denx.de> on
this series.

Stefano,

Should Abel resend this series with you on Cc or can you get review it
from patchwork?

Thanks

[U-Boot] [PATCH v4 00/22] imx: vybrid: Update BK4 and PCM052 boards to only use DM/DTS

[Lukasz Majewski]

This patch series converts PCM052 and BK4 to use Driver Model and Device
Tree.

Some notable changes:
- The way how MAC address is read from fuses can now be adjusted
- DTS improvement/sync with kernel (also extract u-boot specific properties)
- Using generic code instead of one from board

The output of u-boot boot:
U-Boot 2019.01-rc3-00076-gc149229be0 (Jan 14 2019 - 08:38:48 +0100)

CPU: Freescale Vybrid VF610 at 396 MHz
Reset cause: POWER ON RESET
Model: Liebherr (LVF) BK4 Vybrid Board
Board: BK4r1 (L333)
DRAM:  512 MiB
NAND:  1024 MiB
MMC:   FSL_SDHC: 0
Loading Environment from NAND... OK
In:    serial at 40028000
Out:   serial at 40028000
Err:   serial at 40028000
Net:   eth0: fec at 400d0000, eth1: fec at 400d1000
Enter passphrase to stop autoboot, booting in 3 seconds

Buildman CI:
./tools/buildman/buildman.py --branch=HEAD  vf610 mx6 vybrid --detail --verbose --show_errors --force-build --count=22 --output-dir=../BUILD/

Travis-CI:
https://travis-ci.org/lmajewski/u-boot-dfu/builds/492731495

U-boot master branch: SHA1: b1b1bab7f92b838a252ab977f56d9c3584c14fb7


Changes in v4:
- Fix maming of DDRBYTE0 -> DDRBYTE2 (as it is in the documentation)
    - Update DDRBYTE0 -> DDRBYTE2 as in VF610 user manual

Changes in v3:
- Add code to enable I2C0 code as suggested by Stefan (so the code can be
  reused by other boards without regressions)
- Exclude the pcm052.c related code to a separate patch
- New patch (separate board code patch)

Changes in v2:
    - Rename pcm052.dts to vf610-pcm052.dts
    - Rename bk4r1.dts to vf610-bk4r1.dts
    - Extract 'u-boot,dm-pre-reloc;' property to separate file (to facilitate
      sync with Linux kernel dts files)
        - New patch
        - Disable EFI related support and commands (as we do not plan to
          use EFI on this setup)

Lukasz Majewski (22):
  net: FEC: Add compatible for vybrid (vf610) to reuse fec_mxc.c driver
  net: Kconfig: FEC: Add dependency on VF610
  vybrid: ddr: Extend vf610-pinfunc.h with DDR pads definitions
  vybrid: clock: Provide enable_i2c_clk() function for Vybrid
  pcm052: board: Do not enable I2C2 code in the board file
  vybrid: Define the imx_get_mac_from_fuse() as a __weak function
  pcm052: board: Remove "m4go" command as it is superseded by "bootaux"
  pcm052: board: vybrid: Update the board name for BK4 device
  ARM: DTS: vybrid: Update vf.dtsi file to descibe more vf610 hardware
  pcm052: board: cosmetic: Add copyright notice to pcm052.c
  ARM: DTS: Update pcm052 based dts files (bk4r1/pcm052)
  ARM: DTS: Provide vf610-bk4r1-u-boot.dtsi for U-Boot specific
    properties
  defconfig: bk4/pcm052: Update bk4r1|pcm052_defconfig to support DM/DT
  config: pcm052: Use SZ_X{MK} from linux/sizes.h for
    include/configs/pcm052.h
  config: bk4: Update include/configs/bk4r1.h file
  pcm052: board: Remove in-board setup code (it is now replaced by DM
    setup)
  config: bk4: Update u-boot script to support recovery via SD card
  config: bk4: Update u-boot envs to support NOR memories initial setup
  pcm052: bk4: sdcard: Add support for SD card booting/recovery
  pcm052: board: Add code to setup LED default states
  pcm052: mac: Provide board specific imx_get_mac_from_fuse() function
  pcm052: bk4: Add board_phy_config() for BK4 to setup ksz8081 phy

 arch/arm/cpu/armv7/vf610/Kconfig              |   1 +
 arch/arm/cpu/armv7/vf610/generic.c            |  24 +-
 arch/arm/dts/Makefile                         |   4 +-
 arch/arm/dts/bk4r1.dts                        |  47 ----
 arch/arm/dts/vf.dtsi                          |  62 +++++
 arch/arm/dts/vf610-bk4r1-u-boot.dtsi          |  27 ++
 arch/arm/dts/vf610-bk4r1.dts                  |  97 +++++++
 arch/arm/dts/{pcm052.dts => vf610-pcm052.dts} |   6 +-
 arch/arm/dts/vf610-pcm052.dtsi                | 259 +++++++++++++++++
 arch/arm/dts/vf610-pinfunc.h                  |  50 ++++
 arch/arm/include/asm/arch-vf610/clock.h       |   3 +
 arch/arm/include/asm/arch-vf610/imx-regs.h    |   2 +
 board/phytec/pcm052/pcm052.c                  | 386 ++++++--------------------
 configs/bk4r1_defconfig                       |  49 +++-
 configs/pcm052_defconfig                      |  36 ++-
 drivers/net/Kconfig                           |   2 +-
 drivers/net/fec_mxc.c                         |   1 +
 include/configs/bk4r1.h                       | 263 +++++++++++++++++-
 include/configs/pcm052.h                      |  51 +---
 19 files changed, 959 insertions(+), 411 deletions(-)
 delete mode 100644 arch/arm/dts/bk4r1.dts
 create mode 100644 arch/arm/dts/vf610-bk4r1-u-boot.dtsi
 create mode 100644 arch/arm/dts/vf610-bk4r1.dts
 rename arch/arm/dts/{pcm052.dts => vf610-pcm052.dts} (81%)
 create mode 100644 arch/arm/dts/vf610-pcm052.dtsi

-- 
2.11.0

[U-Boot] [PATCH v4 01/22] net: FEC: Add compatible for vybrid (vf610) to reuse fec_mxc.c driver

[Lukasz Majewski]

The NXP's FEC driver can be reused on vf610 device (with DM).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/fec_mxc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 1a59026a62..5ff49224f4 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1486,6 +1486,7 @@ static const struct udevice_id fecmxc_ids[] = {
 	{ .compatible = "fsl,imx6ul-fec" },
 	{ .compatible = "fsl,imx53-fec" },
 	{ .compatible = "fsl,imx7d-fec" },
+	{ .compatible = "fsl,mvf600-fec" },
 	{ }
 };
 
-- 
2.11.0

[U-Boot] [PATCH v4 02/22] net: Kconfig: FEC: Add dependency on VF610

[Lukasz Majewski]

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 6a570285aa..a3e1b4f411 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -187,7 +187,7 @@ config FEC_MXC_MDIO_BASE
 
 config FEC_MXC
 	bool "FEC Ethernet controller"
-	depends on MX5 || MX6 || MX7 || IMX8
+	depends on MX5 || MX6 || MX7 || IMX8 || VF610
 	help
 	  This driver supports the 10/100 Fast Ethernet controller for
 	  NXP i.MX processors.
-- 
2.11.0

[U-Boot] [PATCH v4 03/22] vybrid: ddr: Extend vf610-pinfunc.h with DDR pads definitions

[Lukasz Majewski]

This patch provides definitions necessary for VF610 DDR pad configurations.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>

---

Changes in v4:
- Fix maming of DDRBYTE0 -> DDRBYTE2 (as it is in the documentation)

Changes in v3: None
Changes in v2: None

 arch/arm/dts/vf610-pinfunc.h | 50 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h
index fcad7132c8..9456719074 100644
--- a/arch/arm/dts/vf610-pinfunc.h
+++ b/arch/arm/dts/vf610-pinfunc.h
@@ -807,4 +807,54 @@
 #define VF610_PAD_PTA7__GPIO_134		0x218 0x000 ALT0 0x0
 #define VF610_PAD_PTA7__VIU_PIX_CLK		0x218 0x3AC ALT1 0x1
 
+#define VF610_PAD_DDR_RESETB			0x21c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A15__DDR_A_15		0x220 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A14__DDR_A_14		0x224 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A13__DDR_A_13		0x228 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A12__DDR_A_12		0x22c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A11__DDR_A_11		0x230 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A10__DDR_A_10		0x234 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A9__DDR_A_9		0x238 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A8__DDR_A_8		0x23c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A7__DDR_A_7		0x240 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A6__DDR_A_6		0x244 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A5__DDR_A_5		0x248 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A4__DDR_A_4		0x24c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A3__DDR_A_3		0x250 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A2__DDR_A_2		0x254 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A1__DDR_A_1		0x258 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A0__DDR_A_0		0x25c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA2__DDR_BA_2		0x260 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA1__DDR_BA_1		0x264 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA0__DDR_BA_0		0x268 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CAS__DDR_CAS_B		0x26c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CKE__DDR_CKE_0		0x270 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CLK__DDR_CLK_0		0x274 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CS__DDR_CS_B_0		0x278 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D15__DDR_D_15		0x27c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D14__DDR_D_14		0x280 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D13__DDR_D_13		0x284 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D12__DDR_D_12		0x288 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D11__DDR_D_11		0x28c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D10__DDR_D_10		0x290 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D9__DDR_D_9		0x294 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D8__DDR_D_8		0x298 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D7__DDR_D_7		0x29c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D6__DDR_D_6		0x2a0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D5__DDR_D_5		0x2a4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D4__DDR_D_4		0x2a8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D3__DDR_D_3		0x2ac 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D2__DDR_D_2		0x2b0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D1__DDR_D_1		0x2b4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D0__DDR_D_0		0x2b8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQM1__DDR_DQM_1		0x2bc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQM0__DDR_DQM_0		0x2c0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQS1__DDR_DQS_1		0x2c4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQS0__DDR_DQS_0		0x2c8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_RAS__DDR_RAS_B		0x2cc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_WE__DDR_WE_B		0x2d0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_ODT1__DDR_ODT_0		0x2d4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_ODT0__DDR_ODT_1		0x2d8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1	0x2dc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2	0x2e0 0x000 ALT0 0x0
 #endif
-- 
2.11.0

[U-Boot] [PATCH v4 04/22] vybrid: clock: Provide enable_i2c_clk() function for Vybrid

[Lukasz Majewski]

Provide function to enable I2C clocks for vf610 - in the generic code.
This function overrides the default weak function implementation (which
only returns 1).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v4: None
Changes in v3:
- Add code to enable I2C0 code as suggested by Stefan (so the code can be
  reused by other boards without regressions)
- Exclude the pcm052.c related code to a separate patch

Changes in v2: None

 arch/arm/cpu/armv7/vf610/generic.c      | 22 ++++++++++++++++++++++
 arch/arm/include/asm/arch-vf610/clock.h |  3 +++
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index cbd3391918..e0c0b1bcb0 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -375,3 +375,25 @@ void enable_caches(void)
 	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
 }
 #endif
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* i2c_num can be from 0 - 3 */
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+
+	switch (i2c_num) {
+	case 0:
+		clrsetbits_le32(&ccm->ccgr4, CCM_CCGR4_I2C0_CTRL_MASK,
+				CCM_CCGR4_I2C0_CTRL_MASK);
+	case 2:
+		clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK,
+				CCM_CCGR10_I2C2_CTRL_MASK);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h
index 3bd73a01f3..72184fd608 100644
--- a/arch/arm/include/asm/arch-vf610/clock.h
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -22,6 +22,9 @@ enum mxc_clock {
 void enable_ocotp_clk(unsigned char enable);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 u32 get_lpuart_clk(void);
+#ifdef CONFIG_SYS_I2C_MXC
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
+#endif
 
 #define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
 
-- 
2.11.0

[U-Boot] [PATCH v4 05/22] pcm052: board: Do not enable I2C2 code in the board file

[Lukasz Majewski]

As the I2C2 clock is now enabled in the generic clock code, we can remove
this code from a board file.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v4: None
Changes in v3:
- New patch (separate board code patch)

Changes in v2: None

 board/phytec/pcm052/pcm052.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index f988af2abc..cfc8009102 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -485,7 +485,7 @@ static void clock_init(void)
 	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
 			CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
-			CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK);
+			CCM_CCGR10_NFC_CTRL_MASK);
 
 	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
 			ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
-- 
2.11.0

[U-Boot] [PATCH v4 06/22] vybrid: Define the imx_get_mac_from_fuse() as a __weak function

[Lukasz Majewski]

The proposed way of reading fused MAC in the imx_get_mac_from_fuse() may
be different for other boards.

This commit defines the imx_get_mac_from_fuse() as a weak function to allow
board file overriding it with customized function.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv7/vf610/generic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index e0c0b1bcb0..90fa695e98 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -252,7 +252,7 @@ U_BOOT_CMD(
 );
 
 #ifdef CONFIG_FEC_MXC
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+__weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 	struct fuse_bank *bank = &ocotp->bank[4];
-- 
2.11.0

[U-Boot] [PATCH v4 07/22] pcm052: board: Remove "m4go" command as it is superseded by "bootaux"

[Lukasz Majewski]

The "m4go" provides exactly the same functionality as the IMX generic
"bootaux" command. Remove it to not duplicate the code.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/phytec/pcm052/pcm052.c | 38 --------------------------------------
 1 file changed, 38 deletions(-)

diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index cfc8009102..4e4b870304 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -577,41 +577,3 @@ int checkboard(void)
 
 	return 0;
 }
-
-static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc,
-		       char * const argv[])
-{
-	ulong addr;
-
-	/* Consume 'm4go' */
-	argc--; argv++;
-
-	/*
-	 * Parse provided address - default to load_addr in case not provided.
-	 */
-
-	if (argc)
-		addr = simple_strtoul(argv[0], NULL, 16);
-	else
-		addr = load_addr;
-
-	/*
-	 * Write boot address in PERSISTENT_ENTRY1[31:0] aka SRC_GPR2[31:0]
-	 */
-	writel(addr + 0x401, 0x4006E028);
-
-	/*
-	 * Start secondary processor by enabling its clock
-	 */
-	writel(0x15a5a, 0x4006B08C);
-
-	return 1;
-}
-
-U_BOOT_CMD(
-	m4go, 2 /* one arg max */, 1 /* repeatable */, do_m4go,
-	"start the secondary Cortex-M4 from scatter file image",
-	"[<addr>]\n"
-	"    - start secondary Cortex-M4 core using a scatter file image\n"
-	"The argument needs to be a scatter file\n"
-);
-- 
2.11.0

[U-Boot] [PATCH v4 08/22] pcm052: board: vybrid: Update the board name for BK4 device

[Lukasz Majewski]

This commit provides distinction between PCM052 and BK4.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/phytec/pcm052/pcm052.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index 4e4b870304..5f2c9a9c12 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -573,7 +573,10 @@ int board_init(void)
 
 int checkboard(void)
 {
+#ifdef CONFIG_TARGET_BK4R1
+	puts("Board: BK4r1 (L333)\n");
+#else
 	puts("Board: PCM-052\n");
-
+#endif
 	return 0;
 }
-- 
2.11.0

[U-Boot] [PATCH v4 09/22] ARM: DTS: vybrid: Update vf.dtsi file to descibe more vf610 hardware

[Lukasz Majewski]

This patch allows moving vf610 based boards to a device tree and model.
Ported from Linux kernel - v4.20 (tag)

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/dts/vf.dtsi | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi
index ad30059b9a..5e3b2c5b9d 100644
--- a/arch/arm/dts/vf.dtsi
+++ b/arch/arm/dts/vf.dtsi
@@ -22,6 +22,10 @@
 		spi1 = &dspi1;
 		ehci0 = &ehci0;
 		ehci1 = &ehci1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
 	};
 
 	soc {
@@ -89,6 +93,22 @@
 				status = "disabled";
 			};
 
+			i2c0: i2c at 40066000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-i2c";
+				reg = <0x40066000 0x1000>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at 40067000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-i2c";
+				reg = <0x40067000 0x1000>;
+				status = "disabled";
+			};
+
 			iomuxc: iomuxc at 40048000 {
 				compatible = "fsl,vf610-iomuxc";
 				reg = <0x40048000 0x1000>;
@@ -156,6 +176,48 @@
 				reg = <0x400b4000 0x800>;
 				status = "disabled";
 			};
+
+			esdhc1: esdhc at 400b2000 {
+				compatible = "fsl,esdhc";
+				reg = <0x400b2000 0x1000>;
+				status = "disabled";
+			};
+
+			fec0: fec at 400d0000 {
+			      compatible = "fsl,mvf600-fec";
+			      reg = <0x400d0000 0x1000>;
+			      status = "disabled";
+			};
+
+			fec1: fec at 400d1000 {
+			      compatible = "fsl,mvf600-fec";
+			      reg = <0x400d1000 0x1000>;
+			      status = "disabled";
+			};
+
+			nfc: nand at 400e0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-nfc";
+				reg = <0x400e0000 0x4000>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at 400e6000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-i2c";
+				reg = <0x400e6000 0x1000>;
+				status = "disabled";
+			};
+
+			i2c3: i2c at 400e7000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-i2c";
+				reg = <0x400e7000 0x1000>;
+				status = "disabled";
+			};
 		};
 	};
 };
-- 
2.11.0

[U-Boot] [PATCH v4 10/22] pcm052: board: cosmetic: Add copyright notice to pcm052.c

[Lukasz Majewski]

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/phytec/pcm052/pcm052.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index 5f2c9a9c12..95df0be6c1 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -1,5 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
+ * (C) Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de.
+ *
  * Copyright 2013 Freescale Semiconductor, Inc.
  */
 
-- 
2.11.0

[U-Boot] [PATCH v4 11/22] ARM: DTS: Update pcm052 based dts files (bk4r1/pcm052)

[Lukasz Majewski]

This commit provides update and renames the bk4r1.dts to vf610-bk4r1.dts
file with more on SoC HW description.
The pcm052.dts has been renamed to vf610-pcm052.dts as well.

Moreover, a new vf610-pcm052.drsi file has been introduced
to reuse the common code between devices based on Phytec's
pcm052 modules.
Ported from Linux kernel - v4.20 (tag)

Signed-off-by: Lukasz Majewski <lukma@denx.de>

---

Changes in v4:
    - Update DDRBYTE0 -> DDRBYTE2 as in VF610 user manual

Changes in v3: None
Changes in v2:
    - Rename pcm052.dts to vf610-pcm052.dts
    - Rename bk4r1.dts to vf610-bk4r1.dts
    - Extract 'u-boot,dm-pre-reloc;' property to separate file (to facilitate
      sync with Linux kernel dts files)

 arch/arm/dts/Makefile                         |   4 +-
 arch/arm/dts/bk4r1.dts                        |  47 -----
 arch/arm/dts/vf610-bk4r1.dts                  |  97 ++++++++++
 arch/arm/dts/{pcm052.dts => vf610-pcm052.dts} |   6 +-
 arch/arm/dts/vf610-pcm052.dtsi                | 259 ++++++++++++++++++++++++++
 configs/bk4r1_defconfig                       |   2 +-
 configs/pcm052_defconfig                      |   2 +-
 7 files changed, 361 insertions(+), 56 deletions(-)
 delete mode 100644 arch/arm/dts/bk4r1.dts
 create mode 100644 arch/arm/dts/vf610-bk4r1.dts
 rename arch/arm/dts/{pcm052.dts => vf610-pcm052.dts} (81%)
 create mode 100644 arch/arm/dts/vf610-pcm052.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ca50623480..8861827fcc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -432,8 +432,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \
 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 	vf610-colibri.dtb \
 	vf610-twr.dtb \
-	pcm052.dtb \
-	bk4r1.dtb
+	vf610-pcm052.dtb \
+	vf610-bk4r1.dtb
 
 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
 
diff --git a/arch/arm/dts/bk4r1.dts b/arch/arm/dts/bk4r1.dts
deleted file mode 100644
index 866b80e0b0..0000000000
--- a/arch/arm/dts/bk4r1.dts
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2016 Toradex AG
- */
-
-/dts-v1/;
-#include "vf.dtsi"
-
-/ {
-	model = "Phytec phyCORE-Vybrid";
-	compatible = "phytec,pcm052", "fsl,vf610";
-
-	chosen {
-		stdout-path = &uart1;
-	};
-
-	aliases {
-		spi0 = &qspi0;
-	};
-
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&qspi0 {
-	bus-num = <0>;
-	num-cs = <2>;
-	status = "okay";
-
-	qflash0: spi_flash at 0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-flash";
-		spi-max-frequency = <108000000>;
-		reg = <0>;
-	};
-
-	qflash1: spi_flash at 1 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-flash";
-		spi-max-frequency = <66000000>;
-		reg = <1>;
-	};
-};
diff --git a/arch/arm/dts/vf610-bk4r1.dts b/arch/arm/dts/vf610-bk4r1.dts
new file mode 100644
index 0000000000..55cd53384a
--- /dev/null
+++ b/arch/arm/dts/vf610-bk4r1.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * (C) Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de.
+ *
+ * Copyright 2016 Toradex AG
+ */
+
+/dts-v1/;
+#include "vf610-pcm052.dtsi"
+#include "vf610-pinfunc.h"
+
+/ {
+	model = "Liebherr (LVF) BK4 Vybrid Board";
+	compatible = "lvf,bk4", "fsl,vf610";
+
+	leds {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		compatible = "gpio-leds";
+
+		/* PTE15 PORT3[24] H6 green */
+		led at 0 {
+			label = "0";
+			gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* PTA12 PORT0[5] H5 green */
+		led at 1 {
+			label = "1";
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* PTE20 PORT3[39] H4 green */
+		led at 2 {
+			label = "2";
+			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* PTE12 PORT3[21] H3 green */
+		led at 3 {
+			label = "3";
+			gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* LED6 is now PRESET ETH -> PTA16 PORT0[6]  H6 red */
+		/* PTE9  PORT3[18] H5 red */
+		led at 4 {
+			label = "5";
+			gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* PTE23 PORT4[0]  H4 red */
+		led at 5 {
+			label = "6";
+			gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* PTE16 PORT3[25] H3 red */
+		led at 6 {
+			label = "7";
+			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-0 = <&pinctrl_ddr &pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			/* ETH control pins */
+			VF610_PAD_PTE17__GPIO_122		0x1183
+			VF610_PAD_PTA16__GPIO_6	0x1183
+		>;
+	};
+
+	pinctrl_gpio_leds: gpioledsgrp {
+		fsl,pins = <
+			/* LEDS */
+			VF610_PAD_PTE15__GPIO_120	0x1183
+			VF610_PAD_PTA12__GPIO_5	0x1183
+			VF610_PAD_PTE9__GPIO_114	0x1183
+			VF610_PAD_PTE20__GPIO_125	0x1183
+			VF610_PAD_PTE23__GPIO_128	0x1183
+			VF610_PAD_PTE16__GPIO_121	0x1183
+		>;
+	};
+};
diff --git a/arch/arm/dts/pcm052.dts b/arch/arm/dts/vf610-pcm052.dts
similarity index 81%
rename from arch/arm/dts/pcm052.dts
rename to arch/arm/dts/vf610-pcm052.dts
index 6489fdc6f4..22026024ea 100644
--- a/arch/arm/dts/pcm052.dts
+++ b/arch/arm/dts/vf610-pcm052.dts
@@ -4,7 +4,7 @@
  */
 
 /dts-v1/;
-#include "vf.dtsi"
+#include "vf610-pcm052.dtsi"
 
 / {
 	model = "Phytec phyCORE-Vybrid";
@@ -15,7 +15,3 @@
 	};
 
 };
-
-&uart1 {
-	status = "okay";
-};
diff --git a/arch/arm/dts/vf610-pcm052.dtsi b/arch/arm/dts/vf610-pcm052.dtsi
new file mode 100644
index 0000000000..1383d03c22
--- /dev/null
+++ b/arch/arm/dts/vf610-pcm052.dtsi
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * (C) Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de.
+ *
+ */
+
+/dts-v1/;
+#include "vf.dtsi"
+#include "vf610-pinfunc.h"
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	aliases {
+		spi0 = &qspi0;
+		mmc0 = &esdhc1;
+	};
+};
+
+&esdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esdhc1>;
+	bus-width = <4>;
+	cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&fec0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eth>;
+
+	phy-mode = "rmii";
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eth1>;
+
+	phy-mode = "rmii";
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	eeprom: eeprom at 50 {
+		compatible = "atmel,24c256";
+		reg = <0x50>;
+		pagesize = <64>;
+		u-boot,i2c-offset-len = <2>;
+	};
+
+	m41t62: rtc at 68 {
+		compatible = "st,m41t62";
+		reg = <0x68>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ddr>;
+
+	pinctrl_ddr: ddrgrp {
+		fsl,pins = <
+			VF610_PAD_DDR_A15__DDR_A_15             0x1c0
+			VF610_PAD_DDR_A14__DDR_A_14             0x1c0
+			VF610_PAD_DDR_A13__DDR_A_13             0x1c0
+			VF610_PAD_DDR_A12__DDR_A_12             0x1c0
+			VF610_PAD_DDR_A11__DDR_A_11             0x1c0
+			VF610_PAD_DDR_A10__DDR_A_10             0x1c0
+			VF610_PAD_DDR_A9__DDR_A_9               0x1c0
+			VF610_PAD_DDR_A8__DDR_A_8               0x1c0
+			VF610_PAD_DDR_A7__DDR_A_7               0x1c0
+			VF610_PAD_DDR_A6__DDR_A_6               0x1c0
+			VF610_PAD_DDR_A5__DDR_A_5               0x1c0
+			VF610_PAD_DDR_A4__DDR_A_4               0x1c0
+			VF610_PAD_DDR_A3__DDR_A_3               0x1c0
+			VF610_PAD_DDR_A2__DDR_A_2               0x1c0
+			VF610_PAD_DDR_A1__DDR_A_1               0x1c0
+			VF610_PAD_DDR_A0__DDR_A_0               0x1c0
+			VF610_PAD_DDR_BA2__DDR_BA_2             0x1c0
+			VF610_PAD_DDR_BA1__DDR_BA_1             0x1c0
+			VF610_PAD_DDR_BA0__DDR_BA_0             0x1c0
+			VF610_PAD_DDR_CAS__DDR_CAS_B            0x1c0
+			VF610_PAD_DDR_CKE__DDR_CKE_0            0x1c0
+			VF610_PAD_DDR_CLK__DDR_CLK_0            0x101c0
+			VF610_PAD_DDR_CS__DDR_CS_B_0            0x1c0
+			VF610_PAD_DDR_D15__DDR_D_15             0x1c0
+			VF610_PAD_DDR_D14__DDR_D_14             0x1c0
+			VF610_PAD_DDR_D13__DDR_D_13             0x1c0
+			VF610_PAD_DDR_D12__DDR_D_12             0x1c0
+			VF610_PAD_DDR_D11__DDR_D_11             0x1c0
+			VF610_PAD_DDR_D10__DDR_D_10             0x1c0
+			VF610_PAD_DDR_D9__DDR_D_9               0x1c0
+			VF610_PAD_DDR_D8__DDR_D_8               0x1c0
+			VF610_PAD_DDR_D7__DDR_D_7               0x1c0
+			VF610_PAD_DDR_D6__DDR_D_6               0x1c0
+			VF610_PAD_DDR_D5__DDR_D_5               0x1c0
+			VF610_PAD_DDR_D4__DDR_D_4               0x1c0
+			VF610_PAD_DDR_D3__DDR_D_3               0x1c0
+			VF610_PAD_DDR_D2__DDR_D_2               0x1c0
+			VF610_PAD_DDR_D1__DDR_D_1               0x1c0
+			VF610_PAD_DDR_D0__DDR_D_0               0x1c0
+			VF610_PAD_DDR_DQM1__DDR_DQM_1           0x1c0
+			VF610_PAD_DDR_DQM0__DDR_DQM_0           0x1c0
+			VF610_PAD_DDR_DQS1__DDR_DQS_1           0x101c0
+			VF610_PAD_DDR_DQS0__DDR_DQS_0           0x101c0
+			VF610_PAD_DDR_RAS__DDR_RAS_B            0x1c0
+			VF610_PAD_DDR_WE__DDR_WE_B              0x1c0
+			VF610_PAD_DDR_ODT1__DDR_ODT_0           0x1c0
+			VF610_PAD_DDR_ODT0__DDR_ODT_1           0x1c0
+			VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1    0x1c0
+			VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2    0x1c0
+			VF610_PAD_DDR_RESETB                    0x1006c
+		>;
+	};
+
+	pinctrl_esdhc1: esdhc1grp {
+		fsl,pins = <
+			VF610_PAD_PTA24__ESDHC1_CLK		0x31ef
+			VF610_PAD_PTA25__ESDHC1_CMD		0x31ef
+			VF610_PAD_PTA26__ESDHC1_DAT0		0x31ef
+			VF610_PAD_PTA27__ESDHC1_DAT1		0x31ef
+			VF610_PAD_PTA28__ESDHC1_DATA2		0x31ef
+			VF610_PAD_PTA29__ESDHC1_DAT3		0x31ef
+			VF610_PAD_PTB28__GPIO_98		0x219d
+		>;
+	};
+
+	pinctrl_eth: ethgrp {
+		fsl,pins = <
+			VF610_PAD_PTA6__RMII_CLKIN              0x30dd
+			VF610_PAD_PTC0__ENET_RMII0_MDC          0x30de
+			VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df
+			VF610_PAD_PTC2__ENET_RMII0_CRS          0x30dd
+			VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd
+			VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd
+			VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd
+			VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de
+			VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de
+			VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de
+		>;
+	};
+
+	pinctrl_eth1: eth1grp {
+		fsl,pins = <
+			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30de
+			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30df
+			VF610_PAD_PTC11__ENET_RMII1_CRS	0x30dd
+			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30dd
+			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30dd
+			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30dd
+			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30de
+			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30de
+			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30de
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			VF610_PAD_PTA22__I2C2_SCL		0x34df
+			VF610_PAD_PTA23__I2C2_SDA		0x34df
+		>;
+	};
+
+	pinctrl_nfc: nfcgrp {
+		fsl,pins = <
+			VF610_PAD_PTD31__NF_IO15		0x28df
+			VF610_PAD_PTD30__NF_IO14		0x28df
+			VF610_PAD_PTD29__NF_IO13		0x28df
+			VF610_PAD_PTD28__NF_IO12		0x28df
+			VF610_PAD_PTD27__NF_IO11		0x28df
+			VF610_PAD_PTD26__NF_IO10		0x28df
+			VF610_PAD_PTD25__NF_IO9		0x28df
+			VF610_PAD_PTD24__NF_IO8		0x28df
+			VF610_PAD_PTD23__NF_IO7		0x28df
+			VF610_PAD_PTD22__NF_IO6		0x28df
+			VF610_PAD_PTD21__NF_IO5		0x28df
+			VF610_PAD_PTD20__NF_IO4		0x28df
+			VF610_PAD_PTD19__NF_IO3		0x28df
+			VF610_PAD_PTD18__NF_IO2		0x28df
+			VF610_PAD_PTD17__NF_IO1		0x28df
+			VF610_PAD_PTD16__NF_IO0		0x28df
+			VF610_PAD_PTB24__NF_WE_B		0x28c2
+			VF610_PAD_PTB25__NF_CE0_B		0x28c2
+			VF610_PAD_PTB27__NF_RE_B		0x28c2
+			VF610_PAD_PTC26__NF_RB_B		0x283d
+			VF610_PAD_PTC27__NF_ALE		0x28c2
+			VF610_PAD_PTC28__NF_CLE		0x28c2
+		>;
+	};
+
+	pinctrl_qspi0: qspi0grp {
+		fsl,pins = <
+			VF610_PAD_PTD0__QSPI0_A_QSCK	0x397f
+			VF610_PAD_PTD1__QSPI0_A_CS0	0x397f
+			VF610_PAD_PTD2__QSPI0_A_DATA3	0x397f
+			VF610_PAD_PTD3__QSPI0_A_DATA2	0x397f
+			VF610_PAD_PTD4__QSPI0_A_DATA1	0x397f
+			VF610_PAD_PTD5__QSPI0_A_DATA0	0x397f
+			VF610_PAD_PTD7__QSPI0_B_QSCK	0x397f
+			VF610_PAD_PTD8__QSPI0_B_CS0	0x397f
+			VF610_PAD_PTD11__QSPI0_B_DATA1	0x397f
+			VF610_PAD_PTD12__QSPI0_B_DATA0	0x397f
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			VF610_PAD_PTB4__UART1_TX                0x21a2
+			VF610_PAD_PTB5__UART1_RX                0x21a1
+		>;
+	};
+};
+
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_nfc>;
+
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+
+	status = "okay";
+};
+
+&qspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi0>;
+
+	bus-num = <0>;
+	num-cs = <2>;
+	status = "okay";
+
+	qflash0: spi_flash at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <108000000>;
+		reg = <0>;
+	};
+
+	qflash1: spi_flash at 1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <66000000>;
+		reg = <1>;
+	};
+};
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index 9e31b4ac97..b67a3946ac 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -25,7 +25,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=NAND,nor0=NOR"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root);NOR:-(nor)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="bk4r1"
+CONFIG_DEFAULT_DEVICE_TREE="vf610-bk4r1"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
 CONFIG_DM_GPIO=y
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index e207df51a8..26ee823df3 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -24,7 +24,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=NAND"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="pcm052"
+CONFIG_DEFAULT_DEVICE_TREE="vf610-pcm052"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
 CONFIG_DM_GPIO=y
-- 
2.11.0

[U-Boot] [PATCH v4 12/22] ARM: DTS: Provide vf610-bk4r1-u-boot.dtsi for U-Boot specific properties

[Lukasz Majewski]

This commit brings a separate file in which the U-Boot specific
properties (like 'dm-pre-reloc') are provided.

Such approach allows easy sync with upstream Linux kernel in the
future.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

---

Changes in v4: None
Changes in v3: None
Changes in v2:
        - New patch

 arch/arm/dts/vf610-bk4r1-u-boot.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 arch/arm/dts/vf610-bk4r1-u-boot.dtsi

diff --git a/arch/arm/dts/vf610-bk4r1-u-boot.dtsi b/arch/arm/dts/vf610-bk4r1-u-boot.dtsi
new file mode 100644
index 0000000000..088926bde2
--- /dev/null
+++ b/arch/arm/dts/vf610-bk4r1-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ */
+
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&aips0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_ddr {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart1 {
+	u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+};
-- 
2.11.0

[U-Boot] [PATCH v4 13/22] defconfig: bk4/pcm052: Update bk4r1|pcm052_defconfig to support DM/DT

[Lukasz Majewski]

This commit updates BK4's and PCM052's config files to support as much
as possible device tree and model in u-boot.

Moreover, remove CONFIG_* from pcm052.h (as those are now in
bk4|pcm052_defconfig)

Signed-off-by: Lukasz Majewski <lukma@denx.de>

---

Changes in v4: None
Changes in v3: None
Changes in v2:
        - Disable EFI related support and commands (as we do not plan to
          use EFI on this setup)

 configs/bk4r1_defconfig  | 47 ++++++++++++++++++++++++++++++++++++++++++-----
 configs/pcm052_defconfig | 34 ++++++++++++++++++++++++++++++++--
 include/configs/pcm052.h | 34 ----------------------------------
 3 files changed, 74 insertions(+), 41 deletions(-)

diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index b67a3946ac..e3852f4856 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -2,15 +2,18 @@ CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_VF610=y
 CONFIG_SYS_TEXT_BASE=0x3f401000
+CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_TARGET_BK4R1=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg"
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_EEPROM=y
+# CONFIG_CMD_ELF is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -19,19 +22,45 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
+CONFIG_CMD_BOOTCOUNT=y
 CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=NAND,nor0=NOR"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root);NOR:-(nor)"
+CONFIG_MTDIDS_DEFAULT="nand0=vf610_nfc,nor0=NOR"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=vf610_nfc:2048k(bootloader),128k(env1),128k(env2),10240k(initrd),40960k(dtbkernel),-(system);NOR:-(nor)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-bk4r1"
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_NETCONSOLE=y
 CONFIG_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x4006e02c
 CONFIG_DM_GPIO=y
 CONFIG_VYBRID_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_MXC_OCOTP=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_EEPROM_SIZE=32768
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
 CONFIG_NAND_VF610_NFC=y
+CONFIG_NAND_VF610_NFC_DT=y
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
@@ -39,10 +68,18 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_VYBRID=y
+CONFIG_DM_RTC=y
 CONFIG_RTC_M41T62=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_TPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index 26ee823df3..906abbfd69 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -9,7 +9,6 @@ CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_EEPROM=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
@@ -18,7 +17,6 @@ CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
 CONFIG_CMD_FAT=y
 CONFIG_MTDIDS_DEFAULT="nand0=NAND"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root)"
@@ -29,12 +27,44 @@ CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_VYBRID_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_MISC=y
+CONFIG_MXC_OCOTP=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_EEPROM_SIZE=32768
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
 CONFIG_NAND_VF610_NFC=y
+CONFIG_NAND_VF610_NFC_DT=y
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_VYBRID=y
+CONFIG_DM_RTC=y
 CONFIG_RTC_M41T62=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index e125a38e7d..c2ecb7ec18 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -24,48 +24,14 @@
 /* NAND support */
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 
-#ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
-
-#define CONFIG_JFFS2_NAND
-
-/* Dynamic MTD partition support */
-
-#endif
-
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
-#define CONFIG_SYS_FSL_ESDHC_NUM	1
-
-/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE		RMII
-#define CONFIG_FEC_MXC_PHYADDR          0
-
 /* QSPI Configs*/
-
 #ifdef CONFIG_FSL_QSPI
 #define FSL_QSPI_FLASH_SIZE		(1 << 24)
 #define FSL_QSPI_FLASH_NUM		2
 #define CONFIG_SYS_FSL_QSPI_LE
 #endif
 
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC_I2C3
-#define CONFIG_SYS_I2C_MXC
-
-/* RTC (actually an RV-4162 but M41T62-compatible) */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_RTC_BUS_NUM 2
-
-/* EEPROM (24FC256) */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_BUS 2
-
 
 #define CONFIG_LOADADDR			0x82000000
 
-- 
2.11.0

[U-Boot] [PATCH v4 14/22] config: pcm052: Use SZ_X{MK} from linux/sizes.h for include/configs/pcm052.h

[Lukasz Majewski]

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/pcm052.h | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index c2ecb7ec18..fb8f3c8609 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -9,6 +9,7 @@
 #define __CONFIG_H
 
 #include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
@@ -16,7 +17,7 @@
 #define CONFIG_CMDLINE_TAG
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * SZ_1M)
 
 /* Allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -27,7 +28,7 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 /* QSPI Configs*/
 #ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_SIZE		(SZ_16M)
 #define FSL_QSPI_FLASH_NUM		2
 #define CONFIG_SYS_FSL_QSPI_LE
 #endif
@@ -154,7 +155,7 @@
 
 /* Physical memory map */
 #define PHYS_SDRAM			(0x80000000)
-#define PHYS_SDRAM_SIZE			(CONFIG_PCM052_DDR_SIZE * 1024 * 1024)
+#define PHYS_SDRAM_SIZE			(CONFIG_PCM052_DDR_SIZE * SZ_1M)
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
@@ -167,17 +168,17 @@
 
 /* environment organization */
 #ifdef CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_SIZE			(SZ_8K)
 
-#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
+#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #endif
 
 #ifdef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
-#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(SZ_128K)
+#define CONFIG_ENV_SIZE			(SZ_8K)
 #define CONFIG_ENV_OFFSET		0xA0000
-#define CONFIG_ENV_SIZE_REDUND		(8 * 1024)
+#define CONFIG_ENV_SIZE_REDUND		(SZ_8K)
 #define CONFIG_ENV_OFFSET_REDUND	0xC0000
 #endif
 
-- 
2.11.0

[U-Boot] [PATCH v4 15/22] config: bk4: Update include/configs/bk4r1.h file

[Lukasz Majewski]

The BK4's config file has changed since its initial posting to main line.
This commit reflects those changes.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/bk4r1.h | 214 ++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 206 insertions(+), 8 deletions(-)

diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
index a012705870..bbd3e4e636 100644
--- a/include/configs/bk4r1.h
+++ b/include/configs/bk4r1.h
@@ -1,24 +1,222 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ *
  * Copyright 2016 3ADEV <http://3adev.com>
  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
  *
- * Configuration settings for the phytec PCM-052 SoM-based BK4R1.
+ * Configuration settings for BK4R1.
  */
 
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
 /* Define the BK4r1-specific env commands */
-#define PCM052_EXTRA_ENV_SETTINGS \
+#define BK4_EXTRA_ENV_SETTINGS \
+	"bootlimit=3\0" \
+	"eraseuserdata=false\0" \
+	"altbootcmd=led 5 on; " \
+		"boot\0" \
 	"set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \
-	"set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"
+	"set_gpio102=mw 0x400ff0c4 0x40; mw 0x40048198 0x000011bf\0" \
+	"set_gpio96=mw 0x40048180 0x282; mw 0x400ff0c4 0x1\0"\
+	"set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"\
+	"set_gpio6=mw 0x40048018 0x282; mw 0x400ff008 0x40\0"\
+	"manage_userdata=" MANAGE_USERDATA "\0"\
+	"ncenable=true\0"\
+	"ncserverip=192.168.0.77\0"\
+	"if_netconsole=ping $ncserverip\0"\
+	"start_netconsole=setenv ncip $serverip; setenv bootdelay 10;" \
+	     "setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \
+	"preboot=" BK4_NET_INIT \
+		"if ${ncenable}; then run if_netconsole start_netconsole; fi\0"
 
 /* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/
-#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; "
+#define BK4_BOOTCOMMAND "run set_gpio122; run set_gpio96; sf probe; " \
+			"run manage_userdata; "
+
+/* Enable PREBOOT variable */
+#define CONFIG_PREBOOT
+
+/* Set ARP_TIMEOUT to 500ms */
+#define CONFIG_ARP_TIMEOUT 500UL
+
+/* Set ARP_TIMEOUT_COUNT to 3 repetitions */
+#define CONFIG_NET_RETRY_COUNT	5
 
 /* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */
-#define PCM052_NET_INIT "run set_gpio122; "
+#define BK4_NET_INIT "run set_gpio122;"
+
+/* Check if userdata volume shall be erased */
+#define MANAGE_USERDATA "if ${eraseuserdata}; " \
+						"then ubi part system; " \
+						"ubi remove userdata; " \
+						"ubi create userdata; " \
+						"ubi detach; " \
+						"setenv eraseuserdata false; " \
+						"saveenv; " \
+						"fi; "
+
+/* Autoboot options */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Enter passphrase to stop autoboot, booting in %d seconds\n"
+#define CONFIG_AUTOBOOT_STOP_STR "123"
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 4 * SZ_1M)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* NAND support */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define IMX_FEC1_BASE			ENET1_BASE_ADDR
+
+/* QSPI Configs*/
+#ifdef CONFIG_FSL_QSPI
+#define FSL_QSPI_FLASH_SIZE		(SZ_16M)
+#define FSL_QSPI_FLASH_NUM		2
+#define CONFIG_SYS_FSL_QSPI_LE
+#endif
+
+#define CONFIG_LOADADDR	0x82000000
+
+/* We boot from the gfxRAM area of the OCRAM. */
+#define CONFIG_BOARD_SIZE_LIMIT		520192
+
+/* boot command, including the target-defined one if any */
+#define CONFIG_BOOTCOMMAND	BK4_BOOTCOMMAND "run bootcmd_nand"
+
+/* Extra env settings (including the target-defined ones if any) */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	BK4_EXTRA_ENV_SETTINGS \
+	"autoload=no\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"blimg_file=u-boot.vyb\0" \
+	"blimg_addr=0x81000000\0" \
+	"dtbkernel_file=fitImage\0" \
+	"dtbkernel_addr=0x82000000\0" \
+	"ram_file=uRamdisk\0" \
+	"ram_addr=0x83000000\0" \
+	"filesys=rootfs.ubifs\0" \
+	"sys_addr=0x81000000\0" \
+	"nfs_root=/path/to/nfs/root\0" \
+	"tftptimeout=1000\0" \
+	"tftptimeoutcountmax=1000000\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"ipaddr=192.168.0.60\0" \
+	"serverip=192.168.0.1\0" \
+	"bootargs_base=setenv bootargs rw " \
+	"console=ttyLP1,115200n8\0" \
+	"bootargs_sd=setenv bootargs ${bootargs} " \
+		"root=/dev/mmcblk0p2 rootwait\0" \
+	"bootargs_nand=setenv bootargs ${bootargs} " \
+		"ubi.mtd=5 rootfstype=" \
+				"ubifs root=ubi0:rootfs${active_workset}\0" \
+	"bootargs_ram=setenv bootargs ${bootargs} " \
+		"root=/dev/ram rw initrd=${ram_addr}\0" \
+	"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
+		"fatload mmc 0:2 ${dtbkernel_addr} ${dtbkernel_file}; " \
+		"bootm ${dtbkernel_addr}\0" \
+	"bootcmd_nand=sf probe;run bootargs_base bootargs_nand bootargs_mtd; " \
+		"ubi part dtbkernel; " \
+		"ubi readvol ${dtbkernel_addr} dtbkernel${active_workset}; " \
+		"led 0 on; " \
+		"bootm ${dtbkernel_addr}\0" \
+	"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
+		"nand read ${fdt_addr} dtb; " \
+		"nand read ${kernel_addr} kernel; " \
+		"nand read ${ram_addr} root; " \
+		"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
+	"update_bootloader_from_sd=if fatload mmc 0:2 ${blimg_addr} " \
+		"${blimg_file}; " \
+		"then sf probe; " \
+		"mtdparts default; " \
+		"nand erase.part bootloader; " \
+		"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
+	"update_bootloader_from_tftp=if tftp ${blimg_addr} "\
+		"${tftpdir}${blimg_file}; "\
+		"then sf probe; " \
+		"mtdparts default; " \
+		"nand erase.part bootloader; " \
+		"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
+	"update_dtbkernel_from_sd=if fatload mmc 0:2 ${dtbkernel_addr} " \
+		"${dtbkernel_file}; " \
+		"then sf probe; " \
+		"ubi part dtbkernel; " \
+		"ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \
+		"${filesize}; " \
+		"ubi detach; fi\0" \
+	"update_dtbkernel_from_tftp=if tftp ${dtbkernel_addr} " \
+		"${tftpdir}${dtbkernel_file}; " \
+		"then sf probe; " \
+		"ubi part dtbkernel; " \
+		"ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \
+		"${filesize}; " \
+		"ubi detach; fi\0" \
+	"update_ramdisk_from_sd=if fatload mmc 0:2 ${ram_addr} " \
+		"${ram_file}; " \
+		"then sf probe; " \
+		"mtdparts default; " \
+		"nand erase.part initrd; " \
+		"nand write ${ram_addr} initrd ${filesize}; fi\0" \
+	"update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
+		"then sf probe; " \
+		"nand erase.part initrd; " \
+		"nand write ${ram_addr} initrd ${filesize}; fi\0" \
+	"update_rootfs_from_sd=if fatload mmc 0:2 ${sys_addr} " \
+		"${filesys}; " \
+		"then sf probe; " \
+		"ubi part system; " \
+		"ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \
+		"ubi detach; fi\0" \
+	"update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
+		"then sf probe; " \
+		"ubi part system; " \
+		"ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \
+		"ubi detach; fi\0" \
+	"active_workset=1\0"
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START	0x80010000
+#define CONFIG_SYS_MEMTEST_END		0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical memory map */
+#define PHYS_SDRAM			(0x80000000)
+#define PHYS_SDRAM_SIZE		(SZ_512M)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
-/* add NOR to MTD env */
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
-/* now include standard PCM052 config */
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE	(SZ_128K)
+#define CONFIG_ENV_SIZE		(SZ_8K)
+#define CONFIG_ENV_OFFSET	0x200000
+#define CONFIG_ENV_SIZE_REDUND	(SZ_8K)
+#define CONFIG_ENV_OFFSET_REDUND	0x220000
+#endif
 
-#include "configs/pcm052.h"
+#endif /* __CONFIG_H */
-- 
2.11.0

[U-Boot] [PATCH v4 16/22] pcm052: board: Remove in-board setup code (it is now replaced by DM setup)

[Lukasz Majewski]

This commit cleans up the pcm052.c file to remove dead code after moving to
DTS and DM.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/phytec/pcm052/pcm052.c | 267 -------------------------------------------
 1 file changed, 267 deletions(-)

diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index 95df0be6c1..4a18b0e0f4 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -13,79 +13,9 @@
 #include <asm/arch/ddrmc-vf610.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h
- * do not match our settings. Let us (re)define our own settings here.
- */
-
-#define PCM052_VF610_DDR_PAD_CTRL	PAD_CTL_DSE_20ohm
-#define PCM052_VF610_DDR_PAD_CTRL_1	(PAD_CTL_DSE_20ohm | \
-					PAD_CTL_INPUT_DIFFERENTIAL)
-#define PCM052_VF610_DDR_RESET_PAD_CTL	(PAD_CTL_DSE_150ohm | \
-					PAD_CTL_PUS_100K_UP | \
-					PAD_CTL_INPUT_DIFFERENTIAL)
-
-enum {
-	PCM052_VF610_PAD_DDR_RESETB			= IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL),
-	PCM052_VF610_PAD_DDR_A15__DDR_A_15		= IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A14__DDR_A_14		= IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A13__DDR_A_13		= IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A12__DDR_A_12		= IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A11__DDR_A_11		= IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A10__DDR_A_10		= IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A9__DDR_A_9		= IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A8__DDR_A_8		= IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A7__DDR_A_7		= IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A6__DDR_A_6		= IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A5__DDR_A_5		= IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A4__DDR_A_4		= IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A3__DDR_A_3		= IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A2__DDR_A_2		= IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A1__DDR_A_1		= IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A0__DDR_A_0		= IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_BA2__DDR_BA_2		= IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_BA1__DDR_BA_1		= IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_BA0__DDR_BA_0		= IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B		= IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0		= IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0		= IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
-	PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0		= IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D15__DDR_D_15		= IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D14__DDR_D_14		= IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D13__DDR_D_13		= IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D12__DDR_D_12		= IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D11__DDR_D_11		= IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D10__DDR_D_10		= IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D9__DDR_D_9		= IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D8__DDR_D_8		= IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D7__DDR_D_7		= IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D6__DDR_D_6		= IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D5__DDR_D_5		= IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D4__DDR_D_4		= IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D3__DDR_D_3		= IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D2__DDR_D_2		= IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D1__DDR_D_1		= IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D0__DDR_D_0		= IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1		= IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0		= IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1		= IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
-	PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0		= IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
-	PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B		= IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_WE__DDR_WE_B		= IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0		= IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1		= IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1	= IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0	= IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-};
-
 static struct ddrmc_cr_setting pcm052_cr_settings[] = {
 	/* not in the datasheets, but in the original code */
 	{ 0x00002000, 105 },
@@ -154,59 +84,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = {
 
 int dram_init(void)
 {
-	static const iomux_v3_cfg_t pcm052_pads[] = {
-		PCM052_VF610_PAD_DDR_A15__DDR_A_15,
-		PCM052_VF610_PAD_DDR_A14__DDR_A_14,
-		PCM052_VF610_PAD_DDR_A13__DDR_A_13,
-		PCM052_VF610_PAD_DDR_A12__DDR_A_12,
-		PCM052_VF610_PAD_DDR_A11__DDR_A_11,
-		PCM052_VF610_PAD_DDR_A10__DDR_A_10,
-		PCM052_VF610_PAD_DDR_A9__DDR_A_9,
-		PCM052_VF610_PAD_DDR_A8__DDR_A_8,
-		PCM052_VF610_PAD_DDR_A7__DDR_A_7,
-		PCM052_VF610_PAD_DDR_A6__DDR_A_6,
-		PCM052_VF610_PAD_DDR_A5__DDR_A_5,
-		PCM052_VF610_PAD_DDR_A4__DDR_A_4,
-		PCM052_VF610_PAD_DDR_A3__DDR_A_3,
-		PCM052_VF610_PAD_DDR_A2__DDR_A_2,
-		PCM052_VF610_PAD_DDR_A1__DDR_A_1,
-		PCM052_VF610_PAD_DDR_A0__DDR_A_0,
-		PCM052_VF610_PAD_DDR_BA2__DDR_BA_2,
-		PCM052_VF610_PAD_DDR_BA1__DDR_BA_1,
-		PCM052_VF610_PAD_DDR_BA0__DDR_BA_0,
-		PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B,
-		PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0,
-		PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0,
-		PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0,
-		PCM052_VF610_PAD_DDR_D15__DDR_D_15,
-		PCM052_VF610_PAD_DDR_D14__DDR_D_14,
-		PCM052_VF610_PAD_DDR_D13__DDR_D_13,
-		PCM052_VF610_PAD_DDR_D12__DDR_D_12,
-		PCM052_VF610_PAD_DDR_D11__DDR_D_11,
-		PCM052_VF610_PAD_DDR_D10__DDR_D_10,
-		PCM052_VF610_PAD_DDR_D9__DDR_D_9,
-		PCM052_VF610_PAD_DDR_D8__DDR_D_8,
-		PCM052_VF610_PAD_DDR_D7__DDR_D_7,
-		PCM052_VF610_PAD_DDR_D6__DDR_D_6,
-		PCM052_VF610_PAD_DDR_D5__DDR_D_5,
-		PCM052_VF610_PAD_DDR_D4__DDR_D_4,
-		PCM052_VF610_PAD_DDR_D3__DDR_D_3,
-		PCM052_VF610_PAD_DDR_D2__DDR_D_2,
-		PCM052_VF610_PAD_DDR_D1__DDR_D_1,
-		PCM052_VF610_PAD_DDR_D0__DDR_D_0,
-		PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1,
-		PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0,
-		PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1,
-		PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0,
-		PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B,
-		PCM052_VF610_PAD_DDR_WE__DDR_WE_B,
-		PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0,
-		PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1,
-		PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
-		PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0,
-		PCM052_VF610_PAD_DDR_RESETB,
-	};
-
 #if defined(CONFIG_TARGET_PCM052)
 
 	static const struct ddr3_jedec_timings pcm052_ddr_timings = {
@@ -323,8 +200,6 @@ int dram_init(void)
 
 #endif
 
-	imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
-
 	ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
 			     pcm052_phy_settings, 1, row_diff);
 
@@ -333,135 +208,6 @@ int dram_init(void)
 	return 0;
 }
 
-static void setup_iomux_uart(void)
-{
-	static const iomux_v3_cfg_t uart1_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
-			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
-
-static void setup_iomux_enet(void)
-{
-	static const iomux_v3_cfg_t enet0_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
-}
-
-/*
- * I2C2 is the only I2C used, on pads PTA22/PTA23.
- */
-
-static void setup_iomux_i2c(void)
-{
-	static const iomux_v3_cfg_t i2c_pads[] = {
-		VF610_PAD_PTA22__I2C2_SCL,
-		VF610_PAD_PTA23__I2C2_SDA,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
-}
-
-#ifdef CONFIG_NAND_VF610_NFC
-static void setup_iomux_nfc(void)
-{
-	static const iomux_v3_cfg_t nfc_pads[] = {
-		VF610_PAD_PTD31__NF_IO15,
-		VF610_PAD_PTD30__NF_IO14,
-		VF610_PAD_PTD29__NF_IO13,
-		VF610_PAD_PTD28__NF_IO12,
-		VF610_PAD_PTD27__NF_IO11,
-		VF610_PAD_PTD26__NF_IO10,
-		VF610_PAD_PTD25__NF_IO9,
-		VF610_PAD_PTD24__NF_IO8,
-		VF610_PAD_PTD23__NF_IO7,
-		VF610_PAD_PTD22__NF_IO6,
-		VF610_PAD_PTD21__NF_IO5,
-		VF610_PAD_PTD20__NF_IO4,
-		VF610_PAD_PTD19__NF_IO3,
-		VF610_PAD_PTD18__NF_IO2,
-		VF610_PAD_PTD17__NF_IO1,
-		VF610_PAD_PTD16__NF_IO0,
-		VF610_PAD_PTB24__NF_WE_B,
-		VF610_PAD_PTB25__NF_CE0_B,
-		VF610_PAD_PTB27__NF_RE_B,
-		VF610_PAD_PTC26__NF_RB_B,
-		VF610_PAD_PTC27__NF_ALE,
-		VF610_PAD_PTC28__NF_CLE
-	};
-
-	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
-}
-#endif
-
-static void setup_iomux_qspi(void)
-{
-	static const iomux_v3_cfg_t qspi0_pads[] = {
-		VF610_PAD_PTD0__QSPI0_A_QSCK,
-		VF610_PAD_PTD1__QSPI0_A_CS0,
-		VF610_PAD_PTD2__QSPI0_A_DATA3,
-		VF610_PAD_PTD3__QSPI0_A_DATA2,
-		VF610_PAD_PTD4__QSPI0_A_DATA1,
-		VF610_PAD_PTD5__QSPI0_A_DATA0,
-		VF610_PAD_PTD7__QSPI0_B_QSCK,
-		VF610_PAD_PTD8__QSPI0_B_CS0,
-		VF610_PAD_PTD9__QSPI0_B_DATA3,
-		VF610_PAD_PTD10__QSPI0_B_DATA2,
-		VF610_PAD_PTD11__QSPI0_B_DATA1,
-		VF610_PAD_PTD12__QSPI0_B_DATA0,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
-}
-
-#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
-			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
-
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
-	{ESDHC1_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	/* eSDHC1 is always present */
-	return 1;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	static const iomux_v3_cfg_t esdhc1_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
-	};
-
-	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-	imx_iomux_v3_setup_multiple_pads(
-		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
-
-	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-
 static void clock_init(void)
 {
 	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
@@ -534,23 +280,10 @@ static void mscm_init(void)
 		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 }
 
-int board_phy_config(struct phy_device *phydev)
-{
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
 int board_early_init_f(void)
 {
 	clock_init();
 	mscm_init();
-	setup_iomux_uart();
-	setup_iomux_enet();
-	setup_iomux_i2c();
-	setup_iomux_qspi();
-	setup_iomux_nfc();
 
 	return 0;
 }
-- 
2.11.0

[U-Boot] [PATCH v4 17/22] config: bk4: Update u-boot script to support recovery via SD card

[Lukasz Majewski]

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/bk4r1.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
index bbd3e4e636..7bd3411ff2 100644
--- a/include/configs/bk4r1.h
+++ b/include/configs/bk4r1.h
@@ -189,6 +189,37 @@
 		"ubi part system; " \
 		"ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \
 		"ubi detach; fi\0" \
+	"setup_dtbkernel=nand erase.part dtbkernel; " \
+		"ubi part dtbkernel; " \
+		"ubi create dtbkernel1 972000 s; " \
+		"ubi create dtbkernel2 972000 s; " \
+		"ubi detach\0" \
+	"setup_system=nand erase.part system; " \
+		"ubi part system; " \
+		"ubi create rootfs1 15E15000 d; " \
+		"ubi create rootfs2 15E15000 d; " \
+		"ubi create userdata; " \
+		"ubi detach\0" \
+	"prepare_install_bk4r1_envs=" \
+		"echo 'Preparing envs for SD card recovery!';" \
+		"setenv ipaddr 192.168.0.99;" \
+		"setenv serverip 192.168.0.50;" \
+		"\0" \
+	"install_bk4r1rs="\
+		"led 0 on; " \
+		"nand erase.chip; mtdparts default; "\
+		"led 1 on; "\
+		"run setup_dtbkernel; " \
+		"run setup_system; " \
+		"led 2 on;" \
+		"run update_bootloader_from_sd; "\
+		"run update_dtbkernel_from_sd; "\
+		"run update_rootfs_from_sd; "\
+		"setenv bootcmd 'run bootcmd_nand'; "\
+		"saveenv; " \
+		"led 3 on; " \
+		"echo Finished - Please Power off, REMOVE SDCARD and set boot" \
+			"source to NAND\0" \
 	"active_workset=1\0"
 
 /* Miscellaneous configurable options */
-- 
2.11.0

[U-Boot] [PATCH v4 18/22] config: bk4: Update u-boot envs to support NOR memories initial setup

[Lukasz Majewski]

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/bk4r1.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
index 7bd3411ff2..05ebb7d9c5 100644
--- a/include/configs/bk4r1.h
+++ b/include/configs/bk4r1.h
@@ -200,6 +200,24 @@
 		"ubi create rootfs2 15E15000 d; " \
 		"ubi create userdata; " \
 		"ubi detach\0" \
+	"setup_nor1=" BK4_NET_INIT \
+		"if tftp ${sys_addr} ${tftpdir}ubinor1.img; " \
+		"then sf probe 0:0; " \
+		"sf erase 0 01000000; " \
+		"mtdparts default; " \
+		"ubi part nor; " \
+		"ubi create nor1fs; " \
+		"ubi write ${sys_addr} nor1fs ${filesize}; " \
+		"ubi detach; fi\0" \
+	"setup_nor2=" BK4_NET_INIT \
+		"if tftp ${sys_addr} ${tftpdir}ubinor2.img; " \
+		"then sf probe 0:1; " \
+		"sf erase 0 01000000; " \
+		"mtdparts default; " \
+		"ubi part nor; " \
+		"ubi create nor2fs; " \
+		"ubi write ${sys_addr} nor2fs ${filesize}; " \
+		"ubi detach; fi\0" \
 	"prepare_install_bk4r1_envs=" \
 		"echo 'Preparing envs for SD card recovery!';" \
 		"setenv ipaddr 192.168.0.99;" \
-- 
2.11.0

[U-Boot] [PATCH v4 19/22] pcm052: bk4: sdcard: Add support for SD card booting/recovery

[Lukasz Majewski]

This code allows reusing the default u-boot as in the late board init, the
default envs are restored and proper recovery scripts executed.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv7/vf610/Kconfig           |  1 +
 arch/arm/include/asm/arch-vf610/imx-regs.h |  2 ++
 board/phytec/pcm052/pcm052.c               | 32 ++++++++++++++++++++++++++++++
 3 files changed, 35 insertions(+)

diff --git a/arch/arm/cpu/armv7/vf610/Kconfig b/arch/arm/cpu/armv7/vf610/Kconfig
index 13905b5281..5d485a3ce2 100644
--- a/arch/arm/cpu/armv7/vf610/Kconfig
+++ b/arch/arm/cpu/armv7/vf610/Kconfig
@@ -23,6 +23,7 @@ config TARGET_BK4R1
 	bool "BK4r1"
 	select SYS_FSL_ERRATUM_ESDHC135
 	select SYS_FSL_ERRATUM_ESDHC_A001
+	select BOARD_LATE_INIT
 
 endchoice
 
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 5d1f63c98b..ae0a187c4d 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -289,6 +289,8 @@
 #define SRC_SRSR_WDOG_M4				(0x1 << 4)
 #define SRC_SRSR_WDOG_A5				(0x1 << 3)
 #define SRC_SRSR_POR_RST				(0x1 << 0)
+#define SRC_SBMR1_BOOTCFG1_SDMMC        BIT(6)
+#define SRC_SBMR1_BOOTCFG1_MMC          BIT(4)
 #define SRC_SBMR2_BMOD_MASK             (0x3 << 24)
 #define SRC_SBMR2_BMOD_SHIFT            24
 #define SRC_SBMR2_BMOD_FUSES            0x0
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index 4a18b0e0f4..d4f170a503 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -13,6 +13,7 @@
 #include <asm/arch/ddrmc-vf610.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
+#include <environment.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -307,6 +308,37 @@ int board_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_TARGET_BK4R1
+int board_late_init(void)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	u32 reg;
+
+	/*
+	 * BK4r1 handle emergency/service SD card boot
+	 * Checking the SBMR1 register BOOTCFG1 byte:
+	 * NAND:
+	 *      bit [2] - NAND data width - 16
+	 *	bit [5] - NAND fast boot
+	 *	bit [7] = 1 - NAND as a source of booting
+	 * SD card (0x64):
+	 *      bit [4] = 0 - SD card source
+	 *	bit [6] = 1 - SD/MMC source
+	 */
+
+	reg = readl(&psrc->sbmr1);
+	if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
+	    !(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
+		printf("------ SD card boot -------\n");
+		set_default_env("!LVFBootloader", 0);
+		env_set("bootcmd",
+			"run prepare_install_bk4r1_envs; run install_bk4r1rs");
+	}
+
+	return 0;
+}
+#endif /* CONFIG_TARGET_BK4R1 */
+
 int checkboard(void)
 {
 #ifdef CONFIG_TARGET_BK4R1
-- 
2.11.0

[U-Boot] [PATCH v4 20/22] pcm052: board: Add code to setup LED default states

[Lukasz Majewski]

As one has moved to DM based LEDs, this code is required to setup the
default state.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/phytec/pcm052/pcm052.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index d4f170a503..721e25105a 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -13,6 +13,7 @@
 #include <asm/arch/ddrmc-vf610.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
+#include <led.h>
 #include <environment.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -314,6 +315,9 @@ int board_late_init(void)
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
 	u32 reg;
 
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
 	/*
 	 * BK4r1 handle emergency/service SD card boot
 	 * Checking the SBMR1 register BOOTCFG1 byte:
-- 
2.11.0

[U-Boot] [PATCH v4 21/22] pcm052: mac: Provide board specific imx_get_mac_from_fuse() function

[Lukasz Majewski]

This commit introduces the board specific function to read fused mac
address.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/phytec/pcm052/pcm052.c | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index 721e25105a..1e443a5850 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -310,6 +310,47 @@ int board_init(void)
 }
 
 #ifdef CONFIG_TARGET_BK4R1
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[4];
+	struct fuse_bank4_regs *fuse =
+		(struct fuse_bank4_regs *)bank->fuse_regs;
+	u32 value;
+
+	/*
+	 * BK4 has different layout of stored MAC address
+	 * than one used in imx_get_mac_from_fuse() @ generic.c
+	 */
+
+	switch (dev_id) {
+	case 0:
+		value = readl(&fuse->mac_addr1);
+
+		mac[0] = value >> 8;
+		mac[1] = value;
+
+		value = readl(&fuse->mac_addr0);
+		mac[2] = value >> 24;
+		mac[3] = value >> 16;
+		mac[4] = value >> 8;
+		mac[5] = value;
+		break;
+	case 1:
+		value = readl(&fuse->mac_addr2);
+
+		mac[0] = value >> 24;
+		mac[1] = value >> 16;
+		mac[2] = value >> 8;
+		mac[3] = value;
+
+		value = readl(&fuse->mac_addr1);
+		mac[4] = value >> 24;
+		mac[5] = value >> 16;
+		break;
+	}
+}
+
 int board_late_init(void)
 {
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
-- 
2.11.0

[U-Boot] [PATCH v4 22/22] pcm052: bk4: Add board_phy_config() for BK4 to setup ksz8081 phy

[Lukasz Majewski]

BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY devices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/phytec/pcm052/pcm052.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index 1e443a5850..c30df5df9d 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -15,6 +15,7 @@
 #include <asm/arch/clock.h>
 #include <led.h>
 #include <environment.h>
+#include <miiphy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -382,6 +383,21 @@ int board_late_init(void)
 
 	return 0;
 }
+
+/**
+ * KSZ8081
+ */
+#define MII_KSZ8081_REFERENCE_CLOCK_SELECT	0x1f
+#define RMII_50MHz_CLOCK	0x8180
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* Set 50 MHz reference clock */
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
+		  RMII_50MHz_CLOCK);
+
+	return genphy_config(phydev);
+}
 #endif /* CONFIG_TARGET_BK4R1 */
 
 int checkboard(void)
-- 
2.11.0

[U-Boot] [PATCH v1 2/3] imx: serial_mxc: disable ri and dcd irq in dte mode

[Stefano Babic]

Hi Marcel,

On 01/02/19 16:04, Marcel Ziswiler wrote:
> From: Max Krummenacher <max.krummenacher@toradex.com>
> 
> If the UART is used in DTE mode the RI and DCD bits in UCR3 become
> irq enable bits. Both are set to enabled after reset and both likely
> are pending.
> 
> Disable the bits to prevent an interrupt storm when Linux enables
> the UART interrupts.
> 
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> ---
> 

I never seen this issue, but you fix looks plausible - I applied this to
my working branch and queued for next PR.

Regards,
Stefano

>  drivers/serial/serial_mxc.c | 13 +++++++++----
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
> index 7e4e6d36b8..df35ac9114 100644
> --- a/drivers/serial/serial_mxc.c
> +++ b/drivers/serial/serial_mxc.c
> @@ -138,13 +138,18 @@ struct mxc_uart {
>  	u32 ts;
>  };
>  
> -static void _mxc_serial_init(struct mxc_uart *base)
> +static void _mxc_serial_init(struct mxc_uart *base, int use_dte)
>  {
>  	writel(0, &base->cr1);
>  	writel(0, &base->cr2);
>  
>  	while (!(readl(&base->cr2) & UCR2_SRST));
>  
> +	if (use_dte)
> +		writel(0x404 | UCR3_ADNIMP, &base->cr3);
> +	else
> +		writel(0x704 | UCR3_ADNIMP, &base->cr3);
> +
>  	writel(0x704 | UCR3_ADNIMP, &base->cr3);
>  	writel(0x8000, &base->cr4);
>  	writel(0x2b, &base->esc);
> @@ -226,7 +231,7 @@ static int mxc_serial_tstc(void)
>   */
>  static int mxc_serial_init(void)
>  {
> -	_mxc_serial_init(mxc_base);
> +	_mxc_serial_init(mxc_base, false);
>  
>  	serial_setbrg();
>  
> @@ -271,7 +276,7 @@ static int mxc_serial_probe(struct udevice *dev)
>  {
>  	struct mxc_serial_platdata *plat = dev->platdata;
>  
> -	_mxc_serial_init(plat->reg);
> +	_mxc_serial_init(plat->reg, plat->use_dte);
>  
>  	return 0;
>  }
> @@ -367,7 +372,7 @@ static inline void _debug_uart_init(void)
>  {
>  	struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
>  
> -	_mxc_serial_init(base);
> +	_mxc_serial_init(base, false);
>  	_mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
>  			   CONFIG_BAUDRATE, false);
>  }
> 


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v4 01/20] common: spl_fit: Fix the spl_fit_image_get_os for FIT_IMAGE_TINY

[Stefano Babic]

Hi Abel,

On 01/02/19 17:40, Abel Vesa wrote:
> There is not really reducing codesize here since there is only
> a call. The function is always built in if CONFIG_$(SPL_TPL_)FIT is set.
> Plus, there was a change in behavior if CONFIG_SPL_OS_BOOT is defined.
> If CONFIG_FIT_IMAGE_TINY is defined, the spl_fit_image_get_os was
> returning -ENOTSUPP and then if CONFIG_SPL_OS_BOOT was also
> defined, the spl_image->os was left set to 0 which in turn
> was skipping the fdt appending resulting in boot-up failure.
> 

Really there is a difference in codesize, even if it looks like a side
effect. This patch breaks build for sun8i and sun50i due to increased
size. So I have to drop this patch and I applied the rest of the series
to u-boot-imx.

Best regards,
Stefano Babic

> Fixes: 337bbb6297775e spl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  common/spl/spl_fit.c | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index db43626..a87d02d 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -333,11 +333,7 @@ static int spl_fit_record_loadable(const void *fit, int images, int index,
>  
>  static int spl_fit_image_get_os(const void *fit, int noffset, uint8_t *os)
>  {
> -#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
> -	return -ENOTSUPP;
> -#else
>  	return fit_image_get_os(fit, noffset, os);
> -#endif
>  }
>  
>  int spl_load_simple_fit(struct spl_image_info *spl_image,
> 

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v4,18/20] board: mx6sabresd: Remove non-DM code

[sbabic at denx.de]

> Since the mx6sabreauto has DM support, remove the unused non-DM code
> from mx6sabresd board file.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 3/3] imx: cpu.c: give access to reset cause in spl

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> This makes get_imx_reset_cause() accessible in SPL, but keeps the SRSR
> register content intact so that U-Boot proper can evaluated the
> reset_cause again should this be needed.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 17/20] board: mx6sabreauto: Remove the non-DM code

[sbabic at denx.de]

> Since the mx6sabreauto has DM support, remove the unused non-DM code
> from mx6sabreauto board file.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 07/20] board: mx6sabresd: Add board_fit_config_name_match to support FIT in SPL

[sbabic at denx.de]

> This matches one of the following three boards (or fails):
>  - imx6q-sabresd
>  - imx6qp-sabresd
>  - imx6dl-sabresd
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 15/20] configs: mx6sabreauto: Add DM_SPI_FLASH necessary configs

[sbabic at denx.de]

> Enable all neceassary configs to support DM_SPI_FLASH on mx6sabreauto.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 1/3] ARM: dts: i.MX6Q, i.MX6QDL: fix address/size-cells warnings

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> This fixes the following warnings:
> arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
>  /clocks: unnecessary #address-cells/#size-cells without "ranges" or
>  child "reg" property
> arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
>  /soc/aips-bus at 02100000/mipi at 021e0000: unnecessary #address-cells/
>  #size-cells without "ranges" or child "reg" property
> arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
>  /soc/ipu at 02400000/port at 2: unnecessary #address-cells/#size-cells
>  without "ranges" or child "reg" property
> arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
>  /soc/ipu at 02400000/port at 3: unnecessary #address-cells/#size-cells
>  without "ranges" or child "reg" property
> arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
>  /soc/ipu at 02800000/port at 2: unnecessary #address-cells/#size-cells
>  without "ranges" or child "reg" property
> arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
>  /soc/ipu at 02800000/port at 3: unnecessary #address-cells/#size-cells
>  without "ranges" or child "reg" property
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 05/20] configs: imx6sabreauto: Add DM_USB support

[sbabic at denx.de]

> Add the DM support for USB. For that, DM_REGULATOR is needed.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 06/20] mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL builds

[sbabic at denx.de]

> Since the fsl_esdhc will also be used by SPL, make the
> preprocessor switches more generic to allow any kind of build.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 09/20] arm: dts: Add all the imx6[q|qp|dl] sabre[auto|sd] u-boot dts[i] files

[sbabic at denx.de]

> This allows us to keep the basic dts[i] files up-to-date with
> the ones in kernel, but at the same time allowing the u-boot
> to add its own properties to the existing nodes.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 12/20] configs: mx6sabresd: Add SPL FIT and DM support

[sbabic at denx.de]

> Enable all the necessary configs for SPL DM and FIT support for
> mx6sabresd.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 04/20] configs: imx6sabreauto: Add DM_MMC support

[sbabic at denx.de]

> Add DM_MMC config to imx6sabreauto defconfig.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 01/20] common: spl_fit: Fix the spl_fit_image_get_os for FIT_IMAGE_TINY

[sbabic at denx.de]

> There is not really reducing codesize here since there is only
> a call. The function is always built in if CONFIG_$(SPL_TPL_)FIT is set.
> Plus, there was a change in behavior if CONFIG_SPL_OS_BOOT is defined.
> If CONFIG_FIT_IMAGE_TINY is defined, the spl_fit_image_get_os was
> returning -ENOTSUPP and then if CONFIG_SPL_OS_BOOT was also
> defined, the spl_image->os was left set to 0 which in turn
> was skipping the fdt appending resulting in boot-up failure.
> Fixes: 337bbb6297775e spl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
> Tested-by: Lukasz Majewski <lukma@denx.de>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 16/20] configs: mx6sabresd: Add DM_SPI_FLASH necessary configs

[sbabic at denx.de]

> Enable all neceassary configs to support DM_SPI_FLASH on mx6sabresd.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 19/20] board: mx6sabresd: Remove the enet reset gpio handling

[sbabic at denx.de]

> Rely on the phy-reset-gpios which is set in imx6qdl-sabresd dtsi
> and get rid of the enet reset gpio handling from the board file.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 03/20] usb: ehci-mx6: Make regulator DM_REGULATOR dependent

[sbabic at denx.de]

> Do the regulator related work only if the build has the DM_REGULATOR.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 20/20] configs: mx6sabresd: Reduce SPL size by disabling DOS, EXT and EFI support

[sbabic at denx.de]

> With DM and FIT enabled in SPL, there is an sram overflow. By disabling
> CONFIG_SPL_DOS_PARTITION, CONFIG_SPL_EXT_SUPPORT and
> CONFIG_SPL_EFI_PARTITION, we get to keep the 'one binary to fit all'
> for imx6[q|qp|dl] on sabresd since the final SPL image is now under 64KB.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v4,13/20] mx6sabreauto: Add DM_GPIO support

[sbabic at denx.de]

> Add the DM_GPIO related config for mx6sabreauto.
> Also add the gpio request calls.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 08/20] board: mx6sabreauto: Add board_fit_config_name_match to support FIT in SPL

[sbabic at denx.de]

> This matches one of the following three boards (or fails):
>  - imx6q-sabreauto
>  - imx6qp-sabreauto
>  - imx6dl-sabreauto
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 10/20] arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd]

[sbabic at denx.de]

> Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the ones
> from kernel v4.20 (commit 8fe28cb58bcb2).
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Acked-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 11/20] configs: mx6sabreauto: Add SPL FIT and DM support

[sbabic at denx.de]

> Enable all the necessary configs for SPL DM and FIT support for
> mx6sabreauto.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 2/3] ddr: vybrid: Provide code to perform on-boot calibration

[sbabic at denx.de]

> This patch provides the code to calibrate the DDR's
> DQS to DQ signals (RDLVL).
> It is based on:
> VFxxx Controller Reference Manual, Rev. 0, 10/2016, page 1600
> 10.1.6.16.4.1 "Software Read Leveling in MC Evaluation Mode"
> and NXP's community thread:
> "Vybrid: About DDR leveling feature on DDRMC."
> https://community.nxp.com/thread/395323
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v4,14/20] mx6sabresd: Add DM_GPIO support

[sbabic at denx.de]

> Add the DM_GPIO related config for mx6sabresd.
> Also add the gpio request calls.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 2/3] imx: serial_mxc: disable ri and dcd irq in dte mode

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> If the UART is used in DTE mode the RI and DCD bits in UCR3 become
> irq enable bits. Both are set to enabled after reset and both likely
> are pending.
> Disable the bits to prevent an interrupt storm when Linux enables
> the UART interrupts.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 3/3] ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup code

[sbabic at denx.de]

> This patch extends the vf610 DDR memory controller code to support SW
> leveling.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> Reviewed-by: Stefan Agner <stefan.agner@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 1/3] ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ)

[sbabic at denx.de]

> This commit provides extra defines needed for DDR memory controller
> calibration (read leveling performing).
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> Reviewed-by: Stefan Agner <stefan.agner@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 02/20] usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGE

[sbabic at denx.de]

> Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in SPL,
> makes more sense to rename the SPL_USB_SUPPORT as SPL_USB_STORAGE.
> Everything that is not part of the usb storage support in SPL is now
> build under SPL_USB_HOST_SUPPORT.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v4 01/20] common: spl_fit: Fix the spl_fit_image_get_os for FIT_IMAGE_TINY

[Abel Vesa]

On 19-02-16 10:23:10, Stefano Babic wrote:
> Hi Abel,
> 
> On 01/02/19 17:40, Abel Vesa wrote:
> > There is not really reducing codesize here since there is only
> > a call. The function is always built in if CONFIG_$(SPL_TPL_)FIT is set.
> > Plus, there was a change in behavior if CONFIG_SPL_OS_BOOT is defined.
> > If CONFIG_FIT_IMAGE_TINY is defined, the spl_fit_image_get_os was
> > returning -ENOTSUPP and then if CONFIG_SPL_OS_BOOT was also
> > defined, the spl_image->os was left set to 0 which in turn
> > was skipping the fdt appending resulting in boot-up failure.
> > 
> 
> Really there is a difference in codesize, even if it looks like a side
> effect. This patch breaks build for sun8i and sun50i due to increased
> size. So I have to drop this patch and I applied the rest of the series
> to u-boot-imx.
> 

Ok then, but the real problem here is the fact that the spl_image->os remains
unset. And, as per the comment from the common/spl/spl_fit.c call site, the
fallback should be setting to IH_OS_U_BOOT. See below.

> Best regards,
> Stefano Babic
> 
> > Fixes: 337bbb6297775e spl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> > ---
> >  common/spl/spl_fit.c | 4 ----
> >  1 file changed, 4 deletions(-)
> > 
> > diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> > index db43626..a87d02d 100644
> > --- a/common/spl/spl_fit.c
> > +++ b/common/spl/spl_fit.c
> > @@ -333,11 +333,7 @@ static int spl_fit_record_loadable(const void *fit, int images, int index,
> >  
> >  static int spl_fit_image_get_os(const void *fit, int noffset, uint8_t *os)
> >  {
#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY)

So I guess we can keep as it was before but add the following line here then:
+	*os = IH_OS_U_BOOT;

Let me know if I'm missing something here.

	return -ENOTSUPP;
#else
 	return fit_image_get_os(fit, noffset, os);
#endif
> >  }
> >  
> >  int spl_load_simple_fit(struct spl_image_info *spl_image,
> > 
> 
> -- 
> =====================================================================
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> =====================================================================

[U-Boot] [PATCH 3/3] logos: Add the TechNexion's logo

[Fabio Estevam]

Hi Stefano,

On Tue, Dec 11, 2018 at 4:41 PM Otavio Salvador <otavio@ossystems.com.br> wrote:
>
> From: Fabio Estevam <festevam@gmail.com>
>
> Add the TechNexion's logo from their internal U-Boot tree.
>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> ---
>
>  tools/logos/technexion.bmp | Bin 0 -> 22390 bytes
>  1 file changed, 0 insertions(+), 0 deletions(-)
>  create mode 100644 tools/logos/technexion.bmp

I noticed this patch has not been applied.

Maybe a patchwork bug?

Could you please consider applying it?

Thanks

[U-Boot] [PATCH v2 11/23] apalis_imx6: migrate mmc and sata to using driver model

[Soeren Moch]

On 08.02.19 18:12, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Migrate MMC and SATA to using driver model.
>
> While at it also enable SCSI driver model.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
[also reply to v2 of this series to avoid that this gets lost in patchwork]

Hi Marcel,

Thank you for providing this solution to keep SATA working on i.MX6
under DM_SCSI.
I also want to use this on a tbs2910 board, there was a long list of
other boards needing this functionality [1].

Can you implement the UCLASS at a more general place, e.g.
drivers/ata/dwc_ahsata.c directly, instead of your board file? So this
functionality could easily be enabled for other boards.

Thank you,
Soeren

[1] https://lists.denx.de/pipermail/u-boot/2018-November/349368.html

> ---
>
> Changes in v2: None
>
>  board/toradex/apalis_imx6/apalis_imx6.c | 98 +++++++++++++++----------
>  configs/apalis_imx6_defconfig           |  3 +
>  include/configs/apalis_imx6.h           |  3 -
>  3 files changed, 61 insertions(+), 43 deletions(-)
>
> diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
> index 2c16c31021..db06c4e064 100644
> --- a/board/toradex/apalis_imx6/apalis_imx6.c
> +++ b/board/toradex/apalis_imx6/apalis_imx6.c
> @@ -9,6 +9,7 @@
>  #include <common.h>
>  #include <dm.h>
>
> +#include <ahci.h>
>  #include <asm/arch/clock.h>
>  #include <asm/arch/crm_regs.h>
>  #include <asm/arch/imx-regs.h>
> @@ -22,7 +23,9 @@
>  #include <asm/mach-imx/iomux-v3.h>
>  #include <asm/mach-imx/sata.h>
>  #include <asm/mach-imx/video.h>
> +#include <dm/device-internal.h>
>  #include <dm/platform_data/serial_mxc.h>
> +#include <dwc_ahsata.h>
>  #include <environment.h>
>  #include <fsl_esdhc.h>
>  #include <imx_thermal.h>
> @@ -60,6 +63,8 @@ DECLARE_GLOBAL_DATA_PTR;
>
>  #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
>
> +#define APALIS_IMX6_SATA_INIT_RETRIES	10
> +
>  int dram_init(void)
>  {
>  	/* use the DDR controllers configured size */
> @@ -79,6 +84,7 @@ iomux_v3_cfg_t const uart1_pads_dte[] = {
>  	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
>  };
>
> +#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
>  /* Apalis MMC1 */
>  iomux_v3_cfg_t const usdhc1_pads[] = {
>  	MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> @@ -121,6 +127,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
>  	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>  	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
>  };
> +#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
>
>  int mx6_rgmii_rework(struct phy_device *phydev)
>  {
> @@ -288,7 +295,7 @@ int board_ehci_power(int port, int on)
>  }
>  #endif
>
> -#ifdef CONFIG_FSL_ESDHC
> +#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
>  /* use the following sequence: eMMC, MMC1, SD1 */
>  struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
>  	{USDHC3_BASE_ADDR},
> @@ -319,43 +326,6 @@ int board_mmc_getcd(struct mmc *mmc)
>
>  int board_mmc_init(bd_t *bis)
>  {
> -#ifndef CONFIG_SPL_BUILD
> -	s32 status = 0;
> -	u32 index = 0;
> -
> -	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> -	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> -	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> -
> -	usdhc_cfg[0].max_bus_width = 8;
> -	usdhc_cfg[1].max_bus_width = 8;
> -	usdhc_cfg[2].max_bus_width = 4;
> -
> -	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
> -		switch (index) {
> -		case 0:
> -			imx_iomux_v3_setup_multiple_pads(
> -				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
> -			break;
> -		case 1:
> -			imx_iomux_v3_setup_multiple_pads(
> -				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
> -			break;
> -		case 2:
> -			imx_iomux_v3_setup_multiple_pads(
> -				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
> -			break;
> -		default:
> -			printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
> -			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
> -			return status;
> -		}
> -
> -		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
> -	}
> -
> -	return status;
> -#else /* CONFIG_SPL_BUILD */
>  	struct src *psrc = (struct src *)SRC_BASE_ADDR;
>  	unsigned reg = readl(&psrc->sbmr1) >> 11;
>  	/*
> @@ -394,9 +364,8 @@ int board_mmc_init(bd_t *bis)
>  	}
>
>  	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
> -#endif /* CONFIG_SPL_BUILD */
>  }
> -#endif /* CONFIG_FSL_ESDHC */
> +#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
>
>  int board_phy_config(struct phy_device *phydev)
>  {
> @@ -1162,3 +1131,52 @@ U_BOOT_DEVICE(mxc_serial) = {
>  	.name = "serial_mxc",
>  	.platdata = &mxc_serial_plat,
>  };
> +
> +#if CONFIG_IS_ENABLED(AHCI)
> +static int sata_imx_probe(struct udevice *dev)
> +{
> +	int i, err;
> +
> +	for (i = 0; i < APALIS_IMX6_SATA_INIT_RETRIES; i++) {
> +		err = setup_sata();
> +		if (err) {
> +			printf("SATA setup failed: %d\n", err);
> +			return err;
> +		}
> +
> +		udelay(100);
> +
> +		err = dwc_ahsata_probe(dev);
> +		if (!err)
> +			break;
> +
> +		/* There is no device on the SATA port */
> +		if (sata_dm_port_status(0, 0) == 0)
> +			break;
> +
> +		/* There's a device, but link not established. Retry */
> +		device_remove(dev, DM_REMOVE_NORMAL);
> +	}
> +
> +	return 0;
> +}
> +
> +struct ahci_ops sata_imx_ops = {
> +	.port_status = dwc_ahsata_port_status,
> +	.reset	= dwc_ahsata_bus_reset,
> +	.scan	= dwc_ahsata_scan,
> +};
> +
> +static const struct udevice_id sata_imx_ids[] = {
> +	{ .compatible = "fsl,imx6q-ahci" },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(sata_imx) = {
> +	.name		= "dwc_ahci",
> +	.id		= UCLASS_AHCI,
> +	.of_match	= sata_imx_ids,
> +	.ops		= &sata_imx_ops,
> +	.probe		= sata_imx_probe,
> +};
> +#endif /* AHCI */
> diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
> index 7e973ded74..510161ad32 100644
> --- a/configs/apalis_imx6_defconfig
> +++ b/configs/apalis_imx6_defconfig
> @@ -9,6 +9,7 @@ CONFIG_SPL_MMC_SUPPORT=y
>  CONFIG_SPL_SERIAL_SUPPORT=y
>  CONFIG_SPL=y
>  CONFIG_CMD_HDMIDETECT=y
> +CONFIG_AHCI=y
>  CONFIG_DISTRO_DEFAULTS=y
>  CONFIG_NR_DRAM_BANKS=1
>  CONFIG_FIT=y
> @@ -55,6 +56,7 @@ CONFIG_DWC_AHSATA=y
>  CONFIG_DFU_MMC=y
>  CONFIG_DM_GPIO=y
>  CONFIG_DM_I2C=y
> +CONFIG_DM_MMC=y
>  CONFIG_FSL_ESDHC=y
>  CONFIG_PHYLIB=y
>  CONFIG_PHY_MICREL=y
> @@ -67,6 +69,7 @@ CONFIG_DM_PMIC_PFUZE100=y
>  CONFIG_DM_REGULATOR=y
>  CONFIG_DM_REGULATOR_PFUZE100=y
>  CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_SCSI=y
>  CONFIG_IMX_THERMAL=y
>  CONFIG_USB=y
>  CONFIG_USB_KEYBOARD=y
> diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
> index 5ab009c8f3..6b20d1e104 100644
> --- a/include/configs/apalis_imx6.h
> +++ b/include/configs/apalis_imx6.h
> @@ -57,9 +57,6 @@
>   * SATA Configs
>   */
>  #ifdef CONFIG_CMD_SATA
> -#define CONFIG_SYS_SATA_MAX_DEVICE	1
> -#define CONFIG_DWC_AHSATA_PORT_ID	0
> -#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
>  #define CONFIG_LBA48
>  #endif
>

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Fabio Estevam]

Hi Baruch and Stefano,

On Wed, Jan 2, 2019 at 4:59 AM Baruch Siach <baruch@tkos.co.il> wrote:
>
> Use a single '=' to test string equality for compatibility with non-bash
> shells. Otherwise, if /bin/sh is dash, build fails:
>
> ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
> ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
> ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
> ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
> WARNING './spl/u-boot-spl-ddr.bin' not found, resulting binary is not-functional
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>

I don't see this patch applied yet.

Do we have other solution?

Thanks

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Baruch Siach]

Hi Fabio,

On Thu, Feb 28 2019, Fabio Estevam wrote:
> On Wed, Jan 2, 2019 at 4:59 AM Baruch Siach <baruch@tkos.co.il> wrote:
>>
>> Use a single '=' to test string equality for compatibility with non-bash
>> shells. Otherwise, if /bin/sh is dash, build fails:
>>
>> ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
>> ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
>> ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
>> ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
>> WARNING './spl/u-boot-spl-ddr.bin' not found, resulting binary is not-functional
>>
>> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
>
> I don't see this patch applied yet.
>
> Do we have other solution?

Stefano suggested an alternative in reply to the other patch:

  https://lists.denx.de/pipermail/u-boot/2019-January/356941.html

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -

[U-Boot] [PATCH v4 19/20] board: mx6sabresd: Remove the enet reset gpio handling

[Soeren Moch]

On 02.02.19 10:48, Fabio Estevam wrote:
> On Fri, Feb 1, 2019 at 2:53 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>> Rely on the phy-reset-gpios which is set in imx6qdl-sabresd dtsi
>> and get rid of the enet reset gpio handling from the board file.
>>
>> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Fabio,

I tried to understand this patch, in order to also apply it  for the
tbs2910 board.
What I read from the fec_mxc driver, this only works with DM_ETH
enabled, but this is not enabled for mx6sabresd.

Can you point me to what I miss here?

Thanks,
Soeren

[U-Boot] [PATCH v4 19/20] board: mx6sabresd: Remove the enet reset gpio handling

[Fabio Estevam]

Hi Soeren,

On Thu, Feb 28, 2019 at 4:01 PM Soeren Moch <smoch@web.de> wrote:

> Fabio,
>
> I tried to understand this patch, in order to also apply it  for the
> tbs2910 board.
> What I read from the fec_mxc driver, this only works with DM_ETH
> enabled, but this is not enabled for mx6sabresd.

Good catch. DM_ETH needs to be enabled for mx6sabresd.

However, I noticed that when using U-Boot master I can not boot
mx6sabresd anymore:

U-Boot SPL 2019.04-rc2-00134-g783e66816d (Feb 28 2019 - 16:17:32 -0300)
Trying to boot from MMC1

(It hangs here)

Abel, Peng,

Could you please take a look at this?

Thanks

[U-Boot] [PATCH 00/10] tbs2910 fixes and driver model conversion

[Soeren Moch]

DM_MMC activates BLK, so we have to convert dwc_ahsata to AHCI before.

Soeren Moch (10):
  board: tbs2910: Fix default environment
  board: tbs2910: Remove efi loader support in defconfig to reduce
    u-boot size
  board: tbs2910: Add device tree
  board: tbs2910: Add pinctrl driver and convert gpio to driver model
  board: tbs2910: Convert usb to driver model
  board: tbs2910: Convert i2c and rtc to driver model
  ata: dwc_ahsata: Fix sector reports for large disks
  ata: dwc_ahsata: Add ahci driver model support
  board: tbs2910: Convert sata to ahci driver model
  board: tbs2910: Convert mmc to driver model

 arch/arm/dts/imx6q-tbs2910.dts | 394 +++++++++++++++++++++++++++++++++
 board/tbs/tbs2910/MAINTAINERS  |   1 +
 board/tbs/tbs2910/tbs2910.c    | 184 +--------------
 configs/cm_fx6_defconfig       |   1 +
 configs/tbs2910_defconfig      |  18 +-
 drivers/ata/Kconfig            |   8 +
 drivers/ata/dwc_ahsata.c       |  38 +++-
 include/configs/tbs2910.h      |  38 +---
 8 files changed, 455 insertions(+), 227 deletions(-)
 create mode 100644 arch/arm/dts/imx6q-tbs2910.dts

--
2.17.1

[U-Boot] [PATCH 01/10] board: tbs2910: Fix default environment

[Soeren Moch]

Especially fix usb keyboard support. Other changes are only for
beautification.

Signed-off-by: Soeren Moch <smoch@web.de>
---
Cc: Stefano Babic <sbabic@denx.de>
Cc: u-boot at lists.denx.de
---
 include/configs/tbs2910.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 2d4b9c9bfe..b06c90939c 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -94,7 +94,7 @@
 		"run set_con_hdmi; " \
 	"else " \
 		"run set_con_serial; " \
-	"fi;"
+	"fi"
 #endif /* CONFIG_USB_KEYBOARD */
 #endif /* CONFIG_CMD_USB      */

@@ -142,12 +142,12 @@
 	"console=ttymxc0\0" \
 	"fan=gpio set 92\0" \
 	"set_con_serial=setenv stdout serial; " \
-			"setenv stderr serial;\0" \
+			"setenv stderr serial\0" \
 	"set_con_hdmi=setenv stdout serial,vga; " \
-			"setenv stderr serial,vga;\0" \
-	"stderr=serial,vga;\0" \
-	"stdin=serial,usbkbd;\0" \
-	"stdout=serial,vga;\0"
+			"setenv stderr serial,vga\0" \
+	"stderr=serial,vga\0" \
+	"stdin=serial,usbkbd\0" \
+	"stdout=serial,vga\0"

 #define CONFIG_BOOTCOMMAND \
 	"mmc rescan; " \
--
2.17.1

[U-Boot] [PATCH 02/10] board: tbs2910: Remove efi loader support in defconfig to reduce u-boot size

[Soeren Moch]

Signed-off-by: Soeren Moch <smoch@web.de>
---
Cc: Stefano Babic <sbabic@denx.de>
Cc: u-boot at lists.denx.de
---
 configs/tbs2910_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 78beb9a522..70a3e18e23 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -56,3 +56,4 @@ CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
--
2.17.1

[U-Boot] [PATCH 03/10] board: tbs2910: Add device tree

[Soeren Moch]

... as preparation for additional driver model coonversions.

We use CONFIG_OF_EMBED here to keep u-boot.imx as final binary name. So we
maintain compatibility with the original TBS u-boot and available HOWTOs
for u-boot updates.

Signed-off-by: Soeren Moch <smoch@web.de>
---
Cc: Stefano Babic <sbabic@denx.de>
Cc: u-boot at lists.denx.de
---
 arch/arm/dts/imx6q-tbs2910.dts | 394 +++++++++++++++++++++++++++++++++
 board/tbs/tbs2910/MAINTAINERS  |   1 +
 board/tbs/tbs2910/tbs2910.c    |   6 -
 configs/tbs2910_defconfig      |   4 +-
 4 files changed, 398 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/dts/imx6q-tbs2910.dts

diff --git a/arch/arm/dts/imx6q-tbs2910.dts b/arch/arm/dts/imx6q-tbs2910.dts
new file mode 100644
index 0000000000..21e62c0cab
--- /dev/null
+++ b/arch/arm/dts/imx6q-tbs2910.dts
@@ -0,0 +1,394 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2014-2019 Soeren Moch <smoch@web.de>
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "TBS2910 Matrix ARM mini PC";
+	compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	aliases {
+		mmc0 = &usdhc2;
+		mmc1 = &usdhc3;
+		mmc2 = &usdhc4;
+		usb0 = &usbotg;
+	};
+
+	memory at 10000000 {
+		reg = <0x10000000 0x80000000>;
+	};
+
+	fan {
+		compatible = "gpio-fan";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_fan>;
+		gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+		gpio-fan,speed-map = <0    0
+				      3000 1>;
+	};
+
+	ir_recv {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ir>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		blue {
+			label = "blue_status_led";
+			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+			default-state = "keep";
+		};
+	};
+
+	reg_2p5v: regulator-2p5v {
+		compatible = "regulator-fixed";
+		regulator-name = "2P5V";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_5p0v: regulator-5p0v {
+		compatible = "regulator-fixed";
+		regulator-name = "5P0V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	sound-sgtl5000 {
+		audio-codec = <&sgtl5000>;
+		audio-routing =
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"Headphone Jack", "HP_OUT";
+		compatible = "fsl,imx-audio-sgtl5000";
+		model = "On-board Codec";
+		mux-ext-port = <3>;
+		mux-int-port = <1>;
+		ssi-controller = <&ssi1>;
+	};
+
+	sound-spdif {
+		compatible = "fsl,imx-audio-spdif";
+		model = "On-board SPDIF";
+		spdif-controller = <&spdif>;
+		spdif-out;
+	};
+};
+
+&audmux {
+	status = "okay";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&hdmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi>;
+	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	sgtl5000: sgtl5000 at a {
+		clocks = <&clks IMX6QDL_CLK_CKO>;
+		compatible = "fsl,sgtl5000";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sgtl5000>;
+		reg = <0x0a>;
+		VDDA-supply = <&reg_2p5v>;
+		VDDIO-supply = <&reg_3p3v>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	rtc: ds1307 at 68 {
+		compatible = "dallas,ds1307";
+		reg = <0x68>;
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&sata {
+	fsl,transmit-level-mV = <1104>;
+	fsl,transmit-boost-mdB = <3330>;
+	fsl,transmit-atten-16ths = <16>;
+	fsl,receive-eq-mdB = <3000>;
+	status = "okay";
+};
+
+&snvs_poweroff {
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif>;
+	status = "okay";
+};
+
+&ssi1 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_5p0v>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_5p0v>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	voltage-ranges = <3300 3300>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	voltage-ranges = <3300 3300>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <8>;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	voltage-ranges = <3300 3300>;
+	non-removable;
+	no-1-8-v;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
+			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b059
+		>;
+	};
+
+	pinctrl_gpio_fan: gpiofangrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D28__GPIO3_IO28        0x130b1
+		>;
+	};
+
+	pinctrl_gpio_leds: gpioledsgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02         0x130b1
+		>;
+	};
+
+	pinctrl_hdmi: hdmigrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL        0x4001b8b1
+			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA        0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL         0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA         0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL           0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA           0x4001b8b1
+		>;
+	};
+
+	pinctrl_ir: irgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D18__GPIO3_IO18        0x17059
+		>;
+	};
+
+	pinctrl_pcie: pciegrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12        0x17059
+		>;
+	};
+
+	pinctrl_sgtl5000: sgtl5000grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD        0x130b0
+			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC        0x130b0
+			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD        0x110b0
+			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS       0x130b0
+			MX6QDL_PAD_GPIO_0__CCM_CLKO1          0x130b0
+		>;
+	};
+
+	pinctrl_spdif: spdifgrp {
+		fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT     0x13091
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA  0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA  0x1b0b1
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D26__UART2_TX_DATA     0x1b0b1
+			MX6QDL_PAD_EIM_D27__UART2_RX_DATA     0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID     0x17059
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD           0x17059
+			MX6QDL_PAD_SD2_CLK__SD2_CLK           0x10059
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0        0x17059
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1        0x17059
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2        0x17059
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3        0x17059
+			MX6QDL_PAD_NANDF_D2__GPIO2_IO02       0x17059
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD           0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK           0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0        0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1        0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2        0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3        0x17059
+			MX6QDL_PAD_NANDF_D0__GPIO2_IO00       0x17059
+			MX6QDL_PAD_NANDF_D1__GPIO2_IO01       0x17059
+		>;
+	};
+
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD           0x17059
+			MX6QDL_PAD_SD4_CLK__SD4_CLK           0x10059
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0        0x17059
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1        0x17059
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2        0x17059
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3        0x17059
+			MX6QDL_PAD_SD4_DAT4__SD4_DATA4        0x17059
+			MX6QDL_PAD_SD4_DAT5__SD4_DATA5        0x17059
+			MX6QDL_PAD_SD4_DAT6__SD4_DATA6        0x17059
+			MX6QDL_PAD_SD4_DAT7__SD4_DATA7        0x17059
+		>;
+	};
+};
diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS
index bf176553d2..a3ad2f712a 100644
--- a/board/tbs/tbs2910/MAINTAINERS
+++ b/board/tbs/tbs2910/MAINTAINERS
@@ -1,6 +1,7 @@
 TBS2910 BOARD
 M:	Soeren Moch <smoch@web.de>
 S:	Maintained
+F:	arch/arm/dts/imx6q-tbs2910.dts
 F:	board/tbs/tbs2910/
 F:	configs/tbs2910_defconfig
 F:	include/configs/tbs2910.h
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index ecb45f208d..99b282ca6b 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -446,9 +446,3 @@ int board_init(void)
 #endif
 	return 0;
 }
-
-int checkboard(void)
-{
-	puts("Board: TBS2910 Matrix ARM mini PC\n");
-	return 0;
-}
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 70a3e18e23..3cc68eb922 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -36,6 +36,9 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_EFI_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-tbs2910"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
@@ -55,5 +58,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
 # CONFIG_EFI_LOADER is not set
--
2.17.1

[U-Boot] [PATCH 04/10] board: tbs2910: Add pinctrl driver and convert gpio to driver model

[Soeren Moch]

We need this for additional driver model conversions.

Signed-off-by: Soeren Moch <smoch@web.de>
---
Cc: Stefano Babic <sbabic@denx.de>
Cc: u-boot at lists.denx.de
---
 board/tbs/tbs2910/tbs2910.c | 3 +++
 configs/tbs2910_defconfig   | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index 99b282ca6b..175dd88a69 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -138,6 +138,7 @@ static void setup_iomux_enet(void)
 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

 	/* Reset AR8035 PHY */
+	gpio_request(IMX_GPIO_NR(1, 25), "ETH_PHY_RESET");
 	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
 	udelay(500);
 	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
@@ -230,12 +231,14 @@ int board_mmc_init(bd_t *bis)
 		case 0:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_CD_GPIO, "MMC0_CD");
 			gpio_direction_input(USDHC2_CD_GPIO);
 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 			break;
 		case 1:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			gpio_request(USDHC3_CD_GPIO, "MMC1_CD");
 			gpio_direction_input(USDHC3_CD_GPIO);
 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 			break;
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 3cc68eb922..717cabfa3b 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -42,10 +42,13 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-tbs2910"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
+CONFIG_DM_GPIO=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
--
2.17.1

[U-Boot] [PATCH 05/10] board: tbs2910: Convert usb to driver model

[Soeren Moch]

So we don't need to duplicate settings from the device tree in the board file.

Signed-off-by: Soeren Moch <smoch@web.de>
---
Cc: Stefano Babic <sbabic@denx.de>
Cc: u-boot at lists.denx.de
---
 board/tbs/tbs2910/tbs2910.c | 10 ----------
 configs/tbs2910_defconfig   |  2 ++
 include/configs/tbs2910.h   |  1 -
 3 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index 175dd88a69..20c93778e1 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -418,12 +418,6 @@ static const struct boot_mode board_boot_modes[] = {
 };
 #endif

-#ifdef CONFIG_USB_EHCI_MX6
-static iomux_v3_cfg_t const usb_otg_pads[] = {
-	MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-#endif
-
 int board_init(void)
 {
 	/* address of boot parameters */
@@ -442,10 +436,6 @@ int board_init(void)
 #endif
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
-#endif
-#ifdef CONFIG_USB_EHCI_MX6
-	imx_iomux_v3_setup_multiple_pads(
-		usb_otg_pads, ARRAY_SIZE(usb_otg_pads));
 #endif
 	return 0;
 }
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 717cabfa3b..395275c6dd 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -43,6 +43,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_KEYBOARD=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
@@ -51,6 +52,7 @@ CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index b06c90939c..93f75d72f3 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -81,7 +81,6 @@

 /* USB */
 #ifdef CONFIG_CMD_USB
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #ifdef CONFIG_CMD_USB_MASS_STORAGE
--
2.17.1

[U-Boot] [PATCH 06/10] board: tbs2910: Convert i2c and rtc to driver model

[Soeren Moch]

So we don't need to duplicate settings from the device tree in the board file.

Signed-off-by: Soeren Moch <smoch@web.de>
---
Cc: Stefano Babic <sbabic@denx.de>
Cc: u-boot at lists.denx.de
---
 board/tbs/tbs2910/tbs2910.c | 57 -------------------------------------
 configs/tbs2910_defconfig   |  6 +++-
 include/configs/tbs2910.h   | 17 -----------
 3 files changed, 5 insertions(+), 75 deletions(-)

diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index 20c93778e1..2445efbde2 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -9,7 +9,6 @@
 #include <asm/arch/mx6-pins.h>
 #include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/boot_mode.h>
@@ -22,7 +21,6 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
-#include <i2c.h>
 DECLARE_GLOBAL_DATA_PTR;

 #define WEAK_PULLUP	(PAD_CTL_PUS_47K_UP |			\
@@ -40,56 +38,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

-#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#ifdef CONFIG_SYS_I2C
-/* I2C1, SGTL5000 */
-static struct i2c_pads_info i2c_pad_info0 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
-		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
-		.gp = IMX_GPIO_NR(5, 26)
-	}
-};
-
-/* I2C2 HDMI */
-static struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
-		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-/* I2C3, CON11, DS1307, PCIe_SMB */
-static struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
-		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
-		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
-		.gp = IMX_GPIO_NR(1, 6)
-	}
-};
-#endif /* CONFIG_SYS_I2C */
-
 static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -426,11 +374,6 @@ int board_init(void)
 #ifdef CONFIG_VIDEO_IPUV3
 	setup_display();
 #endif
-#ifdef CONFIG_SYS_I2C
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-#endif
 #ifdef CONFIG_DWC_AHSATA
 	setup_sata();
 #endif
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 395275c6dd..153f61d09d 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -28,7 +28,6 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
@@ -43,6 +42,8 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_KEYBOARD=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
@@ -50,6 +51,8 @@ CONFIG_MII=y
 CONFIG_PCI=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_DS1307=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
@@ -62,5 +65,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_I2C_EDID=y
 CONFIG_VIDEO=y
 # CONFIG_EFI_LOADER is not set
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 93f75d72f3..eff93eff4f 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -97,23 +97,6 @@
 #endif /* CONFIG_USB_KEYBOARD */
 #endif /* CONFIG_CMD_USB      */

-/* RTC */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1307
-#define CONFIG_SYS_RTC_BUS_NUM		2
-#endif
-
-/* I2C */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_I2C_EDID
-#endif
-
 /* Environment organization */
 #define CONFIG_SYS_MMC_ENV_DEV		2 /* overwritten on SD boot */
 #define CONFIG_SYS_MMC_ENV_PART		1 /* overwritten on SD boot */
--
2.17.1

[U-Boot] [PATCH 07/10] ata: dwc_ahsata: Fix sector reports for large disks

[Soeren Moch]

Do not report negative sector numbers for disks > 1TB, do not limit
sector numbers to 32 bit if CONFIG_SYS_64BIT_LBA is enabled.

Signed-off-by: Soeren Moch <smoch@web.de>
---
Cc: Stefano Babic <sbabic@denx.de>
Cc: u-boot at lists.denx.de
---
 drivers/ata/dwc_ahsata.c | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index 4c5b98482f..6fe5641dd9 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -511,15 +511,9 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
 static void dwc_ahsata_print_info(struct blk_desc *pdev)
 {
 	printf("SATA Device Info:\n\r");
-#ifdef CONFIG_SYS_64BIT_LBA
 	printf("S/N: %s\n\rProduct model number: %s\n\r"
-		"Firmware version: %s\n\rCapacity: %lld sectors\n\r",
+		"Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r",
 		pdev->product, pdev->vendor, pdev->revision, pdev->lba);
-#else
-	printf("S/N: %s\n\rProduct model number: %s\n\r"
-		"Firmware version: %s\n\rCapacity: %ld sectors\n\r",
-		pdev->product, pdev->vendor, pdev->revision, pdev->lba);
-#endif
 }

 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
@@ -754,7 +748,6 @@ static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
 	u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
 	u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
 	u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
-	u64 n_sectors;
 	u8 port = uc_priv->hard_port_no;
 	ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);

@@ -773,9 +766,8 @@ static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
 	ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
 	memcpy(pdev->vendor, product, sizeof(product));

-	/* Totoal sectors */
-	n_sectors = ata_id_n_sectors(id);
-	pdev->lba = (u32)n_sectors;
+	/* Total sectors */
+	pdev->lba = ata_id_n_sectors(id);

 	pdev->type = DEV_TYPE_HARDDISK;
 	pdev->blksz = ATA_SECT_SIZE;
--
2.17.1

[U-Boot] [PATCH 08/10] ata: dwc_ahsata: Add ahci driver model support

[Soeren Moch]

Disable this support for cm_fx6 to avoid breakage.

Signed-off-by: Soeren Moch <smoch@web.de>
---
It would be easy to add weak board_ahci_enable/disable functions which
can be overwritten (e.g. in the cm_fx6 board file) to handle power enable/
disable on driver probe/remove. But I have no idea why this board needs these
repeated probe/remove calls for the same sata device. In my tests on a
tbs2910 board a sata harddisk is always recognized by a 'sata init' command,
also without this probe loop.
If this can be ironed out, we can remove the DWC_AHSATA_AHCI config option.

Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: u-boot at lists.denx.de
---
 configs/cm_fx6_defconfig |  1 +
 drivers/ata/Kconfig      |  8 ++++++++
 drivers/ata/dwc_ahsata.c | 24 ++++++++++++++++++++++++
 3 files changed, 33 insertions(+)

diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index c8d1e83111..1623357132 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -51,6 +51,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DWC_AHSATA=y
+# CONFIG_DWC_AHSATA_AHCI is not set
 CONFIG_DM_KEYBOARD=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 49a056e941..d7818c2d68 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -66,6 +66,14 @@ config DWC_AHSATA
 	  Enable this driver to support the DWC AHSATA SATA controller found
 	  in i.MX5 and i.MX6 SoCs.

+config DWC_AHSATA_AHCI
+	bool "Enable DWC AHSATA AHCI driver support"
+	depends on DWC_AHSATA
+	depends on AHCI
+	default y
+	help
+	  Enable this option unless you need your private ahci implementation
+
 config FSL_SATA
 	bool "Enable Freescale SATA controller driver support"
 	select LIBATA
diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index 6fe5641dd9..afced8e7e3 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -16,6 +16,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/sata.h>
 #include <linux/bitops.h>
 #include <linux/ctype.h>
 #include <linux/errno.h>
@@ -1020,6 +1021,9 @@ int dwc_ahsata_probe(struct udevice *dev)
 	struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 	int ret;

+#if defined(CONFIG_MX6)
+	setup_sata();
+#endif
 	uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 			ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
 	uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
@@ -1067,4 +1071,24 @@ U_BOOT_DRIVER(dwc_ahsata_blk) = {
 	.ops		= &dwc_ahsata_blk_ops,
 };

+#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
+struct ahci_ops dwc_ahsata_ahci_ops = {
+	.port_status = dwc_ahsata_port_status,
+	.reset       = dwc_ahsata_bus_reset,
+	.scan        = dwc_ahsata_scan,
+};
+
+static const struct udevice_id dwc_ahsata_ahci_ids[] = {
+	{ .compatible = "fsl,imx6q-ahci" },
+	{ }
+};
+
+U_BOOT_DRIVER(dwc_ahsata_ahci) = {
+	.name     = "dwc_ahsata_ahci",
+	.id       = UCLASS_AHCI,
+	.of_match = dwc_ahsata_ahci_ids,
+	.ops      = &dwc_ahsata_ahci_ops,
+	.probe    = dwc_ahsata_probe,
+};
+#endif
 #endif
--
2.17.1

[U-Boot] [PATCH 09/10] board: tbs2910: Convert sata to ahci driver model

[Soeren Moch]

While at it, also configure 64-bit LBA support.

Signed-off-by: Soeren Moch <smoch@web.de>
---
Cc: Stefano Babic <sbabic@denx.de>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: u-boot at lists.denx.de
---
 board/tbs/tbs2910/tbs2910.c | 4 ----
 configs/tbs2910_defconfig   | 1 +
 include/configs/tbs2910.h   | 1 +
 3 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index 2445efbde2..84c813e29f 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -10,7 +10,6 @@
 #include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
@@ -374,9 +373,6 @@ int board_init(void)
 #ifdef CONFIG_VIDEO_IPUV3
 	setup_display();
 #endif
-#ifdef CONFIG_DWC_AHSATA
-	setup_sata();
-#endif
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 153f61d09d..54e34df6aa 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -4,6 +4,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_TBS2910=y
 CONFIG_CMD_HDMIDETECT=y
+CONFIG_AHCI=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_BOOTDELAY=3
 CONFIG_PRE_CONSOLE_BUFFER=y
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index eff93eff4f..a211b9d611 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -77,6 +77,7 @@
 #define CONFIG_DWC_AHSATA_PORT_ID	0
 #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
 #define CONFIG_LBA48
+#define CONFIG_SYS_64BIT_LBA
 #endif

 /* USB */
--
2.17.1

[U-Boot] [PATCH 10/10] board: tbs2910: Convert mmc to driver model

[Soeren Moch]

So we don't need to duplicate settings from the device tree in the board file.

Signed-off-by: Soeren Moch <smoch@web.de>
---
Cc: Stefano Babic <sbabic@denx.de>
Cc: u-boot at lists.denx.de
---
 board/tbs/tbs2910/tbs2910.c | 108 ------------------------------------
 configs/tbs2910_defconfig   |   1 +
 include/configs/tbs2910.h   |   7 ---
 3 files changed, 1 insertion(+), 115 deletions(-)

diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index 84c813e29f..fb0e773afc 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -30,10 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

@@ -103,110 +99,6 @@ static void setup_iomux_uart(void)
 }

 #ifdef CONFIG_FSL_ESDHC
-static iomux_v3_cfg_t const usdhc2_pads[] = {
-	MX6_PAD_SD2_CLK__SD2_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_CMD__SD2_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT0__SD2_DATA0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__SD2_DATA1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__SD2_DATA2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT3__SD2_DATA3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__SD4_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__SD4_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
-	{USDHC2_BASE_ADDR},
-	{USDHC3_BASE_ADDR},
-	{USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 2)
-#define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC2_BASE_ADDR:
-		ret = !gpio_get_value(USDHC2_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		ret = !gpio_get_value(USDHC3_CD_GPIO);
-		break;
-	case USDHC4_BASE_ADDR:
-		ret = 1; /* eMMC/uSDHC4 is always present */
-		break;
-	}
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	/*
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    SD2
-	 * mmc1                    SD3
-	 * mmc2                    eMMC
-	 */
-	int i, ret;
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-			gpio_request(USDHC2_CD_GPIO, "MMC0_CD");
-			gpio_direction_input(USDHC2_CD_GPIO);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			gpio_request(USDHC3_CD_GPIO, "MMC1_CD");
-			gpio_direction_input(USDHC3_CD_GPIO);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			break;
-		case 2:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-			       "(%d) then supported by the board (%d)\n",
-			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return -EINVAL;
-		}
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		if (ret)
-			return ret;
-	}
-	return 0;
-}
-
 /* set environment device to boot device when booting from SD */
 int board_mmc_get_env_dev(int devno)
 {
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 54e34df6aa..4d755c88c3 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -46,6 +46,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_KEYBOARD=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index a211b9d611..f31cadd951 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -40,13 +40,6 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART1_BASE /* select UART1/UART2 */

-/* Filesystems / image support */
-
-/* MMC */
-#define CONFIG_SYS_FSL_USDHC_NUM	3
-#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
-
 /* Ethernet */
 #define CONFIG_FEC_MXC
 #define CONFIG_FEC_MXC
--
2.17.1

[U-Boot] [PATCH v2 11/23] apalis_imx6: migrate mmc and sata to using driver model

[Soeren Moch]

On 25.02.19 11:39, Soeren Moch wrote:
>
> On 08.02.19 18:12, Marcel Ziswiler wrote:
>> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>>
>> Migrate MMC and SATA to using driver model.
>>
>> While at it also enable SCSI driver model.
>>
>> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> [also reply to v2 of this series to avoid that this gets lost in patchwork]
>
> Hi Marcel,
>
> Thank you for providing this solution to keep SATA working on i.MX6
> under DM_SCSI.
> I also want to use this on a tbs2910 board, there was a long list of
> other boards needing this functionality [1].
>
> Can you implement the UCLASS at a more general place, e.g.
> drivers/ata/dwc_ahsata.c directly, instead of your board file? So this
> functionality could easily be enabled for other boards.
>
> Thank you,
> Soeren
>
> [1] https://lists.denx.de/pipermail/u-boot/2018-November/349368.html
>
>
Since there was no feedback on this so far, I sent a proposal here:
https://lists.denx.de/pipermail/u-boot/2019-March/360521.html

Regards,
Soeren

[U-Boot] [PATCH v2 11/23] apalis_imx6: migrate mmc and sata to using driver model

[Marcel Ziswiler]

Hi Soeren

On Fri, 2019-03-01 at 13:20 +0100, Soeren Moch wrote:
> 
> On 25.02.19 11:39, Soeren Moch wrote:
> > On 08.02.19 18:12, Marcel Ziswiler wrote:
> > > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > > 
> > > Migrate MMC and SATA to using driver model.
> > > 
> > > While at it also enable SCSI driver model.
> > > 
> > > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > [also reply to v2 of this series to avoid that this gets lost in
> > patchwork]
> > 
> > Hi Marcel,
> > 
> > Thank you for providing this solution to keep SATA working on i.MX6
> > under DM_SCSI.
> > I also want to use this on a tbs2910 board, there was a long list
> > of
> > other boards needing this functionality [1].
> > 
> > Can you implement the UCLASS at a more general place, e.g.
> > drivers/ata/dwc_ahsata.c directly, instead of your board file? So
> > this
> > functionality could easily be enabled for other boards.
> > 
> > Thank you,
> > Soeren
> > 
> > [1] 
> > https://lists.denx.de/pipermail/u-boot/2018-November/349368.html
> > 
> > 
> Since there was no feedback on this so far, I sent a proposal here:
> https://lists.denx.de/pipermail/u-boot/2019-March/360521.html

Yeah, sorry. I got trapped at the Embedded World in Nürnberg and your
message disappeared in the spew of emails I just now managed to get on
top off again. I will give your proposal a try and will re-work my
patch set accordingly. Thanks for cleaning up this mess!

> Regards,
> Soeren

Cheers

Marcel

[U-Boot] [PATCH v4 22/22] pcm052: bk4: Add board_phy_config() for BK4 to setup ksz8081 phy

[Joe Hershberger]

On Wed, Feb 13, 2019 at 3:51 PM Lukasz Majewski <lukma@denx.de> wrote:
>
> BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY devices.
>
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  board/phytec/pcm052/pcm052.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
> index 1e443a5850..c30df5df9d 100644
> --- a/board/phytec/pcm052/pcm052.c
> +++ b/board/phytec/pcm052/pcm052.c
> @@ -15,6 +15,7 @@
>  #include <asm/arch/clock.h>
>  #include <led.h>
>  #include <environment.h>
> +#include <miiphy.h>
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -382,6 +383,21 @@ int board_late_init(void)
>
>         return 0;
>  }
> +
> +/**
> + * KSZ8081
> + */
> +#define MII_KSZ8081_REFERENCE_CLOCK_SELECT     0x1f
> +#define RMII_50MHz_CLOCK       0x8180
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> +       /* Set 50 MHz reference clock */
> +       phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
> +                 RMII_50MHz_CLOCK);

Is it reasonable to use the clock infrastructure? Not necessarily
instead of fixing this now, but would be a good direction.

> +
> +       return genphy_config(phydev);
> +}
>  #endif /* CONFIG_TARGET_BK4R1 */
>
>  int checkboard(void)
> --
> 2.11.0
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v4 22/22] pcm052: bk4: Add board_phy_config() for BK4 to setup ksz8081 phy

[Lukasz Majewski]

Hi Joe,

> On Wed, Feb 13, 2019 at 3:51 PM Lukasz Majewski <lukma@denx.de> wrote:
> >
> > BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY
> > devices.
> >
> > Signed-off-by: Lukasz Majewski <lukma@denx.de>  
> 
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
> 
> > ---
> >
> > Changes in v4: None
> > Changes in v3: None
> > Changes in v2: None
> >
> >  board/phytec/pcm052/pcm052.c | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/board/phytec/pcm052/pcm052.c
> > b/board/phytec/pcm052/pcm052.c index 1e443a5850..c30df5df9d 100644
> > --- a/board/phytec/pcm052/pcm052.c
> > +++ b/board/phytec/pcm052/pcm052.c
> > @@ -15,6 +15,7 @@
> >  #include <asm/arch/clock.h>
> >  #include <led.h>
> >  #include <environment.h>
> > +#include <miiphy.h>
> >
> >  DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -382,6 +383,21 @@ int board_late_init(void)
> >
> >         return 0;
> >  }
> > +
> > +/**
> > + * KSZ8081
> > + */
> > +#define MII_KSZ8081_REFERENCE_CLOCK_SELECT     0x1f
> > +#define RMII_50MHz_CLOCK       0x8180
> > +
> > +int board_phy_config(struct phy_device *phydev)
> > +{
> > +       /* Set 50 MHz reference clock */
> > +       phy_write(phydev, MDIO_DEVAD_NONE,
> > MII_KSZ8081_REFERENCE_CLOCK_SELECT,
> > +                 RMII_50MHz_CLOCK);  
> 
> Is it reasonable to use the clock infrastructure?

Yes, I do have in the back of my head that this shall be done via clock
API. However, it is a long way to and I would like first to have the
DM/DTS cleanup patches in main line.

> Not necessarily
> instead of fixing this now, but would be a good direction.
> 
> > +
> > +       return genphy_config(phydev);
> > +}
> >  #endif /* CONFIG_TARGET_BK4R1 */
> >
> >  int checkboard(void)
> > --
> > 2.11.0
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > https://lists.denx.de/listinfo/u-boot  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190304/fa20d279/attachment.sig>

[U-Boot] [PATCH RESEND 01/10] pinctrl: imx8: add i.MX8QM compatible

[Peng Fan]

Add i.MX8QM compatible

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/pinctrl/nxp/pinctrl-imx8.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c
index 0738da0ebe..c1b0ca438a 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8.c
@@ -25,6 +25,7 @@ static int imx8_pinctrl_probe(struct udevice *dev)
 
 static const struct udevice_id imx8_pinctrl_match[] = {
 	{ .compatible = "fsl,imx8qxp-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info },
+	{ .compatible = "fsl,imx8qm-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info },
 	{ /* sentinel */ }
 };
 
-- 
2.16.4

[U-Boot] [PATCH RESEND 02/10] dt-bindings: pinctrl: add i.MX8QM pads definition

[Peng Fan]

Add i.MX8QM pads definition

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/dt-bindings/pinctrl/pads-imx8qm.h | 961 ++++++++++++++++++++++++++++++
 1 file changed, 961 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/pads-imx8qm.h

diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h
new file mode 100644
index 0000000000..e980fd55ed
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pads-imx8qm.h
@@ -0,0 +1,961 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef SC_PADS_H
+#define SC_PADS_H
+
+#define SC_P_SIM0_CLK                            0	/* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
+#define SC_P_SIM0_RST                            1	/* DMA.SIM0.RST, LSIO.GPIO0.IO01 */
+#define SC_P_SIM0_IO                             2	/* DMA.SIM0.IO, LSIO.GPIO0.IO02 */
+#define SC_P_SIM0_PD                             3	/* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
+#define SC_P_SIM0_POWER_EN                       4	/* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
+#define SC_P_SIM0_GPIO0_00                       5	/* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM           6	/*  */
+#define SC_P_M40_I2C0_SCL                        7	/* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
+#define SC_P_M40_I2C0_SDA                        8	/* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
+#define SC_P_M40_GPIO0_00                        9	/* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
+#define SC_P_M40_GPIO0_01                        10	/* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
+#define SC_P_M41_I2C0_SCL                        11	/* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
+#define SC_P_M41_I2C0_SDA                        12	/* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
+#define SC_P_M41_GPIO0_00                        13	/* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
+#define SC_P_M41_GPIO0_01                        14	/* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
+#define SC_P_GPT0_CLK                            15	/* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
+#define SC_P_GPT0_CAPTURE                        16	/* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
+#define SC_P_GPT0_COMPARE                        17	/* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
+#define SC_P_GPT1_CLK                            18	/* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
+#define SC_P_GPT1_CAPTURE                        19	/* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
+#define SC_P_GPT1_COMPARE                        20	/* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
+#define SC_P_UART0_RX                            21	/* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
+#define SC_P_UART0_TX                            22	/* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
+#define SC_P_UART0_RTS_B                         23	/* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
+#define SC_P_UART0_CTS_B                         24	/* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
+#define SC_P_UART1_TX                            25	/* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
+#define SC_P_UART1_RX                            26	/* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
+#define SC_P_UART1_RTS_B                         27	/* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
+#define SC_P_UART1_CTS_B                         28	/* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        29	/*  */
+#define SC_P_SCU_PMIC_MEMC_ON                    30	/* SCU.GPIO0.IOXX_PMIC_MEMC_ON */
+#define SC_P_SCU_WDOG_OUT                        31	/* SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SDA                        32	/* SCU.PMIC_I2C.SDA */
+#define SC_P_PMIC_I2C_SCL                        33	/* SCU.PMIC_I2C.SCL */
+#define SC_P_PMIC_EARLY_WARNING                  34	/* SCU.PMIC_EARLY_WARNING */
+#define SC_P_PMIC_INT_B                          35	/* SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00                        36	/* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
+#define SC_P_SCU_GPIO0_01                        37	/* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
+#define SC_P_SCU_GPIO0_02                        38	/* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
+#define SC_P_SCU_GPIO0_03                        39	/* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
+#define SC_P_SCU_GPIO0_04                        40	/* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
+#define SC_P_SCU_GPIO0_05                        41	/* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
+#define SC_P_SCU_GPIO0_06                        42	/* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
+#define SC_P_SCU_GPIO0_07                        43	/* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
+#define SC_P_SCU_BOOT_MODE0                      44	/* SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1                      45	/* SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2                      46	/* SCU.DSC.BOOT_MODE2 */
+#define SC_P_SCU_BOOT_MODE3                      47	/* SCU.DSC.BOOT_MODE3 */
+#define SC_P_SCU_BOOT_MODE4                      48	/* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
+#define SC_P_SCU_BOOT_MODE5                      49	/* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
+#define SC_P_LVDS0_GPIO00                        50	/* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
+#define SC_P_LVDS0_GPIO01                        51	/* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
+#define SC_P_LVDS0_I2C0_SCL                      52	/* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
+#define SC_P_LVDS0_I2C0_SDA                      53	/* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
+#define SC_P_LVDS0_I2C1_SCL                      54	/* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
+#define SC_P_LVDS0_I2C1_SDA                      55	/* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
+#define SC_P_LVDS1_GPIO00                        56	/* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
+#define SC_P_LVDS1_GPIO01                        57	/* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
+#define SC_P_LVDS1_I2C0_SCL                      58	/* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
+#define SC_P_LVDS1_I2C0_SDA                      59	/* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
+#define SC_P_LVDS1_I2C1_SCL                      60	/* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
+#define SC_P_LVDS1_I2C1_SDA                      61	/* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO      62	/*  */
+#define SC_P_MIPI_DSI0_I2C0_SCL                  63	/* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
+#define SC_P_MIPI_DSI0_I2C0_SDA                  64	/* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
+#define SC_P_MIPI_DSI0_GPIO0_00                  65	/* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
+#define SC_P_MIPI_DSI0_GPIO0_01                  66	/* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
+#define SC_P_MIPI_DSI1_I2C0_SCL                  67	/* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
+#define SC_P_MIPI_DSI1_I2C0_SDA                  68	/* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
+#define SC_P_MIPI_DSI1_GPIO0_00                  69	/* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
+#define SC_P_MIPI_DSI1_GPIO0_01                  70	/* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO   71	/*  */
+#define SC_P_MIPI_CSI0_MCLK_OUT                  72	/* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
+#define SC_P_MIPI_CSI0_I2C0_SCL                  73	/* MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_CSI0_I2C0_SDA                  74	/* MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_CSI0_GPIO0_00                  75	/* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_CSI0_GPIO0_01                  76	/* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_CSI1_MCLK_OUT                  77	/* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_CSI1_GPIO0_00                  78	/* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_CSI1_GPIO0_01                  79	/* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_CSI1_I2C0_SCL                  80	/* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
+#define SC_P_MIPI_CSI1_I2C0_SDA                  81	/* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
+#define SC_P_HDMI_TX0_TS_SCL                     82	/* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
+#define SC_P_HDMI_TX0_TS_SDA                     83	/* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
+#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO          84	/*  */
+#define SC_P_ESAI1_FSR                           85	/* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
+#define SC_P_ESAI1_FST                           86	/* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
+#define SC_P_ESAI1_SCKR                          87	/* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
+#define SC_P_ESAI1_SCKT                          88	/* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
+#define SC_P_ESAI1_TX0                           89	/* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
+#define SC_P_ESAI1_TX1                           90	/* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
+#define SC_P_ESAI1_TX2_RX3                       91	/* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
+#define SC_P_ESAI1_TX3_RX2                       92	/* AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
+#define SC_P_ESAI1_TX4_RX1                       93	/* AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
+#define SC_P_ESAI1_TX5_RX0                       94	/* AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
+#define SC_P_SPDIF0_RX                           95	/* AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
+#define SC_P_SPDIF0_TX                           96	/* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
+#define SC_P_SPDIF0_EXT_CLK                      97	/* AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
+#define SC_P_SPI3_SCK                            98	/* DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
+#define SC_P_SPI3_SDO                            99	/* DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
+#define SC_P_SPI3_SDI                            100	/* DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
+#define SC_P_SPI3_CS0                            101	/* DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
+#define SC_P_SPI3_CS1                            102	/* DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       103	/*  */
+#define SC_P_ESAI0_FSR                           104	/* AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
+#define SC_P_ESAI0_FST                           105	/* AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
+#define SC_P_ESAI0_SCKR                          106	/* AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
+#define SC_P_ESAI0_SCKT                          107	/* AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
+#define SC_P_ESAI0_TX0                           108	/* AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
+#define SC_P_ESAI0_TX1                           109	/* AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
+#define SC_P_ESAI0_TX2_RX3                       110	/* AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
+#define SC_P_ESAI0_TX3_RX2                       111	/* AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
+#define SC_P_ESAI0_TX4_RX1                       112	/* AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
+#define SC_P_ESAI0_TX5_RX0                       113	/* AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
+#define SC_P_MCLK_IN0                            114	/* AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
+#define SC_P_MCLK_OUT0                           115	/* AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC       116	/*  */
+#define SC_P_SPI0_SCK                            117	/* DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
+#define SC_P_SPI0_SDO                            118	/* DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
+#define SC_P_SPI0_SDI                            119	/* DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
+#define SC_P_SPI0_CS0                            120	/* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
+#define SC_P_SPI0_CS1                            121	/* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
+#define SC_P_SPI2_SCK                            122	/* DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
+#define SC_P_SPI2_SDO                            123	/* DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
+#define SC_P_SPI2_SDI                            124	/* DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
+#define SC_P_SPI2_CS0                            125	/* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
+#define SC_P_SPI2_CS1                            126	/* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
+#define SC_P_SAI1_RXC                            127	/* AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
+#define SC_P_SAI1_RXD                            128	/* AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
+#define SC_P_SAI1_RXFS                           129	/* AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
+#define SC_P_SAI1_TXC                            130	/* AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
+#define SC_P_SAI1_TXD                            131	/* AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
+#define SC_P_SAI1_TXFS                           132	/* AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       133	/*  */
+#define SC_P_ADC_IN7                             134	/* DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
+#define SC_P_ADC_IN6                             135	/* DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
+#define SC_P_ADC_IN5                             136	/* DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
+#define SC_P_ADC_IN4                             137	/* DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
+#define SC_P_ADC_IN3                             138	/* DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
+#define SC_P_ADC_IN2                             139	/* DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
+#define SC_P_ADC_IN1                             140	/* DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
+#define SC_P_ADC_IN0                             141	/* DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
+#define SC_P_MLB_SIG                             142	/* CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
+#define SC_P_MLB_CLK                             143	/* CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
+#define SC_P_MLB_DATA                            144	/* CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT       145	/*  */
+#define SC_P_FLEXCAN0_RX                         146	/* DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
+#define SC_P_FLEXCAN0_TX                         147	/* DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
+#define SC_P_FLEXCAN1_RX                         148	/* DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
+#define SC_P_FLEXCAN1_TX                         149	/* DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
+#define SC_P_FLEXCAN2_RX                         150	/* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
+#define SC_P_FLEXCAN2_TX                         151	/* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR       152	/*  */
+#define SC_P_USB_SS3_TC0                         153	/* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1                         154	/* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2                         155	/* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3                         156	/* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            157	/*  */
+#define SC_P_USDHC1_RESET_B                      158	/* CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
+#define SC_P_USDHC1_VSELECT                      159	/* CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
+#define SC_P_USDHC2_RESET_B                      160	/* CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
+#define SC_P_USDHC2_VSELECT                      161	/* CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
+#define SC_P_USDHC2_WP                           162	/* CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
+#define SC_P_USDHC2_CD_B                         163	/* CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       164	/*  */
+#define SC_P_ENET0_MDIO                          165	/* CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
+#define SC_P_ENET0_MDC                           166	/* CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
+#define SC_P_ENET0_REFCLK_125M_25M               167	/* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
+#define SC_P_ENET1_REFCLK_125M_25M               168	/* CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
+#define SC_P_ENET1_MDIO                          169	/* CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
+#define SC_P_ENET1_MDC                           170	/* CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        171	/*  */
+#define SC_P_QSPI1A_SS0_B                        172	/* LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
+#define SC_P_QSPI1A_SS1_B                        173	/* LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
+#define SC_P_QSPI1A_SCLK                         174	/* LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
+#define SC_P_QSPI1A_DQS                          175	/* LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_QSPI1A_DATA3                        176	/* LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
+#define SC_P_QSPI1A_DATA2                        177	/* LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
+#define SC_P_QSPI1A_DATA1                        178	/* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
+#define SC_P_QSPI1A_DATA0                        179	/* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1         180	/*  */
+#define SC_P_QSPI0A_DATA0                        181	/* LSIO.QSPI0A.DATA0 */
+#define SC_P_QSPI0A_DATA1                        182	/* LSIO.QSPI0A.DATA1 */
+#define SC_P_QSPI0A_DATA2                        183	/* LSIO.QSPI0A.DATA2 */
+#define SC_P_QSPI0A_DATA3                        184	/* LSIO.QSPI0A.DATA3 */
+#define SC_P_QSPI0A_DQS                          185	/* LSIO.QSPI0A.DQS */
+#define SC_P_QSPI0A_SS0_B                        186	/* LSIO.QSPI0A.SS0_B */
+#define SC_P_QSPI0A_SS1_B                        187	/* LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
+#define SC_P_QSPI0A_SCLK                         188	/* LSIO.QSPI0A.SCLK */
+#define SC_P_QSPI0B_SCLK                         189	/* LSIO.QSPI0B.SCLK */
+#define SC_P_QSPI0B_DATA0                        190	/* LSIO.QSPI0B.DATA0 */
+#define SC_P_QSPI0B_DATA1                        191	/* LSIO.QSPI0B.DATA1 */
+#define SC_P_QSPI0B_DATA2                        192	/* LSIO.QSPI0B.DATA2 */
+#define SC_P_QSPI0B_DATA3                        193	/* LSIO.QSPI0B.DATA3 */
+#define SC_P_QSPI0B_DQS                          194	/* LSIO.QSPI0B.DQS */
+#define SC_P_QSPI0B_SS0_B                        195	/* LSIO.QSPI0B.SS0_B */
+#define SC_P_QSPI0B_SS1_B                        196	/* LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0         197	/*  */
+#define SC_P_PCIE_CTRL0_CLKREQ_B                 198	/* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
+#define SC_P_PCIE_CTRL0_WAKE_B                   199	/* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
+#define SC_P_PCIE_CTRL0_PERST_B                  200	/* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
+#define SC_P_PCIE_CTRL1_CLKREQ_B                 201	/* HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
+#define SC_P_PCIE_CTRL1_WAKE_B                   202	/* HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
+#define SC_P_PCIE_CTRL1_PERST_B                  203	/* HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       204	/*  */
+#define SC_P_USB_HSIC0_DATA                      205	/* CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
+#define SC_P_USB_HSIC0_STROBE                    206	/* CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
+#define SC_P_CALIBRATION_0_HSIC                  207	/*  */
+#define SC_P_CALIBRATION_1_HSIC                  208	/*  */
+#define SC_P_EMMC0_CLK                           209	/* CONN.EMMC0.CLK, CONN.NAND.READY_B */
+#define SC_P_EMMC0_CMD                           210	/* CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
+#define SC_P_EMMC0_DATA0                         211	/* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
+#define SC_P_EMMC0_DATA1                         212	/* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
+#define SC_P_EMMC0_DATA2                         213	/* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
+#define SC_P_EMMC0_DATA3                         214	/* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
+#define SC_P_EMMC0_DATA4                         215	/* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
+#define SC_P_EMMC0_DATA5                         216	/* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
+#define SC_P_EMMC0_DATA6                         217	/* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
+#define SC_P_EMMC0_DATA7                         218	/* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
+#define SC_P_EMMC0_STROBE                        219	/* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
+#define SC_P_EMMC0_RESET_B                       220	/* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX        221	/*  */
+#define SC_P_USDHC1_CLK                          222	/* CONN.USDHC1.CLK, AUD.MQS.R */
+#define SC_P_USDHC1_CMD                          223	/* CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
+#define SC_P_USDHC1_DATA0                        224	/* CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
+#define SC_P_USDHC1_DATA1                        225	/* CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
+#define SC_P_CTL_NAND_RE_P_N                     226	/*  */
+#define SC_P_USDHC1_DATA2                        227	/* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
+#define SC_P_USDHC1_DATA3                        228	/* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
+#define SC_P_CTL_NAND_DQS_P_N                    229	/*  */
+#define SC_P_USDHC1_DATA4                        230	/* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
+#define SC_P_USDHC1_DATA5                        231	/* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
+#define SC_P_USDHC1_DATA6                        232	/* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
+#define SC_P_USDHC1_DATA7                        233	/* CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
+#define SC_P_USDHC1_STROBE                       234	/* CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2         235	/*  */
+#define SC_P_USDHC2_CLK                          236	/* CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
+#define SC_P_USDHC2_CMD                          237	/* CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
+#define SC_P_USDHC2_DATA0                        238	/* CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
+#define SC_P_USDHC2_DATA1                        239	/* CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
+#define SC_P_USDHC2_DATA2                        240	/* CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
+#define SC_P_USDHC2_DATA3                        241	/* CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         242	/*  */
+#define SC_P_ENET0_RGMII_TXC                     243	/* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
+#define SC_P_ENET0_RGMII_TX_CTL                  244	/* CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
+#define SC_P_ENET0_RGMII_TXD0                    245	/* CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
+#define SC_P_ENET0_RGMII_TXD1                    246	/* CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
+#define SC_P_ENET0_RGMII_TXD2                    247	/* CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
+#define SC_P_ENET0_RGMII_TXD3                    248	/* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
+#define SC_P_ENET0_RGMII_RXC                     249	/* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
+#define SC_P_ENET0_RGMII_RX_CTL                  250	/* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
+#define SC_P_ENET0_RGMII_RXD0                    251	/* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
+#define SC_P_ENET0_RGMII_RXD1                    252	/* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
+#define SC_P_ENET0_RGMII_RXD2                    253	/* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
+#define SC_P_ENET0_RGMII_RXD3                    254	/* CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB    255	/*  */
+#define SC_P_ENET1_RGMII_TXC                     256	/* CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
+#define SC_P_ENET1_RGMII_TX_CTL                  257	/* CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
+#define SC_P_ENET1_RGMII_TXD0                    258	/* CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
+#define SC_P_ENET1_RGMII_TXD1                    259	/* CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
+#define SC_P_ENET1_RGMII_TXD2                    260	/* CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
+#define SC_P_ENET1_RGMII_TXD3                    261	/* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
+#define SC_P_ENET1_RGMII_RXC                     262	/* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
+#define SC_P_ENET1_RGMII_RX_CTL                  263	/* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
+#define SC_P_ENET1_RGMII_RXD0                    264	/* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
+#define SC_P_ENET1_RGMII_RXD1                    265	/* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
+#define SC_P_ENET1_RGMII_RXD2                    266	/* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
+#define SC_P_ENET1_RGMII_RXD3                    267	/* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA    268	/*  */
+/*@}*/
+
+/*!
+ * @name Pad Mux Definitions
+ * format: name padid padmux
+ */
+/*@{*/
+#define SC_P_SIM0_CLK_DMA_SIM0_CLK                              SC_P_SIM0_CLK                      0
+#define SC_P_SIM0_CLK_LSIO_GPIO0_IO00                           SC_P_SIM0_CLK                      3
+#define SC_P_SIM0_RST_DMA_SIM0_RST                              SC_P_SIM0_RST                      0
+#define SC_P_SIM0_RST_LSIO_GPIO0_IO01                           SC_P_SIM0_RST                      3
+#define SC_P_SIM0_IO_DMA_SIM0_IO                                SC_P_SIM0_IO                       0
+#define SC_P_SIM0_IO_LSIO_GPIO0_IO02                            SC_P_SIM0_IO                       3
+#define SC_P_SIM0_PD_DMA_SIM0_PD                                SC_P_SIM0_PD                       0
+#define SC_P_SIM0_PD_DMA_I2C3_SCL                               SC_P_SIM0_PD                       1
+#define SC_P_SIM0_PD_LSIO_GPIO0_IO03                            SC_P_SIM0_PD                       3
+#define SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN                    SC_P_SIM0_POWER_EN                 0
+#define SC_P_SIM0_POWER_EN_DMA_I2C3_SDA                         SC_P_SIM0_POWER_EN                 1
+#define SC_P_SIM0_POWER_EN_LSIO_GPIO0_IO04                      SC_P_SIM0_POWER_EN                 3
+#define SC_P_SIM0_GPIO0_00_DMA_SIM0_POWER_EN                    SC_P_SIM0_GPIO0_00                 0
+#define SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05                      SC_P_SIM0_GPIO0_00                 3
+#define SC_P_M40_I2C0_SCL_M40_I2C0_SCL                          SC_P_M40_I2C0_SCL                  0
+#define SC_P_M40_I2C0_SCL_M40_UART0_RX                          SC_P_M40_I2C0_SCL                  1
+#define SC_P_M40_I2C0_SCL_M40_GPIO0_IO02                        SC_P_M40_I2C0_SCL                  2
+#define SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06                       SC_P_M40_I2C0_SCL                  3
+#define SC_P_M40_I2C0_SDA_M40_I2C0_SDA                          SC_P_M40_I2C0_SDA                  0
+#define SC_P_M40_I2C0_SDA_M40_UART0_TX                          SC_P_M40_I2C0_SDA                  1
+#define SC_P_M40_I2C0_SDA_M40_GPIO0_IO03                        SC_P_M40_I2C0_SDA                  2
+#define SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07                       SC_P_M40_I2C0_SDA                  3
+#define SC_P_M40_GPIO0_00_M40_GPIO0_IO00                        SC_P_M40_GPIO0_00                  0
+#define SC_P_M40_GPIO0_00_M40_TPM0_CH0                          SC_P_M40_GPIO0_00                  1
+#define SC_P_M40_GPIO0_00_DMA_UART4_RX                          SC_P_M40_GPIO0_00                  2
+#define SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08                       SC_P_M40_GPIO0_00                  3
+#define SC_P_M40_GPIO0_01_M40_GPIO0_IO01                        SC_P_M40_GPIO0_01                  0
+#define SC_P_M40_GPIO0_01_M40_TPM0_CH1                          SC_P_M40_GPIO0_01                  1
+#define SC_P_M40_GPIO0_01_DMA_UART4_TX                          SC_P_M40_GPIO0_01                  2
+#define SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09                       SC_P_M40_GPIO0_01                  3
+#define SC_P_M41_I2C0_SCL_M41_I2C0_SCL                          SC_P_M41_I2C0_SCL                  0
+#define SC_P_M41_I2C0_SCL_M41_UART0_RX                          SC_P_M41_I2C0_SCL                  1
+#define SC_P_M41_I2C0_SCL_M41_GPIO0_IO02                        SC_P_M41_I2C0_SCL                  2
+#define SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10                       SC_P_M41_I2C0_SCL                  3
+#define SC_P_M41_I2C0_SDA_M41_I2C0_SDA                          SC_P_M41_I2C0_SDA                  0
+#define SC_P_M41_I2C0_SDA_M41_UART0_TX                          SC_P_M41_I2C0_SDA                  1
+#define SC_P_M41_I2C0_SDA_M41_GPIO0_IO03                        SC_P_M41_I2C0_SDA                  2
+#define SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11                       SC_P_M41_I2C0_SDA                  3
+#define SC_P_M41_GPIO0_00_M41_GPIO0_IO00                        SC_P_M41_GPIO0_00                  0
+#define SC_P_M41_GPIO0_00_M41_TPM0_CH0                          SC_P_M41_GPIO0_00                  1
+#define SC_P_M41_GPIO0_00_DMA_UART3_RX                          SC_P_M41_GPIO0_00                  2
+#define SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12                       SC_P_M41_GPIO0_00                  3
+#define SC_P_M41_GPIO0_01_M41_GPIO0_IO01                        SC_P_M41_GPIO0_01                  0
+#define SC_P_M41_GPIO0_01_M41_TPM0_CH1                          SC_P_M41_GPIO0_01                  1
+#define SC_P_M41_GPIO0_01_DMA_UART3_TX                          SC_P_M41_GPIO0_01                  2
+#define SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13                       SC_P_M41_GPIO0_01                  3
+#define SC_P_GPT0_CLK_LSIO_GPT0_CLK                             SC_P_GPT0_CLK                      0
+#define SC_P_GPT0_CLK_DMA_I2C1_SCL                              SC_P_GPT0_CLK                      1
+#define SC_P_GPT0_CLK_LSIO_KPP0_COL4                            SC_P_GPT0_CLK                      2
+#define SC_P_GPT0_CLK_LSIO_GPIO0_IO14                           SC_P_GPT0_CLK                      3
+#define SC_P_GPT0_CAPTURE_LSIO_GPT0_CAPTURE                     SC_P_GPT0_CAPTURE                  0
+#define SC_P_GPT0_CAPTURE_DMA_I2C1_SDA                          SC_P_GPT0_CAPTURE                  1
+#define SC_P_GPT0_CAPTURE_LSIO_KPP0_COL5                        SC_P_GPT0_CAPTURE                  2
+#define SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15                       SC_P_GPT0_CAPTURE                  3
+#define SC_P_GPT0_COMPARE_LSIO_GPT0_COMPARE                     SC_P_GPT0_COMPARE                  0
+#define SC_P_GPT0_COMPARE_LSIO_PWM3_OUT                         SC_P_GPT0_COMPARE                  1
+#define SC_P_GPT0_COMPARE_LSIO_KPP0_COL6                        SC_P_GPT0_COMPARE                  2
+#define SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16                       SC_P_GPT0_COMPARE                  3
+#define SC_P_GPT1_CLK_LSIO_GPT1_CLK                             SC_P_GPT1_CLK                      0
+#define SC_P_GPT1_CLK_DMA_I2C2_SCL                              SC_P_GPT1_CLK                      1
+#define SC_P_GPT1_CLK_LSIO_KPP0_COL7                            SC_P_GPT1_CLK                      2
+#define SC_P_GPT1_CLK_LSIO_GPIO0_IO17                           SC_P_GPT1_CLK                      3
+#define SC_P_GPT1_CAPTURE_LSIO_GPT1_CAPTURE                     SC_P_GPT1_CAPTURE                  0
+#define SC_P_GPT1_CAPTURE_DMA_I2C2_SDA                          SC_P_GPT1_CAPTURE                  1
+#define SC_P_GPT1_CAPTURE_LSIO_KPP0_ROW4                        SC_P_GPT1_CAPTURE                  2
+#define SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18                       SC_P_GPT1_CAPTURE                  3
+#define SC_P_GPT1_COMPARE_LSIO_GPT1_COMPARE                     SC_P_GPT1_COMPARE                  0
+#define SC_P_GPT1_COMPARE_LSIO_PWM2_OUT                         SC_P_GPT1_COMPARE                  1
+#define SC_P_GPT1_COMPARE_LSIO_KPP0_ROW5                        SC_P_GPT1_COMPARE                  2
+#define SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19                       SC_P_GPT1_COMPARE                  3
+#define SC_P_UART0_RX_DMA_UART0_RX                              SC_P_UART0_RX                      0
+#define SC_P_UART0_RX_SCU_UART0_RX                              SC_P_UART0_RX                      1
+#define SC_P_UART0_RX_LSIO_GPIO0_IO20                           SC_P_UART0_RX                      3
+#define SC_P_UART0_TX_DMA_UART0_TX                              SC_P_UART0_TX                      0
+#define SC_P_UART0_TX_SCU_UART0_TX                              SC_P_UART0_TX                      1
+#define SC_P_UART0_TX_LSIO_GPIO0_IO21                           SC_P_UART0_TX                      3
+#define SC_P_UART0_RTS_B_DMA_UART0_RTS_B                        SC_P_UART0_RTS_B                   0
+#define SC_P_UART0_RTS_B_LSIO_PWM0_OUT                          SC_P_UART0_RTS_B                   1
+#define SC_P_UART0_RTS_B_DMA_UART2_RX                           SC_P_UART0_RTS_B                   2
+#define SC_P_UART0_RTS_B_LSIO_GPIO0_IO22                        SC_P_UART0_RTS_B                   3
+#define SC_P_UART0_CTS_B_DMA_UART0_CTS_B                        SC_P_UART0_CTS_B                   0
+#define SC_P_UART0_CTS_B_LSIO_PWM1_OUT                          SC_P_UART0_CTS_B                   1
+#define SC_P_UART0_CTS_B_DMA_UART2_TX                           SC_P_UART0_CTS_B                   2
+#define SC_P_UART0_CTS_B_LSIO_GPIO0_IO23                        SC_P_UART0_CTS_B                   3
+#define SC_P_UART1_TX_DMA_UART1_TX                              SC_P_UART1_TX                      0
+#define SC_P_UART1_TX_DMA_SPI3_SCK                              SC_P_UART1_TX                      1
+#define SC_P_UART1_TX_LSIO_GPIO0_IO24                           SC_P_UART1_TX                      3
+#define SC_P_UART1_RX_DMA_UART1_RX                              SC_P_UART1_RX                      0
+#define SC_P_UART1_RX_DMA_SPI3_SDO                              SC_P_UART1_RX                      1
+#define SC_P_UART1_RX_LSIO_GPIO0_IO25                           SC_P_UART1_RX                      3
+#define SC_P_UART1_RTS_B_DMA_UART1_RTS_B                        SC_P_UART1_RTS_B                   0
+#define SC_P_UART1_RTS_B_DMA_SPI3_SDI                           SC_P_UART1_RTS_B                   1
+#define SC_P_UART1_RTS_B_DMA_UART1_CTS_B                        SC_P_UART1_RTS_B                   2
+#define SC_P_UART1_RTS_B_LSIO_GPIO0_IO26                        SC_P_UART1_RTS_B                   3
+#define SC_P_UART1_CTS_B_DMA_UART1_CTS_B                        SC_P_UART1_CTS_B                   0
+#define SC_P_UART1_CTS_B_DMA_SPI3_CS0                           SC_P_UART1_CTS_B                   1
+#define SC_P_UART1_CTS_B_DMA_UART1_RTS_B                        SC_P_UART1_CTS_B                   2
+#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO27                        SC_P_UART1_CTS_B                   3
+#define SC_P_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON       SC_P_SCU_PMIC_MEMC_ON              0
+#define SC_P_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT                    SC_P_SCU_WDOG_OUT                  0
+#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA                      SC_P_PMIC_I2C_SDA                  0
+#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL                      SC_P_PMIC_I2C_SCL                  0
+#define SC_P_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING          SC_P_PMIC_EARLY_WARNING            0
+#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B                      SC_P_PMIC_INT_B                    0
+#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00                        SC_P_SCU_GPIO0_00                  0
+#define SC_P_SCU_GPIO0_00_SCU_UART0_RX                          SC_P_SCU_GPIO0_00                  1
+#define SC_P_SCU_GPIO0_00_LSIO_GPIO0_IO28                       SC_P_SCU_GPIO0_00                  3
+#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01                        SC_P_SCU_GPIO0_01                  0
+#define SC_P_SCU_GPIO0_01_SCU_UART0_TX                          SC_P_SCU_GPIO0_01                  1
+#define SC_P_SCU_GPIO0_01_LSIO_GPIO0_IO29                       SC_P_SCU_GPIO0_01                  3
+#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IO02                        SC_P_SCU_GPIO0_02                  0
+#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON           SC_P_SCU_GPIO0_02                  1
+#define SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30                       SC_P_SCU_GPIO0_02                  3
+#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IO03                        SC_P_SCU_GPIO0_03                  0
+#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON           SC_P_SCU_GPIO0_03                  1
+#define SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31                       SC_P_SCU_GPIO0_03                  3
+#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IO04                        SC_P_SCU_GPIO0_04                  0
+#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON            SC_P_SCU_GPIO0_04                  1
+#define SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00                       SC_P_SCU_GPIO0_04                  3
+#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IO05                        SC_P_SCU_GPIO0_05                  0
+#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON            SC_P_SCU_GPIO0_05                  1
+#define SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01                       SC_P_SCU_GPIO0_05                  3
+#define SC_P_SCU_GPIO0_06_SCU_GPIO0_IO06                        SC_P_SCU_GPIO0_06                  0
+#define SC_P_SCU_GPIO0_06_SCU_TPM0_CH0                          SC_P_SCU_GPIO0_06                  1
+#define SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02                       SC_P_SCU_GPIO0_06                  3
+#define SC_P_SCU_GPIO0_07_SCU_GPIO0_IO07                        SC_P_SCU_GPIO0_07                  0
+#define SC_P_SCU_GPIO0_07_SCU_TPM0_CH1                          SC_P_SCU_GPIO0_07                  1
+#define SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K          SC_P_SCU_GPIO0_07                  2
+#define SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03                       SC_P_SCU_GPIO0_07                  3
+#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0                  SC_P_SCU_BOOT_MODE0                0
+#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1                  SC_P_SCU_BOOT_MODE1                0
+#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2                  SC_P_SCU_BOOT_MODE2                0
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3                  SC_P_SCU_BOOT_MODE3                0
+#define SC_P_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4                  SC_P_SCU_BOOT_MODE4                0
+#define SC_P_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL                    SC_P_SCU_BOOT_MODE4                1
+#define SC_P_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5                  SC_P_SCU_BOOT_MODE5                0
+#define SC_P_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA                    SC_P_SCU_BOOT_MODE5                1
+#define SC_P_LVDS0_GPIO00_LVDS0_GPIO0_IO00                      SC_P_LVDS0_GPIO00                  0
+#define SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT                        SC_P_LVDS0_GPIO00                  1
+#define SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04                       SC_P_LVDS0_GPIO00                  3
+#define SC_P_LVDS0_GPIO01_LVDS0_GPIO0_IO01                      SC_P_LVDS0_GPIO01                  0
+#define SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05                       SC_P_LVDS0_GPIO01                  3
+#define SC_P_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL                      SC_P_LVDS0_I2C0_SCL                0
+#define SC_P_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02                    SC_P_LVDS0_I2C0_SCL                1
+#define SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06                     SC_P_LVDS0_I2C0_SCL                3
+#define SC_P_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA                      SC_P_LVDS0_I2C0_SDA                0
+#define SC_P_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03                    SC_P_LVDS0_I2C0_SDA                1
+#define SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07                     SC_P_LVDS0_I2C0_SDA                3
+#define SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL                      SC_P_LVDS0_I2C1_SCL                0
+#define SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX                        SC_P_LVDS0_I2C1_SCL                1
+#define SC_P_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08                     SC_P_LVDS0_I2C1_SCL                3
+#define SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA                      SC_P_LVDS0_I2C1_SDA                0
+#define SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX                        SC_P_LVDS0_I2C1_SDA                1
+#define SC_P_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09                     SC_P_LVDS0_I2C1_SDA                3
+#define SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00                      SC_P_LVDS1_GPIO00                  0
+#define SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT                        SC_P_LVDS1_GPIO00                  1
+#define SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10                       SC_P_LVDS1_GPIO00                  3
+#define SC_P_LVDS1_GPIO01_LVDS1_GPIO0_IO01                      SC_P_LVDS1_GPIO01                  0
+#define SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11                       SC_P_LVDS1_GPIO01                  3
+#define SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL                      SC_P_LVDS1_I2C0_SCL                0
+#define SC_P_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02                    SC_P_LVDS1_I2C0_SCL                1
+#define SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12                     SC_P_LVDS1_I2C0_SCL                3
+#define SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA                      SC_P_LVDS1_I2C0_SDA                0
+#define SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03                    SC_P_LVDS1_I2C0_SDA                1
+#define SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13                     SC_P_LVDS1_I2C0_SDA                3
+#define SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL                      SC_P_LVDS1_I2C1_SCL                0
+#define SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX                        SC_P_LVDS1_I2C1_SCL                1
+#define SC_P_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14                     SC_P_LVDS1_I2C1_SCL                3
+#define SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA                      SC_P_LVDS1_I2C1_SDA                0
+#define SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX                        SC_P_LVDS1_I2C1_SDA                1
+#define SC_P_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15                     SC_P_LVDS1_I2C1_SDA                3
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL              SC_P_MIPI_DSI0_I2C0_SCL            0
+#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16                 SC_P_MIPI_DSI0_I2C0_SCL            3
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA              SC_P_MIPI_DSI0_I2C0_SDA            0
+#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17                 SC_P_MIPI_DSI0_I2C0_SDA            3
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00            SC_P_MIPI_DSI0_GPIO0_00            0
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT              SC_P_MIPI_DSI0_GPIO0_00            1
+#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18                 SC_P_MIPI_DSI0_GPIO0_00            3
+#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01            SC_P_MIPI_DSI0_GPIO0_01            0
+#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19                 SC_P_MIPI_DSI0_GPIO0_01            3
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL              SC_P_MIPI_DSI1_I2C0_SCL            0
+#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20                 SC_P_MIPI_DSI1_I2C0_SCL            3
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA              SC_P_MIPI_DSI1_I2C0_SDA            0
+#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21                 SC_P_MIPI_DSI1_I2C0_SDA            3
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00            SC_P_MIPI_DSI1_GPIO0_00            0
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT              SC_P_MIPI_DSI1_GPIO0_00            1
+#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22                 SC_P_MIPI_DSI1_GPIO0_00            3
+#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01            SC_P_MIPI_DSI1_GPIO0_01            0
+#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23                 SC_P_MIPI_DSI1_GPIO0_01            3
+#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT          SC_P_MIPI_CSI0_MCLK_OUT            0
+#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24                 SC_P_MIPI_CSI0_MCLK_OUT            3
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL              SC_P_MIPI_CSI0_I2C0_SCL            0
+#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25                 SC_P_MIPI_CSI0_I2C0_SCL            3
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA              SC_P_MIPI_CSI0_I2C0_SDA            0
+#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26                 SC_P_MIPI_CSI0_I2C0_SDA            3
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00            SC_P_MIPI_CSI0_GPIO0_00            0
+#define SC_P_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL                    SC_P_MIPI_CSI0_GPIO0_00            1
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL              SC_P_MIPI_CSI0_GPIO0_00            2
+#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27                 SC_P_MIPI_CSI0_GPIO0_00            3
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01            SC_P_MIPI_CSI0_GPIO0_01            0
+#define SC_P_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA                    SC_P_MIPI_CSI0_GPIO0_01            1
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA              SC_P_MIPI_CSI0_GPIO0_01            2
+#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28                 SC_P_MIPI_CSI0_GPIO0_01            3
+#define SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT          SC_P_MIPI_CSI1_MCLK_OUT            0
+#define SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29                 SC_P_MIPI_CSI1_MCLK_OUT            3
+#define SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00            SC_P_MIPI_CSI1_GPIO0_00            0
+#define SC_P_MIPI_CSI1_GPIO0_00_DMA_UART4_RX                    SC_P_MIPI_CSI1_GPIO0_00            1
+#define SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30                 SC_P_MIPI_CSI1_GPIO0_00            3
+#define SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01            SC_P_MIPI_CSI1_GPIO0_01            0
+#define SC_P_MIPI_CSI1_GPIO0_01_DMA_UART4_TX                    SC_P_MIPI_CSI1_GPIO0_01            1
+#define SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31                 SC_P_MIPI_CSI1_GPIO0_01            3
+#define SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL              SC_P_MIPI_CSI1_I2C0_SCL            0
+#define SC_P_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00                 SC_P_MIPI_CSI1_I2C0_SCL            3
+#define SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA              SC_P_MIPI_CSI1_I2C0_SDA            0
+#define SC_P_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01                 SC_P_MIPI_CSI1_I2C0_SDA            3
+#define SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL                  SC_P_HDMI_TX0_TS_SCL               0
+#define SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL                       SC_P_HDMI_TX0_TS_SCL               1
+#define SC_P_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02                    SC_P_HDMI_TX0_TS_SCL               3
+#define SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA                  SC_P_HDMI_TX0_TS_SDA               0
+#define SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA                       SC_P_HDMI_TX0_TS_SDA               1
+#define SC_P_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03                    SC_P_HDMI_TX0_TS_SDA               3
+#define SC_P_ESAI1_FSR_AUD_ESAI1_FSR                            SC_P_ESAI1_FSR                     0
+#define SC_P_ESAI1_FSR_LSIO_GPIO2_IO04                          SC_P_ESAI1_FSR                     3
+#define SC_P_ESAI1_FST_AUD_ESAI1_FST                            SC_P_ESAI1_FST                     0
+#define SC_P_ESAI1_FST_AUD_SPDIF0_EXT_CLK                       SC_P_ESAI1_FST                     1
+#define SC_P_ESAI1_FST_LSIO_GPIO2_IO05                          SC_P_ESAI1_FST                     3
+#define SC_P_ESAI1_SCKR_AUD_ESAI1_SCKR                          SC_P_ESAI1_SCKR                    0
+#define SC_P_ESAI1_SCKR_LSIO_GPIO2_IO06                         SC_P_ESAI1_SCKR                    3
+#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT                          SC_P_ESAI1_SCKT                    0
+#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC                            SC_P_ESAI1_SCKT                    1
+#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK                      SC_P_ESAI1_SCKT                    2
+#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07                         SC_P_ESAI1_SCKT                    3
+#define SC_P_ESAI1_TX0_AUD_ESAI1_TX0                            SC_P_ESAI1_TX0                     0
+#define SC_P_ESAI1_TX0_AUD_SAI2_RXD                             SC_P_ESAI1_TX0                     1
+#define SC_P_ESAI1_TX0_AUD_SPDIF0_RX                            SC_P_ESAI1_TX0                     2
+#define SC_P_ESAI1_TX0_LSIO_GPIO2_IO08                          SC_P_ESAI1_TX0                     3
+#define SC_P_ESAI1_TX1_AUD_ESAI1_TX1                            SC_P_ESAI1_TX1                     0
+#define SC_P_ESAI1_TX1_AUD_SAI2_RXFS                            SC_P_ESAI1_TX1                     1
+#define SC_P_ESAI1_TX1_AUD_SPDIF0_TX                            SC_P_ESAI1_TX1                     2
+#define SC_P_ESAI1_TX1_LSIO_GPIO2_IO09                          SC_P_ESAI1_TX1                     3
+#define SC_P_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3                    SC_P_ESAI1_TX2_RX3                 0
+#define SC_P_ESAI1_TX2_RX3_AUD_SPDIF0_RX                        SC_P_ESAI1_TX2_RX3                 1
+#define SC_P_ESAI1_TX2_RX3_LSIO_GPIO2_IO10                      SC_P_ESAI1_TX2_RX3                 3
+#define SC_P_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2                    SC_P_ESAI1_TX3_RX2                 0
+#define SC_P_ESAI1_TX3_RX2_AUD_SPDIF0_TX                        SC_P_ESAI1_TX3_RX2                 1
+#define SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11                      SC_P_ESAI1_TX3_RX2                 3
+#define SC_P_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1                    SC_P_ESAI1_TX4_RX1                 0
+#define SC_P_ESAI1_TX4_RX1_LSIO_GPIO2_IO12                      SC_P_ESAI1_TX4_RX1                 3
+#define SC_P_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0                    SC_P_ESAI1_TX5_RX0                 0
+#define SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13                      SC_P_ESAI1_TX5_RX0                 3
+#define SC_P_SPDIF0_RX_AUD_SPDIF0_RX                            SC_P_SPDIF0_RX                     0
+#define SC_P_SPDIF0_RX_AUD_MQS_R                                SC_P_SPDIF0_RX                     1
+#define SC_P_SPDIF0_RX_AUD_ACM_MCLK_IN1                         SC_P_SPDIF0_RX                     2
+#define SC_P_SPDIF0_RX_LSIO_GPIO2_IO14                          SC_P_SPDIF0_RX                     3
+#define SC_P_SPDIF0_TX_AUD_SPDIF0_TX                            SC_P_SPDIF0_TX                     0
+#define SC_P_SPDIF0_TX_AUD_MQS_L                                SC_P_SPDIF0_TX                     1
+#define SC_P_SPDIF0_TX_AUD_ACM_MCLK_OUT1                        SC_P_SPDIF0_TX                     2
+#define SC_P_SPDIF0_TX_LSIO_GPIO2_IO15                          SC_P_SPDIF0_TX                     3
+#define SC_P_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK                  SC_P_SPDIF0_EXT_CLK                0
+#define SC_P_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0                    SC_P_SPDIF0_EXT_CLK                1
+#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16                     SC_P_SPDIF0_EXT_CLK                3
+#define SC_P_SPI3_SCK_DMA_SPI3_SCK                              SC_P_SPI3_SCK                      0
+#define SC_P_SPI3_SCK_LSIO_GPIO2_IO17                           SC_P_SPI3_SCK                      3
+#define SC_P_SPI3_SDO_DMA_SPI3_SDO                              SC_P_SPI3_SDO                      0
+#define SC_P_SPI3_SDO_DMA_FTM_CH0                               SC_P_SPI3_SDO                      1
+#define SC_P_SPI3_SDO_LSIO_GPIO2_IO18                           SC_P_SPI3_SDO                      3
+#define SC_P_SPI3_SDI_DMA_SPI3_SDI                              SC_P_SPI3_SDI                      0
+#define SC_P_SPI3_SDI_DMA_FTM_CH1                               SC_P_SPI3_SDI                      1
+#define SC_P_SPI3_SDI_LSIO_GPIO2_IO19                           SC_P_SPI3_SDI                      3
+#define SC_P_SPI3_CS0_DMA_SPI3_CS0                              SC_P_SPI3_CS0                      0
+#define SC_P_SPI3_CS0_DMA_FTM_CH2                               SC_P_SPI3_CS0                      1
+#define SC_P_SPI3_CS0_LSIO_GPIO2_IO20                           SC_P_SPI3_CS0                      3
+#define SC_P_SPI3_CS1_DMA_SPI3_CS1                              SC_P_SPI3_CS1                      0
+#define SC_P_SPI3_CS1_LSIO_GPIO2_IO21                           SC_P_SPI3_CS1                      3
+#define SC_P_ESAI0_FSR_AUD_ESAI0_FSR                            SC_P_ESAI0_FSR                     0
+#define SC_P_ESAI0_FSR_LSIO_GPIO2_IO22                          SC_P_ESAI0_FSR                     3
+#define SC_P_ESAI0_FST_AUD_ESAI0_FST                            SC_P_ESAI0_FST                     0
+#define SC_P_ESAI0_FST_LSIO_GPIO2_IO23                          SC_P_ESAI0_FST                     3
+#define SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR                          SC_P_ESAI0_SCKR                    0
+#define SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24                         SC_P_ESAI0_SCKR                    3
+#define SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT                          SC_P_ESAI0_SCKT                    0
+#define SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25                         SC_P_ESAI0_SCKT                    3
+#define SC_P_ESAI0_TX0_AUD_ESAI0_TX0                            SC_P_ESAI0_TX0                     0
+#define SC_P_ESAI0_TX0_LSIO_GPIO2_IO26                          SC_P_ESAI0_TX0                     3
+#define SC_P_ESAI0_TX1_AUD_ESAI0_TX1                            SC_P_ESAI0_TX1                     0
+#define SC_P_ESAI0_TX1_LSIO_GPIO2_IO27                          SC_P_ESAI0_TX1                     3
+#define SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3                    SC_P_ESAI0_TX2_RX3                 0
+#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28                      SC_P_ESAI0_TX2_RX3                 3
+#define SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2                    SC_P_ESAI0_TX3_RX2                 0
+#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29                      SC_P_ESAI0_TX3_RX2                 3
+#define SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1                    SC_P_ESAI0_TX4_RX1                 0
+#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30                      SC_P_ESAI0_TX4_RX1                 3
+#define SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0                    SC_P_ESAI0_TX5_RX0                 0
+#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31                      SC_P_ESAI0_TX5_RX0                 3
+#define SC_P_MCLK_IN0_AUD_ACM_MCLK_IN0                          SC_P_MCLK_IN0                      0
+#define SC_P_MCLK_IN0_AUD_ESAI0_RX_HF_CLK                       SC_P_MCLK_IN0                      1
+#define SC_P_MCLK_IN0_AUD_ESAI1_RX_HF_CLK                       SC_P_MCLK_IN0                      2
+#define SC_P_MCLK_IN0_LSIO_GPIO3_IO00                           SC_P_MCLK_IN0                      3
+#define SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0                        SC_P_MCLK_OUT0                     0
+#define SC_P_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK                      SC_P_MCLK_OUT0                     1
+#define SC_P_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK                      SC_P_MCLK_OUT0                     2
+#define SC_P_MCLK_OUT0_LSIO_GPIO3_IO01                          SC_P_MCLK_OUT0                     3
+#define SC_P_SPI0_SCK_DMA_SPI0_SCK                              SC_P_SPI0_SCK                      0
+#define SC_P_SPI0_SCK_AUD_SAI0_RXC                              SC_P_SPI0_SCK                      1
+#define SC_P_SPI0_SCK_LSIO_GPIO3_IO02                           SC_P_SPI0_SCK                      3
+#define SC_P_SPI0_SDO_DMA_SPI0_SDO                              SC_P_SPI0_SDO                      0
+#define SC_P_SPI0_SDO_AUD_SAI0_TXD                              SC_P_SPI0_SDO                      1
+#define SC_P_SPI0_SDO_LSIO_GPIO3_IO03                           SC_P_SPI0_SDO                      3
+#define SC_P_SPI0_SDI_DMA_SPI0_SDI                              SC_P_SPI0_SDI                      0
+#define SC_P_SPI0_SDI_AUD_SAI0_RXD                              SC_P_SPI0_SDI                      1
+#define SC_P_SPI0_SDI_LSIO_GPIO3_IO04                           SC_P_SPI0_SDI                      3
+#define SC_P_SPI0_CS0_DMA_SPI0_CS0                              SC_P_SPI0_CS0                      0
+#define SC_P_SPI0_CS0_AUD_SAI0_RXFS                             SC_P_SPI0_CS0                      1
+#define SC_P_SPI0_CS0_LSIO_GPIO3_IO05                           SC_P_SPI0_CS0                      3
+#define SC_P_SPI0_CS1_DMA_SPI0_CS1                              SC_P_SPI0_CS1                      0
+#define SC_P_SPI0_CS1_AUD_SAI0_TXC                              SC_P_SPI0_CS1                      1
+#define SC_P_SPI0_CS1_LSIO_GPIO3_IO06                           SC_P_SPI0_CS1                      3
+#define SC_P_SPI2_SCK_DMA_SPI2_SCK                              SC_P_SPI2_SCK                      0
+#define SC_P_SPI2_SCK_LSIO_GPIO3_IO07                           SC_P_SPI2_SCK                      3
+#define SC_P_SPI2_SDO_DMA_SPI2_SDO                              SC_P_SPI2_SDO                      0
+#define SC_P_SPI2_SDO_LSIO_GPIO3_IO08                           SC_P_SPI2_SDO                      3
+#define SC_P_SPI2_SDI_DMA_SPI2_SDI                              SC_P_SPI2_SDI                      0
+#define SC_P_SPI2_SDI_LSIO_GPIO3_IO09                           SC_P_SPI2_SDI                      3
+#define SC_P_SPI2_CS0_DMA_SPI2_CS0                              SC_P_SPI2_CS0                      0
+#define SC_P_SPI2_CS0_LSIO_GPIO3_IO10                           SC_P_SPI2_CS0                      3
+#define SC_P_SPI2_CS1_DMA_SPI2_CS1                              SC_P_SPI2_CS1                      0
+#define SC_P_SPI2_CS1_AUD_SAI0_TXFS                             SC_P_SPI2_CS1                      1
+#define SC_P_SPI2_CS1_LSIO_GPIO3_IO11                           SC_P_SPI2_CS1                      3
+#define SC_P_SAI1_RXC_AUD_SAI1_RXC                              SC_P_SAI1_RXC                      0
+#define SC_P_SAI1_RXC_AUD_SAI0_TXD                              SC_P_SAI1_RXC                      1
+#define SC_P_SAI1_RXC_LSIO_GPIO3_IO12                           SC_P_SAI1_RXC                      3
+#define SC_P_SAI1_RXD_AUD_SAI1_RXD                              SC_P_SAI1_RXD                      0
+#define SC_P_SAI1_RXD_AUD_SAI0_TXFS                             SC_P_SAI1_RXD                      1
+#define SC_P_SAI1_RXD_LSIO_GPIO3_IO13                           SC_P_SAI1_RXD                      3
+#define SC_P_SAI1_RXFS_AUD_SAI1_RXFS                            SC_P_SAI1_RXFS                     0
+#define SC_P_SAI1_RXFS_AUD_SAI0_RXD                             SC_P_SAI1_RXFS                     1
+#define SC_P_SAI1_RXFS_LSIO_GPIO3_IO14                          SC_P_SAI1_RXFS                     3
+#define SC_P_SAI1_TXC_AUD_SAI1_TXC                              SC_P_SAI1_TXC                      0
+#define SC_P_SAI1_TXC_AUD_SAI0_TXC                              SC_P_SAI1_TXC                      1
+#define SC_P_SAI1_TXC_LSIO_GPIO3_IO15                           SC_P_SAI1_TXC                      3
+#define SC_P_SAI1_TXD_AUD_SAI1_TXD                              SC_P_SAI1_TXD                      0
+#define SC_P_SAI1_TXD_AUD_SAI1_RXC                              SC_P_SAI1_TXD                      1
+#define SC_P_SAI1_TXD_LSIO_GPIO3_IO16                           SC_P_SAI1_TXD                      3
+#define SC_P_SAI1_TXFS_AUD_SAI1_TXFS                            SC_P_SAI1_TXFS                     0
+#define SC_P_SAI1_TXFS_AUD_SAI1_RXFS                            SC_P_SAI1_TXFS                     1
+#define SC_P_SAI1_TXFS_LSIO_GPIO3_IO17                          SC_P_SAI1_TXFS                     3
+#define SC_P_ADC_IN7_DMA_ADC1_IN3                               SC_P_ADC_IN7                       0
+#define SC_P_ADC_IN7_DMA_SPI1_CS1                               SC_P_ADC_IN7                       1
+#define SC_P_ADC_IN7_LSIO_KPP0_ROW3                             SC_P_ADC_IN7                       2
+#define SC_P_ADC_IN7_LSIO_GPIO3_IO25                            SC_P_ADC_IN7                       3
+#define SC_P_ADC_IN6_DMA_ADC1_IN2                               SC_P_ADC_IN6                       0
+#define SC_P_ADC_IN6_DMA_SPI1_CS0                               SC_P_ADC_IN6                       1
+#define SC_P_ADC_IN6_LSIO_KPP0_ROW2                             SC_P_ADC_IN6                       2
+#define SC_P_ADC_IN6_LSIO_GPIO3_IO24                            SC_P_ADC_IN6                       3
+#define SC_P_ADC_IN5_DMA_ADC1_IN1                               SC_P_ADC_IN5                       0
+#define SC_P_ADC_IN5_DMA_SPI1_SDI                               SC_P_ADC_IN5                       1
+#define SC_P_ADC_IN5_LSIO_KPP0_ROW1                             SC_P_ADC_IN5                       2
+#define SC_P_ADC_IN5_LSIO_GPIO3_IO23                            SC_P_ADC_IN5                       3
+#define SC_P_ADC_IN4_DMA_ADC1_IN0                               SC_P_ADC_IN4                       0
+#define SC_P_ADC_IN4_DMA_SPI1_SDO                               SC_P_ADC_IN4                       1
+#define SC_P_ADC_IN4_LSIO_KPP0_ROW0                             SC_P_ADC_IN4                       2
+#define SC_P_ADC_IN4_LSIO_GPIO3_IO22                            SC_P_ADC_IN4                       3
+#define SC_P_ADC_IN3_DMA_ADC0_IN3                               SC_P_ADC_IN3                       0
+#define SC_P_ADC_IN3_DMA_SPI1_SCK                               SC_P_ADC_IN3                       1
+#define SC_P_ADC_IN3_LSIO_KPP0_COL3                             SC_P_ADC_IN3                       2
+#define SC_P_ADC_IN3_LSIO_GPIO3_IO21                            SC_P_ADC_IN3                       3
+#define SC_P_ADC_IN2_DMA_ADC0_IN2                               SC_P_ADC_IN2                       0
+#define SC_P_ADC_IN2_LSIO_KPP0_COL2                             SC_P_ADC_IN2                       2
+#define SC_P_ADC_IN2_LSIO_GPIO3_IO20                            SC_P_ADC_IN2                       3
+#define SC_P_ADC_IN1_DMA_ADC0_IN1                               SC_P_ADC_IN1                       0
+#define SC_P_ADC_IN1_LSIO_KPP0_COL1                             SC_P_ADC_IN1                       2
+#define SC_P_ADC_IN1_LSIO_GPIO3_IO19                            SC_P_ADC_IN1                       3
+#define SC_P_ADC_IN0_DMA_ADC0_IN0                               SC_P_ADC_IN0                       0
+#define SC_P_ADC_IN0_LSIO_KPP0_COL0                             SC_P_ADC_IN0                       2
+#define SC_P_ADC_IN0_LSIO_GPIO3_IO18                            SC_P_ADC_IN0                       3
+#define SC_P_MLB_SIG_CONN_MLB_SIG                               SC_P_MLB_SIG                       0
+#define SC_P_MLB_SIG_AUD_SAI3_RXC                               SC_P_MLB_SIG                       1
+#define SC_P_MLB_SIG_LSIO_GPIO3_IO26                            SC_P_MLB_SIG                       3
+#define SC_P_MLB_CLK_CONN_MLB_CLK                               SC_P_MLB_CLK                       0
+#define SC_P_MLB_CLK_AUD_SAI3_RXFS                              SC_P_MLB_CLK                       1
+#define SC_P_MLB_CLK_LSIO_GPIO3_IO27                            SC_P_MLB_CLK                       3
+#define SC_P_MLB_DATA_CONN_MLB_DATA                             SC_P_MLB_DATA                      0
+#define SC_P_MLB_DATA_AUD_SAI3_RXD                              SC_P_MLB_DATA                      1
+#define SC_P_MLB_DATA_LSIO_GPIO3_IO28                           SC_P_MLB_DATA                      3
+#define SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX                        SC_P_FLEXCAN0_RX                   0
+#define SC_P_FLEXCAN0_RX_LSIO_GPIO3_IO29                        SC_P_FLEXCAN0_RX                   3
+#define SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX                        SC_P_FLEXCAN0_TX                   0
+#define SC_P_FLEXCAN0_TX_LSIO_GPIO3_IO30                        SC_P_FLEXCAN0_TX                   3
+#define SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX                        SC_P_FLEXCAN1_RX                   0
+#define SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31                        SC_P_FLEXCAN1_RX                   3
+#define SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX                        SC_P_FLEXCAN1_TX                   0
+#define SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00                        SC_P_FLEXCAN1_TX                   3
+#define SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX                        SC_P_FLEXCAN2_RX                   0
+#define SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01                        SC_P_FLEXCAN2_RX                   3
+#define SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX                        SC_P_FLEXCAN2_TX                   0
+#define SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02                        SC_P_FLEXCAN2_TX                   3
+#define SC_P_USB_SS3_TC0_DMA_I2C1_SCL                           SC_P_USB_SS3_TC0                   0
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR                      SC_P_USB_SS3_TC0                   1
+#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03                        SC_P_USB_SS3_TC0                   3
+#define SC_P_USB_SS3_TC1_DMA_I2C1_SCL                           SC_P_USB_SS3_TC1                   0
+#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR                      SC_P_USB_SS3_TC1                   1
+#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04                        SC_P_USB_SS3_TC1                   3
+#define SC_P_USB_SS3_TC2_DMA_I2C1_SDA                           SC_P_USB_SS3_TC2                   0
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC                       SC_P_USB_SS3_TC2                   1
+#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05                        SC_P_USB_SS3_TC2                   3
+#define SC_P_USB_SS3_TC3_DMA_I2C1_SDA                           SC_P_USB_SS3_TC3                   0
+#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC                       SC_P_USB_SS3_TC3                   1
+#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06                        SC_P_USB_SS3_TC3                   3
+#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B                 SC_P_USDHC1_RESET_B                0
+#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07                     SC_P_USDHC1_RESET_B                3
+#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT                 SC_P_USDHC1_VSELECT                0
+#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08                     SC_P_USDHC1_VSELECT                3
+#define SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B                 SC_P_USDHC2_RESET_B                0
+#define SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09                     SC_P_USDHC2_RESET_B                3
+#define SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT                 SC_P_USDHC2_VSELECT                0
+#define SC_P_USDHC2_VSELECT_LSIO_GPIO4_IO10                     SC_P_USDHC2_VSELECT                3
+#define SC_P_USDHC2_WP_CONN_USDHC2_WP                           SC_P_USDHC2_WP                     0
+#define SC_P_USDHC2_WP_LSIO_GPIO4_IO11                          SC_P_USDHC2_WP                     3
+#define SC_P_USDHC2_CD_B_CONN_USDHC2_CD_B                       SC_P_USDHC2_CD_B                   0
+#define SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12                        SC_P_USDHC2_CD_B                   3
+#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO                         SC_P_ENET0_MDIO                    0
+#define SC_P_ENET0_MDIO_DMA_I2C4_SDA                            SC_P_ENET0_MDIO                    1
+#define SC_P_ENET0_MDIO_LSIO_GPIO4_IO13                         SC_P_ENET0_MDIO                    3
+#define SC_P_ENET0_MDC_CONN_ENET0_MDC                           SC_P_ENET0_MDC                     0
+#define SC_P_ENET0_MDC_DMA_I2C4_SCL                             SC_P_ENET0_MDC                     1
+#define SC_P_ENET0_MDC_LSIO_GPIO4_IO14                          SC_P_ENET0_MDC                     3
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M   SC_P_ENET0_REFCLK_125M_25M         0
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS               SC_P_ENET0_REFCLK_125M_25M         1
+#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15              SC_P_ENET0_REFCLK_125M_25M         3
+#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M   SC_P_ENET1_REFCLK_125M_25M         0
+#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS               SC_P_ENET1_REFCLK_125M_25M         1
+#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16              SC_P_ENET1_REFCLK_125M_25M         3
+#define SC_P_ENET1_MDIO_CONN_ENET1_MDIO                         SC_P_ENET1_MDIO                    0
+#define SC_P_ENET1_MDIO_DMA_I2C4_SDA                            SC_P_ENET1_MDIO                    1
+#define SC_P_ENET1_MDIO_LSIO_GPIO4_IO17                         SC_P_ENET1_MDIO                    3
+#define SC_P_ENET1_MDC_CONN_ENET1_MDC                           SC_P_ENET1_MDC                     0
+#define SC_P_ENET1_MDC_DMA_I2C4_SCL                             SC_P_ENET1_MDC                     1
+#define SC_P_ENET1_MDC_LSIO_GPIO4_IO18                          SC_P_ENET1_MDC                     3
+#define SC_P_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B                     SC_P_QSPI1A_SS0_B                  0
+#define SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19                       SC_P_QSPI1A_SS0_B                  3
+#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B                     SC_P_QSPI1A_SS1_B                  0
+#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2                     SC_P_QSPI1A_SS1_B                  1
+#define SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20                       SC_P_QSPI1A_SS1_B                  3
+#define SC_P_QSPI1A_SCLK_LSIO_QSPI1A_SCLK                       SC_P_QSPI1A_SCLK                   0
+#define SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21                        SC_P_QSPI1A_SCLK                   3
+#define SC_P_QSPI1A_DQS_LSIO_QSPI1A_DQS                         SC_P_QSPI1A_DQS                    0
+#define SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22                         SC_P_QSPI1A_DQS                    3
+#define SC_P_QSPI1A_DATA3_LSIO_QSPI1A_DATA3                     SC_P_QSPI1A_DATA3                  0
+#define SC_P_QSPI1A_DATA3_DMA_I2C1_SDA                          SC_P_QSPI1A_DATA3                  1
+#define SC_P_QSPI1A_DATA3_CONN_USB_OTG1_OC                      SC_P_QSPI1A_DATA3                  2
+#define SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23                       SC_P_QSPI1A_DATA3                  3
+#define SC_P_QSPI1A_DATA2_LSIO_QSPI1A_DATA2                     SC_P_QSPI1A_DATA2                  0
+#define SC_P_QSPI1A_DATA2_DMA_I2C1_SCL                          SC_P_QSPI1A_DATA2                  1
+#define SC_P_QSPI1A_DATA2_CONN_USB_OTG2_PWR                     SC_P_QSPI1A_DATA2                  2
+#define SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24                       SC_P_QSPI1A_DATA2                  3
+#define SC_P_QSPI1A_DATA1_LSIO_QSPI1A_DATA1                     SC_P_QSPI1A_DATA1                  0
+#define SC_P_QSPI1A_DATA1_DMA_I2C1_SDA                          SC_P_QSPI1A_DATA1                  1
+#define SC_P_QSPI1A_DATA1_CONN_USB_OTG2_OC                      SC_P_QSPI1A_DATA1                  2
+#define SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25                       SC_P_QSPI1A_DATA1                  3
+#define SC_P_QSPI1A_DATA0_LSIO_QSPI1A_DATA0                     SC_P_QSPI1A_DATA0                  0
+#define SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26                       SC_P_QSPI1A_DATA0                  3
+#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0                     SC_P_QSPI0A_DATA0                  0
+#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1                     SC_P_QSPI0A_DATA1                  0
+#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2                     SC_P_QSPI0A_DATA2                  0
+#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3                     SC_P_QSPI0A_DATA3                  0
+#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS                         SC_P_QSPI0A_DQS                    0
+#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B                     SC_P_QSPI0A_SS0_B                  0
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B                     SC_P_QSPI0A_SS1_B                  0
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2                     SC_P_QSPI0A_SS1_B                  1
+#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK                       SC_P_QSPI0A_SCLK                   0
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK                       SC_P_QSPI0B_SCLK                   0
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0                     SC_P_QSPI0B_DATA0                  0
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1                     SC_P_QSPI0B_DATA1                  0
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2                     SC_P_QSPI0B_DATA2                  0
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3                     SC_P_QSPI0B_DATA3                  0
+#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS                         SC_P_QSPI0B_DQS                    0
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B                     SC_P_QSPI0B_SS0_B                  0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B                     SC_P_QSPI0B_SS1_B                  0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2                     SC_P_QSPI0B_SS1_B                  1
+#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B            SC_P_PCIE_CTRL0_CLKREQ_B           0
+#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27                SC_P_PCIE_CTRL0_CLKREQ_B           3
+#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B                SC_P_PCIE_CTRL0_WAKE_B             0
+#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28                  SC_P_PCIE_CTRL0_WAKE_B             3
+#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B              SC_P_PCIE_CTRL0_PERST_B            0
+#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29                 SC_P_PCIE_CTRL0_PERST_B            3
+#define SC_P_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B            SC_P_PCIE_CTRL1_CLKREQ_B           0
+#define SC_P_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA                   SC_P_PCIE_CTRL1_CLKREQ_B           1
+#define SC_P_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC               SC_P_PCIE_CTRL1_CLKREQ_B           2
+#define SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30                SC_P_PCIE_CTRL1_CLKREQ_B           3
+#define SC_P_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B                SC_P_PCIE_CTRL1_WAKE_B             0
+#define SC_P_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL                     SC_P_PCIE_CTRL1_WAKE_B             1
+#define SC_P_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR                SC_P_PCIE_CTRL1_WAKE_B             2
+#define SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31                  SC_P_PCIE_CTRL1_WAKE_B             3
+#define SC_P_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B              SC_P_PCIE_CTRL1_PERST_B            0
+#define SC_P_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL                    SC_P_PCIE_CTRL1_PERST_B            1
+#define SC_P_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR               SC_P_PCIE_CTRL1_PERST_B            2
+#define SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00                 SC_P_PCIE_CTRL1_PERST_B            3
+#define SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA                 SC_P_USB_HSIC0_DATA                0
+#define SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA                        SC_P_USB_HSIC0_DATA                1
+#define SC_P_USB_HSIC0_DATA_LSIO_GPIO5_IO01                     SC_P_USB_HSIC0_DATA                3
+#define SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE             SC_P_USB_HSIC0_STROBE              0
+#define SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL                      SC_P_USB_HSIC0_STROBE              1
+#define SC_P_USB_HSIC0_STROBE_LSIO_GPIO5_IO02                   SC_P_USB_HSIC0_STROBE              3
+#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK                           SC_P_EMMC0_CLK                     0
+#define SC_P_EMMC0_CLK_CONN_NAND_READY_B                        SC_P_EMMC0_CLK                     1
+#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD                           SC_P_EMMC0_CMD                     0
+#define SC_P_EMMC0_CMD_CONN_NAND_DQS                            SC_P_EMMC0_CMD                     1
+#define SC_P_EMMC0_CMD_AUD_MQS_R                                SC_P_EMMC0_CMD                     2
+#define SC_P_EMMC0_CMD_LSIO_GPIO5_IO03                          SC_P_EMMC0_CMD                     3
+#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0                       SC_P_EMMC0_DATA0                   0
+#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00                       SC_P_EMMC0_DATA0                   1
+#define SC_P_EMMC0_DATA0_LSIO_GPIO5_IO04                        SC_P_EMMC0_DATA0                   3
+#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1                       SC_P_EMMC0_DATA1                   0
+#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01                       SC_P_EMMC0_DATA1                   1
+#define SC_P_EMMC0_DATA1_LSIO_GPIO5_IO05                        SC_P_EMMC0_DATA1                   3
+#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2                       SC_P_EMMC0_DATA2                   0
+#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02                       SC_P_EMMC0_DATA2                   1
+#define SC_P_EMMC0_DATA2_LSIO_GPIO5_IO06                        SC_P_EMMC0_DATA2                   3
+#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3                       SC_P_EMMC0_DATA3                   0
+#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03                       SC_P_EMMC0_DATA3                   1
+#define SC_P_EMMC0_DATA3_LSIO_GPIO5_IO07                        SC_P_EMMC0_DATA3                   3
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4                       SC_P_EMMC0_DATA4                   0
+#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04                       SC_P_EMMC0_DATA4                   1
+#define SC_P_EMMC0_DATA4_LSIO_GPIO5_IO08                        SC_P_EMMC0_DATA4                   3
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5                       SC_P_EMMC0_DATA5                   0
+#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05                       SC_P_EMMC0_DATA5                   1
+#define SC_P_EMMC0_DATA5_LSIO_GPIO5_IO09                        SC_P_EMMC0_DATA5                   3
+#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6                       SC_P_EMMC0_DATA6                   0
+#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06                       SC_P_EMMC0_DATA6                   1
+#define SC_P_EMMC0_DATA6_LSIO_GPIO5_IO10                        SC_P_EMMC0_DATA6                   3
+#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7                       SC_P_EMMC0_DATA7                   0
+#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07                       SC_P_EMMC0_DATA7                   1
+#define SC_P_EMMC0_DATA7_LSIO_GPIO5_IO11                        SC_P_EMMC0_DATA7                   3
+#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE                     SC_P_EMMC0_STROBE                  0
+#define SC_P_EMMC0_STROBE_CONN_NAND_CLE                         SC_P_EMMC0_STROBE                  1
+#define SC_P_EMMC0_STROBE_LSIO_GPIO5_IO12                       SC_P_EMMC0_STROBE                  3
+#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B                   SC_P_EMMC0_RESET_B                 0
+#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B                       SC_P_EMMC0_RESET_B                 1
+#define SC_P_EMMC0_RESET_B_CONN_USDHC1_VSELECT                  SC_P_EMMC0_RESET_B                 2
+#define SC_P_EMMC0_RESET_B_LSIO_GPIO5_IO13                      SC_P_EMMC0_RESET_B                 3
+#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK                         SC_P_USDHC1_CLK                    0
+#define SC_P_USDHC1_CLK_AUD_MQS_R                               SC_P_USDHC1_CLK                    1
+#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD                         SC_P_USDHC1_CMD                    0
+#define SC_P_USDHC1_CMD_AUD_MQS_L                               SC_P_USDHC1_CMD                    1
+#define SC_P_USDHC1_CMD_LSIO_GPIO5_IO14                         SC_P_USDHC1_CMD                    3
+#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0                     SC_P_USDHC1_DATA0                  0
+#define SC_P_USDHC1_DATA0_CONN_NAND_RE_N                        SC_P_USDHC1_DATA0                  1
+#define SC_P_USDHC1_DATA0_LSIO_GPIO5_IO15                       SC_P_USDHC1_DATA0                  3
+#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1                     SC_P_USDHC1_DATA1                  0
+#define SC_P_USDHC1_DATA1_CONN_NAND_RE_P                        SC_P_USDHC1_DATA1                  1
+#define SC_P_USDHC1_DATA1_LSIO_GPIO5_IO16                       SC_P_USDHC1_DATA1                  3
+#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2                     SC_P_USDHC1_DATA2                  0
+#define SC_P_USDHC1_DATA2_CONN_NAND_DQS_N                       SC_P_USDHC1_DATA2                  1
+#define SC_P_USDHC1_DATA2_LSIO_GPIO5_IO17                       SC_P_USDHC1_DATA2                  3
+#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3                     SC_P_USDHC1_DATA3                  0
+#define SC_P_USDHC1_DATA3_CONN_NAND_DQS_P                       SC_P_USDHC1_DATA3                  1
+#define SC_P_USDHC1_DATA3_LSIO_GPIO5_IO18                       SC_P_USDHC1_DATA3                  3
+#define SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4                     SC_P_USDHC1_DATA4                  0
+#define SC_P_USDHC1_DATA4_CONN_NAND_CE0_B                       SC_P_USDHC1_DATA4                  1
+#define SC_P_USDHC1_DATA4_AUD_MQS_R                             SC_P_USDHC1_DATA4                  2
+#define SC_P_USDHC1_DATA4_LSIO_GPIO5_IO19                       SC_P_USDHC1_DATA4                  3
+#define SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5                     SC_P_USDHC1_DATA5                  0
+#define SC_P_USDHC1_DATA5_CONN_NAND_RE_B                        SC_P_USDHC1_DATA5                  1
+#define SC_P_USDHC1_DATA5_AUD_MQS_L                             SC_P_USDHC1_DATA5                  2
+#define SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20                       SC_P_USDHC1_DATA5                  3
+#define SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6                     SC_P_USDHC1_DATA6                  0
+#define SC_P_USDHC1_DATA6_CONN_NAND_WE_B                        SC_P_USDHC1_DATA6                  1
+#define SC_P_USDHC1_DATA6_CONN_USDHC1_WP                        SC_P_USDHC1_DATA6                  2
+#define SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21                       SC_P_USDHC1_DATA6                  3
+#define SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7                     SC_P_USDHC1_DATA7                  0
+#define SC_P_USDHC1_DATA7_CONN_NAND_ALE                         SC_P_USDHC1_DATA7                  1
+#define SC_P_USDHC1_DATA7_CONN_USDHC1_CD_B                      SC_P_USDHC1_DATA7                  2
+#define SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22                       SC_P_USDHC1_DATA7                  3
+#define SC_P_USDHC1_STROBE_CONN_USDHC1_STROBE                   SC_P_USDHC1_STROBE                 0
+#define SC_P_USDHC1_STROBE_CONN_NAND_CE1_B                      SC_P_USDHC1_STROBE                 1
+#define SC_P_USDHC1_STROBE_CONN_USDHC1_RESET_B                  SC_P_USDHC1_STROBE                 2
+#define SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23                      SC_P_USDHC1_STROBE                 3
+#define SC_P_USDHC2_CLK_CONN_USDHC2_CLK                         SC_P_USDHC2_CLK                    0
+#define SC_P_USDHC2_CLK_AUD_MQS_R                               SC_P_USDHC2_CLK                    1
+#define SC_P_USDHC2_CLK_LSIO_GPIO5_IO24                         SC_P_USDHC2_CLK                    3
+#define SC_P_USDHC2_CMD_CONN_USDHC2_CMD                         SC_P_USDHC2_CMD                    0
+#define SC_P_USDHC2_CMD_AUD_MQS_L                               SC_P_USDHC2_CMD                    1
+#define SC_P_USDHC2_CMD_LSIO_GPIO5_IO25                         SC_P_USDHC2_CMD                    3
+#define SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0                     SC_P_USDHC2_DATA0                  0
+#define SC_P_USDHC2_DATA0_DMA_UART4_RX                          SC_P_USDHC2_DATA0                  1
+#define SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26                       SC_P_USDHC2_DATA0                  3
+#define SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1                     SC_P_USDHC2_DATA1                  0
+#define SC_P_USDHC2_DATA1_DMA_UART4_TX                          SC_P_USDHC2_DATA1                  1
+#define SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27                       SC_P_USDHC2_DATA1                  3
+#define SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2                     SC_P_USDHC2_DATA2                  0
+#define SC_P_USDHC2_DATA2_DMA_UART4_CTS_B                       SC_P_USDHC2_DATA2                  1
+#define SC_P_USDHC2_DATA2_LSIO_GPIO5_IO28                       SC_P_USDHC2_DATA2                  3
+#define SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3                     SC_P_USDHC2_DATA3                  0
+#define SC_P_USDHC2_DATA3_DMA_UART4_RTS_B                       SC_P_USDHC2_DATA3                  1
+#define SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29                       SC_P_USDHC2_DATA3                  3
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC               SC_P_ENET0_RGMII_TXC               0
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT             SC_P_ENET0_RGMII_TXC               1
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN              SC_P_ENET0_RGMII_TXC               2
+#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30                    SC_P_ENET0_RGMII_TXC               3
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL         SC_P_ENET0_RGMII_TX_CTL            0
+#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31                 SC_P_ENET0_RGMII_TX_CTL            3
+#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0             SC_P_ENET0_RGMII_TXD0              0
+#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00                   SC_P_ENET0_RGMII_TXD0              3
+#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1             SC_P_ENET0_RGMII_TXD1              0
+#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01                   SC_P_ENET0_RGMII_TXD1              3
+#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2             SC_P_ENET0_RGMII_TXD2              0
+#define SC_P_ENET0_RGMII_TXD2_DMA_UART3_TX                      SC_P_ENET0_RGMII_TXD2              1
+#define SC_P_ENET0_RGMII_TXD2_VPU_TSI_S1_VID                    SC_P_ENET0_RGMII_TXD2              2
+#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02                   SC_P_ENET0_RGMII_TXD2              3
+#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3             SC_P_ENET0_RGMII_TXD3              0
+#define SC_P_ENET0_RGMII_TXD3_DMA_UART3_RTS_B                   SC_P_ENET0_RGMII_TXD3              1
+#define SC_P_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC                   SC_P_ENET0_RGMII_TXD3              2
+#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03                   SC_P_ENET0_RGMII_TXD3              3
+#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC               SC_P_ENET0_RGMII_RXC               0
+#define SC_P_ENET0_RGMII_RXC_DMA_UART3_CTS_B                    SC_P_ENET0_RGMII_RXC               1
+#define SC_P_ENET0_RGMII_RXC_VPU_TSI_S1_DATA                    SC_P_ENET0_RGMII_RXC               2
+#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04                    SC_P_ENET0_RGMII_RXC               3
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL         SC_P_ENET0_RGMII_RX_CTL            0
+#define SC_P_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID                  SC_P_ENET0_RGMII_RX_CTL            2
+#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05                 SC_P_ENET0_RGMII_RX_CTL            3
+#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0             SC_P_ENET0_RGMII_RXD0              0
+#define SC_P_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC                   SC_P_ENET0_RGMII_RXD0              2
+#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06                   SC_P_ENET0_RGMII_RXD0              3
+#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1             SC_P_ENET0_RGMII_RXD1              0
+#define SC_P_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA                   SC_P_ENET0_RGMII_RXD1              2
+#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07                   SC_P_ENET0_RGMII_RXD1              3
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2             SC_P_ENET0_RGMII_RXD2              0
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER             SC_P_ENET0_RGMII_RXD2              1
+#define SC_P_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK                    SC_P_ENET0_RGMII_RXD2              2
+#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08                   SC_P_ENET0_RGMII_RXD2              3
+#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3             SC_P_ENET0_RGMII_RXD3              0
+#define SC_P_ENET0_RGMII_RXD3_DMA_UART3_RX                      SC_P_ENET0_RGMII_RXD3              1
+#define SC_P_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK                    SC_P_ENET0_RGMII_RXD3              2
+#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09                   SC_P_ENET0_RGMII_RXD3              3
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC               SC_P_ENET1_RGMII_TXC               0
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT             SC_P_ENET1_RGMII_TXC               1
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN              SC_P_ENET1_RGMII_TXC               2
+#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10                    SC_P_ENET1_RGMII_TXC               3
+#define SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL         SC_P_ENET1_RGMII_TX_CTL            0
+#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11                 SC_P_ENET1_RGMII_TX_CTL            3
+#define SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0             SC_P_ENET1_RGMII_TXD0              0
+#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12                   SC_P_ENET1_RGMII_TXD0              3
+#define SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1             SC_P_ENET1_RGMII_TXD1              0
+#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13                   SC_P_ENET1_RGMII_TXD1              3
+#define SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2             SC_P_ENET1_RGMII_TXD2              0
+#define SC_P_ENET1_RGMII_TXD2_DMA_UART3_TX                      SC_P_ENET1_RGMII_TXD2              1
+#define SC_P_ENET1_RGMII_TXD2_VPU_TSI_S1_VID                    SC_P_ENET1_RGMII_TXD2              2
+#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14                   SC_P_ENET1_RGMII_TXD2              3
+#define SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3             SC_P_ENET1_RGMII_TXD3              0
+#define SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B                   SC_P_ENET1_RGMII_TXD3              1
+#define SC_P_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC                   SC_P_ENET1_RGMII_TXD3              2
+#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15                   SC_P_ENET1_RGMII_TXD3              3
+#define SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC               SC_P_ENET1_RGMII_RXC               0
+#define SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B                    SC_P_ENET1_RGMII_RXC               1
+#define SC_P_ENET1_RGMII_RXC_VPU_TSI_S1_DATA                    SC_P_ENET1_RGMII_RXC               2
+#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO6_IO16                    SC_P_ENET1_RGMII_RXC               3
+#define SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL         SC_P_ENET1_RGMII_RX_CTL            0
+#define SC_P_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID                  SC_P_ENET1_RGMII_RX_CTL            2
+#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17                 SC_P_ENET1_RGMII_RX_CTL            3
+#define SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0             SC_P_ENET1_RGMII_RXD0              0
+#define SC_P_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC                   SC_P_ENET1_RGMII_RXD0              2
+#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18                   SC_P_ENET1_RGMII_RXD0              3
+#define SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1             SC_P_ENET1_RGMII_RXD1              0
+#define SC_P_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA                   SC_P_ENET1_RGMII_RXD1              2
+#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19                   SC_P_ENET1_RGMII_RXD1              3
+#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2             SC_P_ENET1_RGMII_RXD2              0
+#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER             SC_P_ENET1_RGMII_RXD2              1
+#define SC_P_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK                    SC_P_ENET1_RGMII_RXD2              2
+#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20                   SC_P_ENET1_RGMII_RXD2              3
+#define SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3             SC_P_ENET1_RGMII_RXD3              0
+#define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX                      SC_P_ENET1_RGMII_RXD3              1
+#define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK                    SC_P_ENET1_RGMII_RXD3              2
+#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21                   SC_P_ENET1_RGMII_RXD3              3
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB              0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA              0
+
+#endif				/* SC_PADS_H */
-- 
2.16.4

[U-Boot] [PATCH RESEND 03/10] dt-bindings: clock: dt-bindings: pinctrl: add i.MX8QM clocks definition

[Peng Fan]

Add i.MX8QM clocks definition

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/dt-bindings/clock/imx8qm-clock.h | 846 +++++++++++++++++++++++++++++++
 1 file changed, 846 insertions(+)
 create mode 100644 include/dt-bindings/clock/imx8qm-clock.h

diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h
new file mode 100644
index 0000000000..58de976e63
--- /dev/null
+++ b/include/dt-bindings/clock/imx8qm-clock.h
@@ -0,0 +1,846 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H
+#define __DT_BINDINGS_CLOCK_IMX8QM_H
+
+#define IMX8QM_CLK_DUMMY					0
+
+#define IMX8QM_A53_DIV						1
+#define IMX8QM_A53_CLK						2
+#define IMX8QM_A72_DIV						3
+#define IMX8QM_A72_CLK						4
+
+/* SC Clocks. */
+#define IMX8QM_SC_I2C_DIV					5
+#define IMX8QM_SC_I2C_CLK					6
+#define IMX8QM_SC_PID0_DIV					7
+#define IMX8QM_SC_PID0_CLK					8
+#define IMX8QM_SC_PIT_DIV					9
+#define IMX8QM_SC_PIT_CLK					10
+#define IMX8QM_SC_TPM_DIV					11
+#define IMX8QM_SC_TPM_CLK					12
+#define IMX8QM_SC_UART_DIV					13
+#define IMX8QM_SC_UART_CLK					14
+
+/* LSIO */
+#define IMX8QM_PWM0_DIV						15
+#define IMX8QM_PWM0_CLK						16
+#define IMX8QM_PWM1_DIV						17
+#define IMX8QM_PWM1_CLK						18
+#define IMX8QM_PWM2_DIV						19
+#define IMX8QM_PWM2_CLK						20
+#define IMX8QM_PWM3_DIV						21
+#define IMX8QM_PWM3_CLK						22
+#define IMX8QM_PWM4_DIV						23
+#define IMX8QM_PWM4_CLK						24
+#define IMX8QM_PWM5_DIV						26
+#define IMX8QM_PWM5_CLK						27
+#define IMX8QM_PWM6_DIV						28
+#define IMX8QM_PWM6_CLK						29
+#define IMX8QM_PWM7_DIV						30
+#define IMX8QM_PWM7_CLK						31
+#define IMX8QM_FSPI0_DIV					32
+#define IMX8QM_FSPI0_CLK					33
+#define IMX8QM_FSPI1_DIV					34
+#define IMX8QM_FSPI1_CLK					35
+#define IMX8QM_GPT0_DIV						36
+#define IMX8QM_GPT0_CLK						37
+#define IMX8QM_GPT1_DIV						38
+#define IMX8QM_GPT1_CLK						39
+#define IMX8QM_GPT2_DIV						40
+#define IMX8QM_GPT2_CLK						41
+#define IMX8QM_GPT3_DIV						42
+#define IMX8QM_GPT3_CLK						43
+#define IMX8QM_GPT4_DIV						44
+#define IMX8QM_GPT4_CLK						45
+
+/* Connectivity */
+#define IMX8QM_APBHDMA_CLK					46
+#define IMX8QM_GPMI_APB_CLK					47
+#define IMX8QM_GPMI_APB_BCH_CLK				48
+#define IMX8QM_GPMI_BCH_IO_DIV				49
+#define IMX8QM_GPMI_BCH_IO_CLK				50
+#define IMX8QM_GPMI_BCH_DIV				51
+#define IMX8QM_GPMI_BCH_CLK				52
+#define IMX8QM_SDHC0_IPG_CLK				53
+#define IMX8QM_SDHC0_DIV				54
+#define IMX8QM_SDHC0_CLK				55
+#define IMX8QM_SDHC1_IPG_CLK				56
+#define IMX8QM_SDHC1_DIV				57
+#define IMX8QM_SDHC1_CLK				58
+#define IMX8QM_SDHC2_IPG_CLK				59
+#define IMX8QM_SDHC2_DIV				60
+#define IMX8QM_SDHC2_CLK				61
+#define IMX8QM_USB2_OH_AHB_CLK				62
+#define IMX8QM_USB2_OH_IPG_S_CLK			63
+#define IMX8QM_USB2_OH_IPG_S_PL301_CLK			64
+#define IMX8QM_USB2_PHY_IPG_CLK				65
+#define IMX8QM_USB3_IPG_CLK				66
+#define IMX8QM_USB3_CORE_PCLK				67
+#define IMX8QM_USB3_PHY_CLK				68
+#define IMX8QM_USB3_ACLK_DIV				69
+#define IMX8QM_USB3_ACLK				70
+#define IMX8QM_USB3_BUS_DIV				71
+#define IMX8QM_USB3_BUS_CLK				72
+#define IMX8QM_USB3_LPM_DIV				73
+#define IMX8QM_USB3_LPM_CLK				74
+#define IMX8QM_ENET0_AHB_CLK				75
+#define IMX8QM_ENET0_IPG_S_CLK				76
+#define IMX8QM_ENET0_IPG_CLK				77
+#define IMX8QM_ENET0_RGMII_DIV				78
+#define IMX8QM_ENET0_RGMII_TX_CLK			79
+#define IMX8QM_ENET0_ROOT_DIV				80
+#define IMX8QM_ENET0_TX_CLK				81
+#define IMX8QM_ENET0_ROOT_CLK				82
+#define IMX8QM_ENET0_PTP_CLK				83
+#define IMX8QM_ENET0_BYPASS_DIV				84
+#define IMX8QM_ENET1_AHB_CLK				85
+#define IMX8QM_ENET1_IPG_S_CLK				86
+#define IMX8QM_ENET1_IPG_CLK				87
+#define IMX8QM_ENET1_RGMII_DIV				88
+#define IMX8QM_ENET1_RGMII_TX_CLK			89
+#define IMX8QM_ENET1_ROOT_DIV				90
+#define IMX8QM_ENET1_TX_CLK				91
+#define IMX8QM_ENET1_ROOT_CLK				92
+#define IMX8QM_ENET1_PTP_CLK				93
+#define IMX8QM_ENET1_BYPASS_DIV				94
+#define IMX8QM_MLB_CLK					95
+#define IMX8QM_MLB_HCLK					96
+#define IMX8QM_MLB_IPG_CLK				97
+#define IMX8QM_EDMA_CLK					98
+#define IMX8QM_EDMA_IPG_CLK				99
+
+/* DMA */
+#define IMX8QM_SPI0_IPG_CLK				100
+#define IMX8QM_SPI0_DIV					101
+#define IMX8QM_SPI0_CLK					102
+#define IMX8QM_SPI1_IPG_CLK				103
+#define IMX8QM_SPI1_DIV					104
+#define IMX8QM_SPI1_CLK					105
+#define IMX8QM_SPI2_IPG_CLK				106
+#define IMX8QM_SPI2_DIV					107
+#define IMX8QM_SPI2_CLK					108
+#define IMX8QM_SPI3_IPG_CLK				109
+#define IMX8QM_SPI3_DIV					110
+#define IMX8QM_SPI3_CLK					111
+#define IMX8QM_UART0_IPG_CLK				112
+#define IMX8QM_UART0_DIV				113
+#define IMX8QM_UART0_CLK				114
+#define IMX8QM_UART1_IPG_CLK				115
+#define IMX8QM_UART1_DIV				116
+#define IMX8QM_UART1_CLK				117
+#define IMX8QM_UART2_IPG_CLK				118
+#define IMX8QM_UART2_DIV				119
+#define IMX8QM_UART2_CLK				120
+#define IMX8QM_UART3_IPG_CLK				121
+#define IMX8QM_UART3_DIV				122
+#define IMX8QM_UART3_CLK				123
+#define IMX8QM_UART4_IPG_CLK				124
+#define IMX8QM_UART4_DIV				125
+#define IMX8QM_EMVSIM0_IPG_CLK				126
+#define IMX8QM_UART4_CLK				127
+#define IMX8QM_EMVSIM0_DIV				128
+#define IMX8QM_EMVSIM0_CLK				129
+#define IMX8QM_EMVSIM1_IPG_CLK				130
+#define IMX8QM_EMVSIM1_DIV				131
+#define IMX8QM_EMVSIM1_CLK				132
+#define IMX8QM_CAN0_IPG_CHI_CLK				133
+#define IMX8QM_CAN0_IPG_CLK				134
+#define IMX8QM_CAN0_DIV					135
+#define IMX8QM_CAN0_CLK					136
+#define IMX8QM_CAN1_IPG_CHI_CLK				137
+#define IMX8QM_CAN1_IPG_CLK				138
+#define IMX8QM_CAN1_DIV					139
+#define IMX8QM_CAN1_CLK					140
+#define IMX8QM_CAN2_IPG_CHI_CLK				141
+#define IMX8QM_CAN2_IPG_CLK				142
+#define IMX8QM_CAN2_DIV					143
+#define IMX8QM_CAN2_CLK					144
+#define IMX8QM_I2C0_IPG_CLK				145
+#define IMX8QM_I2C0_DIV					146
+#define IMX8QM_I2C0_CLK					147
+#define IMX8QM_I2C1_IPG_CLK				148
+#define IMX8QM_I2C1_DIV					149
+#define IMX8QM_I2C1_CLK					150
+#define IMX8QM_I2C2_IPG_CLK				151
+#define IMX8QM_I2C2_DIV					152
+#define IMX8QM_I2C2_CLK					153
+#define IMX8QM_I2C3_IPG_CLK				154
+#define IMX8QM_I2C3_DIV					155
+#define IMX8QM_I2C3_CLK					156
+#define IMX8QM_I2C4_IPG_CLK				157
+#define IMX8QM_I2C4_DIV					158
+#define IMX8QM_I2C4_CLK					159
+#define IMX8QM_FTM0_IPG_CLK				160
+#define IMX8QM_FTM0_DIV					161
+#define IMX8QM_FTM0_CLK					162
+#define IMX8QM_FTM1_IPG_CLK				163
+#define IMX8QM_FTM1_DIV					164
+#define IMX8QM_FTM1_CLK					165
+#define IMX8QM_ADC0_IPG_CLK				166
+#define IMX8QM_ADC0_DIV					167
+#define IMX8QM_ADC0_CLK					168
+#define IMX8QM_ADC1_IPG_CLK				169
+#define IMX8QM_ADC1_DIV					170
+#define IMX8QM_ADC1_CLK					171
+
+/* Audio */
+#define IMX8QM_AUD_PLL0_DIV				172
+#define IMX8QM_AUD_PLL0					173
+#define IMX8QM_AUD_PLL1_DIV				174
+#define IMX8QM_AUD_PLL1					175
+#define IMX8QM_AUD_AMIX_IPG				182
+#define IMX8QM_AUD_ESAI_0_IPG				183
+#define IMX8QM_AUD_ESAI_1_IPG				184
+#define IMX8QM_AUD_ESAI_0_EXTAL_IPG			185
+#define IMX8QM_AUD_ESAI_1_EXTAL_IPG			186
+#define IMX8QM_AUD_SAI_0_IPG				187
+#define IMX8QM_AUD_SAI_0_IPG_S				188
+#define IMX8QM_AUD_SAI_0_MCLK				189
+#define IMX8QM_AUD_SAI_1_IPG				190
+#define IMX8QM_AUD_SAI_1_IPG_S				191
+#define IMX8QM_AUD_SAI_1_MCLK				192
+#define IMX8QM_AUD_SAI_2_IPG				193
+#define IMX8QM_AUD_SAI_2_IPG_S				194
+#define IMX8QM_AUD_SAI_2_MCLK				195
+#define IMX8QM_AUD_SAI_3_IPG				196
+#define IMX8QM_AUD_SAI_3_IPG_S				197
+#define IMX8QM_AUD_SAI_3_MCLK				198
+#define IMX8QM_AUD_SAI_6_IPG				199
+#define IMX8QM_AUD_SAI_6_IPG_S				200
+#define IMX8QM_AUD_SAI_6_MCLK				201
+#define IMX8QM_AUD_SAI_7_IPG				202
+#define IMX8QM_AUD_SAI_7_IPG_S				203
+#define IMX8QM_AUD_SAI_7_MCLK				204
+#define IMX8QM_AUD_SAI_HDMIRX0_IPG			205
+#define IMX8QM_AUD_SAI_HDMIRX0_IPG_S			206
+#define IMX8QM_AUD_SAI_HDMIRX0_MCLK			207
+#define IMX8QM_AUD_SAI_HDMITX0_IPG			208
+#define IMX8QM_AUD_SAI_HDMITX0_IPG_S			209
+#define IMX8QM_AUD_SAI_HDMITX0_MCLK			210
+#define IMX8QM_AUD_MQS_IPG				211
+#define IMX8QM_AUD_MQS_HMCLK				212
+#define IMX8QM_AUD_GPT5_IPG_S				213
+#define IMX8QM_AUD_GPT5_CLKIN				214
+#define IMX8QM_AUD_GPT5_24M_CLK				215
+#define IMX8QM_AUD_GPT6_IPG_S				216
+#define IMX8QM_AUD_GPT6_CLKIN				217
+#define IMX8QM_AUD_GPT6_24M_CLK				218
+#define IMX8QM_AUD_GPT7_IPG_S				219
+#define IMX8QM_AUD_GPT7_CLKIN				220
+#define IMX8QM_AUD_GPT7_24M_CLK				221
+#define IMX8QM_AUD_GPT8_IPG_S				222
+#define IMX8QM_AUD_GPT8_CLKIN				223
+#define IMX8QM_AUD_GPT8_24M_CLK				224
+#define IMX8QM_AUD_GPT9_IPG_S				225
+#define IMX8QM_AUD_GPT9_CLKIN				226
+#define IMX8QM_AUD_GPT9_24M_CLK				227
+#define IMX8QM_AUD_GPT10_IPG_S				228
+#define IMX8QM_AUD_GPT10_CLKIN				229
+#define IMX8QM_AUD_GPT10_24M_CLK			230
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV		232
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK		233
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV		234
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK		235
+#define IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV		236
+#define IMX8QM_AUD_ACM_AUD_REC_CLK0_CLK		237
+#define IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV		238
+#define IMX8QM_AUD_ACM_AUD_REC_CLK1_CLK		239
+#define IMX8QM_AUD_MCLKOUT0				240
+#define IMX8QM_AUD_MCLKOUT1				241
+#define IMX8QM_AUD_SPDIF_0_TX_CLK			242
+#define IMX8QM_AUD_SPDIF_0_GCLKW			243
+#define IMX8QM_AUD_SPDIF_0_IPG_S			244
+#define IMX8QM_AUD_SPDIF_1_TX_CLK			245
+#define IMX8QM_AUD_SPDIF_1_GCLKW			246
+#define IMX8QM_AUD_SPDIF_1_IPG_S			247
+#define IMX8QM_AUD_ASRC_0_IPG				248
+#define IMX8QM_AUD_ASRC_0_MEM				249
+#define IMX8QM_AUD_ASRC_1_IPG				250
+#define IMX8QM_AUD_ASRC_1_MEM				251
+
+/* VPU */
+#define IMX8QM_VPU_CORE_DIV				252
+#define IMX8QM_VPU_CORE_CLK				253
+#define IMX8QM_VPU_UART_DIV				254
+#define IMX8QM_VPU_UART_CLK				255
+#define IMX8QM_VPU_DDR_DIV				256
+#define IMX8QM_VPU_DDR_CLK				257
+#define IMX8QM_VPU_SYS_DIV				258
+#define IMX8QM_VPU_SYS_CLK				259
+#define IMX8QM_VPU_XUVI_DIV				260
+#define IMX8QM_VPU_XUVI_CLK				261
+
+/* GPU Clocks. */
+#define IMX8QM_GPU0_CORE_DIV				262
+#define IMX8QM_GPU0_CORE_CLK				263
+#define IMX8QM_GPU0_SHADER_DIV				264
+#define IMX8QM_GPU0_SHADER_CLK				265
+#define IMX8QM_GPU1_CORE_DIV				266
+#define IMX8QM_GPU1_CORE_CLK				267
+#define IMX8QM_GPU1_SHADER_DIV				268
+#define IMX8QM_GPU1_SHADER_CLK				269
+
+/* MIPI CSI */
+#define IMX8QM_CSI0_IPG_CLK_S				270
+#define IMX8QM_CSI0_LIS_IPG_CLK				271
+#define IMX8QM_CSI0_APB_CLK				272
+#define IMX8QM_CSI0_I2C0_DIV				273
+#define IMX8QM_CSI0_I2C0_CLK				274
+#define IMX8QM_CSI0_PWM0_DIV				275
+#define IMX8QM_CSI0_PWM0_CLK				276
+#define IMX8QM_CSI0_CORE_DIV				277
+#define IMX8QM_CSI0_CORE_CLK				278
+#define IMX8QM_CSI0_ESC_DIV				279
+#define IMX8QM_CSI0_ESC_CLK				280
+#define IMX8QM_CSI1_IPG_CLK_S				281
+#define IMX8QM_CSI1_LIS_IPG_CLK				282
+#define IMX8QM_CSI1_APB_CLK				283
+#define IMX8QM_CSI1_I2C0_DIV				284
+#define IMX8QM_CSI1_I2C0_CLK				285
+#define IMX8QM_CSI1_PWM0_DIV				286
+#define IMX8QM_CSI1_PWM0_CLK				287
+#define IMX8QM_CSI1_CORE_DIV				288
+#define IMX8QM_CSI1_CORE_CLK				289
+#define IMX8QM_CSI1_ESC_DIV				290
+#define IMX8QM_CSI1_ESC_CLK				291
+
+/* Display */
+#define IMX8QM_DC0_PLL0_DIV				292
+#define IMX8QM_DC0_PLL0_CLK				293
+#define IMX8QM_DC0_PLL1_DIV				294
+#define IMX8QM_DC0_PLL1_CLK				295
+#define IMX8QM_DC0_DISP0_DIV				296
+#define IMX8QM_DC0_DISP0_CLK				297
+#define IMX8QM_DC0_DISP1_DIV				298
+#define IMX8QM_DC0_DISP1_CLK				299
+#define IMX8QM_DC0_BYPASS_0_DIV				300
+#define IMX8QM_DC0_BYPASS_1_DIV				301
+#define IMX8QM_DC0_IRIS_AXI_CLK				302
+#define IMX8AM_DC0_IRIS_MVPL_CLK			303
+#define IMX8QM_DC0_DISP0_MSI_CLK			304
+#define IMX8QM_DC0_LIS_IPG_CLK				305
+#define IMX8QM_DC0_PXL_CMB_APB_CLK			306
+#define IMX8QM_DC0_PRG0_RTRAM_CLK			307
+#define IMX8QM_DC0_PRG1_RTRAM_CLK			308
+#define IMX8QM_DC0_PRG2_RTRAM_CLK			309
+#define IMX8QM_DC0_PRG3_RTRAM_CLK			310
+#define IMX8QM_DC0_PRG4_RTRAM_CLK			311
+#define IMX8QM_DC0_PRG5_RTRAM_CLK			312
+#define IMX8QM_DC0_PRG6_RTRAM_CLK			313
+#define IMX8QM_DC0_PRG7_RTRAM_CLK			314
+#define IMX8QM_DC0_PRG8_RTRAM_CLK			315
+#define IMX8QM_DC0_PRG0_APB_CLK				316
+#define IMX8QM_DC0_PRG1_APB_CLK				317
+#define IMX8QM_DC0_PRG2_APB_CLK				318
+#define IMX8QM_DC0_PRG3_APB_CLK				319
+#define IMX8QM_DC0_PRG4_APB_CLK				320
+#define IMX8QM_DC0_PRG5_APB_CLK				321
+#define IMX8QM_DC0_PRG6_APB_CLK				322
+#define IMX8QM_DC0_PRG7_APB_CLK				323
+#define IMX8QM_DC0_PRG8_APB_CLK				324
+#define IMX8QM_DC0_DPR0_APB_CLK				325
+#define IMX8QM_DC0_DPR1_APB_CLK				326
+#define IMX8QM_DC0_RTRAM0_CLK				327
+#define IMX8QM_DC0_RTRAM1_CLK				328
+#define IMX8QM_DC1_PLL0_DIV				329
+#define IMX8QM_DC1_PLL0_CLK				330
+#define IMX8QM_DC1_PLL1_DIV				331
+#define IMX8QM_DC1_PLL1_CLK				332
+#define IMX8QM_DC1_DISP0_DIV				333
+#define IMX8QM_DC1_DISP0_CLK				334
+#define IMX8QM_DC1_BYPASS_0_DIV				335
+#define IMX8QM_DC1_BYPASS_1_DIV				336
+#define IMX8QM_DC1_DISP1_DIV				337
+#define IMX8QM_DC1_DISP1_CLK				338
+#define IMX8QM_DC1_IRIS_AXI_CLK				339
+#define IMX8AM_DC1_IRIS_MVPL_CLK			340
+#define IMX8QM_DC1_DISP0_MSI_CLK			341
+#define IMX8QM_DC1_LIS_IPG_CLK				342
+#define IMX8QM_DC1_PXL_CMB_APB_CLK			343
+#define IMX8QM_DC1_PRG0_RTRAM_CLK			344
+#define IMX8QM_DC1_PRG1_RTRAM_CLK			345
+#define IMX8QM_DC1_PRG2_RTRAM_CLK			346
+#define IMX8QM_DC1_PRG3_RTRAM_CLK			347
+#define IMX8QM_DC1_PRG4_RTRAM_CLK			348
+#define IMX8QM_DC1_PRG5_RTRAM_CLK			349
+#define IMX8QM_DC1_PRG6_RTRAM_CLK			350
+#define IMX8QM_DC1_PRG7_RTRAM_CLK			351
+#define IMX8QM_DC1_PRG8_RTRAM_CLK			352
+#define IMX8QM_DC1_PRG0_APB_CLK				353
+#define IMX8QM_DC1_PRG1_APB_CLK				354
+#define IMX8QM_DC1_PRG2_APB_CLK				355
+#define IMX8QM_DC1_PRG3_APB_CLK				356
+#define IMX8QM_DC1_PRG4_APB_CLK				357
+#define IMX8QM_DC1_PRG5_APB_CLK				358
+#define IMX8QM_DC1_PRG6_APB_CLK				359
+#define IMX8QM_DC1_PRG7_APB_CLK				360
+#define IMX8QM_DC1_PRG8_APB_CLK				361
+#define IMX8QM_DC1_DPR0_APB_CLK				362
+#define IMX8QM_DC1_DPR1_APB_CLK				363
+#define IMX8QM_DC1_RTRAM0_CLK				364
+#define IMX8QM_DC1_RTRAM1_CLK				365
+
+/* DRC */
+#define IMX8QM_DRC0_PLL0_DIV				366
+#define IMX8QM_DRC0_PLL0_CLK				367
+#define IMX8QM_DRC0_DIV					368
+#define IMX8QM_DRC0_CLK					369
+#define IMX8QM_DRC1_PLL0_DIV				370
+#define IMX8QM_DRC1_PLL0_CLK				371
+#define IMX8QM_DRC1_DIV					372
+#define IMX8QM_DRC1_CLK					373
+
+/* HDMI */
+#define IMX8QM_HDMI_AV_PLL_DIV				374
+#define IMX8QM_HDMI_AV_PLL_CLK				375
+#define IMX8QM_HDMI_I2S_BYPASS_CLK			376
+#define IMX8QM_HDMI_I2C0_DIV				377
+#define IMX8QM_HDMI_I2C0_CLK				378
+#define IMX8QM_HDMI_PXL_DIV				379
+#define IMX8QM_HDMI_PXL_CLK				380
+#define IMX8QM_HDMI_PXL_LINK_DIV			381
+#define IMX8QM_HDMI_PXL_LINK_CLK			382
+#define IMX8QM_HDMI_PXL_MUX_DIV				383
+#define IMX8QM_HDMI_PXL_MUX_CLK				384
+#define IMX8QM_HDMI_I2S_DIV				385
+#define IMX8QM_HDMI_I2S_CLK				386
+#define IMX8QM_HDMI_HDP_CORE_DIV			387
+#define IMX8QM_HDMI_HDP_CORE_CLK			388
+#define IMX8QM_HDMI_I2C_IPG_S_CLK			389
+#define IMX8QM_HDMI_I2C_IPG_CLK				390
+#define IMX8QM_HDMI_PWM_IPG_S_CLK			391
+#define IMX8QM_HDMI_PWM_IPG_CLK				392
+#define IMX8QM_HDMI_PWM_32K_CLK				393
+#define IMX8QM_HDMI_GPIO_IPG_CLK			394
+#define IMX8QM_HDMI_PXL_LINK_SLV_ODD_CLK		395
+#define IMX8QM_HDMI_PXL_LINK_SLV_EVEN_CLK		396
+#define IMX8QM_HDMI_LIS_IPG_CLK				397
+#define IMX8QM_HDMI_MSI_HCLK				398
+#define IMX8QM_HDMI_PXL_EVEN_CLK			399
+#define IMX8QM_HDMI_HDP_CLK				400
+#define IMX8QM_HDMI_PXL_DBL_CLK				401
+#define IMX8QM_HDMI_APB_CLK				402
+#define IMX8QM_HDMI_PXL_LPCG_CLK			403
+#define IMX8QM_HDMI_HDP_PHY_CLK				404
+#define IMX8QM_HDMI_IPG_DIV				405
+#define IMX8QM_HDMI_VIF_CLK				406
+#define IMX8QM_HDMI_DIG_PLL_DIV				407
+#define IMX8QM_HDMI_DIG_PLL_CLK				408
+#define IMX8QM_HDMI_APB_MUX_CSR_CLK			409
+#define IMX8QM_HDMI_APB_MUX_CTRL_CLK			410
+
+/* RX-HDMI */
+#define IMX8QM_HDMI_RX_I2S_BYPASS_CLK			411
+#define IMX8QM_HDMI_RX_BYPASS_CLK			412
+#define IMX8QM_HDMI_RX_SPDIF_BYPASS_CLK			413
+#define IMX8QM_HDMI_RX_I2C0_DIV				414
+#define IMX8QM_HDMI_RX_I2C0_CLK				415
+#define IMX8QM_HDMI_RX_SPDIF_DIV			416
+#define IMX8QM_HDMI_RX_SPDIF_CLK			417
+#define IMX8QM_HDMI_RX_HD_REF_DIV			418
+#define IMX8QM_HDMI_RX_HD_REF_CLK			419
+#define IMX8QM_HDMI_RX_HD_CORE_DIV			420
+#define IMX8QM_HDMI_RX_HD_CORE_CLK			421
+#define IMX8QM_HDMI_RX_PXL_DIV				422
+#define IMX8QM_HDMI_RX_PXL_CLK				423
+#define IMX8QM_HDMI_RX_I2S_DIV				424
+#define IMX8QM_HDMI_RX_I2S_CLK				425
+#define IMX8QM_HDMI_RX_PWM_DIV				426
+#define IMX8QM_HDMI_RX_PWM_CLK				427
+
+/* LVDS */
+#define IMX8QM_LVDS0_BYPASS_CLK				428
+#define IMX8QM_LVDS0_PIXEL_DIV				429
+#define IMX8QM_LVDS0_PIXEL_CLK				430
+#define IMX8QM_LVDS0_PHY_DIV				431
+#define IMX8QM_LVDS0_PHY_CLK				432
+#define IMX8QM_LVDS0_I2C0_IPG_CLK			433
+#define IMX8QM_LVDS0_I2C0_DIV				434
+#define IMX8QM_LVDS0_I2C0_CLK				435
+#define IMX8QM_LVDS0_I2C1_IPG_CLK			436
+#define IMX8QM_LVDS0_I2C1_DIV				437
+#define IMX8QM_LVDS0_I2C1_CLK				438
+#define IMX8QM_LVDS0_PWM0_IPG_CLK			439
+#define IMX8QM_LVDS0_PWM0_DIV				440
+#define IMX8QM_LVDS0_PWM0_CLK				441
+#define IMX8QM_LVDS0_GPIO_IPG_CLK			444
+#define IMX8QM_LVDS1_BYPASS_DIV				445
+#define IMX8QM_LVDS1_BYPASS_CLK				446
+#define IMX8QM_LVDS1_PIXEL_DIV				447
+#define IMX8QM_LVDS1_PIXEL_CLK				448
+#define IMX8QM_LVDS1_PHY_DIV				449
+#define IMX8QM_LVDS1_PHY_CLK				450
+#define IMX8QM_LVDS1_I2C0_IPG_CLK			451
+#define IMX8QM_LVDS1_I2C0_DIV				452
+#define IMX8QM_LVDS1_I2C0_CLK				453
+#define IMX8QM_LVDS1_I2C1_IPG_CLK			454
+#define IMX8QM_LVDS1_I2C1_DIV				455
+#define IMX8QM_LVDS1_I2C1_CLK				456
+#define IMX8QM_LVDS1_PWM0_IPG_CLK			457
+#define IMX8QM_LVDS1_PWM0_DIV				458
+#define IMX8QM_LVDS1_PWM0_CLK				459
+#define IMX8QM_LVDS1_GPIO_IPG_CLK			462
+
+/* MIPI */
+#define IMX8QM_MIPI0_BYPASS_CLK				465
+#define IMX8QM_MIPI0_I2C0_DIV				466
+#define IMX8QM_MIPI0_I2C0_CLK				467
+#define IMX8QM_MIPI0_I2C1_DIV				468
+#define IMX8QM_MIPI0_I2C1_CLK				469
+#define IMX8QM_MIPI0_PWM0_DIV				470
+#define IMX8QM_MIPI0_PWM0_CLK				471
+#define IMX8QM_MIPI0_DSI_TX_ESC_DIV			472
+#define IMX8QM_MIPI0_DSI_TX_ESC_CLK			473
+#define IMX8QM_MIPI0_DSI_RX_ESC_DIV			474
+#define IMX8QM_MIPI0_DSI_RX_ESC_CLK			475
+#define IMX8QM_MIPI0_PXL_DIV				476
+#define IMX8QM_MIPI0_PXL_CLK				477
+#define IMX8QM_MIPI1_BYPASS_CLK				479
+#define IMX8QM_MIPI1_I2C0_DIV				480
+#define IMX8QM_MIPI1_I2C0_CLK				481
+#define IMX8QM_MIPI1_I2C1_DIV				482
+#define IMX8QM_MIPI1_I2C1_CLK				483
+#define IMX8QM_MIPI1_PWM0_DIV				484
+#define IMX8QM_MIPI1_PWM0_CLK				485
+#define IMX8QM_MIPI1_DSI_TX_ESC_DIV			486
+#define IMX8QM_MIPI1_DSI_TX_ESC_CLK			487
+#define IMX8QM_MIPI1_DSI_RX_ESC_DIV			488
+#define IMX8QM_MIPI1_DSI_RX_ESC_CLK			489
+#define IMX8QM_MIPI1_PXL_DIV				490
+#define IMX8QM_MIPI1_PXL_CLK				491
+
+/* Imaging */
+#define IMX8QM_IMG_JPEG_ENC_IPG_CLK			492
+#define IMX8QM_IMG_JPEG_ENC_CLK				493
+#define IMX8QM_IMG_JPEG_DEC_IPG_CLK			494
+#define IMX8QM_IMG_JPEG_DEC_CLK				495
+#define IMX8QM_IMG_PXL_LINK_DC0_CLK			496
+#define IMX8QM_IMG_PXL_LINK_DC1_CLK			497
+#define IMX8QM_IMG_PXL_LINK_CSI0_CLK			498
+#define IMX8QM_IMG_PXL_LINK_CSI1_CLK			499
+#define IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK			500
+#define IMX8QM_IMG_PDMA_0_CLK				501
+#define IMX8QM_IMG_PDMA_1_CLK				502
+#define IMX8QM_IMG_PDMA_2_CLK				503
+#define IMX8QM_IMG_PDMA_3_CLK				504
+#define IMX8QM_IMG_PDMA_4_CLK				505
+#define IMX8QM_IMG_PDMA_5_CLK				506
+#define IMX8QM_IMG_PDMA_6_CLK				507
+#define IMX8QM_IMG_PDMA_7_CLK				508
+
+/* HSIO */
+#define IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK		509
+#define IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK		510
+#define IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK		511
+#define IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK		512
+#define IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK		513
+#define IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK		514
+#define IMX8QM_HSIO_PCIE_X1_PER_CLK			515
+#define IMX8QM_HSIO_PCIE_X2_PER_CLK			516
+#define IMX8QM_HSIO_SATA_PER_CLK			517
+#define IMX8QM_HSIO_PHY_X1_PER_CLK			518
+#define IMX8QM_HSIO_PHY_X2_PER_CLK			519
+#define IMX8QM_HSIO_MISC_PER_CLK			520
+#define IMX8QM_HSIO_PHY_X1_APB_CLK			521
+#define IMX8QM_HSIO_PHY_X2_APB_0_CLK		522
+#define IMX8QM_HSIO_PHY_X2_APB_1_CLK		523
+#define IMX8QM_HSIO_SATA_CLK				524
+#define IMX8QM_HSIO_GPIO_CLK				525
+#define IMX8QM_HSIO_PHY_X1_PCLK				526
+#define IMX8QM_HSIO_PHY_X2_PCLK_0			527
+#define IMX8QM_HSIO_PHY_X2_PCLK_1			528
+#define IMX8QM_HSIO_SATA_EPCS_RX_CLK		529
+#define IMX8QM_HSIO_SATA_EPCS_TX_CLK		530
+
+/* M4 */
+#define IMX8QM_M4_0_CORE_DIV				531
+#define IMX8QM_M4_0_CORE_CLK				532
+#define IMX8QM_M4_0_I2C_DIV				533
+#define IMX8QM_M4_0_I2C_CLK				534
+#define IMX8QM_M4_0_PIT_DIV				535
+#define IMX8QM_M4_0_PIT_CLK				536
+#define IMX8QM_M4_0_TPM_DIV				537
+#define IMX8QM_M4_0_TPM_CLK				538
+#define IMX8QM_M4_0_UART_DIV				539
+#define IMX8QM_M4_0_UART_CLK				540
+#define IMX8QM_M4_0_WDOG_DIV				541
+#define IMX8QM_M4_0_WDOG_CLK				542
+#define IMX8QM_M4_1_CORE_DIV				543
+#define IMX8QM_M4_1_CORE_CLK				544
+#define IMX8QM_M4_1_I2C_DIV				545
+#define IMX8QM_M4_1_I2C_CLK				546
+#define IMX8QM_M4_1_PIT_DIV				547
+#define IMX8QM_M4_1_PIT_CLK				548
+#define IMX8QM_M4_1_TPM_DIV				549
+#define IMX8QM_M4_1_TPM_CLK				550
+#define IMX8QM_M4_1_UART_DIV				551
+#define IMX8QM_M4_1_UART_CLK				552
+#define IMX8QM_M4_1_WDOG_DIV				553
+#define IMX8QM_M4_1_WDOG_CLK				554
+
+/* IPG clocks */
+#define IMX8QM_24MHZ					555
+#define IMX8QM_GPT_3M					556
+#define IMX8QM_IPG_DMA_CLK_ROOT				557
+#define IMX8QM_IPG_AUD_CLK_ROOT				558
+#define IMX8QM_IPG_CONN_CLK_ROOT			559
+#define IMX8QM_AHB_CONN_CLK_ROOT			560
+#define IMX8QM_AXI_CONN_CLK_ROOT			561
+#define IMX8QM_IPG_MIPI_CSI_CLK_ROOT			562
+#define IMX8QM_DC_AXI_EXT_CLK				563
+#define IMX8QM_DC_AXI_INT_CLK				564
+#define IMX8QM_DC_CFG_CLK				565
+#define IMX8QM_HDMI_IPG_CLK				566
+#define IMX8QM_LVDS_IPG_CLK				567
+#define IMX8QM_IMG_AXI_CLK				568
+#define IMX8QM_IMG_IPG_CLK				569
+#define IMX8QM_IMG_PXL_CLK				570
+#define IMX8QM_CSI0_I2C0_IPG_CLK			571
+#define IMX8QM_CSI0_PWM0_IPG_CLK			572
+#define IMX8QM_CSI1_I2C0_IPG_CLK			573
+#define IMX8QM_CSI1_PWM0_IPG_CLK			574
+#define IMX8QM_DC0_DPR0_B_CLK				575
+#define IMX8QM_DC0_DPR1_B_CLK				576
+#define IMX8QM_DC1_DPR0_B_CLK				577
+#define IMX8QM_DC1_DPR1_B_CLK				578
+#define IMX8QM_32KHZ					579
+#define IMX8QM_HSIO_AXI_CLK				580
+#define IMX8QM_HSIO_PER_CLK				581
+#define IMX8QM_HDMI_RX_GPIO_IPG_S_CLK			582
+#define IMX8QM_HDMI_RX_PWM_IPG_S_CLK			583
+#define IMX8QM_HDMI_RX_PWM_IPG_CLK			584
+#define IMX8QM_HDMI_RX_I2C_DIV_CLK			585
+#define IMX8QM_HDMI_RX_I2C_IPG_S_CLK			586
+#define IMX8QM_HDMI_RX_I2C_IPG_CLK			587
+#define IMX8QM_HDMI_RX_SINK_PCLK			588
+#define IMX8QM_HDMI_RX_SINK_SCLK			589
+#define IMX8QM_HDMI_RX_PXL_ENC_CLK			590
+#define IMX8QM_HDMI_RX_IPG_CLK				591
+
+/* ACM */
+#define IMX8QM_HDMI_RX_MCLK			592
+#define IMX8QM_EXT_AUD_MCLK0			593
+#define IMX8QM_EXT_AUD_MCLK1			594
+#define IMX8QM_ESAI0_RX_CLK			595
+#define IMX8QM_ESAI0_RX_HF_CLK			596
+#define IMX8QM_ESAI0_TX_CLK			597
+#define IMX8QM_ESAI0_TX_HF_CLK			598
+#define IMX8QM_ESAI1_RX_CLK			599
+#define IMX8QM_ESAI1_RX_HF_CLK			600
+#define IMX8QM_ESAI1_TX_CLK			601
+#define IMX8QM_ESAI1_TX_HF_CLK			602
+#define IMX8QM_SPDIF0_RX			603
+#define IMX8QM_SPDIF1_RX			604
+#define IMX8QM_SAI0_RX_BCLK			605
+#define IMX8QM_SAI0_TX_BCLK			606
+#define IMX8QM_SAI1_RX_BCLK			607
+#define IMX8QM_SAI1_TX_BCLK			608
+#define IMX8QM_SAI2_RX_BCLK			609
+#define IMX8QM_SAI3_RX_BCLK			610
+#define IMX8QM_HDMI_RX_SAI0_RX_BCLK		611
+#define IMX8QM_SAI6_RX_BCLK			612
+#define IMX8QM_HDMI_TX_SAI0_TX_BCLK		613
+
+#define IMX8QM_ACM_AUD_CLK0_SEL		614
+#define IMX8QM_ACM_AUD_CLK0_CLK		615
+#define IMX8QM_ACM_AUD_CLK1_SEL		616
+#define IMX8QM_ACM_AUD_CLK1_CLK		617
+#define IMX8QM_ACM_MCLKOUT0_SEL		618
+#define IMX8QM_ACM_MCLKOUT0_CLK		619
+#define IMX8QM_ACM_MCLKOUT1_SEL		620
+#define IMX8QM_ACM_MCLKOUT1_CLK		621
+#define IMX8QM_ACM_ASRC0_MUX_CLK_SEL		622
+#define IMX8QM_ACM_ASRC0_MUX_CLK_CLK		623
+#define IMX8QM_ACM_ASRC1_MUX_CLK_SEL		624
+#define IMX8QM_ACM_ASRC1_MUX_CLK_CLK		625
+#define IMX8QM_ACM_ESAI0_MCLK_SEL		626
+#define IMX8QM_ACM_ESAI0_MCLK_CLK		627
+#define IMX8QM_ACM_ESAI1_MCLK_SEL		628
+#define IMX8QM_ACM_ESAI1_MCLK_CLK		629
+#define IMX8QM_ACM_GPT0_MUX_CLK_SEL		630
+#define IMX8QM_ACM_GPT0_MUX_CLK_CLK		631
+#define IMX8QM_ACM_GPT1_MUX_CLK_SEL		632
+#define IMX8QM_ACM_GPT1_MUX_CLK_CLK		633
+#define IMX8QM_ACM_GPT2_MUX_CLK_SEL		634
+#define IMX8QM_ACM_GPT2_MUX_CLK_CLK		635
+#define IMX8QM_ACM_GPT3_MUX_CLK_SEL		636
+#define IMX8QM_ACM_GPT3_MUX_CLK_CLK		637
+#define IMX8QM_ACM_GPT4_MUX_CLK_SEL		638
+#define IMX8QM_ACM_GPT4_MUX_CLK_CLK		639
+#define IMX8QM_ACM_GPT5_MUX_CLK_SEL		640
+#define IMX8QM_ACM_GPT5_MUX_CLK_CLK		641
+#define IMX8QM_ACM_SAI0_MCLK_SEL		642
+#define IMX8QM_ACM_SAI0_MCLK_CLK		643
+#define IMX8QM_ACM_SAI1_MCLK_SEL		644
+#define IMX8QM_ACM_SAI1_MCLK_CLK		645
+#define IMX8QM_ACM_SAI2_MCLK_SEL		646
+#define IMX8QM_ACM_SAI2_MCLK_CLK		647
+#define IMX8QM_ACM_SAI3_MCLK_SEL		648
+#define IMX8QM_ACM_SAI3_MCLK_CLK		649
+#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_SEL	650
+#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_CLK	651
+#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL	652
+#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_CLK	653
+#define IMX8QM_ACM_SAI6_MCLK_SEL		654
+#define IMX8QM_ACM_SAI6_MCLK_CLK		655
+#define IMX8QM_ACM_SAI7_MCLK_SEL		656
+#define IMX8QM_ACM_SAI7_MCLK_CLK		657
+#define IMX8QM_ACM_SPDIF0_TX_CLK_SEL		658
+#define IMX8QM_ACM_SPDIF0_TX_CLK_CLK		659
+#define IMX8QM_ACM_SPDIF1_TX_CLK_SEL		660
+#define IMX8QM_ACM_SPDIF1_TX_CLK_CLK		661
+#define IMX8QM_ACM_MQS_TX_CLK_SEL		662
+#define IMX8QM_ACM_MQS_TX_CLK_CLK		663
+
+#define IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL	664
+#define IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK	665
+#define IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL	666
+#define IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK	667
+#define IMX8QM_ENET0_REF_50MHZ_CLK			668
+#define IMX8QM_ENET1_REF_50MHZ_CLK			669
+#define IMX8QM_ENET_25MHZ_CLK				670
+#define IMX8QM_ENET_125MHZ_CLK				671
+#define IMX8QM_ENET0_REF_DIV				672
+#define IMX8QM_ENET0_REF_CLK				673
+#define IMX8QM_ENET1_REF_DIV				674
+#define IMX8QM_ENET1_REF_CLK				675
+#define IMX8QM_ENET0_RMII_TX_CLK			676
+#define IMX8QM_ENET1_RMII_TX_CLK			677
+#define IMX8QM_ENET0_RMII_TX_SEL			678
+#define IMX8QM_ENET1_RMII_TX_SEL			679
+#define IMX8QM_ENET0_RMII_RX_CLK			680
+#define IMX8QM_ENET1_RMII_RX_CLK			681
+
+#define IMX8QM_KPP_CLK					683
+#define IMX8QM_GPT0_HF_CLK				684
+#define IMX8QM_GPT0_IPG_S_CLK				685
+#define IMX8QM_GPT0_IPG_SLV_CLK				686
+#define IMX8QM_GPT0_IPG_MSTR_CLK			687
+#define IMX8QM_GPT1_HF_CLK				688
+#define IMX8QM_GPT1_IPG_S_CLK				689
+#define IMX8QM_GPT1_IPG_SLV_CLK				690
+#define IMX8QM_GPT1_IPG_MSTR_CLK			691
+#define IMX8QM_GPT2_HF_CLK				692
+#define IMX8QM_GPT2_IPG_S_CLK				693
+#define IMX8QM_GPT2_IPG_SLV_CLK				694
+#define IMX8QM_GPT2_IPG_MSTR_CLK			695
+#define IMX8QM_GPT3_HF_CLK				696
+#define IMX8QM_GPT3_IPG_S_CLK				697
+#define IMX8QM_GPT3_IPG_SLV_CLK				698
+#define IMX8QM_GPT3_IPG_MSTR_CLK			699
+#define IMX8QM_GPT4_HF_CLK				700
+#define IMX8QM_GPT4_IPG_S_CLK				701
+#define IMX8QM_GPT4_IPG_SLV_CLK				702
+#define IMX8QM_GPT4_IPG_MSTR_CLK			703
+#define IMX8QM_PWM0_HF_CLK				704
+#define IMX8QM_PWM0_IPG_S_CLK				705
+#define IMX8QM_PWM0_IPG_SLV_CLK				706
+#define IMX8QM_PWM0_IPG_MSTR_CLK			707
+#define IMX8QM_PWM1_HF_CLK				708
+#define IMX8QM_PWM1_IPG_S_CLK				709
+#define IMX8QM_PWM1_IPG_SLV_CLK				710
+#define IMX8QM_PWM1_IPG_MSTR_CLK			711
+#define IMX8QM_PWM2_HF_CLK				712
+#define IMX8QM_PWM2_IPG_S_CLK				713
+#define IMX8QM_PWM2_IPG_SLV_CLK				714
+#define IMX8QM_PWM2_IPG_MSTR_CLK			715
+#define IMX8QM_PWM3_HF_CLK				716
+#define IMX8QM_PWM3_IPG_S_CLK				717
+#define IMX8QM_PWM3_IPG_SLV_CLK				718
+#define IMX8QM_PWM3_IPG_MSTR_CLK			719
+#define IMX8QM_PWM4_HF_CLK				720
+#define IMX8QM_PWM4_IPG_S_CLK				721
+#define IMX8QM_PWM4_IPG_SLV_CLK				722
+#define IMX8QM_PWM4_IPG_MSTR_CLK			723
+#define IMX8QM_PWM5_HF_CLK				724
+#define IMX8QM_PWM5_IPG_S_CLK				725
+#define IMX8QM_PWM5_IPG_SLV_CLK				726
+#define IMX8QM_PWM5_IPG_MSTR_CLK			727
+#define IMX8QM_PWM6_HF_CLK				728
+#define IMX8QM_PWM6_IPG_S_CLK				729
+#define IMX8QM_PWM6_IPG_SLV_CLK				730
+#define IMX8QM_PWM6_IPG_MSTR_CLK			731
+#define IMX8QM_PWM7_HF_CLK				732
+#define IMX8QM_PWM7_IPG_S_CLK				733
+#define IMX8QM_PWM7_IPG_SLV_CLK				734
+#define IMX8QM_PWM7_IPG_MSTR_CLK			735
+#define IMX8QM_FSPI0_HCLK				736
+#define IMX8QM_FSPI0_IPG_CLK				737
+#define IMX8QM_FSPI0_IPG_S_CLK				738
+#define IMX8QM_FSPI1_HCLK				736
+#define IMX8QM_FSPI1_IPG_CLK				737
+#define IMX8QM_FSPI1_IPG_S_CLK				738
+#define IMX8QM_GPIO0_IPG_S_CLK				739
+#define IMX8QM_GPIO1_IPG_S_CLK				740
+#define IMX8QM_GPIO2_IPG_S_CLK				741
+#define IMX8QM_GPIO3_IPG_S_CLK				742
+#define IMX8QM_GPIO4_IPG_S_CLK				743
+#define IMX8QM_GPIO5_IPG_S_CLK				744
+#define IMX8QM_GPIO6_IPG_S_CLK				745
+#define IMX8QM_GPIO7_IPG_S_CLK				746
+#define IMX8QM_ROMCP_CLK				747
+#define IMX8QM_ROMCP_REG_CLK				748
+#define IMX8QM_96KROM_CLK				749
+#define IMX8QM_OCRAM_MEM_CLK				750
+#define IMX8QM_OCRAM_CTRL_CLK				751
+#define IMX8QM_LSIO_BUS_CLK				752
+#define IMX8QM_LSIO_MEM_CLK				753
+#define IMX8QM_LVDS0_LIS_IPG_CLK			754
+#define IMX8QM_LVDS1_LIS_IPG_CLK			755
+#define IMX8QM_MIPI0_LIS_IPG_CLK			756
+#define IMX8QM_MIPI0_I2C0_IPG_S_CLK			757
+#define IMX8QM_MIPI0_I2C0_IPG_CLK			758
+#define IMX8QM_MIPI0_I2C1_IPG_S_CLK			759
+#define IMX8QM_MIPI0_I2C1_IPG_CLK			760
+#define IMX8QM_MIPI0_CLK_ROOT				761
+#define IMX8QM_MIPI1_LIS_IPG_CLK			762
+#define IMX8QM_MIPI1_I2C0_IPG_S_CLK			763
+#define IMX8QM_MIPI1_I2C0_IPG_CLK			764
+#define IMX8QM_MIPI1_I2C1_IPG_S_CLK			765
+#define IMX8QM_MIPI1_I2C1_IPG_CLK			766
+#define IMX8QM_MIPI1_CLK_ROOT				767
+#define IMX8QM_DC0_DISP0_SEL				768
+#define IMX8QM_DC0_DISP1_SEL				769
+#define IMX8QM_DC1_DISP0_SEL				770
+#define IMX8QM_DC1_DISP1_SEL				771
+
+/* CM40 */
+#define IMX8QM_CM40_IPG_CLK				772
+#define IMX8QM_CM40_I2C_DIV				773
+#define IMX8QM_CM40_I2C_CLK				774
+#define IMX8QM_CM40_I2C_IPG_CLK				775
+
+/* CM41 */
+#define IMX8QM_CM41_IPG_CLK				776
+#define IMX8QM_CM41_I2C_DIV				777
+#define IMX8QM_CM41_I2C_CLK				778
+#define IMX8QM_CM41_I2C_IPG_CLK				779
+
+#define IMX8QM_HDMI_PXL_SEL				780
+#define IMX8QM_HDMI_PXL_LINK_SEL			781
+#define IMX8QM_HDMI_PXL_MUX_SEL				782
+#define IMX8QM_HDMI_AV_PLL_BYPASS_CLK			783
+
+#define IMX8QM_HDMI_RX_PXL_SEL				784
+#define IMX8QM_HDMI_RX_HD_REF_SEL			785
+#define IMX8QM_HDMI_RX_HD_CORE_SEL			786
+#define IMX8QM_HDMI_RX_DIG_PLL_CLK			787
+
+#define IMX8QM_LSIO_MU5A_IPG_S_CLK			788
+#define IMX8QM_LSIO_MU5A_IPG_CLK			789
+#define IMX8QM_LSIO_MU6A_IPG_S_CLK			790
+#define IMX8QM_LSIO_MU6A_IPG_CLK			791
+
+/* DSP */
+#define IMX8QM_AUD_DSP_ADB_ACLK				792
+#define IMX8QM_AUD_DSP_IPG				793
+#define IMX8QM_AUD_DSP_CORE_CLK				794
+#define IMX8QM_AUD_OCRAM_IPG				795
+
+#define IMX8QM_CLK_END					796
+
+#endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */
-- 
2.16.4

[U-Boot] [PATCH RESEND 04/10] arm: dts: introduce dtsi for i.MX8QM

[Peng Fan]

Introduce basic dtsi for i.MX8QM, only support SDHC/FEC/LPUART.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/dts/fsl-imx8qm.dtsi | 400 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 400 insertions(+)
 create mode 100644 arch/arm/dts/fsl-imx8qm.dtsi

diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
new file mode 100644
index 0000000000..b39c40bd98
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -0,0 +1,400 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "fsl-imx8-ca53.dtsi"
+#include <dt-bindings/clock/imx8qm-clock.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <dt-bindings/soc/imx8_pd.h>
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "fsl,imx8qm";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &fec1;
+		ethernet1 = &fec2;
+		serial0 = &lpuart0;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
+	};
+
+	memory at 80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x40000000>;
+		      /* DRAM space - 1, size : 1 GB DRAM */
+	};
+
+	gic: interrupt-controller at 51a00000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x51b00000 0 0xC0000>, /* GICR */
+		      <0x0 0x52000000 0 0x2000>,  /* GICC */
+		      <0x0 0x52010000 0 0x1000>,  /* GICH */
+		      <0x0 0x52020000 0 0x20000>; /* GICV */
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9
+			(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-parent = <&gic>;
+	};
+
+	mu: mu at 5d1c0000 {
+		compatible = "fsl,imx8-mu";
+		reg = <0x0 0x5d1c0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		fsl,scu_ap_mu_id = <0>;
+		status = "okay";
+
+		clk: clk {
+			compatible = "fsl,imx8qm-clk";
+			#clock-cells = <1>;
+		};
+
+		iomuxc: iomuxc {
+			compatible = "fsl,imx8qm-iomuxc";
+		};
+	};
+
+	imx8qm-pm {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pd_lsio: PD_LSIO {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_LAST>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_lsio_gpio0: PD_LSIO_GPIO_0 {
+				reg = <SC_R_GPIO_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio1: PD_LSIO_GPIO_1 {
+				reg = <SC_R_GPIO_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio2: PD_LSIO_GPIO_2 {
+				reg = <SC_R_GPIO_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio3: PD_LSIO_GPIO_3 {
+				reg = <SC_R_GPIO_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio4: PD_LSIO_GPIO_4 {
+				reg = <SC_R_GPIO_4>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio5: PD_LSIO_GPIO_5{
+				reg = <SC_R_GPIO_5>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio6:PD_LSIO_GPIO_6 {
+				reg = <SC_R_GPIO_6>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio7: PD_LSIO_GPIO_7 {
+				reg = <SC_R_GPIO_7>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+		};
+
+		pd_conn: PD_CONN {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_LAST>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_conn_sdch0: PD_CONN_SDHC_0 {
+				reg = <SC_R_SDHC_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_sdch1: PD_CONN_SDHC_1 {
+				reg = <SC_R_SDHC_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_sdch2: PD_CONN_SDHC_2 {
+				reg = <SC_R_SDHC_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_enet0: PD_CONN_ENET_0 {
+				reg = <SC_R_ENET_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+				wakeup-irq = <258>;
+			};
+			pd_conn_enet1: PD_CONN_ENET_1 {
+				reg = <SC_R_ENET_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+				fsl,wakeup_irq = <262>;
+			};
+		};
+
+		pd_dma: PD_DMA {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_LAST>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_dma_lpi2c0: PD_DMA_I2C_0 {
+				reg = <SC_R_I2C_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c1: PD_DMA_I2C_1 {
+				reg = <SC_R_I2C_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c2:PD_DMA_I2C_2 {
+				reg = <SC_R_I2C_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c3: PD_DMA_I2C_3 {
+				reg = <SC_R_I2C_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c4: PD_DMA_I2C_4 {
+				reg = <SC_R_I2C_4>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpuart0: PD_DMA_UART0 {
+				reg = <SC_R_UART_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				wakeup-irq = <345>;
+			};
+		};
+	};
+
+	gpio0: gpio at 5d080000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d080000 0x0 0x10000>;
+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		power-domains = <&pd_lsio_gpio0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio1: gpio at 5d090000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d090000 0x0 0x10000>;
+		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		power-domains = <&pd_lsio_gpio1>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio2: gpio at 5d0a0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0a0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		power-domains = <&pd_lsio_gpio2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio3: gpio at 5d0b0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0b0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		power-domains = <&pd_lsio_gpio3>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio4: gpio at 5d0c0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0c0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		power-domains = <&pd_lsio_gpio4>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio5: gpio at 5d0d0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0d0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		power-domains = <&pd_lsio_gpio5>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio6: gpio at 5d0e0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0e0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		power-domains = <&pd_lsio_gpio6>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio7: gpio at 5d0f0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0f0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		power-domains = <&pd_lsio_gpio7>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	lpuart0: serial at 5a060000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a060000 0x0 0x1000>;
+		interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QM_UART0_CLK>,
+			 <&clk IMX8QM_UART0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_UART0_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpuart0>;
+		status = "disabled";
+	};
+
+	usdhc1: usdhc at 5b010000 {
+		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0x5b010000 0x0 0x10000>;
+		clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
+			 <&clk IMX8QM_SDHC0_CLK>,
+			 <&clk IMX8QM_CLK_DUMMY>;
+		clock-names = "ipg", "per", "ahb";
+		assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
+		assigned-clock-rates = <400000000>;
+		power-domains = <&pd_conn_sdch0>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		status = "disabled";
+	};
+
+	usdhc2: usdhc at 5b020000 {
+		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0x5b020000 0x0 0x10000>;
+		clocks = <&clk IMX8QM_SDHC1_IPG_CLK>,
+			 <&clk IMX8QM_SDHC1_CLK>,
+			 <&clk IMX8QM_CLK_DUMMY>;
+		clock-names = "ipg", "per", "ahb";
+		assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
+		assigned-clock-rates = <200000000>;
+		power-domains = <&pd_conn_sdch1>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		status = "disabled";
+	};
+
+	usdhc3: usdhc at 5b030000 {
+		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0x5b030000 0x0 0x10000>;
+		clocks = <&clk IMX8QM_SDHC2_IPG_CLK>,
+			 <&clk IMX8QM_SDHC2_CLK>,
+			 <&clk IMX8QM_CLK_DUMMY>;
+		clock-names = "ipg", "per", "ahb";
+		assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
+		assigned-clock-rates = <200000000>;
+		power-domains = <&pd_conn_sdch2>;
+		status = "disabled";
+	};
+
+	fec1: ethernet at 5b040000 {
+		compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
+		reg = <0x0 0x5b040000 0x0 0x10000>;
+		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QM_ENET0_IPG_CLK>,
+			 <&clk IMX8QM_ENET0_AHB_CLK>,
+			 <&clk IMX8QM_ENET0_RGMII_TX_CLK>,
+			 <&clk IMX8QM_ENET0_PTP_CLK>,
+			 <&clk IMX8QM_ENET0_TX_CLK>;
+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
+			      "enet_2x_txclk";
+		assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>,
+				  <&clk IMX8QM_ENET0_REF_DIV>;
+		assigned-clock-rates = <250000000>, <125000000>;
+		fsl,num-tx-queues=<3>;
+		fsl,num-rx-queues=<3>;
+		fsl,wakeup_irq = <0>;
+		power-domains = <&pd_conn_enet0>;
+		status = "disabled";
+	};
+
+	fec2: ethernet at 5b050000 {
+		compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
+		reg = <0x0 0x5b050000 0x0 0x10000>;
+		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QM_ENET1_IPG_CLK>,
+			 <&clk IMX8QM_ENET1_AHB_CLK>,
+			 <&clk IMX8QM_ENET1_RGMII_TX_CLK>,
+			 <&clk IMX8QM_ENET1_PTP_CLK>,
+			 <&clk IMX8QM_ENET1_TX_CLK>;
+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
+			      "enet_2x_txclk";
+		assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>,
+				  <&clk IMX8QM_ENET1_REF_DIV>;
+		assigned-clock-rates = <250000000>, <125000000>;
+		fsl,num-tx-queues=<3>;
+		fsl,num-rx-queues=<3>;
+		fsl,wakeup_irq = <0>;
+		power-domains = <&pd_conn_enet1>;
+		status = "disabled";
+	};
+};
+
+&A53_0 {
+	clocks = <&clk IMX8QM_A53_DIV>;
+};
-- 
2.16.4

[U-Boot] [PATCH RESEND 05/10] imx8: add cpu support

[Peng Fan]

Add cpu type and Kconfig entry

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx/cpu.h | 1 +
 arch/arm/mach-imx/imx8/Kconfig      | 5 +++++
 arch/arm/mach-imx/imx8/cpu.c        | 3 +++
 3 files changed, 9 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 667badbc06..d4a83eef72 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -26,6 +26,7 @@
 #define MXC_CPU_MX7D		0x72
 #define MXC_CPU_IMX8MQ		0x82
 #define MXC_CPU_IMX8QXP_A0	0x90 /* dummy ID */
+#define MXC_CPU_IMX8QM		0x91 /* dummy ID */
 #define MXC_CPU_IMX8QXP		0x92 /* dummy ID */
 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
 #define MXC_CPU_VF610		0xF6 /* dummy ID */
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index f76a139684..4336a8c236 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -10,6 +10,11 @@ config MU_BASE_SPL
 	  SPL runs in EL3 mode, it use MU0_A to communicate with SCU.
 	  So we could not reuse the one in dts which is for normal U-Boot.
 
+config IMX8QM
+	select IMX8
+	select SUPPORT_SPL
+	bool
+
 config IMX8QXP
 	select IMX8
 	select SUPPORT_SPL
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 7539e45652..ac65ae74fd 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -542,6 +542,8 @@ const char *get_imx8_type(u32 imxtype)
 	case MXC_CPU_IMX8QXP:
 	case MXC_CPU_IMX8QXP_A0:
 		return "QXP";
+	case MXC_CPU_IMX8QM:
+		return "QM";
 	default:
 		return "??";
 	}
@@ -613,6 +615,7 @@ static const struct cpu_ops cpu_imx8_ops = {
 
 static const struct udevice_id cpu_imx8_ids[] = {
 	{ .compatible = "arm,cortex-a35" },
+	{ .compatible = "arm,cortex-a53" },
 	{ }
 };
 
-- 
2.16.4

[U-Boot] [PATCH RESEND 06/10] clk: imx8: split code into common and soc specific part

[Peng Fan]

To make it easy to add new clk driver for i.MX8, split
the code into common part and SoC specific part.

Make the get/set/enable non static and introduce a num_clks for
soc_clk_dump, because the arrays are moved to clk-imx8qxp.c.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/Makefile      |   4 +
 drivers/clk/imx/clk-imx8.c    | 297 ++--------------------------------------
 drivers/clk/imx/clk-imx8.h    |  19 +++
 drivers/clk/imx/clk-imx8qxp.c | 311 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 342 insertions(+), 289 deletions(-)
 create mode 100644 drivers/clk/imx/clk-imx8.h
 create mode 100644 drivers/clk/imx/clk-imx8qxp.c

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 5505ae52e2..d07d91b88f 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -3,3 +3,7 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
+
+ifdef CONFIG_CLK_IMX8
+obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
+endif
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
index d03fcc2fdd..c69a9ed867 100644
--- a/drivers/clk/imx/clk-imx8.c
+++ b/drivers/clk/imx/clk-imx8.c
@@ -13,302 +13,21 @@
 #include <dt-bindings/soc/imx_rsrc.h>
 #include <misc.h>
 
-struct imx8_clks {
-	ulong id;
-	const char *name;
-};
-
-#if CONFIG_IS_ENABLED(CMD_CLK)
-static struct imx8_clks imx8_clk_names[] = {
-	{ IMX8QXP_A35_DIV, "A35_DIV" },
-	{ IMX8QXP_I2C0_CLK, "I2C0" },
-	{ IMX8QXP_I2C1_CLK, "I2C1" },
-	{ IMX8QXP_I2C2_CLK, "I2C2" },
-	{ IMX8QXP_I2C3_CLK, "I2C3" },
-	{ IMX8QXP_UART0_CLK, "UART0" },
-	{ IMX8QXP_UART1_CLK, "UART1" },
-	{ IMX8QXP_UART2_CLK, "UART2" },
-	{ IMX8QXP_UART3_CLK, "UART3" },
-	{ IMX8QXP_SDHC0_CLK, "SDHC0" },
-	{ IMX8QXP_SDHC1_CLK, "SDHC1" },
-	{ IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" },
-	{ IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" },
-	{ IMX8QXP_ENET0_REF_DIV, "ENET0_REF" },
-	{ IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" },
-	{ IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" },
-	{ IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" },
-	{ IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
-	{ IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
-};
-#endif
+#include "clk-imx8.h"
 
-static ulong imx8_clk_get_rate(struct clk *clk)
+__weak ulong imx8_clk_get_rate(struct clk *clk)
 {
-	sc_pm_clk_t pm_clk;
-	ulong rate;
-	u16 resource;
-	int ret;
-
-	debug("%s(#%lu)\n", __func__, clk->id);
-
-	switch (clk->id) {
-	case IMX8QXP_A35_DIV:
-		resource = SC_R_A35;
-		pm_clk = SC_PM_CLK_CPU;
-		break;
-	case IMX8QXP_I2C0_CLK:
-		resource = SC_R_I2C_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C1_CLK:
-		resource = SC_R_I2C_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C2_CLK:
-		resource = SC_R_I2C_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C3_CLK:
-		resource = SC_R_I2C_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC0_IPG_CLK:
-	case IMX8QXP_SDHC0_CLK:
-	case IMX8QXP_SDHC0_DIV:
-		resource = SC_R_SDHC_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC1_IPG_CLK:
-	case IMX8QXP_SDHC1_CLK:
-	case IMX8QXP_SDHC1_DIV:
-		resource = SC_R_SDHC_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART0_IPG_CLK:
-	case IMX8QXP_UART0_CLK:
-		resource = SC_R_UART_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART1_CLK:
-		resource = SC_R_UART_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART2_CLK:
-		resource = SC_R_UART_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART3_CLK:
-		resource = SC_R_UART_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET0_IPG_CLK:
-	case IMX8QXP_ENET0_AHB_CLK:
-	case IMX8QXP_ENET0_REF_DIV:
-	case IMX8QXP_ENET0_PTP_CLK:
-		resource = SC_R_ENET_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET1_IPG_CLK:
-	case IMX8QXP_ENET1_AHB_CLK:
-	case IMX8QXP_ENET1_REF_DIV:
-	case IMX8QXP_ENET1_PTP_CLK:
-		resource = SC_R_ENET_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	default:
-		if (clk->id < IMX8QXP_UART0_IPG_CLK ||
-		    clk->id >= IMX8QXP_CLK_END) {
-			printf("%s(Invalid clk ID #%lu)\n",
-			       __func__, clk->id);
-			return -EINVAL;
-		}
-		return -ENOTSUPP;
-	};
-
-	ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
-				   (sc_pm_clock_rate_t *)&rate);
-	if (ret) {
-		printf("%s err %d\n", __func__, ret);
-		return ret;
-	}
-
-	return rate;
+	return 0;
 }
 
-static ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
+__weak ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
 {
-	sc_pm_clk_t pm_clk;
-	u32 new_rate = rate;
-	u16 resource;
-	int ret;
-
-	debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
-
-	switch (clk->id) {
-	case IMX8QXP_I2C0_CLK:
-		resource = SC_R_I2C_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C1_CLK:
-		resource = SC_R_I2C_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C2_CLK:
-		resource = SC_R_I2C_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C3_CLK:
-		resource = SC_R_I2C_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART0_CLK:
-		resource = SC_R_UART_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART1_CLK:
-		resource = SC_R_UART_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART2_CLK:
-		resource = SC_R_UART_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART3_CLK:
-		resource = SC_R_UART_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC0_IPG_CLK:
-	case IMX8QXP_SDHC0_CLK:
-	case IMX8QXP_SDHC0_DIV:
-		resource = SC_R_SDHC_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC1_SEL:
-	case IMX8QXP_SDHC0_SEL:
-		return 0;
-	case IMX8QXP_SDHC1_IPG_CLK:
-	case IMX8QXP_SDHC1_CLK:
-	case IMX8QXP_SDHC1_DIV:
-		resource = SC_R_SDHC_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET0_IPG_CLK:
-	case IMX8QXP_ENET0_AHB_CLK:
-	case IMX8QXP_ENET0_REF_DIV:
-	case IMX8QXP_ENET0_PTP_CLK:
-		resource = SC_R_ENET_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET1_IPG_CLK:
-	case IMX8QXP_ENET1_AHB_CLK:
-	case IMX8QXP_ENET1_REF_DIV:
-	case IMX8QXP_ENET1_PTP_CLK:
-		resource = SC_R_ENET_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	default:
-		if (clk->id < IMX8QXP_UART0_IPG_CLK ||
-		    clk->id >= IMX8QXP_CLK_END) {
-			printf("%s(Invalid clk ID #%lu)\n",
-			       __func__, clk->id);
-			return -EINVAL;
-		}
-		return -ENOTSUPP;
-	};
-
-	ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
-	if (ret) {
-		printf("%s err %d\n", __func__, ret);
-		return ret;
-	}
-
-	return new_rate;
+	return 0;
 }
 
-static int __imx8_clk_enable(struct clk *clk, bool enable)
+__weak int __imx8_clk_enable(struct clk *clk, bool enable)
 {
-	sc_pm_clk_t pm_clk;
-	u16 resource;
-	int ret;
-
-	debug("%s(#%lu)\n", __func__, clk->id);
-
-	switch (clk->id) {
-	case IMX8QXP_I2C0_CLK:
-		resource = SC_R_I2C_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C1_CLK:
-		resource = SC_R_I2C_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C2_CLK:
-		resource = SC_R_I2C_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C3_CLK:
-		resource = SC_R_I2C_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART0_CLK:
-		resource = SC_R_UART_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART1_CLK:
-		resource = SC_R_UART_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART2_CLK:
-		resource = SC_R_UART_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART3_CLK:
-		resource = SC_R_UART_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC0_IPG_CLK:
-	case IMX8QXP_SDHC0_CLK:
-	case IMX8QXP_SDHC0_DIV:
-		resource = SC_R_SDHC_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC1_IPG_CLK:
-	case IMX8QXP_SDHC1_CLK:
-	case IMX8QXP_SDHC1_DIV:
-		resource = SC_R_SDHC_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET0_IPG_CLK:
-	case IMX8QXP_ENET0_AHB_CLK:
-	case IMX8QXP_ENET0_REF_DIV:
-	case IMX8QXP_ENET0_PTP_CLK:
-		resource = SC_R_ENET_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET1_IPG_CLK:
-	case IMX8QXP_ENET1_AHB_CLK:
-	case IMX8QXP_ENET1_REF_DIV:
-	case IMX8QXP_ENET1_PTP_CLK:
-		resource = SC_R_ENET_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	default:
-		if (clk->id < IMX8QXP_UART0_IPG_CLK ||
-		    clk->id >= IMX8QXP_CLK_END) {
-			printf("%s(Invalid clk ID #%lu)\n",
-			       __func__, clk->id);
-			return -EINVAL;
-		}
-		return -ENOTSUPP;
-	}
-
-	ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
-	if (ret) {
-		printf("%s err %d\n", __func__, ret);
-		return ret;
-	}
-
-	return 0;
+	return -ENOTSUPP;
 }
 
 static int imx8_clk_disable(struct clk *clk)
@@ -336,7 +55,7 @@ int soc_clk_dump(void)
 
 	printf("Clk\t\tHz\n");
 
-	for (i = 0; i < ARRAY_SIZE(imx8_clk_names); i++) {
+	for (i = 0; i < num_clks; i++) {
 		clk.id = imx8_clk_names[i].id;
 		ret = clk_request(dev, &clk);
 		if (ret < 0) {
diff --git a/drivers/clk/imx/clk-imx8.h b/drivers/clk/imx/clk-imx8.h
new file mode 100644
index 0000000000..68ad6755e8
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+struct imx8_clks {
+	ulong id;
+	const char *name;
+};
+
+#if CONFIG_IS_ENABLED(CMD_CLK)
+extern struct imx8_clks imx8_clk_names[];
+extern int num_clks;
+#endif
+
+ulong imx8_clk_get_rate(struct clk *clk);
+ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate);
+int __imx8_clk_enable(struct clk *clk, bool enable);
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
new file mode 100644
index 0000000000..1fca36ac91
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/clock.h>
+#include <dt-bindings/clock/imx8qxp-clock.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <misc.h>
+
+#include "clk-imx8.h"
+
+#if CONFIG_IS_ENABLED(CMD_CLK)
+struct imx8_clks imx8_clk_names[] = {
+	{ IMX8QXP_A35_DIV, "A35_DIV" },
+	{ IMX8QXP_I2C0_CLK, "I2C0" },
+	{ IMX8QXP_I2C1_CLK, "I2C1" },
+	{ IMX8QXP_I2C2_CLK, "I2C2" },
+	{ IMX8QXP_I2C3_CLK, "I2C3" },
+	{ IMX8QXP_UART0_CLK, "UART0" },
+	{ IMX8QXP_UART1_CLK, "UART1" },
+	{ IMX8QXP_UART2_CLK, "UART2" },
+	{ IMX8QXP_UART3_CLK, "UART3" },
+	{ IMX8QXP_SDHC0_CLK, "SDHC0" },
+	{ IMX8QXP_SDHC1_CLK, "SDHC1" },
+	{ IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" },
+	{ IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" },
+	{ IMX8QXP_ENET0_REF_DIV, "ENET0_REF" },
+	{ IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" },
+	{ IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" },
+	{ IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" },
+	{ IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
+	{ IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
+};
+
+int num_clks = ARRAY_SIZE(imx8_clk_names);
+#endif
+
+ulong imx8_clk_get_rate(struct clk *clk)
+{
+	sc_pm_clk_t pm_clk;
+	ulong rate;
+	u16 resource;
+	int ret;
+
+	debug("%s(#%lu)\n", __func__, clk->id);
+
+	switch (clk->id) {
+	case IMX8QXP_A35_DIV:
+		resource = SC_R_A35;
+		pm_clk = SC_PM_CLK_CPU;
+		break;
+	case IMX8QXP_I2C0_CLK:
+		resource = SC_R_I2C_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C1_CLK:
+		resource = SC_R_I2C_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C2_CLK:
+		resource = SC_R_I2C_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C3_CLK:
+		resource = SC_R_I2C_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_SDHC0_IPG_CLK:
+	case IMX8QXP_SDHC0_CLK:
+	case IMX8QXP_SDHC0_DIV:
+		resource = SC_R_SDHC_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_SDHC1_IPG_CLK:
+	case IMX8QXP_SDHC1_CLK:
+	case IMX8QXP_SDHC1_DIV:
+		resource = SC_R_SDHC_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART0_IPG_CLK:
+	case IMX8QXP_UART0_CLK:
+		resource = SC_R_UART_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART1_CLK:
+		resource = SC_R_UART_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART2_CLK:
+		resource = SC_R_UART_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART3_CLK:
+		resource = SC_R_UART_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_ENET0_IPG_CLK:
+	case IMX8QXP_ENET0_AHB_CLK:
+	case IMX8QXP_ENET0_REF_DIV:
+	case IMX8QXP_ENET0_PTP_CLK:
+		resource = SC_R_ENET_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_ENET1_IPG_CLK:
+	case IMX8QXP_ENET1_AHB_CLK:
+	case IMX8QXP_ENET1_REF_DIV:
+	case IMX8QXP_ENET1_PTP_CLK:
+		resource = SC_R_ENET_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	default:
+		if (clk->id < IMX8QXP_UART0_IPG_CLK ||
+		    clk->id >= IMX8QXP_CLK_END) {
+			printf("%s(Invalid clk ID #%lu)\n",
+			       __func__, clk->id);
+			return -EINVAL;
+		}
+		return -ENOTSUPP;
+	};
+
+	ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
+				   (sc_pm_clock_rate_t *)&rate);
+	if (ret) {
+		printf("%s err %d\n", __func__, ret);
+		return ret;
+	}
+
+	return rate;
+}
+
+ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	sc_pm_clk_t pm_clk;
+	u32 new_rate = rate;
+	u16 resource;
+	int ret;
+
+	debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+	switch (clk->id) {
+	case IMX8QXP_I2C0_CLK:
+		resource = SC_R_I2C_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C1_CLK:
+		resource = SC_R_I2C_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C2_CLK:
+		resource = SC_R_I2C_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C3_CLK:
+		resource = SC_R_I2C_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART0_CLK:
+		resource = SC_R_UART_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART1_CLK:
+		resource = SC_R_UART_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART2_CLK:
+		resource = SC_R_UART_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART3_CLK:
+		resource = SC_R_UART_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_SDHC0_IPG_CLK:
+	case IMX8QXP_SDHC0_CLK:
+	case IMX8QXP_SDHC0_DIV:
+		resource = SC_R_SDHC_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_SDHC1_SEL:
+	case IMX8QXP_SDHC0_SEL:
+		return 0;
+	case IMX8QXP_SDHC1_IPG_CLK:
+	case IMX8QXP_SDHC1_CLK:
+	case IMX8QXP_SDHC1_DIV:
+		resource = SC_R_SDHC_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_ENET0_IPG_CLK:
+	case IMX8QXP_ENET0_AHB_CLK:
+	case IMX8QXP_ENET0_REF_DIV:
+	case IMX8QXP_ENET0_PTP_CLK:
+		resource = SC_R_ENET_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_ENET1_IPG_CLK:
+	case IMX8QXP_ENET1_AHB_CLK:
+	case IMX8QXP_ENET1_REF_DIV:
+	case IMX8QXP_ENET1_PTP_CLK:
+		resource = SC_R_ENET_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	default:
+		if (clk->id < IMX8QXP_UART0_IPG_CLK ||
+		    clk->id >= IMX8QXP_CLK_END) {
+			printf("%s(Invalid clk ID #%lu)\n",
+			       __func__, clk->id);
+			return -EINVAL;
+		}
+		return -ENOTSUPP;
+	};
+
+	ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
+	if (ret) {
+		printf("%s err %d\n", __func__, ret);
+		return ret;
+	}
+
+	return new_rate;
+}
+
+int __imx8_clk_enable(struct clk *clk, bool enable)
+{
+	sc_pm_clk_t pm_clk;
+	u16 resource;
+	int ret;
+
+	debug("%s(#%lu)\n", __func__, clk->id);
+
+	switch (clk->id) {
+	case IMX8QXP_I2C0_CLK:
+		resource = SC_R_I2C_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C1_CLK:
+		resource = SC_R_I2C_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C2_CLK:
+		resource = SC_R_I2C_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C3_CLK:
+		resource = SC_R_I2C_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART0_CLK:
+		resource = SC_R_UART_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART1_CLK:
+		resource = SC_R_UART_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART2_CLK:
+		resource = SC_R_UART_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART3_CLK:
+		resource = SC_R_UART_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_SDHC0_IPG_CLK:
+	case IMX8QXP_SDHC0_CLK:
+	case IMX8QXP_SDHC0_DIV:
+		resource = SC_R_SDHC_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_SDHC1_IPG_CLK:
+	case IMX8QXP_SDHC1_CLK:
+	case IMX8QXP_SDHC1_DIV:
+		resource = SC_R_SDHC_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_ENET0_IPG_CLK:
+	case IMX8QXP_ENET0_AHB_CLK:
+	case IMX8QXP_ENET0_REF_DIV:
+	case IMX8QXP_ENET0_PTP_CLK:
+		resource = SC_R_ENET_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_ENET1_IPG_CLK:
+	case IMX8QXP_ENET1_AHB_CLK:
+	case IMX8QXP_ENET1_REF_DIV:
+	case IMX8QXP_ENET1_PTP_CLK:
+		resource = SC_R_ENET_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	default:
+		if (clk->id < IMX8QXP_UART0_IPG_CLK ||
+		    clk->id >= IMX8QXP_CLK_END) {
+			printf("%s(Invalid clk ID #%lu)\n",
+			       __func__, clk->id);
+			return -EINVAL;
+		}
+		return -ENOTSUPP;
+	}
+
+	ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
+	if (ret) {
+		printf("%s err %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
-- 
2.16.4

[U-Boot] [PATCH RESEND 07/10] clk: imx8: add i.MX8QM clk driver

[Peng Fan]

Add i.MX8QM clk driver, SDHC/FEC/UART/I2C supported.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/Makefile     |   1 +
 drivers/clk/imx/clk-imx8.c   |   1 +
 drivers/clk/imx/clk-imx8qm.c | 307 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 309 insertions(+)
 create mode 100644 drivers/clk/imx/clk-imx8qm.c

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index d07d91b88f..eb379c188a 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
 
 ifdef CONFIG_CLK_IMX8
 obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
+obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
 endif
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
index c69a9ed867..a755e26501 100644
--- a/drivers/clk/imx/clk-imx8.c
+++ b/drivers/clk/imx/clk-imx8.c
@@ -101,6 +101,7 @@ static int imx8_clk_probe(struct udevice *dev)
 
 static const struct udevice_id imx8_clk_ids[] = {
 	{ .compatible = "fsl,imx8qxp-clk" },
+	{ .compatible = "fsl,imx8qm-clk" },
 	{ },
 };
 
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c
new file mode 100644
index 0000000000..6b5561e178
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8qm.c
@@ -0,0 +1,307 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/clock.h>
+#include <dt-bindings/clock/imx8qm-clock.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <misc.h>
+
+#include "clk-imx8.h"
+
+#if CONFIG_IS_ENABLED(CMD_CLK)
+struct imx8_clks imx8_clk_names[] = {
+	{ IMX8QM_A53_DIV, "A53_DIV" },
+	{ IMX8QM_UART0_CLK, "UART0" },
+	{ IMX8QM_UART1_CLK, "UART1" },
+	{ IMX8QM_UART2_CLK, "UART2" },
+	{ IMX8QM_UART3_CLK, "UART3" },
+	{ IMX8QM_SDHC0_CLK, "SDHC0" },
+	{ IMX8QM_SDHC1_CLK, "SDHC1" },
+	{ IMX8QM_SDHC2_CLK, "SDHC2" },
+	{ IMX8QM_ENET0_AHB_CLK, "ENET0_AHB" },
+	{ IMX8QM_ENET0_IPG_CLK, "ENET0_IPG" },
+	{ IMX8QM_ENET0_REF_DIV, "ENET0_REF" },
+	{ IMX8QM_ENET0_PTP_CLK, "ENET0_PTP" },
+	{ IMX8QM_ENET1_AHB_CLK, "ENET1_AHB" },
+	{ IMX8QM_ENET1_IPG_CLK, "ENET1_IPG" },
+	{ IMX8QM_ENET1_REF_DIV, "ENET1_REF" },
+	{ IMX8QM_ENET1_PTP_CLK, "ENET1_PTP" },
+};
+
+int num_clks = ARRAY_SIZE(imx8_clk_names);
+#endif
+
+ulong imx8_clk_get_rate(struct clk *clk)
+{
+	sc_pm_clk_t pm_clk;
+	ulong rate;
+	u16 resource;
+	int ret;
+
+	debug("%s(#%lu)\n", __func__, clk->id);
+
+	switch (clk->id) {
+	case IMX8QM_A53_DIV:
+		resource = SC_R_A53;
+		pm_clk = SC_PM_CLK_CPU;
+		break;
+	case IMX8QM_I2C0_CLK:
+		resource = SC_R_I2C_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_I2C1_CLK:
+		resource = SC_R_I2C_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_I2C2_CLK:
+		resource = SC_R_I2C_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_I2C3_CLK:
+		resource = SC_R_I2C_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_SDHC0_IPG_CLK:
+	case IMX8QM_SDHC0_CLK:
+	case IMX8QM_SDHC0_DIV:
+		resource = SC_R_SDHC_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_SDHC1_IPG_CLK:
+	case IMX8QM_SDHC1_CLK:
+	case IMX8QM_SDHC1_DIV:
+		resource = SC_R_SDHC_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART0_IPG_CLK:
+	case IMX8QM_UART0_CLK:
+		resource = SC_R_UART_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART1_CLK:
+		resource = SC_R_UART_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART2_CLK:
+		resource = SC_R_UART_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART3_CLK:
+		resource = SC_R_UART_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_ENET0_IPG_CLK:
+	case IMX8QM_ENET0_AHB_CLK:
+	case IMX8QM_ENET0_REF_DIV:
+	case IMX8QM_ENET0_PTP_CLK:
+		resource = SC_R_ENET_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_ENET1_IPG_CLK:
+	case IMX8QM_ENET1_AHB_CLK:
+	case IMX8QM_ENET1_REF_DIV:
+	case IMX8QM_ENET1_PTP_CLK:
+		resource = SC_R_ENET_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	default:
+		if (clk->id < IMX8QM_UART0_IPG_CLK ||
+		    clk->id >= IMX8QM_CLK_END) {
+			printf("%s(Invalid clk ID #%lu)\n",
+			       __func__, clk->id);
+			return -EINVAL;
+		}
+		return -ENOTSUPP;
+	};
+
+	ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
+				   (sc_pm_clock_rate_t *)&rate);
+	if (ret) {
+		printf("%s err %d\n", __func__, ret);
+		return ret;
+	}
+
+	return rate;
+}
+
+ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	sc_pm_clk_t pm_clk;
+	u32 new_rate = rate;
+	u16 resource;
+	int ret;
+
+	debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+	switch (clk->id) {
+	case IMX8QM_I2C0_CLK:
+		resource = SC_R_I2C_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_I2C1_CLK:
+		resource = SC_R_I2C_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_I2C2_CLK:
+		resource = SC_R_I2C_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_I2C3_CLK:
+		resource = SC_R_I2C_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART0_CLK:
+		resource = SC_R_UART_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART1_CLK:
+		resource = SC_R_UART_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART2_CLK:
+		resource = SC_R_UART_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART3_CLK:
+		resource = SC_R_UART_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_SDHC0_IPG_CLK:
+	case IMX8QM_SDHC0_CLK:
+	case IMX8QM_SDHC0_DIV:
+		resource = SC_R_SDHC_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_SDHC1_IPG_CLK:
+	case IMX8QM_SDHC1_CLK:
+	case IMX8QM_SDHC1_DIV:
+		resource = SC_R_SDHC_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_ENET0_IPG_CLK:
+	case IMX8QM_ENET0_AHB_CLK:
+	case IMX8QM_ENET0_REF_DIV:
+	case IMX8QM_ENET0_PTP_CLK:
+	case IMX8QM_ENET0_ROOT_DIV:
+		resource = SC_R_ENET_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_ENET1_IPG_CLK:
+	case IMX8QM_ENET1_AHB_CLK:
+	case IMX8QM_ENET1_REF_DIV:
+	case IMX8QM_ENET1_PTP_CLK:
+	case IMX8QM_ENET1_ROOT_DIV:
+		resource = SC_R_ENET_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	default:
+		if (clk->id < IMX8QM_UART0_IPG_CLK ||
+		    clk->id >= IMX8QM_CLK_END) {
+			printf("%s(Invalid clk ID #%lu)\n",
+			       __func__, clk->id);
+			return -EINVAL;
+		}
+		return -ENOTSUPP;
+	};
+
+	ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
+	if (ret) {
+		printf("%s err %d\n", __func__, ret);
+		return ret;
+	}
+
+	return new_rate;
+}
+
+int __imx8_clk_enable(struct clk *clk, bool enable)
+{
+	sc_pm_clk_t pm_clk;
+	u16 resource;
+	int ret;
+
+	debug("%s(#%lu)\n", __func__, clk->id);
+
+	switch (clk->id) {
+	case IMX8QM_I2C0_CLK:
+		resource = SC_R_I2C_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_I2C1_CLK:
+		resource = SC_R_I2C_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_I2C2_CLK:
+		resource = SC_R_I2C_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_I2C3_CLK:
+		resource = SC_R_I2C_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART0_CLK:
+		resource = SC_R_UART_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART1_CLK:
+		resource = SC_R_UART_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART2_CLK:
+		resource = SC_R_UART_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_UART3_CLK:
+		resource = SC_R_UART_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_SDHC0_IPG_CLK:
+	case IMX8QM_SDHC0_CLK:
+	case IMX8QM_SDHC0_DIV:
+		resource = SC_R_SDHC_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_SDHC1_IPG_CLK:
+	case IMX8QM_SDHC1_CLK:
+	case IMX8QM_SDHC1_DIV:
+		resource = SC_R_SDHC_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_ENET0_IPG_CLK:
+	case IMX8QM_ENET0_AHB_CLK:
+	case IMX8QM_ENET0_REF_DIV:
+	case IMX8QM_ENET0_PTP_CLK:
+		resource = SC_R_ENET_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QM_ENET1_IPG_CLK:
+	case IMX8QM_ENET1_AHB_CLK:
+	case IMX8QM_ENET1_REF_DIV:
+	case IMX8QM_ENET1_PTP_CLK:
+		resource = SC_R_ENET_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	default:
+		if (clk->id < IMX8QM_UART0_IPG_CLK ||
+		    clk->id >= IMX8QM_CLK_END) {
+			printf("%s(Invalid clk ID #%lu)\n",
+			       __func__, clk->id);
+			return -EINVAL;
+		}
+		return -ENOTSUPP;
+	}
+
+	ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
+	if (ret) {
+		printf("%s err %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
-- 
2.16.4

[U-Boot] [PATCH RESEND 08/10] imx8: imx8-pins: add i.MX8QM

[Peng Fan]

Add i.MX8QM entry

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8/imx8-pins.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8/imx8-pins.h b/arch/arm/include/asm/arch-imx8/imx8-pins.h
index dcced1010b..2130298163 100644
--- a/arch/arm/include/asm/arch-imx8/imx8-pins.h
+++ b/arch/arm/include/asm/arch-imx8/imx8-pins.h
@@ -8,6 +8,8 @@
 
 #if defined(CONFIG_IMX8QXP)
 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
+#elif defined(CONFIG_IMX8QM)
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
 #else
 #error "No pin header"
 #endif
-- 
2.16.4

[U-Boot] [PATCH RESEND 09/10] misc: imx8: scu: add i.MX8QM support

[Peng Fan]

According to IMX8QXP/8QM config option, choose the clk/iomuxc
compatible.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/misc/imx8/scu.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c
index 1b9c49c99c..9ec00457b8 100644
--- a/drivers/misc/imx8/scu.c
+++ b/drivers/misc/imx8/scu.c
@@ -219,11 +219,21 @@ static int imx8_scu_bind(struct udevice *dev)
 	int ret;
 	struct udevice *child;
 	int node;
+	char *clk_compatible, *iomuxc_compatible;
+
+	if (IS_ENABLED(CONFIG_IMX8QXP)) {
+		clk_compatible = "fsl,imx8qxp-clk";
+		iomuxc_compatible = "fsl,imx8qxp-iomuxc";
+	} else if (IS_ENABLED(CONFIG_IMX8QM)) {
+		clk_compatible = "fsl,imx8qm-clk";
+		iomuxc_compatible = "fsl,imx8qm-iomuxc";
+	} else {
+		return -EINVAL;
+	}
 
 	debug("%s(dev=%p)\n", __func__, dev);
 
-	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
-					     "fsl,imx8qxp-clk");
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, clk_compatible);
 	if (node < 0)
 		panic("No clk node found\n");
 
@@ -234,7 +244,7 @@ static int imx8_scu_bind(struct udevice *dev)
 	plat->clk = child;
 
 	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
-					     "fsl,imx8qxp-iomuxc");
+					     iomuxc_compatible);
 	if (node < 0)
 		panic("No iomuxc node found\n");
 
-- 
2.16.4

[U-Boot] [PATCH RESEND 10/10] imx: support i.MX8QM MEK board

[Peng Fan]

Add i.MX8QM MEK board support.
Included a basic dts, enabled SPL FIT

Boot log as below:
U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
Normal Boot
Trying to boot from MMC2_2

U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)

CPU:   NXP i.MX8QM RevB A53 at 142933 MHz

Model: Freescale i.MX8QM MEK
Board: iMX8QM MEK
Build: SCFW 9330215b
Boot:  SD1
DRAM:  6 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial at 5a060000
Out:   serial at 5a060000
Err:   serial at 5a060000
Net:
Error: ethernet at 5b040000 address not set.
eth-1: ethernet at 5b040000
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/dts/Makefile                   |   4 +-
 arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 112 +++++++++++++++++++
 arch/arm/dts/fsl-imx8qm-mek.dts         | 184 ++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/imx8/Kconfig          |   6 ++
 board/freescale/imx8qm_mek/Kconfig      |  14 +++
 board/freescale/imx8qm_mek/MAINTAINERS  |   6 ++
 board/freescale/imx8qm_mek/Makefile     |   8 ++
 board/freescale/imx8qm_mek/README       |  57 ++++++++++
 board/freescale/imx8qm_mek/imx8qm_mek.c | 157 +++++++++++++++++++++++++++
 board/freescale/imx8qm_mek/imximage.cfg |  19 ++++
 board/freescale/imx8qm_mek/spl.c        |  75 +++++++++++++
 configs/imx8qm_mek_defconfig            |  75 +++++++++++++
 include/configs/imx8qm_mek.h            | 176 ++++++++++++++++++++++++++++++
 13 files changed, 892 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
 create mode 100644 arch/arm/dts/fsl-imx8qm-mek.dts
 create mode 100644 board/freescale/imx8qm_mek/Kconfig
 create mode 100644 board/freescale/imx8qm_mek/MAINTAINERS
 create mode 100644 board/freescale/imx8qm_mek/Makefile
 create mode 100644 board/freescale/imx8qm_mek/README
 create mode 100644 board/freescale/imx8qm_mek/imx8qm_mek.c
 create mode 100644 board/freescale/imx8qm_mek/imximage.cfg
 create mode 100644 board/freescale/imx8qm_mek/spl.c
 create mode 100644 configs/imx8qm_mek_defconfig
 create mode 100644 include/configs/imx8qm_mek.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2a040b20a5..954d595391 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -486,7 +486,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
 
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
 
-dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_IMX8) += \
+	fsl-imx8qxp-mek.dtb \
+	fsl-imx8qm-mek.dtb \
 
 dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
 
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
new file mode 100644
index 0000000000..5d50eb028e
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-spl;
+};
+
+&gpio0 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&gpio6 {
+	u-boot,dm-spl;
+};
+
+&gpio7 {
+	u-boot,dm-spl;
+};
+
+&lpuart0 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts b/arch/arm/dts/fsl-imx8qm-mek.dts
new file mode 100644
index 0000000000..63908ba6bf
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-mek.dts
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qm.dtsi"
+#include "fsl-imx8qm-mek-u-boot.dtsi"
+
+/ {
+	model = "Freescale i.MX8QM MEK";
+	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+		stdout-path = &lpuart0;
+	};
+
+	reg_usdhc2_vmmc: usdhc2_vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "sw-3p3-sd1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+		off-on-delay = <4800>;
+		enable-active-high;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx8qm-mek {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0	0x0600004c
+				SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25	0x0600004c
+				SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31	0x0600004c
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD	0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000061
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000061
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000061
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000061
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000061
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000061
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000061
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000061
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000061
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000061
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000061
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000061
+			>;
+		};
+
+		pinctrl_fec2: fec2grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD	0x000014a0
+				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
+				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x00000060
+				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x00000060
+				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x00000060
+				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x00000060
+				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x00000060
+				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x00000060
+				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
+				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x00000060
+				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x00000060
+				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x00000060
+				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
+				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021
+				SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021
+				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+	};
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	fsl,rgmii_rxc_dly;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy at 0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+		};
+
+		ethphy1: ethernet-phy at 1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+			status = "disabled";
+		};
+	};
+};
+
+&lpuart0 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 4336a8c236..c32f7dbb61 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -32,8 +32,14 @@ config TARGET_IMX8QXP_MEK
 	select BOARD_LATE_INIT
 	select IMX8QXP
 
+config TARGET_IMX8QM_MEK
+	bool "Support i.MX8QM MEK board"
+	select BOARD_LATE_INIT
+	select IMX8QM
+
 endchoice
 
 source "board/freescale/imx8qxp_mek/Kconfig"
+source "board/freescale/imx8qm_mek/Kconfig"
 
 endif
diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig
new file mode 100644
index 0000000000..93d7d5f9c5
--- /dev/null
+++ b/board/freescale/imx8qm_mek/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8QM_MEK
+
+config SYS_BOARD
+	default "imx8qm_mek"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8qm_mek"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx8qm_mek/MAINTAINERS b/board/freescale/imx8qm_mek/MAINTAINERS
new file mode 100644
index 0000000000..115830df19
--- /dev/null
+++ b/board/freescale/imx8qm_mek/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8QM MEK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/imx8qm_mek/
+F:	include/configs/imx8qm_mek.h
+F:	configs/imx8qm_mek_defconfig
diff --git a/board/freescale/imx8qm_mek/Makefile b/board/freescale/imx8qm_mek/Makefile
new file mode 100644
index 0000000000..bc9a1260bd
--- /dev/null
+++ b/board/freescale/imx8qm_mek/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += imx8qm_mek.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README
new file mode 100644
index 0000000000..c3523801ae
--- /dev/null
+++ b/board/freescale/imx8qm_mek/README
@@ -0,0 +1,57 @@
+U-Boot for the NXP i.MX8QM EVK board
+
+Quick Start
+===========
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ cd imx-atf/
+$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
+$ make PLAT=imx8qm bl31
+
+Get scfw_tcm.bin and ahab-container.img
+==============================
+
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
+$ chmod +x imx-sc-firmware-1.1.bin
+$ ./imx-sc-firmware-1.1.bin
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+$ chmod +x firmware-imx-8.0.bin
+$ ./firmware-imx-8.0.bin
+
+Copy the following binaries to U-Boot folder:
+
+$ cp imx-atf/build/imx8qm/release/bl31.bin .
+$ cp u-boot/u-boot.bin .
+
+Copy the following firmwares U-Boot folder :
+
+$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
+$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin	.
+
+Build U-Boot
+============
+$ export ATF_LOAD_ADDR=0x80000000
+$ export BL33_LOAD_ADDR=0x80020000
+$ make imx8qm_mek_defconfig
+$ make flash.bin
+$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984
+
+Flash the binary into the SD card
+=================================
+
+Burn the flash.bin binary to SD card offset 32KB:
+
+$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
+
+Boot
+====
+Set Boot switch SW2: 1100.
diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c
new file mode 100644
index 0000000000..e69efc4dd6
--- /dev/null
+++ b/board/freescale/imx8qm_mek/imx8qm_mek.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+#include <environment.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	int ret;
+	/* Set UART0 clock root to 80 MHz */
+	sc_pm_clock_rate_t rate = 80000000;
+
+	/* Power up UART0 */
+	ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
+	if (ret)
+		return ret;
+
+	ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
+	if (ret)
+		return ret;
+
+	/* Enable UART0 clock root */
+	ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+	sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_DM_GPIO)
+static void board_gpio_init(void)
+{
+	/* TODO */
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+void build_info(void)
+{
+	u32 sc_build = 0, sc_commit = 0;
+
+	/* Get SCFW build and commit id */
+	sc_misc_build_info(-1, &sc_build, &sc_commit);
+	if (!sc_build) {
+		printf("SCFW does not support build info\n");
+		sc_commit = 0; /* Display 0 when the build info is not supported*/
+	}
+	printf("Build: SCFW %x\n", sc_commit);
+}
+
+int checkboard(void)
+{
+	puts("Board: iMX8QM MEK\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Power up base board */
+	sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
+
+	board_gpio_init();
+
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+	/* TODO */
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "MEK");
+	env_set("board_rev", "iMX8QM");
+#endif
+
+	return 0;
+}
diff --git a/board/freescale/imx8qm_mek/imximage.cfg b/board/freescale/imx8qm_mek/imximage.cfg
new file mode 100644
index 0000000000..7dc6b93eb5
--- /dev/null
+++ b/board/freescale/imx8qm_mek/imximage.cfg
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QM */
+SOC_TYPE IMX8QM
+/* Append seco container image */
+APPEND mx8qm-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qm-mek-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c
new file mode 100644
index 0000000000..95ce9f37e8
--- /dev/null
+++ b/board/freescale/imx8qm_mek/spl.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+	int offset;
+
+	uclass_find_first_device(UCLASS_MISC, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
+	while (offset != -FDT_ERR_NOTFOUND) {
+		lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
+			       NULL, true);
+		offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
+						       "nxp,imx8-pd");
+	}
+
+	uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
new file mode 100644
index 0000000000..238d44d1f5
--- /dev/null
+++ b/configs/imx8qm_mek_defconfig
@@ -0,0 +1,75 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
new file mode 100644
index 0000000000..02c5d1c054
--- /dev/null
+++ b/include/configs/imx8qm_mek.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8QM_MEK_H
+#define __IMX8QM_MEK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_TEXT_BASE				0x0
+#define CONFIG_SPL_MAX_SIZE				(124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0x800
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION		0
+
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x013E000
+#define CONFIG_SPL_BSS_START_ADDR	0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x00120000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x3000	/* 12 KB */
+#define CONFIG_SERIAL_LPUART_BASE	0x5a060000
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_MALLOC_F_ADDR		0x00120000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_OF_EMBED
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define USDHC1_BASE_ADDR                0x5B010000
+#define USDHC2_BASE_ADDR                0x5B020000
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"panel=NULL\0" \
+	"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
+	"fdt_addr=0x83000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+	"fdt_file=fsl-imx8qxp-mek.dtb\0" \
+	"initrd_addr=0x83800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR         0x80200000
+
+/* Default environment is in SD */
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_OFFSET		(64 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
+#define PHYS_SDRAM_2_SIZE		0x100000000	/* 4 GB */
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Monitor Command Prompt */
+#define CONFIG_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+/* Networking */
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define FEC_QUIRK_ENET_MAC
+
+#endif /* __IMX8QM_MEK_H */
-- 
2.16.4

[U-Boot] [PATCH 08/10] ata: dwc_ahsata: Add ahci driver model support

[Soeren Moch]

On 01.03.19 13:10, Soeren Moch wrote:
> Disable this support for cm_fx6 to avoid breakage.
>
> Signed-off-by: Soeren Moch <smoch@web.de>
> ---
> It would be easy to add weak board_ahci_enable/disable functions which
> can be overwritten (e.g. in the cm_fx6 board file) to handle power enable/
> disable on driver probe/remove. But I have no idea why this board needs these
> repeated probe/remove calls for the same sata device. In my tests on a
> tbs2910 board a sata harddisk is always recognized by a 'sata init' command,
> also without this probe loop.
> If this can be ironed out, we can remove the DWC_AHSATA_AHCI config option.
>
> Cc: Nikita Kiryanov <nikita@compulab.co.il>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Marcel Ziswiler <marcel@ziswiler.com>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: u-boot at lists.denx.de
> ---

After rebasing this patch series from v2019.04-rc2 to -rc3, I get this:

Matrix U-Boot> sata init

AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode

flags: ncq stag pm led clo only pmp pio slum part

Can not start port 0

data abort

pc : [<8ffab37c>]          lr : [<8ffab595>]

reloc pc : [<1781837c>]    lr : [<17818595>]

sp : 87f909c8  ip : 87f90cd4     fp : 00000004

r10: 6c41202e  r9 : 87f90ea0     r8 : 00000000

r7 : 87f90a80  r6 : 00000200     r5 : 00000000  r4 : 87f90a80

r3 : 00000070  r2 : 87f90cc0     r1 : 87f90cc0  r0 : 00000000

Flags: nzcv  IRQs off  FIQs off  Mode SVC_32

Code: fb03231c f8d3030b 9001a00c 9e0c4611 (3038f8da)

Resetting CPU ...


Any idea what got broken here?

Thanks,
Soeren

[U-Boot] [PATCH] imx8qxp: mek: enable dm-spl for pm

[Peng Fan]

with u-boot,dm-spl added for imx8qx-pm node, and SPL_SIMPLE_BUS enabled,
the bind and probe code in board file could be removed.

Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi |  5 +++++
 board/freescale/imx8qxp_mek/spl.c        | 15 ---------------
 configs/imx8qxp_mek_defconfig            |  2 +-
 3 files changed, 6 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
index 5d50eb028e..201559008c 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -3,6 +3,11 @@
  * Copyright 2018 NXP
  */
 
+&{/imx8qx-pm} {
+
+	u-boot,dm-spl;
+};
+
 &mu {
 	u-boot,dm-spl;
 };
diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c
index 95ce9f37e8..51f323811a 100644
--- a/board/freescale/imx8qxp_mek/spl.c
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -27,21 +27,6 @@ void spl_board_init(void)
 			continue;
 	}
 
-	offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
-	while (offset != -FDT_ERR_NOTFOUND) {
-		lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
-			       NULL, true);
-		offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
-						       "nxp,imx8-pd");
-	}
-
-	uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
-
-	for (; dev; uclass_find_next_device(&dev)) {
-		if (device_probe(dev))
-			continue;
-	}
-
 	arch_cpu_init();
 
 	board_early_init_f();
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index a94998b8b5..915d8812ad 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_TARGET_IMX8QXP_MEK=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
-- 
2.16.4

[U-Boot] [PATCH 08/10] ata: dwc_ahsata: Add ahci driver model support

[Soeren Moch]

On 07.03.19 09:33, Soeren Moch wrote:
> On 01.03.19 13:10, Soeren Moch wrote:
>> Disable this support for cm_fx6 to avoid breakage.
>>
>> Signed-off-by: Soeren Moch <smoch@web.de>
>> ---
>> It would be easy to add weak board_ahci_enable/disable functions which
>> can be overwritten (e.g. in the cm_fx6 board file) to handle power enable/
>> disable on driver probe/remove. But I have no idea why this board needs these
>> repeated probe/remove calls for the same sata device. In my tests on a
>> tbs2910 board a sata harddisk is always recognized by a 'sata init' command,
>> also without this probe loop.
>> If this can be ironed out, we can remove the DWC_AHSATA_AHCI config option.
>>
>> Cc: Nikita Kiryanov <nikita@compulab.co.il>
>> Cc: Stefano Babic <sbabic@denx.de>
>> Cc: Fabio Estevam <festevam@gmail.com>
>> Cc: Marcel Ziswiler <marcel@ziswiler.com>
>> Cc: Stefan Roese <sr@denx.de>
>> Cc: Simon Glass <sjg@chromium.org>
>> Cc: u-boot at lists.denx.de
>> ---
> After rebasing this patch series from v2019.04-rc2 to -rc3, I get this:
>
> Matrix U-Boot> sata init
>
> AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
>
> flags: ncq stag pm led clo only pmp pio slum part
>
> Can not start port 0
>
> data abort
>
> pc : [<8ffab37c>]          lr : [<8ffab595>]
>
> reloc pc : [<1781837c>]    lr : [<17818595>]
>
> sp : 87f909c8  ip : 87f90cd4     fp : 00000004
>
> r10: 6c41202e  r9 : 87f90ea0     r8 : 00000000
>
> r7 : 87f90a80  r6 : 00000200     r5 : 00000000  r4 : 87f90a80
>
> r3 : 00000070  r2 : 87f90cc0     r1 : 87f90cc0  r0 : 00000000
>
> Flags: nzcv  IRQs off  FIQs off  Mode SVC_32
>
> Code: fb03231c f8d3030b 9001a00c 9e0c4611 (3038f8da)
>
> Resetting CPU ...
>
>
> Any idea what got broken here?
This was caused by a bad power supply.
So this patch series still works fine on top of v2019.04-rc3.

Sorry for the noise,
Soeren

[U-Boot] [PATCH v2 04/23] apalis_imx6: enable fit image, gpt, imx thermal, efi loader support

[Igor Opaniuk]

Hi Marcel,

s/Enbale/Enable/g


On Fri, 8 Feb 2019 at 19:13, Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Enbale FIT image, GPT command, i.MX thermal and EFI loader support.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v2: None
>
>  configs/apalis_imx6_defconfig | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
> index 098d791a62..b262bb88b9 100644
> --- a/configs/apalis_imx6_defconfig
> +++ b/configs/apalis_imx6_defconfig
> @@ -11,6 +11,7 @@ CONFIG_SPL=y
>  CONFIG_CMD_HDMIDETECT=y
>  CONFIG_DISTRO_DEFAULTS=y
>  CONFIG_NR_DRAM_BANKS=1
> +CONFIG_FIT=y
>  CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
>  CONFIG_BOOTDELAY=1
>  # CONFIG_CONSOLE_MUX is not set
> @@ -36,6 +37,7 @@ CONFIG_CMD_MEMTEST=y
>  CONFIG_SYS_ALT_MEMTEST=y
>  CONFIG_CMD_DFU=y
>  CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
>  CONFIG_CMD_I2C=y
>  CONFIG_CMD_MMC=y
>  CONFIG_CMD_USB=y
> @@ -52,6 +54,7 @@ CONFIG_PHYLIB=y
>  CONFIG_PHY_MICREL=y
>  CONFIG_PHY_MICREL_KSZ90X1=y
>  CONFIG_MII=y
> +CONFIG_IMX_THERMAL=y
>  CONFIG_USB=y
>  CONFIG_USB_KEYBOARD=y
>  CONFIG_USB_GADGET=y
> @@ -65,4 +68,3 @@ CONFIG_VIDEO=y
>  CONFIG_FAT_WRITE=y
>  CONFIG_OF_LIBFDT=y
>  CONFIG_OF_LIBFDT_OVERLAY=y
> -# CONFIG_EFI_LOADER is not set
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 05/23] apalis_imx6: remove obsolete USB_GADGET_MASS_STORAGE configuration

[Igor Opaniuk]

Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

On Fri, 8 Feb 2019 at 19:16, Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Remove obsolete USB_GADGET_MASS_STORAGE configuration.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v2: None
>
>  include/configs/apalis_imx6.h | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
> index a1ba16fc79..7222285ab3 100644
> --- a/include/configs/apalis_imx6.h
> +++ b/include/configs/apalis_imx6.h
> @@ -82,8 +82,6 @@
>  /* Client */
>  #define CONFIG_USBD_HS
>
> -#define CONFIG_USB_GADGET_MASS_STORAGE
> -
>  /* Framebuffer and LCD */
>  #define CONFIG_VIDEO_IPUV3
>  #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [U-Boot, v4, 17/22] config: bk4: Update u-boot script to support recovery via SD card

[sbabic at denx.de]

> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 05/22] pcm052: board: Do not enable I2C2 code in the board file

[sbabic at denx.de]

> As the I2C2 clock is now enabled in the generic clock code, we can remove
> this code from a board file.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 25/26] colibri_imx6: added nreset gpio on reboot

[sbabic at denx.de]

> From: Gerard Salvatella <gerard.salvatella@toradex.com>
> RGMII_RD1 pin (active high, GPIO6_IO27) is triggered on reboot during
> the SPL phase. This asserts (active low) nReset_Out from the PMIC.
> Only V1.1 and later Colibri iMX6 modules implement this in hw. Previous
> versions do not use this pin, so it is safe to leave it enabled at all
> times.
> Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 07/22] pcm052: board: Remove "m4go" command as it is superseded by "bootaux"

[sbabic at denx.de]

> The "m4go" provides exactly the same functionality as the IMX generic
> "bootaux" command. Remove it to not duplicate the code.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 19/22] pcm052: bk4: sdcard: Add support for SD card booting/recovery

[sbabic at denx.de]

> This code allows reusing the default u-boot as in the late board init, the
> default envs are restored and proper recovery scripts executed.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 06/22] vybrid: Define the imx_get_mac_from_fuse() as a __weak function

[sbabic at denx.de]

> The proposed way of reading fused MAC in the imx_get_mac_from_fuse() may
> be different for other boards.
> This commit defines the imx_get_mac_from_fuse() as a weak function to allow
> board file overriding it with customized function.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 11/26] colibri_imx6: migrate mmc to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate MMC to using driver model.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 15/22] config: bk4: Update include/configs/bk4r1.h file

[sbabic at denx.de]

> The BK4's config file has changed since its initial posting to main line.
> This commit reflects those changes.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 10/22] pcm052: board: cosmetic: Add copyright notice to pcm052.c

[sbabic at denx.de]

> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v1,15/26] colibri_imx6: add distroboot support

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Add support for distro boot. This is especially helpful for external
> devices. There is a global boot command which scans a predefined
> list of boot targets:
>   run distro_bootcmd
> As well as direct boot commands such as:
>   run bootcmd_mmc1
>   run bootcmd_usb
>   run bootcmd_dhcp
>   ...
> Refer to doc/README.distro fo details.
> While at it, remove the CONFIG_DRIVE_TYPES define which has not
> been used and was meant to be used for multi device boot support
> which is now provided by distroboot.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 10/23] apalis_imx6: migrate pmic and regulator to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate PMIC and regulator to using driver model.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 17/26] colibri imx6: pf0100: reorder and cleanup message printing

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> Keep debug code at the end of the function.
> Use a one line informational message for the PMIC only.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 22/26] configs: colibri_imx6: Use ext4 file system by default

[sbabic at denx.de]

> From: Sanchayan Maity <maitysanchayan@gmail.com>
> Use ext4 file system by default.
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v1,14/26] colibri_imx6: print also 64-bit IT

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> Print also for Colibri iMX6 512MB IT with 64-bit RAM bus.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 04/22] vybrid: clock: Provide enable_i2c_clk() function for Vybrid

[sbabic at denx.de]

> Provide function to enable I2C clocks for vf610 - in the generic code.
> This function overrides the default weak function implementation (which
> only returns 1).
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 11/22] ARM: DTS: Update pcm052 based dts files (bk4r1/pcm052)

[sbabic at denx.de]

> This commit provides update and renames the bk4r1.dts to vf610-bk4r1.dts
> file with more on SoC HW description.
> The pcm052.dts has been renamed to vf610-pcm052.dts as well.
> Moreover, a new vf610-pcm052.drsi file has been introduced
> to reuse the common code between devices based on Phytec's
> pcm052 modules.
> Ported from Linux kernel - v4.20 (tag)
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 14/22] config: pcm052: Use SZ_X{MK} from linux/sizes.h for include/configs/pcm052.h

[sbabic at denx.de]

> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 13/23] apalis_imx6: drop CONFIG_OF_SYSTEM_SETUP

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> This doesn't do anything anymore, probably never did.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v2,02/23] apalis_imx6: use distro defaults

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Use distro defaults and minimise default configuration again using
> savedefconfig.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 07/23] apalis_imx6: clean-up and migrate gpios to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate GPIOs to using driver model, properly request backlight,
> Ethernet PHY reset, MMC/SD card detect and USB power GPIOs and also
> enable SION bit in pin muxing for Apalis, backlight, eMMC reset,
> Ethernet PHY reset and USB power enable GPIOs.
> While at it also update copyright year, clean-up/re-order includes,
> add some comments clarifying ifdef scope and do some White-space
> clean-up.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 12/23] apalis_imx6: migrate usb to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate USB to using driver model.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 12/26] colibri_imx6: migrate usb to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate USB to using driver model.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 15/23] apalis_imx6: use both sd/mmc interfaces for setsdupdate

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> During porting to 2016.11 the check of a SD (mmc2) interface
> was dropped, this was unintended.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 16/23] apalis_imx6: unify sd/mmc drive strength with linux kernel settings

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> In the Linux device tree we use 40Ohm drive strength. So use the same
> value in U-Boot.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 18/22] config: bk4: Update u-boot envs to support NOR memories initial setup

[sbabic at denx.de]

> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 05/26] colibri_imx6: remove obsolete USB_GADGET_MASS_STORAGE configuration

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Remove obsolete USB_GADGET_MASS_STORAGE configuration.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 08/26] colibri_imx6: enable pin control driver

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Enable pin control driver as required for further driver model
> migration.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 19/23] apalis_imx6: revert fuse value set in mfgr_fuse

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> We have two commands to change the bootmode fuses:
> mfgr_fuse which set fuse 0/5 and 0/6
> and
> updt_fuse which burns bit 4 of 0/5.
> Before BSP 2.6 we fused in mfgr_fuse 0x5062, which boots
> from the user partition of the eMMC.
> To workaround certain hangs we moved to fastboot mode and
> using the first bootpartition of the eMMC requiring a fuse
> value of 0x5072 which could be achieved by the then added
> updt_fuse command. At the same time the mfgr_fuse command
> was changed to also fuse 0x5072, revert that second change
> so that one can fuse both values, one with just mfgr_fuse
> and the later with mfgr_fuse;updt_fuse.
> Note that the mfgr_fuse command is only needed at module
> production time, a customer might need to use updt_fuse
> when upgrading an older module to be compatible with a
> newer image. The command is integrated into the image
> update scripts.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v2,22/23] apalis_imx6: switch to zimage

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Switch to the generic compressed Kernel image type (zImage) instead of
> the U-Boot specific uImage format.
> While at it also fix device tree naming for MMC DFU.
> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v1,02/26] colibri_imx6: use distro defaults

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Use distro defaults and minimise default configuration again using
> savedefconfig.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 03/23] apalis_imx6: move console in env from header file to defconfig

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Move console in env from header file to defconfig.
> While at it also update copyright year and remove spurious comments and
> new lines.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 12/22] ARM: DTS: Provide vf610-bk4r1-u-boot.dtsi for U-Boot specific properties

[sbabic at denx.de]

> This commit brings a separate file in which the U-Boot specific
> properties (like 'dm-pre-reloc') are provided.
> Such approach allows easy sync with upstream Linux kernel in the
> future.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 21/22] pcm052: mac: Provide board specific imx_get_mac_from_fuse() function

[sbabic at denx.de]

> This commit introduces the board specific function to read fused mac
> address.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 09/22] ARM: DTS: vybrid: Update vf.dtsi file to descibe more vf610 hardware

[sbabic at denx.de]

> This patch allows moving vf610 based boards to a device tree and model.
> Ported from Linux kernel - v4.20 (tag)
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 21/26] toradex: colibri_imx6: overwrite CMA memory set in device tree

[sbabic at denx.de]

> From: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> Make sure CMA memory is not greater than 50% of available physical
> memory.
> Allow user to change the CMA memory via 'cma-size' U-Boot environment
> variable.
> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v1,24/26] colibri_imx6: switch to zimage

[sbabic at denx.de]

> From: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> Switch to the generic compressed Kernel image type (zImage) instead of
> the U-Boot specific uImage format.
> While at it also fix device tree naming for MMC DFU.
> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 13/22] defconfig: bk4/pcm052: Update bk4r1|pcm052_defconfig to support DM/DT

[sbabic at denx.de]

> This commit updates BK4's and PCM052's config files to support as much
> as possible device tree and model in u-boot.
> Moreover, remove CONFIG_* from pcm052.h (as those are now in
> bk4|pcm052_defconfig)
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v2,14/23] apalis_imx6: add distroboot support

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Add support for distro boot. This is especially helpful for external
> devices. There is a global boot command which scans a predefined
> list of boot targets:
>   run distro_bootcmd
> As well as direct boot commands such as:
>   run bootcmd_mmc1
>   run bootcmd_mmc2
>   run bootcmd_usb
>   run bootcmd_dhcp
>   ...
> Refer to doc/README.distro for details.
> While at it, remove the CONFIG_DRIVE_TYPES define which has not
> been used and was meant to be used for multi device boot support
> which is now provided by distroboot.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 06/23] apalis_imx6: migrate to using device tree

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate to using device tree required for further driver model
> integration.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 19/26] colibri_imx6: change pmic fusing according to hw 1.1 requirements

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> Colibri iMX6 V1.1 HW can use the PMIC GEN3 to power the NVCC_SD1.
> Change the settings fused into the PMIC's OTP to powerup with
> GEN3 set to output 3.3V.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 20/23] configs: apalis_imx6: Use ext4 file system by default

[sbabic at denx.de]

> From: Sanchayan Maity <maitysanchayan@gmail.com>
> Use ext4 file system by default.
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 10/26] colibri_imx6: migrate pmic and regulator to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate PMIC and regulator to using driver model.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 23/26] colibri_imx6: use SDP if USB serial downloader has been used

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> In case USB serial downloader has been used to load U-Boot start the
> serial download protocol (SDP) emulation. This allows to download
> complete images such as Toradex Easy Installer over USB SDP as well.
> This code uses the boot ROM provided boot information to reliably
> detect USB serial downloader.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 18/23] apalis_imx6: disable ri and dcd irq in uarts

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> If the UART is used in DTE mode the RI and DCD bits in UCR3 become
> irq enable bits. Both are set to enabled after reset and both likely
> are pending.
> Disable the bits also on UARTs not used in the boot loader to prevent
> an interrupt storm when Linux enables the UART interrupts.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 16/22] pcm052: board: Remove in-board setup code (it is now replaced by DM setup)

[sbabic at denx.de]

> This commit cleans up the pcm052.c file to remove dead code after moving to
> DTS and DM.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 09/23] apalis_imx6: migrate i2c to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate I2C to using driver model.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 01/23] apalis_imx6: get rid of obsolete nospl configurations

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Now with SPL long since being in place even for recovery using SDP
> finally get rid of those nospl configurations.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 18/26] colibri imx6: disable ri and dcd irq in uarts

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> If the UART is used in DTE mode the RI and DCD bits in UCR3 become
> irq enable bits. Both are set to enabled after reset and both likely
> are pending.
> Disable the bits also on UARTs not used in the boot loader to prevent
> an interrupt storm when Linux enables the UART interrupts.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 06/26] colibri_imx6: migrate to using device tree

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate to using device tree required for further driver model
> integration.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 03/22] vybrid: ddr: Extend vf610-pinfunc.h with DDR pads definitions

[sbabic at denx.de]

> This patch provides definitions necessary for VF610 DDR pad configurations.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> Reviewed-by: Stefan Agner <stefan.agner@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 03/26] colibri_imx6: move console in env from header file to defconfig

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Move console in env from header file to defconfig.
> While at it also update copyright year.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 26/26] board: colibri_imx6: check for and report ecc errors in fuses

[sbabic at denx.de]

> From: Gerard Salvatella <gerard.salvatella@toradex.com>
> The PMIC on the Colibri iMX6 may have ECC errors in fuses that will
> prevent correct settings. Up to one bit error per fuse bank can be
> reported and corrected by the ECC logic. Two bit errors can only be
> reported.
> Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 11/23] apalis_imx6: migrate mmc and sata to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate MMC and SATA to using driver model.
> While at it also enable SCSI driver model.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 20/26] colibri_imx6: revert fuse value set in mfgr_fuse

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> We have two commands to change the bootmode fuses:
> mfgr_fuse which set fuse 0/5 and 0/6
> and
> updt_fuse which burns bit 4 of 0/5.
> Before Image 2.6 we fused in mfgr_fuse 0x5062, which boots
> from the user partition of the eMMC.
> To workaround certain hangs we moved to fastboot mode and
> using the first bootpartition of the eMMC requiring a fuse
> value of 0x5072 which could be achived by the then added
> updt_fuse command. At the same time the mfgr_fuse command
> was changed to also fuse 0x5072, revert that second change
> so that one can fuse both values, one with just mfgr_fuse
> and the later with mfgr_fuse;updt_fuse.
> Note that the mfgr_fuse command is only needed at module
> production time, a customer might need to use updt_fuse
> when upgrading an older module to be compatible with a
> newer image. The command is integrated into the image
> update scripts.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 07/26] colibri_imx6: clean-up and migrate gpios to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate GPIOs to using driver model, properly request backlight, MMC/SD
> card detect and USB power enable GPIOs and also enable SION bit in pin
> muxing for auxiliary, backlight and USB power enable GPIOs.
> While at it also update copyright year, clean-up/re-order includes, add
> some comments clarifying ifdef scope and do some white-space clean-up.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 09/26] colibri_imx6: migrate i2c to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate I2C to using driver model.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 16/26] colibri_imx6: unify sd/mmc drive strenght with linux kernel settings

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> In the linux device tree we use 40Ohm drive strenght. So use the same
> value in U-Boot.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v2,08/23] apalis_imx6: enable pin control driver

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Enable pin control driver as required for further driver model
> migration.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 04/26] colibri_imx6: enable fit image, gpt, imx thermal, efi loader support

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Enbale FIT image, GPT command, i.MX thermal and EFI loader support.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 01/26] colibri_imx6: get rid of obsolete nospl configurations

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Now with SPL long since being in place even for recovery using SDP
> finally get rid of those nospl configurations.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 23/23] board: apalis_imx6: check for and report ecc errors in fuses

[sbabic at denx.de]

> From: Gerard Salvatella <gerard.salvatella@toradex.com>
> The PMIC on Apalis iMX6 may have ECC errors in fuses that will prevent
> correct settings. Up to one bit error per fuse bank may be reported and
> corrected by the ECC logic. Two bit errors can only be reported.
> Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 05/23] apalis_imx6: remove obsolete USB_GADGET_MASS_STORAGE configuration

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Remove obsolete USB_GADGET_MASS_STORAGE configuration.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1, 13/26] colibri_imx6: drop CONFIG_OF_SYSTEM_SETUP

[sbabic at denx.de]

> From: Max Krummenacher <max.krummenacher@toradex.com>
> This doesn't do anything anymore, probably never did.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 04/23] apalis_imx6: enable fit image, gpt, imx thermal, efi loader support

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Enbale FIT image, GPT command, i.MX thermal and EFI loader support.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 17/23] apalis_imx6: pf0100: reorder and cleanup message printing

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Keep debug code at the end of the function.
> Use a one line informational message for the PMIC only.
> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 21/23] apalis_imx6: use SDP if USB serial downloader has been used

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> In case USB serial downloader has been used to load U-Boot start the
> serial download protocol (SDP) emulation. This allows to download
> complete images such as Toradex Easy Installer over USB SDP as well.
> This code uses the boot ROM provided boot information to reliably
> detect USB serial downloader.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 20/22] pcm052: board: Add code to setup LED default states

[sbabic at denx.de]

> As one has moved to DM based LEDs, this code is required to setup the
> default state.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 02/22] net: Kconfig: FEC: Add dependency on VF610

[sbabic at denx.de]

> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> Reviewed-by: Stefan Agner <stefan.agner@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 08/22] pcm052: board: vybrid: Update the board name for BK4 device

[sbabic at denx.de]

> This commit provides distinction between PCM052 and BK4.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 22/22] pcm052: bk4: Add board_phy_config() for BK4 to setup ksz8081 phy

[sbabic at denx.de]

> BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY devices.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v4, 01/22] net: FEC: Add compatible for vybrid (vf610) to reuse fec_mxc.c driver

[sbabic at denx.de]

> The NXP's FEC driver can be reused on vf610 device (with DM).
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> Reviewed-by: Stefan Agner <stefan.agner@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 01/10] board: tbs2910: Fix default environment

[Soeren Moch]

On 01.03.19 13:10, Soeren Moch wrote:
> Especially fix usb keyboard support. Other changes are only for
> beautification.
>
> Signed-off-by: Soeren Moch <smoch@web.de>
> ---
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: u-boot at lists.denx.de
Stefano,

apparently you decided to pull fixes for v2019.04 and DM conversions for
v2019.07. Since this patch (1/10) is a fix, can you at least pull this
now, and the rest of the series later (or for -next)?

Thanks,
Soeren

[U-Boot] [PATCH 01/10] board: tbs2910: Fix default environment

[Stefano Babic]

On 14/03/19 20:16, Soeren Moch wrote:
> On 01.03.19 13:10, Soeren Moch wrote:
>> Especially fix usb keyboard support. Other changes are only for
>> beautification.
>>
>> Signed-off-by: Soeren Moch <smoch@web.de>
>> ---
>> Cc: Stefano Babic <sbabic@denx.de>
>> Cc: u-boot at lists.denx.de
> Stefano,
> 
> apparently you decided to pull fixes for v2019.04 and DM conversions for
> v2019.07.

That is right.

> Since this patch (1/10) is a fix, can you at least pull this
> now, and the rest of the series later (or for -next)?

I pick up 1/10

Regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH RESEND 01/10] pinctrl: imx8: add i.MX8QM compatible

[Peng Fan]

Ping..

Thanks,
Peng.

> -----Original Message-----
> From: Peng Fan [mailto:peng.fan at nxp.com]
> Sent: 2019年3月5日 10:32
> To: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>
> Cc: u-boot at lists.denx.de; van.freenix at gmail.com; dl-uboot-imx
> <uboot-imx@nxp.com>; Peng Fan <peng.fan@nxp.com>
> Subject: [PATCH RESEND 01/10] pinctrl: imx8: add i.MX8QM compatible
> 
> Add i.MX8QM compatible
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/pinctrl/nxp/pinctrl-imx8.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c
> b/drivers/pinctrl/nxp/pinctrl-imx8.c
> index 0738da0ebe..c1b0ca438a 100644
> --- a/drivers/pinctrl/nxp/pinctrl-imx8.c
> +++ b/drivers/pinctrl/nxp/pinctrl-imx8.c
> @@ -25,6 +25,7 @@ static int imx8_pinctrl_probe(struct udevice *dev)
> 
>  static const struct udevice_id imx8_pinctrl_match[] = {
>  	{ .compatible = "fsl,imx8qxp-iomuxc", .data =
> (ulong)&imx8_pinctrl_soc_info },
> +	{ .compatible = "fsl,imx8qm-iomuxc", .data =
> (ulong)&imx8_pinctrl_soc_info },
>  	{ /* sentinel */ }
>  };
> 
> --
> 2.16.4

[U-Boot] [PATCH] imx8qxp: mek: enable dm-spl for pm

[Peng Fan]

Hi Stefano,

Are you fine with this patch?

Thanks,
Peng.

> -----Original Message-----
> From: Peng Fan
> Sent: 2019年3月7日 20:44
> To: sbabic at denx.de; festevam at gmail.com
> Cc: dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de; Peng Fan
> <peng.fan@nxp.com>
> Subject: [PATCH] imx8qxp: mek: enable dm-spl for pm
> 
> with u-boot,dm-spl added for imx8qx-pm node, and SPL_SIMPLE_BUS
> enabled, the bind and probe code in board file could be removed.
> 
> Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi |  5 +++++
>  board/freescale/imx8qxp_mek/spl.c        | 15 ---------------
>  configs/imx8qxp_mek_defconfig            |  2 +-
>  3 files changed, 6 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> index 5d50eb028e..201559008c 100644
> --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> @@ -3,6 +3,11 @@
>   * Copyright 2018 NXP
>   */
> 
> +&{/imx8qx-pm} {
> +
> +	u-boot,dm-spl;
> +};
> +
>  &mu {
>  	u-boot,dm-spl;
>  };
> diff --git a/board/freescale/imx8qxp_mek/spl.c
> b/board/freescale/imx8qxp_mek/spl.c
> index 95ce9f37e8..51f323811a 100644
> --- a/board/freescale/imx8qxp_mek/spl.c
> +++ b/board/freescale/imx8qxp_mek/spl.c
> @@ -27,21 +27,6 @@ void spl_board_init(void)
>  			continue;
>  	}
> 
> -	offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
> "nxp,imx8-pd");
> -	while (offset != -FDT_ERR_NOTFOUND) {
> -		lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
> -			       NULL, true);
> -		offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
> -						       "nxp,imx8-pd");
> -	}
> -
> -	uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
> -
> -	for (; dev; uclass_find_next_device(&dev)) {
> -		if (device_probe(dev))
> -			continue;
> -	}
> -
>  	arch_cpu_init();
> 
>  	board_early_init_f();
> diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
> index a94998b8b5..915d8812ad 100644
> --- a/configs/imx8qxp_mek_defconfig
> +++ b/configs/imx8qxp_mek_defconfig
> @@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x80020000
> CONFIG_SPL_GPIO_SUPPORT=y  CONFIG_SPL_LIBCOMMON_SUPPORT=y
> CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_SYS_MALLOC_F_LEN=0x4000
>  CONFIG_TARGET_IMX8QXP_MEK=y
>  CONFIG_SPL_MMC_SUPPORT=y
>  CONFIG_SPL_SERIAL_SUPPORT=y
> --
> 2.16.4

[U-Boot] [PATCH 00/17] Convert some imx6 boards to DM_VIDEO

[Anatolij Gustschin]

This series starts conversion of ipuv3 driver to DM_VIDEO.
It has been tested on apalis_imx6 module with LVDS display
attached and on wandboard with HDMI display.

With applied "[PATCH 17/17] imx6: wandboard: convert to DM_MMC"
building wandboard target doesn't work. To fix this please
apply patches [1], [2] and enable CONFIG_AHCI and CONFIG_DM_SCSI
in wandboard_defconfig.

[1] http://patchwork.ozlabs.org/patch/1050141
[2] http://patchwork.ozlabs.org/patch/1050143

Anatolij Gustschin (17):
  video: ipuv3: add DM_VIDEO support
  video: move ipuv3 files to subdirectory
  imx: move CONFIG_VIDEO_IPUV3 to defconfigs
  imx6: dts: add 'u-boot,dm-pre-reloc' to soc and ipu nodes
  apalis_imx6: convert to DM_VIDEO
  imx6: icore: convert to DM_VIDEO
  imx6: ge_bx50v3: convert to DM_VIDEO
  colibri_imx6: convert to DM_VIDEO
  mx6sabresd: convert to DM_VIDEO
  mx6sabreauto: convert to DM_VIDEO
  imx6: wandboard: add device tree
  imx6: wandboard: convert to DM_GPIO and enable pinctrl driver
  imx6: wandboard: convert to DM_USB
  imx6: wandboard: convert to DM_VIDEO
  imx6: wandboard: convert to DM_PMIC
  imx6: wandboard: convert to DM_I2C
  imx6: wandboard: convert to DM_MMC

 arch/arm/dts/imx6dl-wandboard-revb1.dts   |  18 +
 arch/arm/dts/imx6qdl-wandboard-revb1.dtsi |  41 +++
 arch/arm/dts/imx6qdl-wandboard.dtsi       | 380 ++++++++++++++++++++++
 arch/arm/dts/imx6qdl.dtsi                 |   2 +
 arch/arm/include/asm/mach-imx/video.h     |   1 +
 arch/arm/mach-imx/video.c                 |  25 +-
 board/wandboard/MAINTAINERS               |   3 +
 board/wandboard/spl.c                     |  92 ++++++
 board/wandboard/wandboard.c               | 160 +++------
 configs/apalis_imx6_defconfig             |   4 +-
 configs/aristainetos2_defconfig           |   1 +
 configs/aristainetos2b_defconfig          |   1 +
 configs/aristainetos_defconfig            |   1 +
 configs/cgtqmx6eval_defconfig             |   1 +
 configs/cm_fx6_defconfig                  |   1 +
 configs/colibri_imx6_defconfig            |   3 +-
 configs/dms-ba16-1g_defconfig             |   1 +
 configs/dms-ba16_defconfig                |   1 +
 configs/ge_bx50v3_defconfig               |   2 +
 configs/gwventana_emmc_defconfig          |   1 +
 configs/gwventana_gw5904_defconfig        |   1 +
 configs/gwventana_nand_defconfig          |   1 +
 configs/imx6dl_icore_nand_defconfig       |   2 +-
 configs/imx6q_icore_nand_defconfig        |   2 +-
 configs/imx6qdl_icore_mmc_defconfig       |   2 +-
 configs/imx6qdl_icore_nand_defconfig      |   2 +-
 configs/m53menlo_defconfig                |   1 +
 configs/marsboard_defconfig               |   1 +
 configs/mx51evk_defconfig                 |   1 +
 configs/mx53cx9020_defconfig              |   1 +
 configs/mx53loco_defconfig                |   1 +
 configs/mx53ppd_defconfig                 |   1 +
 configs/mx6cuboxi_defconfig               |   1 +
 configs/mx6qsabrelite_defconfig           |   1 +
 configs/mx6sabreauto_defconfig            |   3 +-
 configs/mx6sabresd_defconfig              |   3 +-
 configs/nitrogen6dl2g_defconfig           |   1 +
 configs/nitrogen6dl_defconfig             |   1 +
 configs/nitrogen6q2g_defconfig            |   1 +
 configs/nitrogen6q_defconfig              |   1 +
 configs/nitrogen6s1g_defconfig            |   1 +
 configs/nitrogen6s_defconfig              |   1 +
 configs/novena_defconfig                  |   1 +
 configs/riotboard_defconfig               |   1 +
 configs/riotboard_spl_defconfig           |   1 +
 configs/tbs2910_defconfig                 |   1 +
 configs/wandboard_defconfig               |  18 +-
 drivers/video/Kconfig                     |   9 +-
 drivers/video/Makefile                    |   2 +-
 drivers/video/imx/Kconfig                 |   8 +
 drivers/video/imx/Makefile                |   6 +
 drivers/video/{ => imx}/ipu.h             |   0
 drivers/video/{ => imx}/ipu_common.c      |   0
 drivers/video/{ => imx}/ipu_disp.c        |   0
 drivers/video/{ => imx}/ipu_regs.h        |   0
 drivers/video/{ => imx}/mxc_ipuv3_fb.c    |  89 ++++-
 drivers/video/{ => imx}/mxcfb.h           |   0
 include/configs/advantech_dms-ba16.h      |   1 -
 include/configs/apalis_imx6.h             |   1 -
 include/configs/aristainetos-common.h     |   1 -
 include/configs/cgtqmx6eval.h             |   1 -
 include/configs/cm_fx6.h                  |   1 -
 include/configs/colibri_imx6.h            |   1 -
 include/configs/embestmx6boards.h         |   1 -
 include/configs/ge_bx50v3.h               |   8 -
 include/configs/gw_ventana.h              |   1 -
 include/configs/m53menlo.h                |   1 -
 include/configs/mx51evk.h                 |   1 -
 include/configs/mx53cx9020.h              |   1 -
 include/configs/mx53loco.h                |   1 -
 include/configs/mx53ppd.h                 |   5 -
 include/configs/mx6cuboxi.h               |   1 -
 include/configs/mx6sabre_common.h         |   1 -
 include/configs/nitrogen6x.h              |   1 -
 include/configs/novena.h                  |   1 -
 include/configs/tbs2910.h                 |   1 -
 include/configs/wandboard.h               |  18 -
 77 files changed, 766 insertions(+), 187 deletions(-)
 create mode 100644 arch/arm/dts/imx6dl-wandboard-revb1.dts
 create mode 100644 arch/arm/dts/imx6qdl-wandboard-revb1.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-wandboard.dtsi
 create mode 100644 drivers/video/imx/Kconfig
 create mode 100644 drivers/video/imx/Makefile
 rename drivers/video/{ => imx}/ipu.h (100%)
 rename drivers/video/{ => imx}/ipu_common.c (100%)
 rename drivers/video/{ => imx}/ipu_disp.c (100%)
 rename drivers/video/{ => imx}/ipu_regs.h (100%)
 rename drivers/video/{ => imx}/mxc_ipuv3_fb.c (88%)
 rename drivers/video/{ => imx}/mxcfb.h (100%)

-- 
2.17.1

[U-Boot] [PATCH 01/17] video: ipuv3: add DM_VIDEO support

[Anatolij Gustschin]

Extend the driver to build with DM_VIDEO enabled. DTS files
must additionally include 'u-boot,dm-pre-reloc' property in
soc and ipu nodes to enable driver binding to ipu device.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 arch/arm/include/asm/mach-imx/video.h |  1 +
 arch/arm/mach-imx/video.c             | 25 +++++---
 drivers/video/Kconfig                 | 14 ++---
 drivers/video/mxc_ipuv3_fb.c          | 87 +++++++++++++++++++++++++++
 4 files changed, 113 insertions(+), 14 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/video.h b/arch/arm/include/asm/mach-imx/video.h
index 812e6f85e4..d1a14ad7d3 100644
--- a/arch/arm/include/asm/mach-imx/video.h
+++ b/arch/arm/include/asm/mach-imx/video.h
@@ -26,4 +26,5 @@ extern size_t display_count;
 #endif
 
 int ipu_set_ldb_clock(int rate);
+int ipu_displays_init(void);
 #endif
diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c
index 953fe53cb4..22a371a212 100644
--- a/arch/arm/mach-imx/video.c
+++ b/arch/arm/mach-imx/video.c
@@ -4,6 +4,17 @@
 #include <linux/errno.h>
 #include <asm/mach-imx/video.h>
 
+#ifdef CONFIG_IMX_HDMI
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/io.h>
+
+int detect_hdmi(struct display_info_t const *dev)
+{
+	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
+}
+#endif
+
 int board_video_skip(void)
 {
 	int i;
@@ -42,6 +53,11 @@ int board_video_skip(void)
 			       displays[i].mode.name,
 			       displays[i].mode.xres,
 			       displays[i].mode.yres);
+
+#ifdef CONFIG_IMX_HDMI
+			if (!strcmp(displays[i].mode.name, "HDMI"))
+				imx_enable_hdmi_phy();
+#endif
 		} else
 			printf("LCD %s cannot be configured: %d\n",
 			       displays[i].mode.name, ret);
@@ -53,12 +69,7 @@ int board_video_skip(void)
 	return ret;
 }
 
-#ifdef CONFIG_IMX_HDMI
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/io.h>
-int detect_hdmi(struct display_info_t const *dev)
+int ipu_displays_init(void)
 {
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-	return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
+	return board_video_skip();
 }
-#endif
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2eac4b6381..73a2402f41 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -538,6 +538,13 @@ config VIDEO_TEGRA124
 
 source "drivers/video/bridge/Kconfig"
 
+config VIDEO_IPUV3
+	bool "i.MX IPUv3 Core video support"
+	depends on (VIDEO || DM_VIDEO) && (MX5 || MX6)
+	help
+	  This enables framebuffer driver for i.MX processors working
+	  on the IPUv3(Image Processing Unit) internal graphic processor.
+
 config VIDEO
 	bool "Enable legacy video support"
 	depends on !DM_VIDEO
@@ -547,13 +554,6 @@ config VIDEO
 	  model. Video drivers typically provide a colour text console and
 	  cursor.
 
-config VIDEO_IPUV3
-	bool "i.MX IPUv3 Core video support"
-	depends on VIDEO && MX6
-	help
-	  This enables framebuffer driver for i.MX processors working
-	  on the IPUv3(Image Processing Unit) internal graphic processor.
-
 config CFB_CONSOLE
 	bool "Enable colour frame buffer console"
 	depends on VIDEO
diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c
index 23cd55de47..5b3ba7b3a9 100644
--- a/drivers/video/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc_ipuv3_fb.c
@@ -17,6 +17,7 @@
 #include <linux/list.h>
 #include <linux/fb.h>
 #include <asm/io.h>
+#include <asm/mach-imx/video.h>
 #include <malloc.h>
 #include <video_fb.h>
 #include "videomodes.h"
@@ -24,6 +25,9 @@
 #include "mxcfb.h"
 #include "ipu_regs.h"
 
+#include <dm.h>
+#include <video.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static int mxcfb_map_video_memory(struct fb_info *fbi);
@@ -401,8 +405,14 @@ static int mxcfb_map_video_memory(struct fb_info *fbi)
 				    fbi->fix.line_length;
 	}
 	fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN);
+
+#if CONFIG_IS_ENABLED(DM_VIDEO)
+	fbi->screen_base = (char *)gd->video_bottom;
+#else
 	fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
 					    fbi->fix.smem_len);
+#endif
+
 	fbi->fix.smem_start = (unsigned long)fbi->screen_base;
 	if (fbi->screen_base == 0) {
 		puts("Unable to allocate framebuffer memory\n");
@@ -416,7 +426,9 @@ static int mxcfb_map_video_memory(struct fb_info *fbi)
 
 	fbi->screen_size = fbi->fix.smem_len;
 
+#if CONFIG_IS_ENABLED(VIDEO)
 	gd->fb_base = fbi->fix.smem_start;
+#endif
 
 	/* Clear the screen */
 	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
@@ -611,3 +623,78 @@ int ipuv3_fb_init(struct fb_videomode const *mode,
 
 	return 0;
 }
+
+#if CONFIG_IS_ENABLED(DM_VIDEO)
+enum {
+	/* Maximum display size we support */
+	LCD_MAX_WIDTH		= 1920,
+	LCD_MAX_HEIGHT		= 1080,
+	LCD_MAX_LOG2_BPP	= VIDEO_BPP16,
+};
+
+static int ipuv3_video_probe(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	u32 fb_start, fb_end;
+	int ret;
+
+	debug("%s() plat: base 0x%lx, size 0x%x\n",
+	      __func__, plat->base, plat->size);
+
+	ret = ipu_probe();
+	if (ret)
+		return ret;
+
+	ret = ipu_displays_init();
+	if (ret < 0)
+		return ret;
+
+	ret = mxcfb_probe(gpixfmt, gdisp, gmode);
+	if (ret < 0)
+		return ret;
+
+	uc_priv->xsize = gmode->xres;
+	uc_priv->ysize = gmode->yres;
+	uc_priv->bpix = LCD_MAX_LOG2_BPP;
+
+	/* Enable dcache for the frame buffer */
+	fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
+	fb_end = plat->base + plat->size;
+	fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
+	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
+					DCACHE_WRITEBACK);
+	video_set_flush_dcache(dev, true);
+
+	return 0;
+}
+
+struct ipuv3_video_priv {
+	ulong regs;
+};
+
+static int ipuv3_video_bind(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+
+	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
+		     (1 << LCD_MAX_LOG2_BPP) / 8;
+
+	return 0;
+}
+
+static const struct udevice_id ipuv3_video_ids[] = {
+	{ .compatible = "fsl,imx6q-ipu" },
+	{ }
+};
+
+U_BOOT_DRIVER(ipuv3_video) = {
+	.name	= "ipuv3_video",
+	.id	= UCLASS_VIDEO,
+	.of_match = ipuv3_video_ids,
+	.bind	= ipuv3_video_bind,
+	.probe	= ipuv3_video_probe,
+	.priv_auto_alloc_size = sizeof(struct ipuv3_video_priv),
+	.flags	= DM_FLAG_PRE_RELOC,
+};
+#endif /* CONFIG_DM_VIDEO */
-- 
2.17.1

[U-Boot] [PATCH 02/17] video: move ipuv3 files to subdirectory

[Anatolij Gustschin]

Place ipuv3 files and headers in custom driver subdirectory.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 drivers/video/Kconfig                  | 7 +------
 drivers/video/Makefile                 | 2 +-
 drivers/video/imx/Kconfig              | 8 ++++++++
 drivers/video/imx/Makefile             | 6 ++++++
 drivers/video/{ => imx}/ipu.h          | 0
 drivers/video/{ => imx}/ipu_common.c   | 0
 drivers/video/{ => imx}/ipu_disp.c     | 0
 drivers/video/{ => imx}/ipu_regs.h     | 0
 drivers/video/{ => imx}/mxc_ipuv3_fb.c | 2 +-
 drivers/video/{ => imx}/mxcfb.h        | 0
 10 files changed, 17 insertions(+), 8 deletions(-)
 create mode 100644 drivers/video/imx/Kconfig
 create mode 100644 drivers/video/imx/Makefile
 rename drivers/video/{ => imx}/ipu.h (100%)
 rename drivers/video/{ => imx}/ipu_common.c (100%)
 rename drivers/video/{ => imx}/ipu_disp.c (100%)
 rename drivers/video/{ => imx}/ipu_regs.h (100%)
 rename drivers/video/{ => imx}/mxc_ipuv3_fb.c (99%)
 rename drivers/video/{ => imx}/mxcfb.h (100%)

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 73a2402f41..53871f864f 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -538,12 +538,7 @@ config VIDEO_TEGRA124
 
 source "drivers/video/bridge/Kconfig"
 
-config VIDEO_IPUV3
-	bool "i.MX IPUv3 Core video support"
-	depends on (VIDEO || DM_VIDEO) && (MX5 || MX6)
-	help
-	  This enables framebuffer driver for i.MX processors working
-	  on the IPUv3(Image Processing Unit) internal graphic processor.
+source "drivers/video/imx/Kconfig"
 
 config VIDEO
 	bool "Enable legacy video support"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 671f037c35..349a207035 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -46,7 +46,7 @@ obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
 obj-$(CONFIG_VIDEO_EFI) += efi.o
 obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
-obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+obj-$(CONFIG_VIDEO_IPUV3) += imx/
 obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig
new file mode 100644
index 0000000000..c33620e075
--- /dev/null
+++ b/drivers/video/imx/Kconfig
@@ -0,0 +1,8 @@
+
+config VIDEO_IPUV3
+	bool "i.MX IPUv3 Core video support"
+	depends on (VIDEO || DM_VIDEO) && (MX5 || MX6)
+	help
+	  This enables framebuffer driver for i.MX processors working
+	  on the IPUv3(Image Processing Unit) internal graphic processor.
+
diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile
new file mode 100644
index 0000000000..179ea651fe
--- /dev/null
+++ b/drivers/video/imx/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+
+obj-y += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
diff --git a/drivers/video/ipu.h b/drivers/video/imx/ipu.h
similarity index 100%
rename from drivers/video/ipu.h
rename to drivers/video/imx/ipu.h
diff --git a/drivers/video/ipu_common.c b/drivers/video/imx/ipu_common.c
similarity index 100%
rename from drivers/video/ipu_common.c
rename to drivers/video/imx/ipu_common.c
diff --git a/drivers/video/ipu_disp.c b/drivers/video/imx/ipu_disp.c
similarity index 100%
rename from drivers/video/ipu_disp.c
rename to drivers/video/imx/ipu_disp.c
diff --git a/drivers/video/ipu_regs.h b/drivers/video/imx/ipu_regs.h
similarity index 100%
rename from drivers/video/ipu_regs.h
rename to drivers/video/imx/ipu_regs.h
diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c
similarity index 99%
rename from drivers/video/mxc_ipuv3_fb.c
rename to drivers/video/imx/mxc_ipuv3_fb.c
index 5b3ba7b3a9..3e38d4bdcc 100644
--- a/drivers/video/mxc_ipuv3_fb.c
+++ b/drivers/video/imx/mxc_ipuv3_fb.c
@@ -20,7 +20,7 @@
 #include <asm/mach-imx/video.h>
 #include <malloc.h>
 #include <video_fb.h>
-#include "videomodes.h"
+#include "../videomodes.h"
 #include "ipu.h"
 #include "mxcfb.h"
 #include "ipu_regs.h"
diff --git a/drivers/video/mxcfb.h b/drivers/video/imx/mxcfb.h
similarity index 100%
rename from drivers/video/mxcfb.h
rename to drivers/video/imx/mxcfb.h
-- 
2.17.1

[U-Boot] [PATCH 03/17] imx: move CONFIG_VIDEO_IPUV3 to defconfigs

[Anatolij Gustschin]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 configs/apalis_imx6_defconfig         | 1 +
 configs/aristainetos2_defconfig       | 1 +
 configs/aristainetos2b_defconfig      | 1 +
 configs/aristainetos_defconfig        | 1 +
 configs/cgtqmx6eval_defconfig         | 1 +
 configs/cm_fx6_defconfig              | 1 +
 configs/colibri_imx6_defconfig        | 1 +
 configs/dms-ba16-1g_defconfig         | 1 +
 configs/dms-ba16_defconfig            | 1 +
 configs/ge_bx50v3_defconfig           | 2 ++
 configs/gwventana_emmc_defconfig      | 1 +
 configs/gwventana_gw5904_defconfig    | 1 +
 configs/gwventana_nand_defconfig      | 1 +
 configs/m53menlo_defconfig            | 1 +
 configs/marsboard_defconfig           | 1 +
 configs/mx51evk_defconfig             | 1 +
 configs/mx53cx9020_defconfig          | 1 +
 configs/mx53loco_defconfig            | 1 +
 configs/mx53ppd_defconfig             | 1 +
 configs/mx6cuboxi_defconfig           | 1 +
 configs/mx6qsabrelite_defconfig       | 1 +
 configs/mx6sabreauto_defconfig        | 1 +
 configs/mx6sabresd_defconfig          | 1 +
 configs/nitrogen6dl2g_defconfig       | 1 +
 configs/nitrogen6dl_defconfig         | 1 +
 configs/nitrogen6q2g_defconfig        | 1 +
 configs/nitrogen6q_defconfig          | 1 +
 configs/nitrogen6s1g_defconfig        | 1 +
 configs/nitrogen6s_defconfig          | 1 +
 configs/novena_defconfig              | 1 +
 configs/riotboard_defconfig           | 1 +
 configs/riotboard_spl_defconfig       | 1 +
 configs/tbs2910_defconfig             | 1 +
 configs/wandboard_defconfig           | 1 +
 include/configs/advantech_dms-ba16.h  | 1 -
 include/configs/apalis_imx6.h         | 1 -
 include/configs/aristainetos-common.h | 1 -
 include/configs/cgtqmx6eval.h         | 1 -
 include/configs/cm_fx6.h              | 1 -
 include/configs/colibri_imx6.h        | 1 -
 include/configs/embestmx6boards.h     | 1 -
 include/configs/ge_bx50v3.h           | 6 ------
 include/configs/gw_ventana.h          | 1 -
 include/configs/m53menlo.h            | 1 -
 include/configs/mx51evk.h             | 1 -
 include/configs/mx53cx9020.h          | 1 -
 include/configs/mx53loco.h            | 1 -
 include/configs/mx53ppd.h             | 5 -----
 include/configs/mx6cuboxi.h           | 1 -
 include/configs/mx6sabre_common.h     | 1 -
 include/configs/nitrogen6x.h          | 1 -
 include/configs/novena.h              | 1 -
 include/configs/tbs2910.h             | 1 -
 include/configs/wandboard.h           | 1 -
 54 files changed, 35 insertions(+), 29 deletions(-)

diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 1ab5edc966..60ca8a5147 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -82,5 +82,6 @@ CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 CONFIG_FAT_WRITE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index f7de4e3b9a..60be6ba17b 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -51,6 +51,7 @@ CONFIG_MXC_SPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_IMX_WATCHDOG=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index ff21f1f2c4..64f56ab58e 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -51,6 +51,7 @@ CONFIG_MXC_SPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_IMX_WATCHDOG=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index 950f9f6baa..757d6ccb42 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -50,6 +50,7 @@ CONFIG_MXC_SPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_IMX_WATCHDOG=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 99c581b2de..fb99c6c73c 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -72,5 +72,6 @@ CONFIG_CI_UDC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index c8d1e83111..abdfc7f705 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -76,4 +76,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index df5a7be39f..611f9f0950 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -78,5 +78,6 @@ CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 CONFIG_FAT_WRITE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig
index a2f4395b9e..845e75f145 100644
--- a/configs/dms-ba16-1g_defconfig
+++ b/configs/dms-ba16-1g_defconfig
@@ -51,5 +51,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig
index 2784c1268e..c04786a974 100644
--- a/configs/dms-ba16_defconfig
+++ b/configs/dms-ba16_defconfig
@@ -50,5 +50,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 22349a08c7..91782b06a8 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -60,3 +60,5 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index 07171c7009..2e04127014 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -84,6 +84,7 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_HEXDUMP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index 0ed2209e3b..275aa89ed6 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -88,6 +88,7 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_HEXDUMP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 57e4a999ab..477d205bc3 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -87,6 +87,7 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_HEXDUMP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index 5555e05030..e830b2c92e 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -64,6 +64,7 @@ CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_IMX_WATCHDOG=y
 CONFIG_FAT_WRITE=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 48bec11c10..30d765946e 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -33,5 +33,6 @@ CONFIG_USB=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index e93e81f3c3..dc0b3b3f77 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -31,5 +31,6 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig
index 07f3a23028..831d50925f 100644
--- a/configs/mx53cx9020_defconfig
+++ b/configs/mx53cx9020_defconfig
@@ -32,4 +32,5 @@ CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX5=y
 CONFIG_MXC_UART=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index 4e161371e3..776fc8bab4 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -32,5 +32,6 @@ CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index db31d817aa..2a6183b77b 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -39,6 +39,7 @@ CONFIG_RTC_S35392A=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_IMX_WATCHDOG=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 506e3a71df..f1c2fd4dba 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -39,5 +39,6 @@ CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 2666340615..3d0e57d087 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -55,5 +55,6 @@ CONFIG_CI_UDC=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index f51b5af7ab..e52ad368d2 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -83,4 +83,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index ac879a3d20..ea34217e1c 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -94,4 +94,5 @@ CONFIG_CI_UDC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index af59a71d3b..a5c1e7a492 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -57,5 +57,6 @@ CONFIG_CI_UDC=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 9072c04446..6fe9e9da20 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -57,5 +57,6 @@ CONFIG_CI_UDC=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index b92d27a475..b8fb34ca25 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -59,5 +59,6 @@ CONFIG_CI_UDC=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index 3b8cc6ad2f..3c4c386101 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -59,5 +59,6 @@ CONFIG_CI_UDC=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 36cfe2196c..9c0356b3a9 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -57,5 +57,6 @@ CONFIG_CI_UDC=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 40c09d7ab6..dc104bab56 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -57,5 +57,6 @@ CONFIG_CI_UDC=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 4c9c1cb9eb..103d9183cb 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -58,6 +58,7 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_FAT_WRITE=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index a9191ad846..cdfc5c6a16 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -33,5 +33,6 @@ CONFIG_USB=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig
index 2298d5b615..8d67599469 100644
--- a/configs/riotboard_spl_defconfig
+++ b/configs/riotboard_spl_defconfig
@@ -42,6 +42,7 @@ CONFIG_USB=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
 CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 78beb9a522..ad37daa98f 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -55,4 +55,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 5725487446..9a67e63132 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -42,5 +42,6 @@ CONFIG_MII=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
index 0c9de6125d..382750986d 100644
--- a/include/configs/advantech_dms-ba16.h
+++ b/include/configs/advantech_dms-ba16.h
@@ -227,7 +227,6 @@
 
 /* Framebuffer */
 #ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index c8aa1bdddf..fc72a55255 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -80,7 +80,6 @@
 #define CONFIG_USBD_HS
 
 /* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
index ca974c015f..3d0e7cf5d9 100644
--- a/include/configs/aristainetos-common.h
+++ b/include/configs/aristainetos-common.h
@@ -193,7 +193,6 @@
 /* UBI support */
 
 /* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
 /* check this console not needed, after test remove it */
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index e01bf5bf1b..ac3b96a200 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -63,7 +63,6 @@
 #define CONFIG_USBD_HS
 
 /* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index f7e82dfbdb..3aafa7e815 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -220,7 +220,6 @@
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
 
 /* Display */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_IMX_HDMI
 
 #define CONFIG_SPLASH_SCREEN
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index a6a823ee1f..802270e401 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -71,7 +71,6 @@
 #define CONFIG_USBD_HS
 
 /* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index 7e7de4dae6..d8935499c1 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -97,7 +97,6 @@
 #endif
 
 /* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index a5d7cb1be0..cc6a4f9bac 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -208,13 +208,7 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	3
 
 /* Framebuffer */
-#define CONFIG_VIDEO
 #ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_FG_COL 0xFF
-#define CONFIG_SYS_CONSOLE_BG_COL 0x00
 #define CONFIG_HIDE_LOGO_VERSION
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 6e23fa29b3..d1fabc64dc 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -136,7 +136,6 @@
 #define CONFIG_NETCONSOLE
 
 /* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 51456fbe55..84d061339e 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -138,7 +138,6 @@
  * LCD
  */
 #ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SPLASH_SCREEN
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index eb172c97b3..9bf9773c69 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -68,7 +68,6 @@
 
 /* Framebuffer and LCD */
 #define CONFIG_PREBOOT
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index 3ed5ee3c57..1e3ea88b77 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h
@@ -161,7 +161,6 @@
 
 /* Framebuffer and LCD */
 #define CONFIG_PREBOOT
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 816164e87e..2d18f05423 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -178,7 +178,6 @@
 
 /* Framebuffer and LCD */
 #define CONFIG_PREBOOT
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index 5b97fe9843..f002324fdd 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h
@@ -215,9 +215,4 @@
 #define CONFIG_PWM_IMX
 #define CONFIG_IMX6_PWM_PER_CLK 66666000
 
-/* Framebuffer and LCD */
-#ifdef CONFIG_VIDEO
-	#define CONFIG_VIDEO_IPUV3
-#endif
-
 #endif				/* __CONFIG_H */
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index a62e14f7c6..7b4ae2102e 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -35,7 +35,6 @@
 #define CONFIG_PHY_ATHEROS
 
 /* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 711aa82f9c..73888c7f4f 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -192,7 +192,6 @@
 #endif
 
 /* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index c364442244..e8a6c6697c 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -65,7 +65,6 @@
 #define CONFIG_MXC_USB_FLAGS	0
 
 /* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 25736f3c03..bb5bf808c2 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -125,7 +125,6 @@
 
 /* Video output */
 #ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 2d4b9c9bfe..761be0987b 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -58,7 +58,6 @@
 
 /* Framebuffer */
 #ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index b03a1c550c..e6d1fcacf5 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -65,7 +65,6 @@
 
 /* Framebuffer */
 #ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
-- 
2.17.1

[U-Boot] [PATCH 04/17] imx6: dts: add 'u-boot, dm-pre-reloc' to soc and ipu nodes

[Anatolij Gustschin]

u-boot,dm-pre-reloc is required for reserving video memory
when binding DM_VIDEO driver.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 arch/arm/dts/imx6qdl.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index e4daf15088..c0a9478008 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -145,6 +145,7 @@
 		compatible = "simple-bus";
 		interrupt-parent = <&gpc>;
 		ranges;
+		u-boot,dm-pre-reloc;
 
 		dma_apbh: dma-apbh at 110000 {
 			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@@ -1261,6 +1262,7 @@
 				 <&clks IMX6QDL_CLK_IPU1_DI1>;
 			clock-names = "bus", "di0", "di1";
 			resets = <&src 2>;
+			u-boot,dm-pre-reloc;
 
 			ipu1_csi0: port at 0 {
 				reg = <0>;
-- 
2.17.1

[U-Boot] [PATCH 05/17] apalis_imx6: convert to DM_VIDEO

[Anatolij Gustschin]

Enable DM_VIDEO in defconfig.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 configs/apalis_imx6_defconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 60ca8a5147..06695208bc 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -81,7 +81,8 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
 CONFIG_FAT_WRITE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-- 
2.17.1

[U-Boot] [PATCH 06/17] imx6: icore: convert to DM_VIDEO

[Anatolij Gustschin]

Enable DM_VIDEO in defconfigs.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 configs/imx6dl_icore_nand_defconfig  | 2 +-
 configs/imx6q_icore_nand_defconfig   | 2 +-
 configs/imx6qdl_icore_mmc_defconfig  | 2 +-
 configs/imx6qdl_icore_nand_defconfig | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
index c34c515080..d81f00faec 100644
--- a/configs/imx6dl_icore_nand_defconfig
+++ b/configs/imx6dl_icore_nand_defconfig
@@ -49,5 +49,5 @@ CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
index cf149d615b..8702426561 100644
--- a/configs/imx6q_icore_nand_defconfig
+++ b/configs/imx6q_icore_nand_defconfig
@@ -50,5 +50,5 @@ CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index 68ad1c6d20..a8b0c6ef49 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -67,5 +67,5 @@ CONFIG_PINCTRL_IMX6=y
 CONFIG_DEBUG_UART_MXC=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig
index cf149d615b..8702426561 100644
--- a/configs/imx6qdl_icore_nand_defconfig
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -50,5 +50,5 @@ CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
-- 
2.17.1

[U-Boot] [PATCH 07/17] imx6: ge_bx50v3: convert to DM_VIDEO

[Anatolij Gustschin]

Enable DM_VIDEO in defconfig.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 configs/ge_bx50v3_defconfig | 2 +-
 include/configs/ge_bx50v3.h | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 91782b06a8..da8a5ee28d 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -60,5 +60,5 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_OF_BOARD_SETUP=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index cc6a4f9bac..8762d7e095 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -208,12 +208,10 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	3
 
 /* Framebuffer */
-#ifdef CONFIG_VIDEO
 #define CONFIG_HIDE_LOGO_VERSION
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #define CONFIG_CMD_BMP
-#endif
 
 #define CONFIG_PWM_IMX
 #define CONFIG_IMX6_PWM_PER_CLK	66000000
-- 
2.17.1

[U-Boot] [PATCH 08/17] colibri_imx6: convert to DM_VIDEO

[Anatolij Gustschin]

Enable DM_VIDEO in defconfig.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 configs/colibri_imx6_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 611f9f0950..bf05c68807 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -77,7 +77,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
 CONFIG_FAT_WRITE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-- 
2.17.1

[U-Boot] [PATCH 09/17] mx6sabresd: convert to DM_VIDEO

[Anatolij Gustschin]

Enable DM_VIDEO in defconfig.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 configs/mx6sabresd_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index ea34217e1c..825218c0d6 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -93,6 +93,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
-- 
2.17.1

[U-Boot] [PATCH 10/17] mx6sabreauto: convert to DM_VIDEO

[Anatolij Gustschin]

Enable DM_VIDEO in defconfig.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 configs/mx6sabreauto_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index e52ad368d2..bcb3f314b1 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -82,6 +82,6 @@ CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
-- 
2.17.1

[U-Boot] [PATCH 11/17] imx6: wandboard: add device tree

[Anatolij Gustschin]

Add device trees from Linux in preparation for driver model
conversions.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 arch/arm/dts/imx6dl-wandboard-revb1.dts   |  18 ++
 arch/arm/dts/imx6qdl-wandboard-revb1.dtsi |  41 ++++
 arch/arm/dts/imx6qdl-wandboard.dtsi       | 279 ++++++++++++++++++++++
 board/wandboard/MAINTAINERS               |   3 +
 configs/wandboard_defconfig               |   3 +-
 5 files changed, 343 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx6dl-wandboard-revb1.dts
 create mode 100644 arch/arm/dts/imx6qdl-wandboard-revb1.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-wandboard.dtsi

diff --git a/arch/arm/dts/imx6dl-wandboard-revb1.dts b/arch/arm/dts/imx6dl-wandboard-revb1.dts
new file mode 100644
index 0000000000..738db4fc77
--- /dev/null
+++ b/arch/arm/dts/imx6dl-wandboard-revb1.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-wandboard-revb1.dtsi"
+
+/ {
+	model = "Wandboard i.MX6 Dual Lite Board rev B1";
+	compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
+
+	memory at 10000000 {
+		reg = <0x10000000 0x40000000>;
+	};
+};
diff --git a/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi
new file mode 100644
index 0000000000..855dc6f9df
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "imx6qdl-wandboard.dtsi"
+
+&iomuxc {
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx6qdl-wandboard {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x80000000	/* uSDHC1 CD */
+				MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0x80000000	/* uSDHC3 CD */
+				MX6QDL_PAD_EIM_EB1__GPIO2_IO29		0x0f0b0		/* WL_REF_ON */
+				MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x0f0b0		/* WL_RST_N */
+				MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x000b0		/* WL_REG_ON */
+				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x80000000	/* WL_HOST_WAKE */
+				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x80000000	/* WL_WAKE */
+				MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x80000000	/* RGMII_nRST */
+				MX6QDL_PAD_EIM_DA13__GPIO3_IO13		0x80000000	/* BT_ON */
+				MX6QDL_PAD_EIM_DA14__GPIO3_IO14		0x80000000	/* BT_WAKE */
+				MX6QDL_PAD_EIM_DA15__GPIO3_IO15		0x80000000	/* BT_HOST_WAKE */
+			>;
+		};
+	};
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	non-removable;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl-wandboard.dtsi b/arch/arm/dts/imx6qdl-wandboard.dtsi
new file mode 100644
index 0000000000..381bf61fcd
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-wandboard.dtsi
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	sound {
+		compatible = "fsl,imx6-wandboard-sgtl5000",
+			     "fsl,imx-audio-sgtl5000";
+		model = "imx6-wandboard-sgtl5000";
+		ssi-controller = <&ssi1>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"Headphone Jack", "HP_OUT";
+		mux-int-port = <1>;
+		mux-ext-port = <3>;
+	};
+
+	sound-spdif {
+		compatible = "fsl,imx-audio-spdif";
+		model = "imx-spdif";
+		spdif-controller = <&spdif>;
+		spdif-out;
+	};
+
+	reg_2p5v: regulator-2p5v {
+		compatible = "regulator-fixed";
+		regulator-name = "2P5V";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_usb_otg_vbus: regulator-usbotgvbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbotgvbus>;
+		gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c1>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	codec: sgtl5000 at a {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_mclk>;
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
+		VDDA-supply = <&reg_2p5v>;
+		VDDIO-supply = <&reg_3p3v>;
+		lrclk-strength = <3>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx6qdl-wandboard {
+
+		pinctrl_audmux: audmuxgrp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
+				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
+				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
+				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
+			>;
+		};
+
+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
+				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
+				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
+				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
+				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_mclk: mclkgrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0
+			>;
+		};
+
+		pinctrl_spdif: spdifgrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_RXD0__SPDIF_OUT		0x1b0b0
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+			>;
+		};
+
+		pinctrl_uart3: uart3grp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
+				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
+				MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
+				MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
+			>;
+		};
+
+		pinctrl_usbotg: usbotggrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
+			>;
+		};
+
+		pinctrl_usbotgvbus: usbotgvbusgrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x130b0
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
+				MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
+				MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
+				MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
+				MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
+				MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+			>;
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+	fsl,err006687-workaround-present;
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif>;
+	status = "okay";
+};
+
+&ssi1 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&usbh1 {
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
diff --git a/board/wandboard/MAINTAINERS b/board/wandboard/MAINTAINERS
index d7cbae8f95..00a31a9346 100644
--- a/board/wandboard/MAINTAINERS
+++ b/board/wandboard/MAINTAINERS
@@ -1,6 +1,9 @@
 WANDBOARD BOARD
 M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
+F:	arch/arm/dts/imx6qdl-wandboard.dtsi
+F:	arch/arm/dts/imx6qdl-wandboard-revb1.dtsi
+F:	arch/arm/dts/imx6dl-wandboard-revb1.dts
 F:	board/wandboard/
 F:	include/configs/wandboard.h
 F:	configs/wandboard_defconfig
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 9a67e63132..9307ea6c64 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -32,6 +32,8 @@ CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-wandboard-revb1"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
@@ -44,4 +46,3 @@ CONFIG_USB=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
-- 
2.17.1

[U-Boot] [PATCH 12/17] imx6: wandboard: convert to DM_GPIO and enable pinctrl driver

[Anatolij Gustschin]

Enable DM_GPIO and pinctrl in defconfig and add gpio_request()
calls where required.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 board/wandboard/wandboard.c | 12 ++++++++++++
 configs/wandboard_defconfig |  3 +++
 2 files changed, 15 insertions(+)

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 6af1b45882..e0d5769131 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -131,12 +131,14 @@ static void setup_iomux_enet(void)
 	if (with_pmic) {
 		SETUP_IOMUX_PADS(enet_ar8035_power_pads);
 		/* enable AR8035 POWER */
+		gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
 		gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
 	}
 	/* wait until 3.3V of PHY and clock become stable */
 	mdelay(10);
 
 	/* Reset AR8031 PHY */
+	gpio_request(ETH_PHY_RESET, "PHY_RESET");
 	gpio_direction_output(ETH_PHY_RESET, 0);
 	mdelay(10);
 	gpio_set_value(ETH_PHY_RESET, 1);
@@ -170,6 +172,11 @@ int board_mmc_init(bd_t *bis)
 	int ret;
 	u32 index = 0;
 
+#if !CONFIG_IS_ENABLED(DM_MMC)
+	gpio_request(USDHC1_CD_GPIO, "USDHC1_CD");
+	gpio_request(USDHC3_CD_GPIO, "USDHC3_CD");
+#endif
+
 	/*
 	 * Following map is done:
 	 * (U-Boot device node)    (Physical Port)
@@ -356,6 +363,8 @@ static void enable_fwadapt_7wvga(struct display_info_t const *dev)
 {
 	SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
 
+	gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
+	gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
 	gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
 	gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
 }
@@ -418,6 +427,7 @@ static void setup_display(void)
 
 	/* Disable LCD backlight */
 	SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
+	gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
 	gpio_direction_input(IMX_GPIO_NR(4, 20));
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
@@ -548,6 +558,8 @@ int board_init(void)
 
 int checkboard(void)
 {
+	gpio_request(REV_DETECTION, "REV_DETECT");
+
 	if (is_revd1())
 		puts("Board: Wandboard rev D1\n");
 	else if (is_revc1())
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 9307ea6c64..11cf4415ae 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -38,9 +38,12 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
+CONFIG_DM_GPIO=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_VIDEO=y
-- 
2.17.1

[U-Boot] [PATCH 13/17] imx6: wandboard: convert to DM_USB

[Anatolij Gustschin]

Drop CONFIG_USB_MAX_CONTROLLER_COUNT and enable DM_USB
in defconfig.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 configs/wandboard_defconfig | 1 +
 include/configs/wandboard.h | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 11cf4415ae..9e13d7f67c 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -46,6 +46,7 @@ CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index e6d1fcacf5..e01e3e3669 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -51,7 +51,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 
 /* USB Configs */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS		0
 
-- 
2.17.1

[U-Boot] [PATCH 14/17] imx6: wandboard: convert to DM_VIDEO

[Anatolij Gustschin]

Enable DM_VIDEO in defconfig.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 configs/wandboard_defconfig | 2 +-
 include/configs/wandboard.h | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 9e13d7f67c..c4018cce4a 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -47,6 +47,6 @@ CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index e01e3e3669..13a9fd2450 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -63,7 +63,6 @@
 #define CONFIG_PHY_ATHEROS
 
 /* Framebuffer */
-#ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
@@ -72,7 +71,6 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
-#endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"console=ttymxc0\0" \
-- 
2.17.1

[U-Boot] [PATCH 15/17] imx6: wandboard: convert to DM_PMIC

[Anatolij Gustschin]

Enable DM_PMIC_PFUZE100 driver and add PMIC description to DTS.
Rework power_init_board() code.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 arch/arm/dts/imx6qdl-wandboard.dtsi | 101 ++++++++++++++++++++++++++++
 board/wandboard/wandboard.c         |  38 ++++++-----
 configs/wandboard_defconfig         |   2 +
 include/configs/wandboard.h         |   6 --
 4 files changed, 125 insertions(+), 22 deletions(-)

diff --git a/arch/arm/dts/imx6qdl-wandboard.dtsi b/arch/arm/dts/imx6qdl-wandboard.dtsi
index 381bf61fcd..4d03d49fde 100644
--- a/arch/arm/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/dts/imx6qdl-wandboard.dtsi
@@ -90,6 +90,107 @@
 		VDDIO-supply = <&reg_3p3v>;
 		lrclk-strength = <3>;
 	};
+
+	pmic: pfuze100 at 8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
 };
 
 &iomuxc {
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index e0d5769131..23589df932 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -453,24 +453,30 @@ int board_early_init_f(void)
 
 int power_init_board(void)
 {
-	struct pmic *p;
-	u32 reg;
-
-	/* configure PFUZE100 PMIC */
-	power_pfuze100_init(PMIC_I2C_BUS);
-	p = pmic_get("PFUZE100");
-	if (p && !pmic_probe(p)) {
-		pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
-		printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
-		with_pmic = true;
-
-		/* Set VGEN2 to 1.5V and enable */
-		pmic_reg_read(p, PFUZE100_VGEN2VOL, &reg);
-		reg &= ~(LDO_VOL_MASK);
-		reg |= (LDOA_1_50V | (1 << (LDO_EN)));
-		pmic_reg_write(p, PFUZE100_VGEN2VOL, reg);
+	struct udevice *dev;
+	int reg, ret;
+
+	puts("PMIC:  ");
+
+	ret = pmic_get("pfuze100", &dev);
+	if (ret < 0) {
+		printf("pmic_get() ret %d\n", ret);
+		return 0;
 	}
 
+	reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	if (reg < 0) {
+		printf("pmic_reg_read() ret %d\n", reg);
+		return 0;
+	}
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+	with_pmic = true;
+
+	/* Set VGEN2 to 1.5V and enable */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
+	reg &= ~(LDO_VOL_MASK);
+	reg |= (LDOA_1_50V | (1 << (LDO_EN)));
+	pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
 	return 0;
 }
 
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index c4018cce4a..63f2639bd3 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -44,6 +44,8 @@ CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 13a9fd2450..aeb66ad454 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -40,12 +40,6 @@
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
-
 /* MMC Configuration */
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
-- 
2.17.1

[U-Boot] [PATCH 16/17] imx6: wandboard: convert to DM_I2C

[Anatolij Gustschin]

Allow building with DM_I2C enabled.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 board/wandboard/wandboard.c | 23 ++++++++++++++++++-----
 configs/wandboard_defconfig |  5 +++++
 include/configs/wandboard.h |  8 --------
 3 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 23589df932..c0902abe38 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -355,8 +355,21 @@ static void do_enable_hdmi(struct display_info_t const *dev)
 
 static int detect_i2c(struct display_info_t const *dev)
 {
+#ifdef CONFIG_DM_I2C
+	struct udevice *bus, *udev;
+	int rc;
+
+	rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
+	if (rc)
+		return rc;
+	rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
+	if (rc)
+		return 0;
+	return 1;
+#else
 	return (0 == i2c_set_bus_num(dev->bus)) &&
 			(0 == i2c_probe(dev->addr));
+#endif
 }
 
 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
@@ -547,13 +560,13 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 #if defined(CONFIG_VIDEO_IPUV3)
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+	setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
 	if (is_mx6dq() || is_mx6dqp()) {
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
-		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
+		setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6q_i2c2_pad_info);
+		setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6q_i2c3_pad_info);
 	} else {
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
-		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
+		setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+		setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
 	}
 
 	setup_display();
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 63f2639bd3..9d9fbffbbd 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -39,6 +39,11 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index aeb66ad454..2e6262f0f4 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -32,14 +32,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
 
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED		100000
-
 /* MMC Configuration */
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
-- 
2.17.1

[U-Boot] [PATCH 17/17] imx6: wandboard: convert to DM_MMC

[Anatolij Gustschin]

Move SDHC init to SPL code since it is not required with
DM_MMC. Enable DM_MMC support.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 board/wandboard/spl.c       | 92 +++++++++++++++++++++++++++++++++++
 board/wandboard/wandboard.c | 97 -------------------------------------
 configs/wandboard_defconfig |  1 +
 3 files changed, 93 insertions(+), 97 deletions(-)

diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 9c3350019c..000cb109fc 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -422,4 +422,96 @@ void board_init_f(ulong dummy)
 	/* DDR initialization */
 	spl_dram_init();
 }
+
+#define USDHC1_CD_GPIO		IMX_GPIO_NR(1, 2)
+#define USDHC3_CD_GPIO		IMX_GPIO_NR(3, 9)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC1_BASE_ADDR},
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* Carrier MicroSD Card Detect */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* SOM MicroSD Card Detect */
+	IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+	u32 index = 0;
+
+	/*
+	 * Following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    SOM MicroSD
+	 * mmc1                    Carrier board MicroSD
+	 */
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			usdhc_cfg[0].max_bus_width = 4;
+			gpio_direction_input(USDHC3_CD_GPIO);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			usdhc_cfg[1].max_bus_width = 4;
+			gpio_direction_input(USDHC1_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+			       "(%d) then supported by the board (%d)\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 #endif
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index c0902abe38..69fbc8b690 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -22,8 +22,6 @@
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
-#include <fsl_esdhc.h>
-#include <mmc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <phy.h>
@@ -37,10 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
@@ -48,8 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
-#define USDHC1_CD_GPIO		IMX_GPIO_NR(1, 2)
-#define USDHC3_CD_GPIO		IMX_GPIO_NR(3, 9)
 #define ETH_PHY_RESET		IMX_GPIO_NR(3, 29)
 #define ETH_PHY_AR8035_POWER	IMX_GPIO_NR(7, 13)
 #define REV_DETECTION		IMX_GPIO_NR(2, 28)
@@ -68,28 +60,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	/* Carrier MicroSD Card Detect */
-	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	/* SOM MicroSD Card Detect */
-	IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
 static iomux_v3_cfg_t const enet_pads[] = {
 	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
@@ -145,73 +115,6 @@ static void setup_iomux_enet(void)
 	udelay(100);
 }
 
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
-	{USDHC3_BASE_ADDR},
-	{USDHC1_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC1_BASE_ADDR:
-		ret = !gpio_get_value(USDHC1_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		ret = !gpio_get_value(USDHC3_CD_GPIO);
-		break;
-	}
-
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int ret;
-	u32 index = 0;
-
-#if !CONFIG_IS_ENABLED(DM_MMC)
-	gpio_request(USDHC1_CD_GPIO, "USDHC1_CD");
-	gpio_request(USDHC3_CD_GPIO, "USDHC3_CD");
-#endif
-
-	/*
-	 * Following map is done:
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    SOM MicroSD
-	 * mmc1                    Carrier board MicroSD
-	 */
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-		switch (index) {
-		case 0:
-			SETUP_IOMUX_PADS(usdhc3_pads);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			usdhc_cfg[0].max_bus_width = 4;
-			gpio_direction_input(USDHC3_CD_GPIO);
-			break;
-		case 1:
-			SETUP_IOMUX_PADS(usdhc1_pads);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-			usdhc_cfg[1].max_bus_width = 4;
-			gpio_direction_input(USDHC1_CD_GPIO);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-			       "(%d) then supported by the board (%d)\n",
-			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
 	unsigned short val;
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 9d9fbffbbd..7f64ea65b1 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -44,6 +44,7 @@ CONFIG_SYS_I2C_MXC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
-- 
2.17.1

[U-Boot] [PATCH 00/17] Convert some imx6 boards to DM_VIDEO

[Anatolij Gustschin]

On Mon, 18 Mar 2019 23:29:30 +0100
Anatolij Gustschin agust at denx.de wrote:

> This series starts conversion of ipuv3 driver to DM_VIDEO.

These patches are based on 'next' branch of git://git.denx.de/u-boot-imx.git.

--
Anatolij

[U-Boot] [PATCH 00/17] Convert some imx6 boards to DM_VIDEO

[Fabio Estevam]

Hi Anatolij,

On Mon, Mar 18, 2019 at 7:30 PM Anatolij Gustschin <agust@denx.de> wrote:
>
> This series starts conversion of ipuv3 driver to DM_VIDEO.
> It has been tested on apalis_imx6 module with LVDS display
> attached and on wandboard with HDMI display.
>
> With applied "[PATCH 17/17] imx6: wandboard: convert to DM_MMC"
> building wandboard target doesn't work. To fix this please
> apply patches [1], [2] and enable CONFIG_AHCI and CONFIG_DM_SCSI
> in wandboard_defconfig.
>
> [1] http://patchwork.ozlabs.org/patch/1050141
> [2] http://patchwork.ozlabs.org/patch/1050143
>
> Anatolij Gustschin (17):
>   video: ipuv3: add DM_VIDEO support
>   video: move ipuv3 files to subdirectory
>   imx: move CONFIG_VIDEO_IPUV3 to defconfigs
>   imx6: dts: add 'u-boot,dm-pre-reloc' to soc and ipu nodes
>   apalis_imx6: convert to DM_VIDEO
>   imx6: icore: convert to DM_VIDEO
>   imx6: ge_bx50v3: convert to DM_VIDEO
>   colibri_imx6: convert to DM_VIDEO
>   mx6sabresd: convert to DM_VIDEO
>   mx6sabreauto: convert to DM_VIDEO
>   imx6: wandboard: add device tree

Thanks for converting wandboard to DM.

I haven't had a chance to test this series yet, but I am wondering if
the SPL size can still fit in the 64k of the internal RAM available on
mx6solo.

Do you know?

Thanks

[U-Boot] [PATCH 00/17] Convert some imx6 boards to DM_VIDEO

[Anatolij Gustschin]

Hi Fabio,

On Wed, 20 Mar 2019 10:25:02 -0300
Fabio Estevam festevam at gmail.com wrote:
...
> Thanks for converting wandboard to DM.
> 
> I haven't had a chance to test this series yet, but I am wondering if
> the SPL size can still fit in the 64k of the internal RAM available on
> mx6solo.
> 
> Do you know?

I've tested on wandboard with MX6Solo, the SPL size was 47 KiB.

Thanks,
Anatolij

[U-Boot] [PATCH 00/17] Convert some imx6 boards to DM_VIDEO

[Fabio Estevam]

Hi Anatolij,

On Wed, Mar 20, 2019 at 10:38 AM Anatolij Gustschin <agust@denx.de> wrote:

> I've tested on wandboard with MX6Solo, the SPL size was 47 KiB.

Excellent! That's great news, thanks :-)

[U-Boot] [PATCH 3/3] logos: Add the TechNexion's logo

[Fabio Estevam]

Hi Stefano,

On Mon, Feb 18, 2019 at 7:53 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Stefano,
>
> On Tue, Dec 11, 2018 at 4:41 PM Otavio Salvador <otavio@ossystems.com.br> wrote:
> >
> > From: Fabio Estevam <festevam@gmail.com>
> >
> > Add the TechNexion's logo from their internal U-Boot tree.
> >
> > Signed-off-by: Fabio Estevam <festevam@gmail.com>
> > Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> > ---
> >
> >  tools/logos/technexion.bmp | Bin 0 -> 22390 bytes
> >  1 file changed, 0 insertions(+), 0 deletions(-)
> >  create mode 100644 tools/logos/technexion.bmp
>
> I noticed this patch has not been applied.
>
> Maybe a patchwork bug?
>
> Could you please consider applying it?

Would you like me to resend this one?

[U-Boot] [U-Boot, v1, 26/26] board: colibri_imx6: check for and report ecc errors in fuses

[Marcel Ziswiler]

Hi Stefano

On Wed, 2019-03-13 at 09:38 +0000, sbabic at denx.de wrote:
> > From: Gerard Salvatella <gerard.salvatella@toradex.com>
> > The PMIC on the Colibri iMX6 may have ECC errors in fuses that will
> > prevent correct settings. Up to one bit error per fuse bank can be
> > reported and corrected by the ECC logic. Two bit errors can only be
> > reported.
> > Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
> > Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> Applied to u-boot-imx, -next, thanks !

Unfortunately, I can't find that one anywhere on u-boot-imx.git/next.

I will resend it as a separate patch for you to pick up, OK?

BTW: I will also send a V2 of the Colibri Vybrid stuff, plus the
Colibri iMX6ULL overhaul and the initial add of the Colibri iMX8QXP.

> Best regards,
> Stefano Babic

Cheers

Marcel

[U-Boot] [U-Boot, v1, 26/26] board: colibri_imx6: check for and report ecc errors in fuses

[Stefano Babic]

On 24/03/19 22:42, Marcel Ziswiler wrote:
> Hi Stefano
> 
> On Wed, 2019-03-13 at 09:38 +0000, sbabic at denx.de wrote:
>>> From: Gerard Salvatella <gerard.salvatella@toradex.com>
>>> The PMIC on the Colibri iMX6 may have ECC errors in fuses that will
>>> prevent correct settings. Up to one bit error per fuse bank can be
>>> reported and corrected by the ECC logic. Two bit errors can only be
>>> reported.
>>> Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
>>> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>>
>> Applied to u-boot-imx, -next, thanks !
> 
> Unfortunately, I can't find that one anywhere on u-boot-imx.git/next.
> 
> I will resend it as a separate patch for you to pick up, OK?

mmhhh...I have applied them, I see in my local -next, I am sure I pushed
before. Let me see why they do not appear on git.denx.de, you do not
need to repush, they are alreay applied.

> 
> BTW: I will also send a V2 of the Colibri Vybrid stuff, plus the
> Colibri iMX6ULL overhaul and the initial add of the Colibri iMX8QXP.

Ok, thanks for info. I set V1 as obsolete in patchwork.

Regards,
Stefano

> 
>> Best regards,
>> Stefano Babic
> 
> Cheers
> 
> Marcel
> 


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 00/22] colibri vybrid fixes, device tree enablement and driver model conversion

[Marcel Ziswiler]

This series addresses some shortcomings, enables/introduces device tree
support and converts all except video to using the driver model. This is
fully tested both running our latest downstream BSP as well as the
mainline Linux kernel.

This series is based on Lukasz' previous work on Vybrid [1] and is
available together with his and my previous series addressing Apalis
and Colibri iMX6 on our git server [2].

[1] https://patchwork.ozlabs.org/cover/1041597/
[2] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next

Changes in v2:
- Added various reviewed-bys.

Bhuvanchandra DV (1):
  colibri_vf: sync the board info message

Gerard Salvatella (1):
  colibri_vf: fix sdboot for vybrid modules

Marcel Ziswiler (12):
  Add missing space in comment
  vf610: ddrmc: add missing include
  imx: bootaux: add dependency on vf610
  configs: move CONFIG_USB_EHCI_VF to Kconfig
  configs: colibri_vf: remove obsolete mmc/sd card environment
  configs: colibri_vf: limit size of malloc() pool before relocation
  configs: move CONFIG_MXC_OCOTP to Kconfig
  ARM: dts: colibri_vf: update device trees
  configs: colibri_vf: disable obscure options
  colibri_vf: migrate pinctrl and regulators to dtb/dm
  colibri_vf: migrate fec, esdhc, nfc and usb to driver model
  config: colibri_vf: use macros from linux/sizes.h

Stefan Agner (8):
  colibri_vf: add distroboot support
  colibri_vf: set fdtfile for distroboot
  colibri_vf: enable user debug by default
  colibri_vf: disable undefined instruction events in user debug
  config: colibri_vf: enable mtd partitions via dt
  arm: vf610: add uart2 clock/pinmux support
  colibri_vf: adjust timing according to data sheet
  colibri_vf: use leveling evaluated by DDR validation tools

 arch/arm/dts/vf-colibri-u-boot.dtsi           |  23 ++
 arch/arm/dts/vf-colibri.dtsi                  | 198 ++++++++++++++-
 arch/arm/dts/vf500-colibri.dts                |   1 +
 arch/arm/dts/vf610-colibri.dts                |   1 +
 arch/arm/include/asm/arch-vf610/crm_regs.h    |   1 +
 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h |   2 +
 arch/arm/include/asm/arch-vf610/iomux-vf610.h |   6 +-
 arch/arm/mach-imx/Kconfig                     |   2 +-
 board/freescale/imx8qxp_mek/imx8qxp_mek.c     |   2 +-
 board/toradex/colibri_vf/MAINTAINERS          |   4 +-
 board/toradex/colibri_vf/colibri_vf.c         | 240 ++----------------
 configs/bk4r1_defconfig                       |   1 -
 configs/colibri_vf_defconfig                  |  22 +-
 configs/pcm052_defconfig                      |   1 -
 drivers/misc/Kconfig                          |   2 +
 drivers/usb/host/Kconfig                      |   7 +
 drivers/video/videomodes.c                    |   2 +-
 include/configs/advantech_dms-ba16.h          |   2 -
 include/configs/apalis_imx6.h                 |   5 -
 include/configs/colibri_imx6.h                |   5 -
 include/configs/colibri_vf.h                  | 109 ++++----
 include/configs/dh_imx6.h                     |   5 -
 include/configs/ge_bx50v3.h                   |   2 -
 include/configs/imx8mq_evk.h                  |   1 -
 include/configs/kp_imx6q_tpc.h                |   5 -
 include/configs/mx6_common.h                  |   3 -
 include/configs/mx7_common.h                  |   3 -
 include/configs/vf610twr.h                    |   4 -
 scripts/config_whitelist.txt                  |   1 -
 29 files changed, 344 insertions(+), 316 deletions(-)
 create mode 100644 arch/arm/dts/vf-colibri-u-boot.dtsi

-- 
2.20.1

[U-Boot] [PATCH v2 01/22] Add missing space in comment

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Spotted two missing spaces in comments.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2: None

 board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +-
 drivers/video/videomodes.c                | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
index a4c587a390..63cd605b6a 100644
--- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -112,7 +112,7 @@ void build_info(void)
 	sc_misc_build_info(-1, &sc_build, &sc_commit);
 	if (!sc_build) {
 		printf("SCFW does not support build info\n");
-		sc_commit = 0; /* Display 0 when the build info is not supported*/
+		sc_commit = 0; /* Display 0 when the build info is not supported */
 	}
 	printf("Build: SCFW %x\n", sc_commit);
 }
diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index 1cfeaa980f..d7614329ff 100644
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -397,7 +397,7 @@ int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
 	    EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) == 0 ||
 	    EDID_DETAILED_TIMING_HSYNC_OFFSET(*t) == 0 ||
 	    EDID_DETAILED_TIMING_VSYNC_OFFSET(*t) == 0 ||
-	    /* 3d formats are not supported*/
+	    /* 3d formats are not supported */
 	    EDID_DETAILED_TIMING_FLAG_STEREO(*t) != 0)
 		return -EINVAL;
 
-- 
2.20.1

[U-Boot] [PATCH v2 02/22] vf610: ddrmc: add missing include

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

The DDR memory controller include file for the Vybrid uses
iomux_v3_cfg_t without actually including iomux-vf610.h.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2: None

 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
index c7da2b8a5e..03e3cecb95 100644
--- a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
@@ -10,6 +10,8 @@
 #ifndef __ASM_ARCH_VF610_DDRMC_H
 #define __ASM_ARCH_VF610_DDRMC_H
 
+#include <asm/arch/iomux-vf610.h>
+
 struct ddr3_jedec_timings {
 	u8 tinit;
 	u32 trst_pwron;
-- 
2.20.1

[U-Boot] [PATCH v2 03/22] imx: bootaux: add dependency on vf610

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Allow using bootaux also on VF610 aka Vybrid.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2: None

 arch/arm/mach-imx/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 8631fbd481..ec09ef240f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -23,7 +23,7 @@ config IMX_RDC
 
 config IMX_BOOTAUX
 	bool "Support boot auxiliary core"
-	depends on ARCH_MX7 || ARCH_MX6
+	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610
 	help
 	  bootaux [addr] to boot auxiliary core.
 
-- 
2.20.1

[U-Boot] [PATCH v2 04/22] configs: move CONFIG_USB_EHCI_VF to Kconfig

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Move CONFIG_USB_EHCI_VF to drivers/usb/host/Kconfig and update the one
and only user thereof being colibri_vf.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2: None

 drivers/usb/host/Kconfig     | 7 +++++++
 include/configs/colibri_vf.h | 1 -
 scripts/config_whitelist.txt | 1 -
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index ba1e6bfa43..0fbc115801 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -154,6 +154,13 @@ config USB_EHCI_OMAP
 	  Enables support for the on-chip EHCI controller on OMAP3 and later
 	  SoCs.
 
+config USB_EHCI_VF
+	bool "Support for Vybrid on-chip EHCI USB controller"
+	depends on ARCH_VF610
+	default y
+	help
+	  Enables support for the on-chip EHCI controller on Vybrid SoCs.
+
 if USB_EHCI_MX7
 
 config MXC_USB_OTG_HACTIVE
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 31ff8a00a6..2fe7f217fa 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -159,7 +159,6 @@
 #endif
 
 /* USB Host Support */
-#define CONFIG_USB_EHCI_VF
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index db00376d92..7c14b24bc1 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4522,7 +4522,6 @@ CONFIG_USB_EHCI_MXS
 CONFIG_USB_EHCI_SPEAR
 CONFIG_USB_EHCI_TXFIFO_THRESH
 CONFIG_USB_EHCI_VCT
-CONFIG_USB_EHCI_VF
 CONFIG_USB_ETH_QMULT
 CONFIG_USB_ETH_SUBSET
 CONFIG_USB_EXT2_BOOT
-- 
2.20.1

[U-Boot] [PATCH v2 05/22] configs: colibri_vf: remove obsolete mmc/sd card environment

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Remove obsolete MMC/SD card environment configuration dating back to
un-fused samples times.

While at it also remove meanwhile spurious "USB Storage" comment.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2: None

 include/configs/colibri_vf.h | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 2fe7f217fa..7b974d9e97 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -145,13 +145,6 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /* Environment organization */
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
-#define CONFIG_ENV_SIZE			(8 * 1024)
-#endif
-
 #ifdef CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			(64 * 2048)
 #define CONFIG_ENV_RANGE		(4 * 64 * 2048)
@@ -165,6 +158,4 @@
 /* USB DFU */
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024)
 
-/* USB Storage */
-
 #endif /* __CONFIG_H */
-- 
2.20.1

[U-Boot] [PATCH v2 06/22] configs: colibri_vf: limit size of malloc() pool before relocation

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Limit the size of the malloc() pool before relocation
(SYS_MALLOC_F_LEN).

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2: None

 configs/colibri_vf_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 4192501257..8188582ed9 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_VF610=y
 CONFIG_SYS_TEXT_BASE=0x3f401000
+CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_TARGET_COLIBRI_VF=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_NR_DRAM_BANKS=1
-- 
2.20.1

[U-Boot] [PATCH v2 07/22] configs: move CONFIG_MXC_OCOTP to Kconfig

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

While commit 3e020f03e94f ("driver: misc: add MXC_OCOTP Kconfig entry")
introduced a Kconfig entry it did not actually migrate all
configurations to using it.

As CONFIG_MXC_OCOTP was in mx{6/7}_common.h enable it by default on
those architectures. Additionally, also enable it on ARCH_IMX8M and
ARCH_VF610 where all current members enabled it through their legacy
configuration header files.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>

---

Changes in v2: None

 configs/bk4r1_defconfig              | 1 -
 configs/pcm052_defconfig             | 1 -
 drivers/misc/Kconfig                 | 2 ++
 include/configs/advantech_dms-ba16.h | 2 --
 include/configs/apalis_imx6.h        | 5 -----
 include/configs/colibri_imx6.h       | 5 -----
 include/configs/colibri_vf.h         | 4 ----
 include/configs/dh_imx6.h            | 5 -----
 include/configs/ge_bx50v3.h          | 2 --
 include/configs/imx8mq_evk.h         | 1 -
 include/configs/kp_imx6q_tpc.h       | 5 -----
 include/configs/mx6_common.h         | 3 ---
 include/configs/mx7_common.h         | 3 ---
 include/configs/vf610twr.h           | 4 ----
 14 files changed, 2 insertions(+), 41 deletions(-)

diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index e3852f4856..439207fd39 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -49,7 +49,6 @@ CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_MISC=y
-CONFIG_MXC_OCOTP=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_SYS_I2C_EEPROM_BUS=2
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index 906abbfd69..fd093b35c2 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -36,7 +36,6 @@ CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_MISC=y
-CONFIG_MXC_OCOTP=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_SYS_I2C_EEPROM_BUS=2
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index d6e677fba8..0e645f58be 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -128,6 +128,8 @@ config JZ4780_EFUSE
 
 config MXC_OCOTP
 	bool "Enable MXC OCOTP Driver"
+	depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_VF610
+	default y
 	help
 	  If you say Y here, you will get support for the One Time
 	  Programmable memory pages that are stored on the some
diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
index 0c9de6125d..a22c6a7d45 100644
--- a/include/configs/advantech_dms-ba16.h
+++ b/include/configs/advantech_dms-ba16.h
@@ -34,8 +34,6 @@
 
 #define CONFIG_MXC_UART
 
-#define CONFIG_MXC_OCOTP
-
 /* SATA Configs */
 #define CONFIG_SYS_SATA_MAX_DEVICE	1
 #define CONFIG_DWC_AHSATA_PORT_ID	0
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index c8aa1bdddf..95dd6f9362 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -41,11 +41,6 @@
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_MXC_I2C3_SPEED	400000
 
-/* OCOTP Configs */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* MMC Configs */
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index a6a823ee1f..d2f8a58e80 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -39,11 +39,6 @@
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_MXC_I2C3_SPEED	400000
 
-/* OCOTP Configs */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* MMC Configs */
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 7b974d9e97..e7b786e48b 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -17,10 +17,6 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 #define CONFIG_SPLASH_SCREEN_ALIGN
 #define CONFIG_VIDEO_LOGO
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 9231bd853f..4dc795c3f4 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -48,11 +48,6 @@
 #define CONFIG_FEC_MXC_PHYADDR		0
 #define CONFIG_ARP_TIMEOUT		200UL
 
-/* Fuses */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* I2C Configs */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index a5d7cb1be0..134145c473 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -35,8 +35,6 @@
 
 #define CONFIG_MXC_UART
 
-#define CONFIG_MXC_OCOTP
-
 /* SATA Configs */
 #ifdef CONFIG_CMD_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	1
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index a9e38a70e6..6094d1bf18 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -230,7 +230,6 @@
 
 #define CONFIG_MXC_GPIO
 
-#define CONFIG_MXC_OCOTP
 #define CONFIG_CMD_FUSE
 
 /* I2C Configs */
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
index b6b27ee1d5..d2ebf92953 100644
--- a/include/configs/kp_imx6q_tpc.h
+++ b/include/configs/kp_imx6q_tpc.h
@@ -31,11 +31,6 @@
 #define CONFIG_FEC_MXC_PHYADDR		0
 #define CONFIG_ARP_TIMEOUT		200UL
 
-/* Fuses */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* I2C Configs */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index cdc8833778..6b20c6db58 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -57,9 +57,6 @@
 /* MMC */
 #define CONFIG_FSL_USDHC
 
-/* Fuses */
-#define CONFIG_MXC_OCOTP
-
 /* Secure boot (HAB) support */
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_CSF_SIZE			0x2000
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index a895c936aa..cc7e87269e 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -42,9 +42,6 @@
 /* MMC */
 #define CONFIG_FSL_USDHC
 
-/* Fuses */
-#define CONFIG_MXC_OCOTP
-
 #define CONFIG_ARMV7_SECURE_BASE	0x00900000
 
 #define CONFIG_ARMV7_PSCI_1_0
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 686a383739..ba85bc91e7 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -19,10 +19,6 @@
 /* Enable passing of ATAGs */
 #define CONFIG_CMDLINE_TAG
 
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 
-- 
2.20.1

[U-Boot] [PATCH v2 08/22] ARM: dts: colibri_vf: update device trees

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Update device tree in preparation of further driver model migration:
Ethernet FEC, ESDHC aka MMC/SD card, I2C, NFC aka NAND flash controller,
USBH_PEN GPIO regulator.

Add iomux resp. pinctrl entries to be removed from proprietary platform
data: DSPI, ESDHC, FEC, I2C, NFC, UART, USBH_PEN GPIO.

Introduce a U-Boot specific device tree with some required
u-boot,dm-pre-reloc properties: soc, aips0, pinctrl_ddr and uart0 incl.
pinctrl.

While at it also update the MAINTAINERS file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 arch/arm/dts/vf-colibri-u-boot.dtsi  |  23 ++++
 arch/arm/dts/vf-colibri.dtsi         | 198 ++++++++++++++++++++++++++-
 arch/arm/dts/vf500-colibri.dts       |   1 +
 arch/arm/dts/vf610-colibri.dts       |   1 +
 board/toradex/colibri_vf/MAINTAINERS |   4 +-
 5 files changed, 224 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/vf-colibri-u-boot.dtsi

diff --git a/arch/arm/dts/vf-colibri-u-boot.dtsi b/arch/arm/dts/vf-colibri-u-boot.dtsi
new file mode 100644
index 0000000000..db86739805
--- /dev/null
+++ b/arch/arm/dts/vf-colibri-u-boot.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&aips0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_ddr {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi
index 923dc2451c..5ce17076e9 100644
--- a/arch/arm/dts/vf-colibri.dtsi
+++ b/arch/arm/dts/vf-colibri.dtsi
@@ -1,18 +1,37 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2014 Toradex AG
+ * Copyright 2014-2019 Toradex AG
  */
+
+/dts-v1/;
 #include "vf.dtsi"
+#include "vf610-pinfunc.h"
 
 / {
 	chosen {
 		stdout-path = &uart0;
 	};
+
+	aliases {
+		usb0 = &ehci0; /* required for ums */
+	};
+
+	reg_usbh_vbus: regulator-usbh-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh1_reg>;
+		regulator-name = "VCC_USB[1-4]";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN */
+	};
 };
 
 &dspi1 {
-	status = "okay";
 	bus-num = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dspi1>;
+	status = "okay";
 
 	spi_cmd: sspi at 0 {
 		reg = <0>;
@@ -29,8 +48,183 @@
 &ehci1 {
 	dr_mode = "host";
 	status = "okay";
+	vbus-supply = <&reg_usbh_vbus>;
+};
+
+&esdhc1 {
+	bus-width = <4>;
+	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esdhc1>;
+	status = "okay";
+};
+
+&fec1 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0>;
+	status = "okay";
+
+	/* M41T0M6 real time clock on carrier board */
+	rtc: m41t0m6 at 68 {
+		compatible = "st,m41t0";
+		reg = <0x68>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ddr>;
+
+	pinctrl_ddr: ddrgrp {
+		fsl,pins = <
+			VF610_PAD_DDR_A15__DDR_A_15             0x180
+			VF610_PAD_DDR_A14__DDR_A_14             0x180
+			VF610_PAD_DDR_A13__DDR_A_13             0x180
+			VF610_PAD_DDR_A12__DDR_A_12             0x180
+			VF610_PAD_DDR_A11__DDR_A_11             0x180
+			VF610_PAD_DDR_A10__DDR_A_10             0x180
+			VF610_PAD_DDR_A9__DDR_A_9               0x180
+			VF610_PAD_DDR_A8__DDR_A_8               0x180
+			VF610_PAD_DDR_A7__DDR_A_7               0x180
+			VF610_PAD_DDR_A6__DDR_A_6               0x180
+			VF610_PAD_DDR_A5__DDR_A_5               0x180
+			VF610_PAD_DDR_A4__DDR_A_4               0x180
+			VF610_PAD_DDR_A3__DDR_A_3               0x180
+			VF610_PAD_DDR_A2__DDR_A_2               0x180
+			VF610_PAD_DDR_A1__DDR_A_1               0x180
+			VF610_PAD_DDR_A0__DDR_A_0               0x180
+			VF610_PAD_DDR_BA2__DDR_BA_2             0x180
+			VF610_PAD_DDR_BA1__DDR_BA_1             0x180
+			VF610_PAD_DDR_BA0__DDR_BA_0             0x180
+			VF610_PAD_DDR_CAS__DDR_CAS_B            0x180
+			VF610_PAD_DDR_CKE__DDR_CKE_0            0x180
+			VF610_PAD_DDR_CLK__DDR_CLK_0            0x180
+			VF610_PAD_DDR_CS__DDR_CS_B_0            0x180
+			VF610_PAD_DDR_D15__DDR_D_15             0x10180
+			VF610_PAD_DDR_D14__DDR_D_14             0x10180
+			VF610_PAD_DDR_D13__DDR_D_13             0x10180
+			VF610_PAD_DDR_D12__DDR_D_12             0x10180
+			VF610_PAD_DDR_D11__DDR_D_11             0x10180
+			VF610_PAD_DDR_D10__DDR_D_10             0x10180
+			VF610_PAD_DDR_D9__DDR_D_9               0x10180
+			VF610_PAD_DDR_D8__DDR_D_8               0x10180
+			VF610_PAD_DDR_D7__DDR_D_7               0x10180
+			VF610_PAD_DDR_D6__DDR_D_6               0x10180
+			VF610_PAD_DDR_D5__DDR_D_5               0x10180
+			VF610_PAD_DDR_D4__DDR_D_4               0x10180
+			VF610_PAD_DDR_D3__DDR_D_3               0x10180
+			VF610_PAD_DDR_D2__DDR_D_2               0x10180
+			VF610_PAD_DDR_D1__DDR_D_1               0x10180
+			VF610_PAD_DDR_D0__DDR_D_0               0x10180
+			VF610_PAD_DDR_DQM1__DDR_DQM_1           0x10180
+			VF610_PAD_DDR_DQM0__DDR_DQM_0           0x10180
+			VF610_PAD_DDR_DQS1__DDR_DQS_1           0x10180
+			VF610_PAD_DDR_DQS0__DDR_DQS_0           0x10180
+			VF610_PAD_DDR_RAS__DDR_RAS_B            0x180
+			VF610_PAD_DDR_WE__DDR_WE_B              0x180
+			VF610_PAD_DDR_ODT1__DDR_ODT_0           0x180
+			VF610_PAD_DDR_ODT0__DDR_ODT_1           0x180
+			VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1    0x180
+			VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2    0x180
+			VF610_PAD_DDR_RESETB                    0x180
+		>;
+	};
+
+	pinctrl_dspi1: dspi1grp {
+		fsl,pins = <
+			VF610_PAD_PTD5__DSPI1_CS0		0x33e2
+			VF610_PAD_PTD6__DSPI1_SIN		0x33e1
+			VF610_PAD_PTD7__DSPI1_SOUT		0x33e2
+			VF610_PAD_PTD8__DSPI1_SCK		0x33e2
+		>;
+	};
+
+	pinctrl_esdhc1: esdhc1grp {
+		fsl,pins = <
+			VF610_PAD_PTA24__ESDHC1_CLK		0x31ef
+			VF610_PAD_PTA25__ESDHC1_CMD		0x31ef
+			VF610_PAD_PTA26__ESDHC1_DAT0		0x31ef
+			VF610_PAD_PTA27__ESDHC1_DAT1		0x31ef
+			VF610_PAD_PTA28__ESDHC1_DATA2		0x31ef
+			VF610_PAD_PTA29__ESDHC1_DAT3		0x31ef
+			VF610_PAD_PTB20__GPIO_42		0x219d
+		>;
+	};
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			VF610_PAD_PTA6__RMII_CLKOUT		0x30df
+			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30df
+			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30df
+			VF610_PAD_PTC11__ENET_RMII1_CRS		0x30df
+			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30df
+			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30df
+			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30df
+			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30df
+			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30df
+			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30df
+		>;
+	};
+
+	pinctrl_i2c0: i2c0grp {
+		fsl,pins = <
+			VF610_PAD_PTB14__I2C0_SCL		0x37ff
+			VF610_PAD_PTB15__I2C0_SDA		0x37ff
+		>;
+	};
+
+	pinctrl_nfc: nfcgrp {
+		fsl,pins = <
+			VF610_PAD_PTD23__NF_IO7			0x28df
+			VF610_PAD_PTD22__NF_IO6			0x28df
+			VF610_PAD_PTD21__NF_IO5			0x28df
+			VF610_PAD_PTD20__NF_IO4			0x28df
+			VF610_PAD_PTD19__NF_IO3			0x28df
+			VF610_PAD_PTD18__NF_IO2			0x28df
+			VF610_PAD_PTD17__NF_IO1			0x28df
+			VF610_PAD_PTD16__NF_IO0			0x28df
+			VF610_PAD_PTB24__NF_WE_B		0x28c2
+			VF610_PAD_PTB25__NF_CE0_B		0x28c2
+			VF610_PAD_PTB27__NF_RE_B		0x28c2
+			VF610_PAD_PTC26__NF_RB_B		0x283d
+			VF610_PAD_PTC27__NF_ALE			0x28c2
+			VF610_PAD_PTC28__NF_CLE			0x28c2
+		>;
+	};
+
+	pinctrl_uart0: uart0grp {
+		fsl,pins = <
+			VF610_PAD_PTB10__UART0_TX		0x11af
+			VF610_PAD_PTB11__UART0_RX		0x11af
+			VF610_PAD_PTB12__UART0_RTS		0x11af
+			VF610_PAD_PTB13__UART0_CTS		0x11af
+		>;
+	};
+
+	pinctrl_usbh1_reg: gpio_usb_vbus {
+		fsl,pins = <
+			VF610_PAD_PTD4__GPIO_83			0x22ed
+		>;
+	};
+};
+
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_nfc>;
+	status = "okay";
 };
 
 &uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart0>;
 	status = "okay";
 };
diff --git a/arch/arm/dts/vf500-colibri.dts b/arch/arm/dts/vf500-colibri.dts
index 3f33d970e0..c83a16fdcb 100644
--- a/arch/arm/dts/vf500-colibri.dts
+++ b/arch/arm/dts/vf500-colibri.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "vf-colibri.dtsi"
+#include "vf-colibri-u-boot.dtsi"
 
 / {
 	model = "Toradex Colibri VF50";
diff --git a/arch/arm/dts/vf610-colibri.dts b/arch/arm/dts/vf610-colibri.dts
index 0a6b937fee..7275fec279 100644
--- a/arch/arm/dts/vf610-colibri.dts
+++ b/arch/arm/dts/vf610-colibri.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "vf-colibri.dtsi"
+#include "vf-colibri-u-boot.dtsi"
 
 / {
 	model = "Toradex Colibri VF61";
diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS
index a1217a47bd..3ee2b33152 100644
--- a/board/toradex/colibri_vf/MAINTAINERS
+++ b/board/toradex/colibri_vf/MAINTAINERS
@@ -1,10 +1,12 @@
 Colibri VFxx
 M:	Stefan Agner <stefan.agner@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+W:      https://www.toradex.com/community
 S:	Maintained
 F:	board/toradex/colibri_vf/
 F:	include/configs/colibri_vf.h
 F:	configs/colibri_vf_defconfig
-F:	configs/colibri_vf_dtb_defconfig
 F:	arch/arm/dts/vf-colibri.dtsi
+F:	arch/arm/dts/vf-colibri-u-boot.dtsi
 F:	arch/arm/dts/vf500-colibri.dts
 F:	arch/arm/dts/vf610-colibri.dts
-- 
2.20.1

[U-Boot] [PATCH v2 09/22] configs: colibri_vf: disable obscure options

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Disable more obscure options to save another 26 KB in preparation of
the upcoming driver model migration.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 configs/colibri_vf_defconfig | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 8188582ed9..706d7ca634 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -17,11 +17,17 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
+# CONFIG_SYS_LONGHELP is not set
 CONFIG_SYS_PROMPT="Colibri VFxx # "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
 CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADB is not set
@@ -46,10 +52,10 @@ CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
-CONFIG_DFU_MMC=y
 CONFIG_DFU_NAND=y
 CONFIG_DM_GPIO=y
 CONFIG_VYBRID_GPIO=y
+# CONFIG_MMC_HW_PARTITIONING is not set
 CONFIG_FSL_ESDHC=y
 CONFIG_NAND_VF610_NFC=y
 CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
@@ -57,6 +63,8 @@ CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_MII=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_TPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_USB=y
-- 
2.20.1

[U-Boot] [PATCH v2 10/22] colibri_vf: migrate pinctrl and regulators to dtb/dm

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate pinctrl and regulators to device tree resp. driver model: DDR,
DSPI, ENET, ESDHC, I2C, NFC and UART.

Enable CMD_DM, PINCTRL and DM_REGULATOR.

While at it also update copyright period and sort include files.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/colibri_vf/colibri_vf.c | 139 ++------------------------
 configs/colibri_vf_defconfig          |   5 +
 2 files changed, 16 insertions(+), 128 deletions(-)

diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index 79f702f2bf..8e0dea2dc2 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -1,43 +1,36 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2015 Toradex, Inc.
+ * Copyright 2015-2019 Toradex, Inc.
  *
  * Based on vf610twr.c:
  * Copyright 2013 Freescale Semiconductor, Inc.
  */
 
 #include <common.h>
-#include <asm/io.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/ddrmc-vf610.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux-vf610.h>
-#include <asm/arch/ddrmc-vf610.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <mmc.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
 #include <fdt_support.h>
 #include <fsl_esdhc.h>
 #include <fsl_dcu_fb.h>
+#include <g_dnl.h>
+#include <i2c.h>
 #include <jffs2/load_kernel.h>
 #include <miiphy.h>
+#include <mmc.h>
 #include <mtd_node.h>
 #include <netdev.h>
-#include <i2c.h>
-#include <g_dnl.h>
-#include <asm/gpio.h>
 #include <usb.h>
+
 #include "../common/tdx-common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
-
-#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
-			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
-
-#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
-			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
-
 #define USB_PEN_GPIO		83
 #define USB_CDET_GPIO		102
 #define PTC0_GPIO_45		45
@@ -89,11 +82,6 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
 	{ 0, -1 }
 };
 
-static const iomux_v3_cfg_t usb_pads[] = {
-	VF610_PAD_PTD4__GPIO_83,
-	VF610_PAD_PTC29__GPIO_102,
-};
-
 int dram_init(void)
 {
 	static const struct ddr3_jedec_timings timings = {
@@ -147,92 +135,12 @@ int dram_init(void)
 		.wldqsen           = 25,
 	};
 
-	ddrmc_setup_iomux(NULL, 0);
-
 	ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 
 	return 0;
 }
 
-static void setup_iomux_uart(void)
-{
-	static const iomux_v3_cfg_t uart_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-static void setup_iomux_enet(void)
-{
-	static const iomux_v3_cfg_t enet0_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
-}
-
-static void setup_iomux_i2c(void)
-{
-	static const iomux_v3_cfg_t i2c0_pads[] = {
-		VF610_PAD_PTB14__I2C0_SCL,
-		VF610_PAD_PTB15__I2C0_SDA,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
-}
-
-#ifdef CONFIG_NAND_VF610_NFC
-static void setup_iomux_nfc(void)
-{
-	static const iomux_v3_cfg_t nfc_pads[] = {
-		VF610_PAD_PTD23__NF_IO7,
-		VF610_PAD_PTD22__NF_IO6,
-		VF610_PAD_PTD21__NF_IO5,
-		VF610_PAD_PTD20__NF_IO4,
-		VF610_PAD_PTD19__NF_IO3,
-		VF610_PAD_PTD18__NF_IO2,
-		VF610_PAD_PTD17__NF_IO1,
-		VF610_PAD_PTD16__NF_IO0,
-		VF610_PAD_PTB24__NF_WE_B,
-		VF610_PAD_PTB25__NF_CE0_B,
-		VF610_PAD_PTB27__NF_RE_B,
-		VF610_PAD_PTC26__NF_RB_B,
-		VF610_PAD_PTC27__NF_ALE,
-		VF610_PAD_PTC28__NF_CLE
-	};
-
-	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
-}
-#endif
-
-#ifdef CONFIG_FSL_DSPI
-static void setup_iomux_dspi(void)
-{
-	static const iomux_v3_cfg_t dspi1_pads[] = {
-		VF610_PAD_PTD5__DSPI1_CS0,
-		VF610_PAD_PTD6__DSPI1_SIN,
-		VF610_PAD_PTD7__DSPI1_SOUT,
-		VF610_PAD_PTD8__DSPI1_SCK,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads));
-}
-#endif
-
 #ifdef CONFIG_VYBRID_GPIO
 static void setup_iomux_gpio(void)
 {
@@ -344,20 +252,8 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_init(bd_t *bis)
 {
-	static const iomux_v3_cfg_t esdhc1_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
-	};
-
 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 
-	imx_iomux_v3_setup_multiple_pads(
-		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
-
 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 }
 #endif
@@ -496,21 +392,10 @@ int board_early_init_f(void)
 	clock_init();
 	mscm_init();
 
-	setup_iomux_uart();
-	setup_iomux_enet();
-	setup_iomux_i2c();
-#ifdef CONFIG_NAND_VF610_NFC
-	setup_iomux_nfc();
-#endif
-
 #ifdef CONFIG_VYBRID_GPIO
 	setup_iomux_gpio();
 #endif
 
-#ifdef CONFIG_FSL_DSPI
-	setup_iomux_dspi();
-#endif
-
 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 	setup_tcon();
 	setup_iomux_fsl_dcu();
@@ -594,8 +479,6 @@ int ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_USB_EHCI_VF
 int board_ehci_hcd_init(int port)
 {
-	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
-
 	switch (port) {
 	case 0:
 		/* USBC does not have PEN, also configured as USB client only */
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 706d7ca634..9a91cb4b82 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_DFU=y
+CONFIG_CMD_DM=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
@@ -63,6 +64,10 @@ CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_VYBRID=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 # CONFIG_TPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
-- 
2.20.1

[U-Boot] [PATCH v2 11/22] colibri_vf: migrate fec, esdhc, nfc and usb to driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate FEC, ESDHC, NFC and USB to driver model.

While at it also do no longer enable optional I2C clock in board file as
the generic clock code now handles this. Note for space reason and as
it is not required just for booting we do not enable I2C in U-Boot by
default.

While at it also update copyright period.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/colibri_vf/colibri_vf.c | 82 +--------------------------
 configs/colibri_vf_defconfig          |  5 ++
 include/configs/colibri_vf.h          | 13 +----
 3 files changed, 7 insertions(+), 93 deletions(-)

diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index 8e0dea2dc2..c4d05532fe 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -16,23 +16,16 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <fdt_support.h>
-#include <fsl_esdhc.h>
 #include <fsl_dcu_fb.h>
 #include <g_dnl.h>
-#include <i2c.h>
 #include <jffs2/load_kernel.h>
-#include <miiphy.h>
-#include <mmc.h>
 #include <mtd_node.h>
-#include <netdev.h>
 #include <usb.h>
 
 #include "../common/tdx-common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define USB_PEN_GPIO		83
-#define USB_CDET_GPIO		102
 #define PTC0_GPIO_45		45
 
 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
@@ -239,25 +232,6 @@ static void setup_tcon(void)
 }
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
-	{ESDHC1_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	/* eSDHC1 is always present */
-	return 1;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-#endif
-
 static inline int is_colibri_vf61(void)
 {
 	struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
@@ -290,7 +264,7 @@ static void clock_init(void)
 			CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
 			CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
-			CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
+			CCM_CCGR4_GPC_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
 			CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
@@ -379,14 +353,6 @@ static void mscm_init(void)
 		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 }
 
-int board_phy_config(struct phy_device *phydev)
-{
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
 int board_early_init_f(void)
 {
 	clock_init();
@@ -433,13 +399,8 @@ int board_init(void)
 	 * so we must use the external oscillator in order
 	 * to maintain correct time in the hwclock
 	 */
-
 	setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
 
-#ifdef CONFIG_USB_EHCI_VF
-	gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
-#endif
-
 	return 0;
 }
 
@@ -476,47 +437,6 @@ int ft_board_setup(void *blob, bd_t *bd)
 }
 #endif
 
-#ifdef CONFIG_USB_EHCI_VF
-int board_ehci_hcd_init(int port)
-{
-	switch (port) {
-	case 0:
-		/* USBC does not have PEN, also configured as USB client only */
-		break;
-	case 1:
-		gpio_request(USB_PEN_GPIO, "usb-pen-gpio");
-		gpio_direction_output(USB_PEN_GPIO, 0);
-		break;
-	}
-	return 0;
-}
-
-int board_usb_phy_mode(int port)
-{
-	switch (port) {
-	case 0:
-		/*
-		 * Port 0 is used only in client mode on Colibri Vybrid modules
-		 * Check for state of USB client gpio pin and accordingly return
-		 * USB_INIT_DEVICE or USB_INIT_HOST.
-		 */
-		if (gpio_get_value(USB_CDET_GPIO))
-			return USB_INIT_DEVICE;
-		else
-			return USB_INIT_HOST;
-	case 1:
-		/* Port 1 is used only in host mode on Colibri Vybrid modules */
-		return USB_INIT_HOST;
-	default:
-		/*
-		 * There are only two USB controllers on Vybrid. Ideally we will
-		 * not reach here. However return USB_INIT_HOST if we do.
-		 */
-		return USB_INIT_HOST;
-	}
-}
-#endif
-
 /*
  * Backlight off before OS handover
  */
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 9a91cb4b82..344fe77234 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -56,13 +56,18 @@ CONFIG_DM=y
 CONFIG_DFU_NAND=y
 CONFIG_DM_GPIO=y
 CONFIG_VYBRID_GPIO=y
+CONFIG_DM_MMC=y
 # CONFIG_MMC_HW_PARTITIONING is not set
 CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
 CONFIG_NAND_VF610_NFC=y
+CONFIG_NAND_VF610_NFC_DT=y
 CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_VYBRID=y
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index e7b786e48b..1acc6e5056 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2015-2016 Toradex, Inc.
+ * Copyright 2015-2019 Toradex, Inc.
  *
  * Configuration settings for the Toradex VF50/VF61 modules.
  *
@@ -36,17 +36,6 @@
 /* NAND support */
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
-
-/* Dynamic MTD partition support */
-
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
-#define CONFIG_SYS_FSL_ESDHC_NUM	1
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE			ENET1_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE		RMII
-#define CONFIG_FEC_MXC_PHYADDR          0
 
 #define CONFIG_IPADDR		192.168.10.2
 #define CONFIG_NETMASK		255.255.255.0
-- 
2.20.1

[U-Boot] [PATCH v2 12/22] config: colibri_vf: use macros from linux/sizes.h

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Use SZ_X{MK} macros from linux/sizes.h for include/configs/colibri_vf.h.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2: None

 include/configs/colibri_vf.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 1acc6e5056..9effa56539 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -12,6 +12,7 @@
 #define __CONFIG_H
 
 #include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
 
 #define CONFIG_SYS_FSL_CLK
 
@@ -28,7 +29,7 @@
 #endif
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * SZ_1M)
 
 /* Allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -118,7 +119,7 @@
 
 /* Physical memory map */
 #define PHYS_SDRAM			(0x80000000)
-#define PHYS_SDRAM_SIZE			(256 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE			(256 * SZ_1M)
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
@@ -141,6 +142,6 @@
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 
 /* USB DFU */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024)
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
 
 #endif /* __CONFIG_H */
-- 
2.20.1

[U-Boot] [PATCH v2 13/22] colibri_vf: add distroboot support

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Add support for distro boot. This is especially helpful for external
devices. There is a global boot command which scans a predefined
list of boot targets:
  run distro_bootcmd

As well as direct boot commands such as:
  run bootcmd_mmc0
  run bootcmd_usb
  run bootcmd_dhcp
  ...

Refer to doc/README.distro fo details.

While at it also re-order boot command macros as well as the
CONFIG_EXTRA_ENV_SETTINGS.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 include/configs/colibri_vf.h | 75 ++++++++++++++++++++++--------------
 1 file changed, 46 insertions(+), 29 deletions(-)

diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 9effa56539..83a33ff786 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -48,13 +48,15 @@
 /* We boot from the gfxRAM area of the OCRAM. */
 #define CONFIG_BOARD_SIZE_LIMIT		520192
 
-#define SD_BOOTCMD \
-	"sdargs=root=/dev/mmcblk0p2 rw rootwait\0"	\
-	"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
-	"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
-	"load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
-	"load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
-	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"pxefile_addr_r=0x87100000\0" \
+	"ramdisk_addr_r=0x82100000\0" \
+	"scriptaddr=0x87000000\0"
 
 #define NFS_BOOTCMD \
 	"nfsargs=ip=:::::eth0: root=/dev/nfs\0"	\
@@ -65,7 +67,15 @@
 	"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
 	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
 
-#define UBI_BOOTCMD	\
+#define SD_BOOTCMD \
+	"sdargs=root=/dev/mmcblk0p2 rw rootwait\0"	\
+	"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
+	"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
+	"load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
+	"load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
+	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define UBI_BOOTCMD \
 	"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
 	"ubi.fm_autoconvert=1\0" \
 	"ubiboot=run setup; " \
@@ -76,36 +86,43 @@
 	"ubi read ${fdt_addr_r} dtb && " \
 	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
 
-#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
+#define CONFIG_BOOTCOMMAND "run ubiboot; run distro_bootcmd;"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
 
 #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4"
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"kernel_addr_r=0x82000000\0" \
-	"fdt_addr_r=0x84000000\0" \
-	"kernel_file=zImage\0" \
-	"fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
+	BOOTENV \
+	MEM_LAYOUT_ENV_SETTINGS \
+	NFS_BOOTCMD \
+	SD_BOOTCMD \
+	UBI_BOOTCMD \
+	"console=ttyLP0\0" \
+	"defargs=\0" \
+	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
 	"fdt_board=eval-v3\0" \
+	"fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
 	"fdt_fixup=;\0" \
-	"defargs=\0" \
-	"console=ttyLP0\0" \
-	"setup=setenv setupargs " \
-	"console=tty1 console=${console}" \
-	",${baudrate}n8 ${memargs}\0" \
+	"kernel_file=zImage\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
 	"setsdupdate=mmc rescan && set interface mmc && " \
-	"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
-	"source ${loadaddr}\0" \
-	"setusbupdate=usb start && set interface usb && " \
-	"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
-	"source ${loadaddr}\0" \
+		"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	"setup=setenv setupargs console=tty1 console=${console}" \
+		",${baudrate}n8 ${memargs}\0" \
 	"setupdate=run setsdupdate || run setusbupdate\0" \
-	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
-	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
-	"video-mode=dcufb:640x480-16 at 60,monitor=lcd\0" \
+	"setusbupdate=usb start && set interface usb && " \
+		"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
 	"splashpos=m,m\0" \
-	SD_BOOTCMD \
-	NFS_BOOTCMD \
-	UBI_BOOTCMD
+	"video-mode=dcufb:640x480-16 at 60,monitor=lcd\0"
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-- 
2.20.1

[U-Boot] [PATCH v2 14/22] colibri_vf: set fdtfile for distroboot

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Set fdtfile to represent the current board. This allows distribution
to load the correct device tree, which in the module case often
deviates from the common fallback ${soc}-${board}${boardver}.dtb...

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 include/configs/colibri_vf.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 83a33ff786..0bbeeb902e 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -86,7 +86,8 @@
 	"ubi read ${fdt_addr_r} dtb && " \
 	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
 
-#define CONFIG_BOOTCOMMAND "run ubiboot; run distro_bootcmd;"
+#define CONFIG_BOOTCOMMAND "run ubiboot; " \
+	"setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;"
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
@@ -108,7 +109,6 @@
 	"defargs=\0" \
 	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
 	"fdt_board=eval-v3\0" \
-	"fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
 	"fdt_fixup=;\0" \
 	"kernel_file=zImage\0" \
 	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
-- 
2.20.1

[U-Boot] [PATCH v2 15/22] colibri_vf: sync the board info message

[Marcel Ziswiler]

From: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>

Use similar info message as on other modules.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2: None

 board/toradex/colibri_vf/colibri_vf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index c4d05532fe..9c5bf4951b 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -407,9 +407,9 @@ int board_init(void)
 int checkboard(void)
 {
 	if (is_colibri_vf61())
-		puts("Board: Colibri VF61\n");
+		puts("Model: Toradex Colibri VF61\n");
 	else
-		puts("Board: Colibri VF50\n");
+		puts("Model: Toradex Colibri VF50\n");
 
 	return 0;
 }
-- 
2.20.1

[U-Boot] [PATCH v2 16/22] colibri_vf: enable user debug by default

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Let the kernel print some debug messages when a user program
crashes due to an exception.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2: None

 include/configs/colibri_vf.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 0bbeeb902e..030281bb67 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -106,7 +106,7 @@
 	SD_BOOTCMD \
 	UBI_BOOTCMD \
 	"console=ttyLP0\0" \
-	"defargs=\0" \
+	"defargs=user_debug=31\0" \
 	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
 	"fdt_board=eval-v3\0" \
 	"fdt_fixup=;\0" \
-- 
2.20.1

[U-Boot] [PATCH v2 17/22] colibri_vf: disable undefined instruction events in user debug

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

It turns out that OpenSSL calls undefined instructions to detect
ARM capabilities at runtime (via SIGILL handler). This leads to
stack traces e.g. when logging in using SSH:
  [  877.464442] sshd (613): undefined instruction: pc=76ee2da8
  ...

Disable undefined instruction events since it is used as an
autodetecion mechanism.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2: None

 include/configs/colibri_vf.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 030281bb67..b2f27c1977 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -106,7 +106,7 @@
 	SD_BOOTCMD \
 	UBI_BOOTCMD \
 	"console=ttyLP0\0" \
-	"defargs=user_debug=31\0" \
+	"defargs=user_debug=30\0" \
 	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
 	"fdt_board=eval-v3\0" \
 	"fdt_fixup=;\0" \
-- 
2.20.1

[U-Boot] [PATCH v2 18/22] config: colibri_vf: enable mtd partitions via dt

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Use device tree to set MTD partitions of the NAND chip.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2: None

 configs/colibri_vf_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 344fe77234..8f6cceca7f 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -91,4 +91,5 @@ CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_VIDEO=y
 CONFIG_SYS_CONSOLE_FG_COL=0x00
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
 # CONFIG_EFI_UNICODE_CAPITALIZATION is not set
-- 
2.20.1

[U-Boot] [PATCH v2 19/22] arm: vf610: add uart2 clock/pinmux support

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Add support for Vybrid's UART2 (Colibri UART_B).

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 arch/arm/include/asm/arch-vf610/crm_regs.h    | 1 +
 arch/arm/include/asm/arch-vf610/iomux-vf610.h | 6 +++++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 9fce49ddc6..0c9ed52933 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -200,6 +200,7 @@ struct anadig_reg {
 #define CCM_REG_CTRL_MASK			0xffffffff
 #define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR0_UART2_CTRL_MASK		(0x3 << 18)
 #define CCM_CCGR0_DSPI0_CTRL_MASK		(0x3 << 24)
 #define CCM_CCGR0_DSPI1_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index 01bc2998b8..8ba03e5a17 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -132,10 +132,14 @@ enum {
 	VF610_PAD_PTD24__GPIO_70		= IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD23__NF_IO7			= IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
 	VF610_PAD_PTD0__QSPI0_A_QSCK		= IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD0__UART2_TX		= IOMUX_PAD(0x013c, 0x013c, 2, 0x38c, 2, VF610_UART_PAD_CTRL),
 	VF610_PAD_PTD1__QSPI0_A_CS0		= IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD1__UART2_RX		= IOMUX_PAD(0x0140, 0x0140, 2, 0x388, 2, VF610_UART_PAD_CTRL),
 	VF610_PAD_PTD2__QSPI0_A_DATA3		= IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD2__GPIO_81			= IOMUX_PAD(0x0144, 0x0144, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD3__QSPI0_A_DATA2		= IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD4__GPIO_83         = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD3__GPIO_82			= IOMUX_PAD(0x0148, 0x0148, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD4__GPIO_83			= IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD4__QSPI0_A_DATA1		= IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTD5__QSPI0_A_DATA0		= IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTD7__QSPI0_B_QSCK		= IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-- 
2.20.1

[U-Boot] [PATCH v2 20/22] colibri_vf: adjust timing according to data sheet

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Using the DDR Validation tool in Processor Expert uncovered two
timing inconsistencies. Since those timings are related to the
suspend mode they do not affect or change regular memory behaviour.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/colibri_vf/colibri_vf.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index 9c5bf4951b..3e39912f91 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -101,15 +101,21 @@ int dram_init(void)
 		.tras_lockout      = 0,
 		.tdal              = 12,
 		.bstlen            = 3,
-		.tdll              = 512,
+		.tdll              = 512, /* not applicable since freq. scaling
+					   * is not used
+					   */
 		.trp_ab            = 6,
 		.tref              = 3120,
 		.trfc              = 64,
 		.tref_int          = 0,
 		.tpdex             = 3,
 		.txpdll            = 10,
-		.txsnr             = 48,
-		.txsr              = 468,
+		.txsnr             = 68,  /* changed to conform to JEDEC
+					   * specifications
+					   */
+		.txsr              = 506, /* changed to conform to JEDEC
+					   * specifications
+					   */
 		.cksrx             = 5,
 		.cksre             = 5,
 		.freq_chg_en       = 0,
-- 
2.20.1

[U-Boot] [PATCH v2 21/22] colibri_vf: use leveling evaluated by DDR validation tools

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

The DDR validation tool (which is part of Processor Expert) allows
to evaluate leveling parameters for CR105/CR106/CR110. Several
runs have been made with Colibri VF50 and VF61 and it seems to
evaluate very similar values. Use this values by default.

Note: The newly evaluated parameters seem to require CTLUPD_AREF
to be enabled!

Note 2: The tool also evaluated 6 as a new value for PHY02/18
GATE_CFG (Coarse adjust of gate open time). However, this seems
not to work in practise.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2: None

 board/toradex/colibri_vf/colibri_vf.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index 3e39912f91..9d63fbf3bd 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -29,6 +29,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PTC0_GPIO_45		45
 
 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
+	{ DDRMC_CR79_CTLUPD_AREF(1), 79 },
+	/* sets manual values for read lvl. (gate) delay of data slice 0/1 */
+	{ DDRMC_CR105_RDLVL_DL_0(28), 105 },
+	{ DDRMC_CR106_RDLVL_GTDL_0(24), 106 },
+	{ DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 },
+	{ DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 },
+
 	/* AXI */
 	{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
 	{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
-- 
2.20.1

[U-Boot] [PATCH v2 22/22] colibri_vf: fix sdboot for vybrid modules

[Marcel Ziswiler]

From: Gerard Salvatella <gerard.salvatella@toradex.com>

Currently, Vybrid's sdboot variable tries to load the kernel from /boot
of the root partition (typically second partition when using the sdcard
image). However, since we moved to flash the kernel in a separate UBI
volume, we no longer deploy the kernel/device tree to /boot, hence
sdboot does not work in its current state.

Load the kernel and device tree from the first (typically FAT) partition
as customary on all Toradex modules.

While at it also change from rw to ro as e.g. systemd will re-mount the
root file system rw anyway after checking it.

Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added various reviewed-bys.

 include/configs/colibri_vf.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index b2f27c1977..0d57e303a1 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -68,11 +68,11 @@
 	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
 
 #define SD_BOOTCMD \
-	"sdargs=root=/dev/mmcblk0p2 rw rootwait\0"	\
+	"sdargs=root=/dev/mmcblk0p2 ro rootwait\0"	\
 	"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
 	"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
-	"load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
-	"load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
+	"load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \
+	"load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
 	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
 
 #define UBI_BOOTCMD \
-- 
2.20.1

[U-Boot] [PATCH v2 11/22] colibri_vf: migrate fec, esdhc, nfc and usb to driver model

[Igor Opaniuk]

Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

On Mon, Mar 25, 2019 at 6:30 PM Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Migrate FEC, ESDHC, NFC and USB to driver model.
>
> While at it also do no longer enable optional I2C clock in board file as
> the generic clock code now handles this. Note for space reason and as
> it is not required just for booting we do not enable I2C in U-Boot by
> default.
>
> While at it also update copyright period.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v2: None
>
>  board/toradex/colibri_vf/colibri_vf.c | 82 +--------------------------
>  configs/colibri_vf_defconfig          |  5 ++
>  include/configs/colibri_vf.h          | 13 +----
>  3 files changed, 7 insertions(+), 93 deletions(-)
>
> diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
> index 8e0dea2dc2..c4d05532fe 100644
> --- a/board/toradex/colibri_vf/colibri_vf.c
> +++ b/board/toradex/colibri_vf/colibri_vf.c
> @@ -16,23 +16,16 @@
>  #include <asm/gpio.h>
>  #include <asm/io.h>
>  #include <fdt_support.h>
> -#include <fsl_esdhc.h>
>  #include <fsl_dcu_fb.h>
>  #include <g_dnl.h>
> -#include <i2c.h>
>  #include <jffs2/load_kernel.h>
> -#include <miiphy.h>
> -#include <mmc.h>
>  #include <mtd_node.h>
> -#include <netdev.h>
>  #include <usb.h>
>
>  #include "../common/tdx-common.h"
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> -#define USB_PEN_GPIO           83
> -#define USB_CDET_GPIO          102
>  #define PTC0_GPIO_45           45
>
>  static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
> @@ -239,25 +232,6 @@ static void setup_tcon(void)
>  }
>  #endif
>
> -#ifdef CONFIG_FSL_ESDHC
> -struct fsl_esdhc_cfg esdhc_cfg[1] = {
> -       {ESDHC1_BASE_ADDR},
> -};
> -
> -int board_mmc_getcd(struct mmc *mmc)
> -{
> -       /* eSDHC1 is always present */
> -       return 1;
> -}
> -
> -int board_mmc_init(bd_t *bis)
> -{
> -       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> -
> -       return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
> -}
> -#endif
> -
>  static inline int is_colibri_vf61(void)
>  {
>         struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
> @@ -290,7 +264,7 @@ static void clock_init(void)
>                         CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
>         clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
>                         CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
> -                       CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
> +                       CCM_CCGR4_GPC_CTRL_MASK);
>         clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
>                         CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
>         clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
> @@ -379,14 +353,6 @@ static void mscm_init(void)
>                 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
>  }
>
> -int board_phy_config(struct phy_device *phydev)
> -{
> -       if (phydev->drv->config)
> -               phydev->drv->config(phydev);
> -
> -       return 0;
> -}
> -
>  int board_early_init_f(void)
>  {
>         clock_init();
> @@ -433,13 +399,8 @@ int board_init(void)
>          * so we must use the external oscillator in order
>          * to maintain correct time in the hwclock
>          */
> -
>         setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
>
> -#ifdef CONFIG_USB_EHCI_VF
> -       gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
> -#endif
> -
>         return 0;
>  }
>
> @@ -476,47 +437,6 @@ int ft_board_setup(void *blob, bd_t *bd)
>  }
>  #endif
>
> -#ifdef CONFIG_USB_EHCI_VF
> -int board_ehci_hcd_init(int port)
> -{
> -       switch (port) {
> -       case 0:
> -               /* USBC does not have PEN, also configured as USB client only */
> -               break;
> -       case 1:
> -               gpio_request(USB_PEN_GPIO, "usb-pen-gpio");
> -               gpio_direction_output(USB_PEN_GPIO, 0);
> -               break;
> -       }
> -       return 0;
> -}
> -
> -int board_usb_phy_mode(int port)
> -{
> -       switch (port) {
> -       case 0:
> -               /*
> -                * Port 0 is used only in client mode on Colibri Vybrid modules
> -                * Check for state of USB client gpio pin and accordingly return
> -                * USB_INIT_DEVICE or USB_INIT_HOST.
> -                */
> -               if (gpio_get_value(USB_CDET_GPIO))
> -                       return USB_INIT_DEVICE;
> -               else
> -                       return USB_INIT_HOST;
> -       case 1:
> -               /* Port 1 is used only in host mode on Colibri Vybrid modules */
> -               return USB_INIT_HOST;
> -       default:
> -               /*
> -                * There are only two USB controllers on Vybrid. Ideally we will
> -                * not reach here. However return USB_INIT_HOST if we do.
> -                */
> -               return USB_INIT_HOST;
> -       }
> -}
> -#endif
> -
>  /*
>   * Backlight off before OS handover
>   */
> diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
> index 9a91cb4b82..344fe77234 100644
> --- a/configs/colibri_vf_defconfig
> +++ b/configs/colibri_vf_defconfig
> @@ -56,13 +56,18 @@ CONFIG_DM=y
>  CONFIG_DFU_NAND=y
>  CONFIG_DM_GPIO=y
>  CONFIG_VYBRID_GPIO=y
> +CONFIG_DM_MMC=y
>  # CONFIG_MMC_HW_PARTITIONING is not set
>  CONFIG_FSL_ESDHC=y
> +CONFIG_MTD=y
>  CONFIG_NAND_VF610_NFC=y
> +CONFIG_NAND_VF610_NFC_DT=y
>  CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
>  CONFIG_MTD_UBI_FASTMAP=y
>  CONFIG_PHYLIB=y
>  CONFIG_PHY_MICREL=y
> +CONFIG_DM_ETH=y
> +CONFIG_FEC_MXC=y
>  CONFIG_MII=y
>  CONFIG_PINCTRL=y
>  CONFIG_PINCTRL_VYBRID=y
> diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
> index e7b786e48b..1acc6e5056 100644
> --- a/include/configs/colibri_vf.h
> +++ b/include/configs/colibri_vf.h
> @@ -1,6 +1,6 @@
>  /* SPDX-License-Identifier: GPL-2.0+ */
>  /*
> - * Copyright 2015-2016 Toradex, Inc.
> + * Copyright 2015-2019 Toradex, Inc.
>   *
>   * Configuration settings for the Toradex VF50/VF61 modules.
>   *
> @@ -36,17 +36,6 @@
>  /* NAND support */
>  #define CONFIG_SYS_NAND_ONFI_DETECTION
>  #define CONFIG_SYS_MAX_NAND_DEVICE     1
> -#define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
> -
> -/* Dynamic MTD partition support */
> -
> -#define CONFIG_SYS_FSL_ESDHC_ADDR      0
> -#define CONFIG_SYS_FSL_ESDHC_NUM       1
> -
> -#define CONFIG_FEC_MXC
> -#define IMX_FEC_BASE                   ENET1_BASE_ADDR
> -#define CONFIG_FEC_XCV_TYPE            RMII
> -#define CONFIG_FEC_MXC_PHYADDR          0
>
>  #define CONFIG_IPADDR          192.168.10.2
>  #define CONFIG_NETMASK         255.255.255.0
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 13/22] colibri_vf: add distroboot support

[Igor Opaniuk]

Hi Marcel,

Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Please check some minor comments below (could be addressed in a
separate patchset):

On Mon, Mar 25, 2019 at 6:35 PM Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Stefan Agner <stefan.agner@toradex.com>
>
> Add support for distro boot. This is especially helpful for external
> devices. There is a global boot command which scans a predefined
> list of boot targets:
>   run distro_bootcmd
>
> As well as direct boot commands such as:
>   run bootcmd_mmc0
>   run bootcmd_usb
>   run bootcmd_dhcp
>   ...
>
> Refer to doc/README.distro fo details.
>
> While at it also re-order boot command macros as well as the
> CONFIG_EXTRA_ENV_SETTINGS.
>
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v2: None
>
>  include/configs/colibri_vf.h | 75 ++++++++++++++++++++++--------------
>  1 file changed, 46 insertions(+), 29 deletions(-)
>
> diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
> index 9effa56539..83a33ff786 100644
> --- a/include/configs/colibri_vf.h
> +++ b/include/configs/colibri_vf.h
> @@ -48,13 +48,15 @@
>  /* We boot from the gfxRAM area of the OCRAM. */
>  #define CONFIG_BOARD_SIZE_LIMIT                520192
>
> -#define SD_BOOTCMD \
> -       "sdargs=root=/dev/mmcblk0p2 rw rootwait\0"      \
minor: "mmcblk0p2" (it's used in multiple places) can also be put into
the separate variable in case if we decide to change the partition
layout in the future.

> -       "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
> -       "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
> -       "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
> -       "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
minor: I think we should unify (can be addressed in another patchset)
the way how dtb names are concatenated (and for example use this
scheme for all Toradex SoMs; particularly for Colibri iMX6DL the
full-name is still hardcoded "imx6dl-colibri-eval-v3.dtb")

> -       "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
> +#define MEM_LAYOUT_ENV_SETTINGS \
> +       "bootm_size=0x10000000\0" \
> +       "fdt_addr_r=0x82000000\0" \
> +       "fdt_high=0xffffffff\0" \
> +       "initrd_high=0xffffffff\0" \
> +       "kernel_addr_r=0x81000000\0" \
> +       "pxefile_addr_r=0x87100000\0" \
> +       "ramdisk_addr_r=0x82100000\0" \
> +       "scriptaddr=0x87000000\0"
>
>  #define NFS_BOOTCMD \
>         "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
> @@ -65,7 +67,15 @@
>         "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
>         "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
>
> -#define UBI_BOOTCMD    \
> +#define SD_BOOTCMD \
> +       "sdargs=root=/dev/mmcblk0p2 rw rootwait\0"      \
> +       "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
> +       "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
> +       "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
> +       "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
> +       "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
> +
> +#define UBI_BOOTCMD \
>         "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
>         "ubi.fm_autoconvert=1\0" \
>         "ubiboot=run setup; " \
> @@ -76,36 +86,43 @@
>         "ubi read ${fdt_addr_r} dtb && " \
>         "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
>
> -#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
> +#define CONFIG_BOOTCOMMAND "run ubiboot; run distro_bootcmd;"
> +
> +#define BOOT_TARGET_DEVICES(func) \
> +       func(MMC, mmc, 0) \
> +       func(USB, usb, 0) \
> +       func(DHCP, dhcp, na)
> +#include <config_distro_bootcmd.h>
> +#undef BOOTENV_RUN_NET_USB_START
> +#define BOOTENV_RUN_NET_USB_START ""
>
>  #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4"
>
>  #define CONFIG_EXTRA_ENV_SETTINGS \
> -       "kernel_addr_r=0x82000000\0" \
> -       "fdt_addr_r=0x84000000\0" \
> -       "kernel_file=zImage\0" \
> -       "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
> +       BOOTENV \
> +       MEM_LAYOUT_ENV_SETTINGS \
> +       NFS_BOOTCMD \
> +       SD_BOOTCMD \
> +       UBI_BOOTCMD \
> +       "console=ttyLP0\0" \
> +       "defargs=\0" \
> +       "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
>         "fdt_board=eval-v3\0" \
> +       "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
>         "fdt_fixup=;\0" \
> -       "defargs=\0" \
> -       "console=ttyLP0\0" \
> -       "setup=setenv setupargs " \
> -       "console=tty1 console=${console}" \
> -       ",${baudrate}n8 ${memargs}\0" \
> +       "kernel_file=zImage\0" \
> +       "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
>         "setsdupdate=mmc rescan && set interface mmc && " \
> -       "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
> -       "source ${loadaddr}\0" \
> -       "setusbupdate=usb start && set interface usb && " \
> -       "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
> -       "source ${loadaddr}\0" \
> +               "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
> +               "source ${loadaddr}\0" \
> +       "setup=setenv setupargs console=tty1 console=${console}" \
what is the point providing console configuration two times?

> +               ",${baudrate}n8 ${memargs}\0" \
>         "setupdate=run setsdupdate || run setusbupdate\0" \
> -       "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
> -       "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
> -       "video-mode=dcufb:640x480-16 at 60,monitor=lcd\0" \
> +       "setusbupdate=usb start && set interface usb && " \
> +               "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
> +               "source ${loadaddr}\0" \
>         "splashpos=m,m\0" \
> -       SD_BOOTCMD \
> -       NFS_BOOTCMD \
> -       UBI_BOOTCMD
> +       "video-mode=dcufb:640x480-16 at 60,monitor=lcd\0"
>
>  /* Miscellaneous configurable options */
>  #define CONFIG_SYS_CBSIZE              1024    /* Console I/O Buffer Size */
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 14/22] colibri_vf: set fdtfile for distroboot

[Igor Opaniuk]

Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

On Mon, Mar 25, 2019 at 6:32 PM Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Stefan Agner <stefan.agner@toradex.com>
>
> Set fdtfile to represent the current board. This allows distribution
> to load the correct device tree, which in the module case often
> deviates from the common fallback ${soc}-${board}${boardver}.dtb...
>
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v2: None
>
>  include/configs/colibri_vf.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
> index 83a33ff786..0bbeeb902e 100644
> --- a/include/configs/colibri_vf.h
> +++ b/include/configs/colibri_vf.h
> @@ -86,7 +86,8 @@
>         "ubi read ${fdt_addr_r} dtb && " \
>         "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
>
> -#define CONFIG_BOOTCOMMAND "run ubiboot; run distro_bootcmd;"
> +#define CONFIG_BOOTCOMMAND "run ubiboot; " \
> +       "setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;"
>
>  #define BOOT_TARGET_DEVICES(func) \
>         func(MMC, mmc, 0) \
> @@ -108,7 +109,6 @@
>         "defargs=\0" \
>         "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
>         "fdt_board=eval-v3\0" \
> -       "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
>         "fdt_fixup=;\0" \
>         "kernel_file=zImage\0" \
>         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 10/22] colibri_vf: migrate pinctrl and regulators to dtb/dm

[Igor Opaniuk]

Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

On Mon, Mar 25, 2019 at 6:30 PM Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Migrate pinctrl and regulators to device tree resp. driver model: DDR,
> DSPI, ENET, ESDHC, I2C, NFC and UART.
>
> Enable CMD_DM, PINCTRL and DM_REGULATOR.
>
> While at it also update copyright period and sort include files.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v2: None
>
>  board/toradex/colibri_vf/colibri_vf.c | 139 ++------------------------
>  configs/colibri_vf_defconfig          |   5 +
>  2 files changed, 16 insertions(+), 128 deletions(-)
>
> diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
> index 79f702f2bf..8e0dea2dc2 100644
> --- a/board/toradex/colibri_vf/colibri_vf.c
> +++ b/board/toradex/colibri_vf/colibri_vf.c
> @@ -1,43 +1,36 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
> - * Copyright 2015 Toradex, Inc.
> + * Copyright 2015-2019 Toradex, Inc.
>   *
>   * Based on vf610twr.c:
>   * Copyright 2013 Freescale Semiconductor, Inc.
>   */
>
>  #include <common.h>
> -#include <asm/io.h>
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/ddrmc-vf610.h>
>  #include <asm/arch/imx-regs.h>
>  #include <asm/arch/iomux-vf610.h>
> -#include <asm/arch/ddrmc-vf610.h>
> -#include <asm/arch/crm_regs.h>
> -#include <asm/arch/clock.h>
> -#include <mmc.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
>  #include <fdt_support.h>
>  #include <fsl_esdhc.h>
>  #include <fsl_dcu_fb.h>
> +#include <g_dnl.h>
> +#include <i2c.h>
>  #include <jffs2/load_kernel.h>
>  #include <miiphy.h>
> +#include <mmc.h>
>  #include <mtd_node.h>
>  #include <netdev.h>
> -#include <i2c.h>
> -#include <g_dnl.h>
> -#include <asm/gpio.h>
>  #include <usb.h>
> +
>  #include "../common/tdx-common.h"
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> -#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> -                       PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
> -
> -#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
> -                       PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
> -
> -#define ENET_PAD_CTRL  (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
> -                       PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
> -
>  #define USB_PEN_GPIO           83
>  #define USB_CDET_GPIO          102
>  #define PTC0_GPIO_45           45
> @@ -89,11 +82,6 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
>         { 0, -1 }
>  };
>
> -static const iomux_v3_cfg_t usb_pads[] = {
> -       VF610_PAD_PTD4__GPIO_83,
> -       VF610_PAD_PTC29__GPIO_102,
> -};
> -
>  int dram_init(void)
>  {
>         static const struct ddr3_jedec_timings timings = {
> @@ -147,92 +135,12 @@ int dram_init(void)
>                 .wldqsen           = 25,
>         };
>
> -       ddrmc_setup_iomux(NULL, 0);
> -
>         ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
>         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
>
>         return 0;
>  }
>
> -static void setup_iomux_uart(void)
> -{
> -       static const iomux_v3_cfg_t uart_pads[] = {
> -               NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),
> -       };
> -
> -       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> -}
> -
> -static void setup_iomux_enet(void)
> -{
> -       static const iomux_v3_cfg_t enet0_pads[] = {
> -               NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
> -       };
> -
> -       imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
> -}
> -
> -static void setup_iomux_i2c(void)
> -{
> -       static const iomux_v3_cfg_t i2c0_pads[] = {
> -               VF610_PAD_PTB14__I2C0_SCL,
> -               VF610_PAD_PTB15__I2C0_SDA,
> -       };
> -
> -       imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
> -}
> -
> -#ifdef CONFIG_NAND_VF610_NFC
> -static void setup_iomux_nfc(void)
> -{
> -       static const iomux_v3_cfg_t nfc_pads[] = {
> -               VF610_PAD_PTD23__NF_IO7,
> -               VF610_PAD_PTD22__NF_IO6,
> -               VF610_PAD_PTD21__NF_IO5,
> -               VF610_PAD_PTD20__NF_IO4,
> -               VF610_PAD_PTD19__NF_IO3,
> -               VF610_PAD_PTD18__NF_IO2,
> -               VF610_PAD_PTD17__NF_IO1,
> -               VF610_PAD_PTD16__NF_IO0,
> -               VF610_PAD_PTB24__NF_WE_B,
> -               VF610_PAD_PTB25__NF_CE0_B,
> -               VF610_PAD_PTB27__NF_RE_B,
> -               VF610_PAD_PTC26__NF_RB_B,
> -               VF610_PAD_PTC27__NF_ALE,
> -               VF610_PAD_PTC28__NF_CLE
> -       };
> -
> -       imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
> -}
> -#endif
> -
> -#ifdef CONFIG_FSL_DSPI
> -static void setup_iomux_dspi(void)
> -{
> -       static const iomux_v3_cfg_t dspi1_pads[] = {
> -               VF610_PAD_PTD5__DSPI1_CS0,
> -               VF610_PAD_PTD6__DSPI1_SIN,
> -               VF610_PAD_PTD7__DSPI1_SOUT,
> -               VF610_PAD_PTD8__DSPI1_SCK,
> -       };
> -
> -       imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads));
> -}
> -#endif
> -
>  #ifdef CONFIG_VYBRID_GPIO
>  static void setup_iomux_gpio(void)
>  {
> @@ -344,20 +252,8 @@ int board_mmc_getcd(struct mmc *mmc)
>
>  int board_mmc_init(bd_t *bis)
>  {
> -       static const iomux_v3_cfg_t esdhc1_pads[] = {
> -               NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
> -               NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
> -       };
> -
>         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
>
> -       imx_iomux_v3_setup_multiple_pads(
> -               esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
> -
>         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
>  }
>  #endif
> @@ -496,21 +392,10 @@ int board_early_init_f(void)
>         clock_init();
>         mscm_init();
>
> -       setup_iomux_uart();
> -       setup_iomux_enet();
> -       setup_iomux_i2c();
> -#ifdef CONFIG_NAND_VF610_NFC
> -       setup_iomux_nfc();
> -#endif
> -
>  #ifdef CONFIG_VYBRID_GPIO
>         setup_iomux_gpio();
>  #endif
>
> -#ifdef CONFIG_FSL_DSPI
> -       setup_iomux_dspi();
> -#endif
> -
>  #ifdef CONFIG_VIDEO_FSL_DCU_FB
>         setup_tcon();
>         setup_iomux_fsl_dcu();
> @@ -594,8 +479,6 @@ int ft_board_setup(void *blob, bd_t *bd)
>  #ifdef CONFIG_USB_EHCI_VF
>  int board_ehci_hcd_init(int port)
>  {
> -       imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
> -
>         switch (port) {
>         case 0:
>                 /* USBC does not have PEN, also configured as USB client only */
> diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
> index 706d7ca634..9a91cb4b82 100644
> --- a/configs/colibri_vf_defconfig
> +++ b/configs/colibri_vf_defconfig
> @@ -27,6 +27,7 @@ CONFIG_CMD_BOOTZ=y
>  CONFIG_CMD_ASKENV=y
>  CONFIG_CMD_MEMTEST=y
>  CONFIG_CMD_DFU=y
> +CONFIG_CMD_DM=y
>  # CONFIG_CMD_FLASH is not set
>  CONFIG_CMD_FUSE=y
>  CONFIG_CMD_GPIO=y
> @@ -63,6 +64,10 @@ CONFIG_MTD_UBI_FASTMAP=y
>  CONFIG_PHYLIB=y
>  CONFIG_PHY_MICREL=y
>  CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_VYBRID=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
>  # CONFIG_SPL_SERIAL_PRESENT is not set
>  # CONFIG_TPL_SERIAL_PRESENT is not set
>  CONFIG_DM_SERIAL=y
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 13/22] colibri_vf: add distroboot support

[Marcel Ziswiler]

Hi Igor

On Thu, 2019-03-28 at 15:01 +0000, Igor Opaniuk wrote:
> Hi Marcel,
> 
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> 
> Please check some minor comments below (could be addressed in a
> separate patchset):
> 
> On Mon, Mar 25, 2019 at 6:35 PM Marcel Ziswiler <marcel@ziswiler.com>
> wrote:
> > From: Stefan Agner <stefan.agner@toradex.com>
> > 
> > Add support for distro boot. This is especially helpful for
> > external
> > devices. There is a global boot command which scans a predefined
> > list of boot targets:
> >   run distro_bootcmd
> > 
> > As well as direct boot commands such as:
> >   run bootcmd_mmc0
> >   run bootcmd_usb
> >   run bootcmd_dhcp
> >   ...
> > 
> > Refer to doc/README.distro fo details.
> > 
> > While at it also re-order boot command macros as well as the
> > CONFIG_EXTRA_ENV_SETTINGS.
> > 
> > Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> > Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
> > Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > 
> > ---
> > 
> > Changes in v2: None
> > 
> >  include/configs/colibri_vf.h | 75 ++++++++++++++++++++++--------
> > ------
> >  1 file changed, 46 insertions(+), 29 deletions(-)
> > 
> > diff --git a/include/configs/colibri_vf.h
> > b/include/configs/colibri_vf.h
> > index 9effa56539..83a33ff786 100644
> > --- a/include/configs/colibri_vf.h
> > +++ b/include/configs/colibri_vf.h
> > @@ -48,13 +48,15 @@
> >  /* We boot from the gfxRAM area of the OCRAM. */
> >  #define CONFIG_BOARD_SIZE_LIMIT                520192
> > 
> > -#define SD_BOOTCMD \
> > -       "sdargs=root=/dev/mmcblk0p2 rw rootwait\0"      \
> minor: "mmcblk0p2" (it's used in multiple places) can also be put
> into
> the separate variable in case if we decide to change the partition
> layout in the future.

With BSP 3.0 we anyway plan to transition to proper distroboot.

> > -       "sdboot=run setup; setenv bootargs ${defargs} ${sdargs}
> > ${mtdparts} " \
> > -       "${setupargs} ${vidargs}; echo Booting from MMC/SD card...;
> > " \
> > -       "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
> > -       "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-
> > ${fdt_board}.dtb && " \
> minor: I think we should unify (can be addressed in another patchset)
> the way how dtb names are concatenated (and for example use this
> scheme for all Toradex SoMs; particularly for Colibri iMX6DL the
> full-name is still hardcoded "imx6dl-colibri-eval-v3.dtb")

Yeah, that is another legacy in need of cleaning up.

> > -       "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0"
> > \
> > +#define MEM_LAYOUT_ENV_SETTINGS \
> > +       "bootm_size=0x10000000\0" \
> > +       "fdt_addr_r=0x82000000\0" \
> > +       "fdt_high=0xffffffff\0" \
> > +       "initrd_high=0xffffffff\0" \
> > +       "kernel_addr_r=0x81000000\0" \
> > +       "pxefile_addr_r=0x87100000\0" \
> > +       "ramdisk_addr_r=0x82100000\0" \
> > +       "scriptaddr=0x87000000\0"
> > 
> >  #define NFS_BOOTCMD \
> >         "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
> > @@ -65,7 +67,15 @@
> >         "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
> >         "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0"
> > \
> > 
> > -#define UBI_BOOTCMD    \
> > +#define SD_BOOTCMD \
> > +       "sdargs=root=/dev/mmcblk0p2 rw rootwait\0"      \
> > +       "sdboot=run setup; setenv bootargs ${defargs} ${sdargs}
> > ${mtdparts} " \
> > +       "${setupargs} ${vidargs}; echo Booting from MMC/SD card...;
> > " \
> > +       "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
> > +       "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-
> > ${fdt_board}.dtb && " \
> > +       "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0"
> > \
> > +
> > +#define UBI_BOOTCMD \
> >         "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
> >         "ubi.fm_autoconvert=1\0" \
> >         "ubiboot=run setup; " \
> > @@ -76,36 +86,43 @@
> >         "ubi read ${fdt_addr_r} dtb && " \
> >         "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0"
> > \
> > 
> > -#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
> > +#define CONFIG_BOOTCOMMAND "run ubiboot; run distro_bootcmd;"
> > +
> > +#define BOOT_TARGET_DEVICES(func) \
> > +       func(MMC, mmc, 0) \
> > +       func(USB, usb, 0) \
> > +       func(DHCP, dhcp, na)
> > +#include <config_distro_bootcmd.h>
> > +#undef BOOTENV_RUN_NET_USB_START
> > +#define BOOTENV_RUN_NET_USB_START ""
> > 
> >  #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi
> > part 0,4"
> > 
> >  #define CONFIG_EXTRA_ENV_SETTINGS \
> > -       "kernel_addr_r=0x82000000\0" \
> > -       "fdt_addr_r=0x84000000\0" \
> > -       "kernel_file=zImage\0" \
> > -       "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
> > +       BOOTENV \
> > +       MEM_LAYOUT_ENV_SETTINGS \
> > +       NFS_BOOTCMD \
> > +       SD_BOOTCMD \
> > +       UBI_BOOTCMD \
> > +       "console=ttyLP0\0" \
> > +       "defargs=\0" \
> > +       "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
> >         "fdt_board=eval-v3\0" \
> > +       "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
> >         "fdt_fixup=;\0" \
> > -       "defargs=\0" \
> > -       "console=ttyLP0\0" \
> > -       "setup=setenv setupargs " \
> > -       "console=tty1 console=${console}" \
> > -       ",${baudrate}n8 ${memargs}\0" \
> > +       "kernel_file=zImage\0" \
> > +       "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
> >         "setsdupdate=mmc rescan && set interface mmc && " \
> > -       "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
> > -       "source ${loadaddr}\0" \
> > -       "setusbupdate=usb start && set interface usb && " \
> > -       "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
> > -       "source ${loadaddr}\0" \
> > +               "fatload ${interface} 0:1 ${loadaddr} flash_blk.img
> > && " \
> > +               "source ${loadaddr}\0" \
> > +       "setup=setenv setupargs console=tty1 console=${console}" \
> what is the point providing console configuration two times?

That fist one is the frame buffer console vs. the later serial console.

> > +               ",${baudrate}n8 ${memargs}\0" \
> >         "setupdate=run setsdupdate || run setusbupdate\0" \
> > -       "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
> > -       "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
> > -       "video-mode=dcufb:640x480-16 at 60,monitor=lcd\0" \
> > +       "setusbupdate=usb start && set interface usb && " \
> > +               "fatload ${interface} 0:1 ${loadaddr} flash_blk.img
> > && " \
> > +               "source ${loadaddr}\0" \
> >         "splashpos=m,m\0" \
> > -       SD_BOOTCMD \
> > -       NFS_BOOTCMD \
> > -       UBI_BOOTCMD
> > +       "video-mode=dcufb:640x480-16 at 60,monitor=lcd\0"
> > 
> >  /* Miscellaneous configurable options */
> >  #define CONFIG_SYS_CBSIZE              1024    /* Console I/O
> > Buffer Size */
> > --
> > 2.20.1
> > 
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > https://lists.denx.de/listinfo/u-boot

Cheers

Marcel

[U-Boot] [PATCH v2 20/22] colibri_vf: adjust timing according to data sheet

[Igor Opaniuk]

Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

On Mon, Mar 25, 2019 at 6:32 PM Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Stefan Agner <stefan.agner@toradex.com>
>
> Using the DDR Validation tool in Processor Expert uncovered two
> timing inconsistencies. Since those timings are related to the
> suspend mode they do not affect or change regular memory behaviour.
>
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v2: None
>
>  board/toradex/colibri_vf/colibri_vf.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
> index 9c5bf4951b..3e39912f91 100644
> --- a/board/toradex/colibri_vf/colibri_vf.c
> +++ b/board/toradex/colibri_vf/colibri_vf.c
> @@ -101,15 +101,21 @@ int dram_init(void)
>                 .tras_lockout      = 0,
>                 .tdal              = 12,
>                 .bstlen            = 3,
> -               .tdll              = 512,
> +               .tdll              = 512, /* not applicable since freq. scaling
> +                                          * is not used
> +                                          */
>                 .trp_ab            = 6,
>                 .tref              = 3120,
>                 .trfc              = 64,
>                 .tref_int          = 0,
>                 .tpdex             = 3,
>                 .txpdll            = 10,
> -               .txsnr             = 48,
> -               .txsr              = 468,
> +               .txsnr             = 68,  /* changed to conform to JEDEC
> +                                          * specifications
> +                                          */
> +               .txsr              = 506, /* changed to conform to JEDEC
> +                                          * specifications
> +                                          */
>                 .cksrx             = 5,
>                 .cksre             = 5,
>                 .freq_chg_en       = 0,
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 09/22] configs: colibri_vf: disable obscure options

[Igor Opaniuk]

Hi Marcel,

The actual line which does have impact is `CONFIG_DFU_MMC=y`.

Not sure I understand the reason of adding "# ... is not set" lines in
this defconfig. Could you please explain?

Regards,
Igor

On Mon, Mar 25, 2019 at 6:30 PM Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Disable more obscure options to save another 26 KB in preparation of
> the upcoming driver model migration.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v2: None
>
>  configs/colibri_vf_defconfig | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
> index 8188582ed9..706d7ca634 100644
> --- a/configs/colibri_vf_defconfig
> +++ b/configs/colibri_vf_defconfig
> @@ -17,11 +17,17 @@ CONFIG_BOARD_EARLY_INIT_F=y
>  CONFIG_HUSH_PARSER=y
>  # CONFIG_CMDLINE_EDITING is not set
>  # CONFIG_AUTO_COMPLETE is not set
> +# CONFIG_SYS_LONGHELP is not set
>  CONFIG_SYS_PROMPT="Colibri VFxx # "
> +# CONFIG_CMD_BOOTD is not set
> +# CONFIG_CMD_BOOTM is not set
>  CONFIG_CMD_BOOTZ=y
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_IMI is not set
>  CONFIG_CMD_ASKENV=y
>  CONFIG_CMD_MEMTEST=y
>  CONFIG_CMD_DFU=y
> +# CONFIG_CMD_FLASH is not set
>  CONFIG_CMD_FUSE=y
>  CONFIG_CMD_GPIO=y
>  # CONFIG_CMD_LOADB is not set
> @@ -46,10 +52,10 @@ CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
>  CONFIG_ENV_IS_IN_NAND=y
>  CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
>  CONFIG_DM=y
> -CONFIG_DFU_MMC=y
>  CONFIG_DFU_NAND=y
>  CONFIG_DM_GPIO=y
>  CONFIG_VYBRID_GPIO=y
> +# CONFIG_MMC_HW_PARTITIONING is not set
>  CONFIG_FSL_ESDHC=y
>  CONFIG_NAND_VF610_NFC=y
>  CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
> @@ -57,6 +63,8 @@ CONFIG_MTD_UBI_FASTMAP=y
>  CONFIG_PHYLIB=y
>  CONFIG_PHY_MICREL=y
>  CONFIG_MII=y
> +# CONFIG_SPL_SERIAL_PRESENT is not set
> +# CONFIG_TPL_SERIAL_PRESENT is not set
>  CONFIG_DM_SERIAL=y
>  CONFIG_FSL_LPUART=y
>  CONFIG_USB=y
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1] colibri_vf: fix ethernet by adding explicit phy node

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

The implicit fallback mechanism for searching the whole MDIO bus for at
least one PHY has been gone with the following commit b882005a18de
("drivers/net/fec: phy_init: remove redundant logic"). This lead to the
Ethernet driver erroring out as follows:

Net:   Could not get PHY for FEC0: addr -19
eth-1: fec at 400d1000
Colibri VFxx # dhcp
Could not get PHY for FEC0: addr -19
Could not get PHY for FEC0: addr -19
Could not get PHY for FEC0: addr -19
Could not get PHY for FEC0: addr -19
No ethernet found.
Could not get PHY for FEC0: addr -19
Colibri VFxx #

This commit adds an explicit PHY node which makes it work again.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 arch/arm/dts/vf-colibri.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi
index 5ce17076e9..91ca4e4ddd 100644
--- a/arch/arm/dts/vf-colibri.dtsi
+++ b/arch/arm/dts/vf-colibri.dtsi
@@ -60,11 +60,24 @@
 	status = "okay";
 };
 
+/* Ethernet */
 &fec1 {
 	phy-mode = "rmii";
+	phy-handle = <&ethphy1>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
 	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy at 1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			max-speed = <100>;
+			reg = <1>;
+		};
+	};
 };
 
 &i2c0 {
-- 
2.20.1

[U-Boot] [PATCH v1] colibri_vf: fix tab vs. spaces

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Fix indentation using tab vs. spaces.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_vf/MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS
index 3ee2b33152..66b2150986 100644
--- a/board/toradex/colibri_vf/MAINTAINERS
+++ b/board/toradex/colibri_vf/MAINTAINERS
@@ -1,7 +1,7 @@
 Colibri VFxx
 M:	Stefan Agner <stefan.agner@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
-W:      https://www.toradex.com/community
+W:	https://www.toradex.com/community
 S:	Maintained
 F:	board/toradex/colibri_vf/
 F:	include/configs/colibri_vf.h
-- 
2.20.1

[U-Boot] [PATCH v1] colibri_vf: fix ethernet by adding explicit phy node

[Hannes Schmelzer]

Marcel Ziswiler <marcel@ziswiler.com> schrieb am 28.03.2019 23:24:50:

> Von: Marcel Ziswiler <marcel@ziswiler.com>
> An: u-boot at lists.denx.de
> Kopie: Hannes Schmelzer <hannes.schmelzer@br-automation.com>, Marcel 
Ziswiler 
> <marcel.ziswiler@toradex.com>, Albert Aribaud 
<albert.u.boot@aribaud.net>, 
> Stefan Agner <stefan.agner@toradex.com>
> Datum: 28.03.2019 23:25
> Betreff: [PATCH v1] colibri_vf: fix ethernet by adding explicit phy node
> 
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> The implicit fallback mechanism for searching the whole MDIO bus for at
> least one PHY has been gone with the following commit b882005a18de
> ("drivers/net/fec: phy_init: remove redundant logic"). This lead to the
> Ethernet driver erroring out as follows:
> 
> Net:   Could not get PHY for FEC0: addr -19
> eth-1: fec at 400d1000
> Colibri VFxx # dhcp
> Could not get PHY for FEC0: addr -19
> Could not get PHY for FEC0: addr -19
> Could not get PHY for FEC0: addr -19
> Could not get PHY for FEC0: addr -19
> No ethernet found.
> Could not get PHY for FEC0: addr -19
> Colibri VFxx #
> 
> This commit adds an explicit PHY node which makes it work again.
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> ---

Looks good to me,
now the hardware is fully defined, which should be the normal case.

I will provide today a patch which "brings back" the fallback mechanism 
within the
"phy-subsystem". This should be the starting point for the disussion if we 
need such
fallback or if we want describe our hardware.

Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>

[U-Boot] [PATCH v2 09/22] configs: colibri_vf: disable obscure options

[Marcel Ziswiler]

On Thu, 2019-03-28 at 16:58 +0000, Igor Opaniuk wrote:
> Hi Marcel,
> 
> The actual line which does have impact is `CONFIG_DFU_MMC=y`.

Vybrid is using raw NAND and not eMMC.

> Not sure I understand the reason of adding "# ... is not set" lines
> in
> this defconfig. Could you please explain?

That just explicitly disables stuff.

> Regards,
> Igor
> 
> On Mon, Mar 25, 2019 at 6:30 PM Marcel Ziswiler <marcel@ziswiler.com>
> wrote:
> > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > 
> > Disable more obscure options to save another 26 KB

That's the short explanation.

The long one involves understanding that the Vybrid currently runs U-
Boot in its SRAM (rather than DDR) which is limited in size.

> >  in preparation of
> > the upcoming driver model migration.
> > 
> > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > 
> > ---
> > 
> > Changes in v2: None
> > 
> >  configs/colibri_vf_defconfig | 10 +++++++++-
> >  1 file changed, 9 insertions(+), 1 deletion(-)
> > 
> > diff --git a/configs/colibri_vf_defconfig
> > b/configs/colibri_vf_defconfig
> > index 8188582ed9..706d7ca634 100644
> > --- a/configs/colibri_vf_defconfig
> > +++ b/configs/colibri_vf_defconfig
> > @@ -17,11 +17,17 @@ CONFIG_BOARD_EARLY_INIT_F=y
> >  CONFIG_HUSH_PARSER=y
> >  # CONFIG_CMDLINE_EDITING is not set
> >  # CONFIG_AUTO_COMPLETE is not set
> > +# CONFIG_SYS_LONGHELP is not set
> >  CONFIG_SYS_PROMPT="Colibri VFxx # "
> > +# CONFIG_CMD_BOOTD is not set
> > +# CONFIG_CMD_BOOTM is not set
> >  CONFIG_CMD_BOOTZ=y
> > +# CONFIG_CMD_ELF is not set
> > +# CONFIG_CMD_IMI is not set
> >  CONFIG_CMD_ASKENV=y
> >  CONFIG_CMD_MEMTEST=y
> >  CONFIG_CMD_DFU=y
> > +# CONFIG_CMD_FLASH is not set
> >  CONFIG_CMD_FUSE=y
> >  CONFIG_CMD_GPIO=y
> >  # CONFIG_CMD_LOADB is not set
> > @@ -46,10 +52,10 @@ CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
> >  CONFIG_ENV_IS_IN_NAND=y
> >  CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> >  CONFIG_DM=y
> > -CONFIG_DFU_MMC=y
> >  CONFIG_DFU_NAND=y
> >  CONFIG_DM_GPIO=y
> >  CONFIG_VYBRID_GPIO=y
> > +# CONFIG_MMC_HW_PARTITIONING is not set
> >  CONFIG_FSL_ESDHC=y
> >  CONFIG_NAND_VF610_NFC=y
> >  CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
> > @@ -57,6 +63,8 @@ CONFIG_MTD_UBI_FASTMAP=y
> >  CONFIG_PHYLIB=y
> >  CONFIG_PHY_MICREL=y
> >  CONFIG_MII=y
> > +# CONFIG_SPL_SERIAL_PRESENT is not set
> > +# CONFIG_TPL_SERIAL_PRESENT is not set
> >  CONFIG_DM_SERIAL=y
> >  CONFIG_FSL_LPUART=y
> >  CONFIG_USB=y
> > --
> > 2.20.1
> > 
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1] colibri_vf: fix ethernet by adding explicit phy node

[Igor Opaniuk]

Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

On Fri, Mar 29, 2019 at 12:25 AM Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> The implicit fallback mechanism for searching the whole MDIO bus for at
> least one PHY has been gone with the following commit b882005a18de
> ("drivers/net/fec: phy_init: remove redundant logic"). This lead to the
> Ethernet driver erroring out as follows:
>
> Net:   Could not get PHY for FEC0: addr -19
> eth-1: fec at 400d1000
> Colibri VFxx # dhcp
> Could not get PHY for FEC0: addr -19
> Could not get PHY for FEC0: addr -19
> Could not get PHY for FEC0: addr -19
> Could not get PHY for FEC0: addr -19
> No ethernet found.
> Could not get PHY for FEC0: addr -19
> Colibri VFxx #
>
> This commit adds an explicit PHY node which makes it work again.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
>  arch/arm/dts/vf-colibri.dtsi | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi
> index 5ce17076e9..91ca4e4ddd 100644
> --- a/arch/arm/dts/vf-colibri.dtsi
> +++ b/arch/arm/dts/vf-colibri.dtsi
> @@ -60,11 +60,24 @@
>         status = "okay";
>  };
>
> +/* Ethernet */
>  &fec1 {
>         phy-mode = "rmii";
> +       phy-handle = <&ethphy1>;
>         pinctrl-names = "default";
>         pinctrl-0 = <&pinctrl_fec1>;
>         status = "okay";
> +
> +       mdio {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               ethphy1: ethernet-phy at 1 {
> +                       compatible = "ethernet-phy-ieee802.3-c22";
> +                       max-speed = <100>;
> +                       reg = <1>;
> +               };
> +       };
>  };
>
>  &i2c0 {
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1] colibri_vf: fix tab vs. spaces

[Igor Opaniuk]

Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

On Fri, Mar 29, 2019 at 12:25 AM Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Fix indentation using tab vs. spaces.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
>  board/toradex/colibri_vf/MAINTAINERS | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS
> index 3ee2b33152..66b2150986 100644
> --- a/board/toradex/colibri_vf/MAINTAINERS
> +++ b/board/toradex/colibri_vf/MAINTAINERS
> @@ -1,7 +1,7 @@
>  Colibri VFxx
>  M:     Stefan Agner <stefan.agner@toradex.com>
>  W:     http://developer.toradex.com/software/linux/linux-software
> -W:      https://www.toradex.com/community
> +W:     https://www.toradex.com/community
>  S:     Maintained
>  F:     board/toradex/colibri_vf/
>  F:     include/configs/colibri_vf.h
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 02/22] vf610: ddrmc: add missing include

[Lukasz Majewski]

On Mon, 25 Mar 2019 17:24:52 +0100
Marcel Ziswiler <marcel@ziswiler.com> wrote:

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> The DDR memory controller include file for the Vybrid uses
> iomux_v3_cfg_t without actually including iomux-vf610.h.
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> 
> ---
> 
> Changes in v2: None
> 
>  arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
> b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h index
> c7da2b8a5e..03e3cecb95 100644 ---
> a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h +++
> b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h @@ -10,6 +10,8 @@
>  #ifndef __ASM_ARCH_VF610_DDRMC_H
>  #define __ASM_ARCH_VF610_DDRMC_H
>  
> +#include <asm/arch/iomux-vf610.h>
> +
>  struct ddr3_jedec_timings {
>  	u8 tinit;
>  	u32 trst_pwron;

Reviewed-by: Lukasz Majewski <lukma@denx.de>


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190401/f5ad76a7/attachment.sig>

[U-Boot] [PATCH v2 03/22] imx: bootaux: add dependency on vf610

[Lukasz Majewski]

On Mon, 25 Mar 2019 17:24:53 +0100
Marcel Ziswiler <marcel@ziswiler.com> wrote:

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> Allow using bootaux also on VF610 aka Vybrid.
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> 
> ---
> 
> Changes in v2: None
> 
>  arch/arm/mach-imx/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 8631fbd481..ec09ef240f 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -23,7 +23,7 @@ config IMX_RDC
>  
>  config IMX_BOOTAUX
>  	bool "Support boot auxiliary core"
> -	depends on ARCH_MX7 || ARCH_MX6
> +	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610
>  	help
>  	  bootaux [addr] to boot auxiliary core.
>  

Reviewed-by: Lukasz Majewski <lukma@denx.de>


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190401/041d38c0/attachment.sig>

[U-Boot] [PATCH v2 04/22] configs: move CONFIG_USB_EHCI_VF to Kconfig

[Lukasz Majewski]

On Mon, 25 Mar 2019 17:24:54 +0100
Marcel Ziswiler <marcel@ziswiler.com> wrote:

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> Move CONFIG_USB_EHCI_VF to drivers/usb/host/Kconfig and update the one
> and only user thereof being colibri_vf.
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> 
> ---
> 
> Changes in v2: None
> 
>  drivers/usb/host/Kconfig     | 7 +++++++
>  include/configs/colibri_vf.h | 1 -
>  scripts/config_whitelist.txt | 1 -
>  3 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index ba1e6bfa43..0fbc115801 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -154,6 +154,13 @@ config USB_EHCI_OMAP
>  	  Enables support for the on-chip EHCI controller on OMAP3
> and later SoCs.
>  
> +config USB_EHCI_VF
> +	bool "Support for Vybrid on-chip EHCI USB controller"
> +	depends on ARCH_VF610
> +	default y
> +	help
> +	  Enables support for the on-chip EHCI controller on Vybrid
> SoCs. +
>  if USB_EHCI_MX7
>  
>  config MXC_USB_OTG_HACTIVE
> diff --git a/include/configs/colibri_vf.h
> b/include/configs/colibri_vf.h index 31ff8a00a6..2fe7f217fa 100644
> --- a/include/configs/colibri_vf.h
> +++ b/include/configs/colibri_vf.h
> @@ -159,7 +159,6 @@
>  #endif
>  
>  /* USB Host Support */
> -#define CONFIG_USB_EHCI_VF
>  #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
>  #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
>  
> diff --git a/scripts/config_whitelist.txt
> b/scripts/config_whitelist.txt index db00376d92..7c14b24bc1 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -4522,7 +4522,6 @@ CONFIG_USB_EHCI_MXS
>  CONFIG_USB_EHCI_SPEAR
>  CONFIG_USB_EHCI_TXFIFO_THRESH
>  CONFIG_USB_EHCI_VCT
> -CONFIG_USB_EHCI_VF
>  CONFIG_USB_ETH_QMULT
>  CONFIG_USB_ETH_SUBSET
>  CONFIG_USB_EXT2_BOOT

Reviewed-by: Lukasz Majewski <lukma@denx.de>


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190401/38abe258/attachment.sig>

[U-Boot] [PATCH v2 05/22] configs: colibri_vf: remove obsolete mmc/sd card environment

[Lukasz Majewski]

On Mon, 25 Mar 2019 17:24:55 +0100
Marcel Ziswiler <marcel@ziswiler.com> wrote:

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> Remove obsolete MMC/SD card environment configuration dating back to
> un-fused samples times.
> 
> While at it also remove meanwhile spurious "USB Storage" comment.
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> 
> ---
> 
> Changes in v2: None
> 
>  include/configs/colibri_vf.h | 9 ---------
>  1 file changed, 9 deletions(-)
> 
> diff --git a/include/configs/colibri_vf.h
> b/include/configs/colibri_vf.h index 2fe7f217fa..7b974d9e97 100644
> --- a/include/configs/colibri_vf.h
> +++ b/include/configs/colibri_vf.h
> @@ -145,13 +145,6 @@
>  	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>  
>  /* Environment organization */
> -
> -#ifdef CONFIG_ENV_IS_IN_MMC
> -#define CONFIG_SYS_MMC_ENV_DEV		0
> -#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
> -#define CONFIG_ENV_SIZE			(8 * 1024)
> -#endif
> -
>  #ifdef CONFIG_ENV_IS_IN_NAND
>  #define CONFIG_ENV_SIZE			(64 * 2048)
>  #define CONFIG_ENV_RANGE		(4 * 64 * 2048)
> @@ -165,6 +158,4 @@
>  /* USB DFU */
>  #define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024)
>  
> -/* USB Storage */
> -
>  #endif /* __CONFIG_H */

Reviewed-by: Lukasz Majewski <lukma@denx.de>


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190401/66931e5e/attachment.sig>

[U-Boot] [PATCH v2 06/22] configs: colibri_vf: limit size of malloc() pool before relocation

[Lukasz Majewski]

On Mon, 25 Mar 2019 17:24:56 +0100
Marcel Ziswiler <marcel@ziswiler.com> wrote:

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> Limit the size of the malloc() pool before relocation
> (SYS_MALLOC_F_LEN).
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> 
> ---
> 
> Changes in v2: None
> 
>  configs/colibri_vf_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/configs/colibri_vf_defconfig
> b/configs/colibri_vf_defconfig index 4192501257..8188582ed9 100644
> --- a/configs/colibri_vf_defconfig
> +++ b/configs/colibri_vf_defconfig
> @@ -2,6 +2,7 @@ CONFIG_ARM=y
>  CONFIG_SYS_THUMB_BUILD=y
>  CONFIG_ARCH_VF610=y
>  CONFIG_SYS_TEXT_BASE=0x3f401000
> +CONFIG_SYS_MALLOC_F_LEN=0x800
>  CONFIG_TARGET_COLIBRI_VF=y
>  CONFIG_ENV_VARS_UBOOT_CONFIG=y
>  CONFIG_NR_DRAM_BANKS=1

Reviewed-by: Lukasz Majewski <lukma@denx.de>


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190401/eaab60a5/attachment.sig>

[U-Boot] [U-Boot,13/17] imx6: wandboard: convert to DM_USB

[sbabic at denx.de]

> Drop CONFIG_USB_MAX_CONTROLLER_COUNT and enable DM_USB
> in defconfig.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 19/22] arm: vf610: add uart2 clock/pinmux support

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Add support for Vybrid's UART2 (Colibri UART_B).
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,11/17] imx6: wandboard: add device tree

[sbabic at denx.de]

> Add device trees from Linux in preparation for driver model
> conversions.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,17/17] imx6: wandboard: convert to DM_MMC

[sbabic at denx.de]

> Move SDHC init to SPL code since it is not required with
> DM_MMC. Enable DM_MMC support.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,08/17] colibri_imx6: convert to DM_VIDEO

[sbabic at denx.de]

> Enable DM_VIDEO in defconfig.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 11/22] colibri_vf: migrate fec, esdhc, nfc and usb to driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate FEC, ESDHC, NFC and USB to driver model.
> While at it also do no longer enable optional I2C clock in board file as
> the generic clock code now handles this. Note for space reason and as
> it is not required just for booting we do not enable I2C in U-Boot by
> default.
> While at it also update copyright period.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 04/10] board: tbs2910: Add pinctrl driver and convert gpio to driver model

[sbabic at denx.de]

> We need this for additional driver model conversions.
> Signed-off-by: Soeren Moch <smoch@web.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 22/22] colibri_vf: fix sdboot for vybrid modules

[sbabic at denx.de]

> From: Gerard Salvatella <gerard.salvatella@toradex.com>
> Currently, Vybrid's sdboot variable tries to load the kernel from /boot
> of the root partition (typically second partition when using the sdcard
> image). However, since we moved to flash the kernel in a separate UBI
> volume, we no longer deploy the kernel/device tree to /boot, hence
> sdboot does not work in its current state.
> Load the kernel and device tree from the first (typically FAT) partition
> as customary on all Toradex modules.
> While at it also change from rw to ro as e.g. systemd will re-mount the
> root file system rw anyway after checking it.
> Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
> Acked-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,10/17] mx6sabreauto: convert to DM_VIDEO

[sbabic at denx.de]

> Enable DM_VIDEO in defconfig.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v2,13/22] colibri_vf: add distroboot support

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Add support for distro boot. This is especially helpful for external
> devices. There is a global boot command which scans a predefined
> list of boot targets:
>   run distro_bootcmd
> As well as direct boot commands such as:
>   run bootcmd_mmc0
>   run bootcmd_usb
>   run bootcmd_dhcp
>   ...
> Refer to doc/README.distro fo details.
> While at it also re-order boot command macros as well as the
> CONFIG_EXTRA_ENV_SETTINGS.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 05/10] board: tbs2910: Convert usb to driver model

[sbabic at denx.de]

> So we don't need to duplicate settings from the device tree in the board file.
> Signed-off-by: Soeren Moch <smoch@web.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 08/10] ata: dwc_ahsata: Add ahci driver model support

[sbabic at denx.de]

> Disable this support for cm_fx6 to avoid breakage.
> Signed-off-by: Soeren Moch <smoch@web.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 04/22] configs: move CONFIG_USB_EHCI_VF to Kconfig

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Move CONFIG_USB_EHCI_VF to drivers/usb/host/Kconfig and update the one
> and only user thereof being colibri_vf.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 03/17] imx: move CONFIG_VIDEO_IPUV3 to defconfigs

[sbabic at denx.de]

> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 12/17] imx6: wandboard: convert to DM_GPIO and enable pinctrl driver

[sbabic at denx.de]

> Enable DM_GPIO and pinctrl in defconfig and add gpio_request()
> calls where required.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 15/22] colibri_vf: sync the board info message

[sbabic at denx.de]

> From: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> Use similar info message as on other modules.
> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 20/22] colibri_vf: adjust timing according to data sheet

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Using the DDR Validation tool in Processor Expert uncovered two
> timing inconsistencies. Since those timings are related to the
> suspend mode they do not affect or change regular memory behaviour.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 12/22] config: colibri_vf: use macros from linux/sizes.h

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Use SZ_X{MK} macros from linux/sizes.h for include/configs/colibri_vf.h.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 07/10] ata: dwc_ahsata: Fix sector reports for large disks

[sbabic at denx.de]

> Do not report negative sector numbers for disks > 1TB, do not limit
> sector numbers to 32 bit if CONFIG_SYS_64BIT_LBA is enabled.
> Signed-off-by: Soeren Moch <smoch@web.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 10/22] colibri_vf: migrate pinctrl and regulators to dtb/dm

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate pinctrl and regulators to device tree resp. driver model: DDR,
> DSPI, ENET, ESDHC, I2C, NFC and UART.
> Enable CMD_DM, PINCTRL and DM_REGULATOR.
> While at it also update copyright period and sort include files.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,16/17] imx6: wandboard: convert to DM_I2C

[sbabic at denx.de]

> Allow building with DM_I2C enabled.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v2,02/22] vf610: ddrmc: add missing include

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> The DDR memory controller include file for the Vybrid uses
> iomux_v3_cfg_t without actually including iomux-vf610.h.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,14/17] imx6: wandboard: convert to DM_VIDEO

[sbabic at denx.de]

> Enable DM_VIDEO in defconfig.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,05/17] apalis_imx6: convert to DM_VIDEO

[sbabic at denx.de]

> Enable DM_VIDEO in defconfig.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 21/22] colibri_vf: use leveling evaluated by DDR validation tools

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> The DDR validation tool (which is part of Processor Expert) allows
> to evaluate leveling parameters for CR105/CR106/CR110. Several
> runs have been made with Colibri VF50 and VF61 and it seems to
> evaluate very similar values. Use this values by default.
> Note: The newly evaluated parameters seem to require CTLUPD_AREF
> to be enabled!
> Note 2: The tool also evaluated 6 as a new value for PHY02/18
> GATE_CFG (Coarse adjust of gate open time). However, this seems
> not to work in practise.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,09/17] mx6sabresd: convert to DM_VIDEO

[sbabic at denx.de]

> Enable DM_VIDEO in defconfig.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 05/22] configs: colibri_vf: remove obsolete mmc/sd card environment

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Remove obsolete MMC/SD card environment configuration dating back to
> un-fused samples times.
> While at it also remove meanwhile spurious "USB Storage" comment.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v2,14/22] colibri_vf: set fdtfile for distroboot

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Set fdtfile to represent the current board. This allows distribution
> to load the correct device tree, which in the module case often
> deviates from the common fallback ${soc}-${board}${boardver}.dtb...
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,06/17] imx6: icore: convert to DM_VIDEO

[sbabic at denx.de]

> Enable DM_VIDEO in defconfigs.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 06/22] configs: colibri_vf: limit size of malloc() pool before relocation

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Limit the size of the malloc() pool before relocation
> (SYS_MALLOC_F_LEN).
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 08/22] ARM: dts: colibri_vf: update device trees

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Update device tree in preparation of further driver model migration:
> Ethernet FEC, ESDHC aka MMC/SD card, I2C, NFC aka NAND flash controller,
> USBH_PEN GPIO regulator.
> Add iomux resp. pinctrl entries to be removed from proprietary platform
> data: DSPI, ESDHC, FEC, I2C, NFC, UART, USBH_PEN GPIO.
> Introduce a U-Boot specific device tree with some required
> u-boot,dm-pre-reloc properties: soc, aips0, pinctrl_ddr and uart0 incl.
> pinctrl.
> While at it also update the MAINTAINERS file.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v2,03/22] imx: bootaux: add dependency on vf610

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Allow using bootaux also on VF610 aka Vybrid.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,01/17] video: ipuv3: add DM_VIDEO support

[sbabic at denx.de]

> Extend the driver to build with DM_VIDEO enabled. DTS files
> must additionally include 'u-boot,dm-pre-reloc' property in
> soc and ipu nodes to enable driver binding to ipu device.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 06/10] board: tbs2910: Convert i2c and rtc to driver model

[sbabic at denx.de]

> So we don't need to duplicate settings from the device tree in the board file.
> Signed-off-by: Soeren Moch <smoch@web.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 17/22] colibri_vf: disable undefined instruction events in user debug

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> It turns out that OpenSSL calls undefined instructions to detect
> ARM capabilities at runtime (via SIGILL handler). This leads to
> stack traces e.g. when logging in using SSH:
>   [  877.464442] sshd (613): undefined instruction: pc=76ee2da8
>   ...
> Disable undefined instruction events since it is used as an
> autodetecion mechanism.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,02/17] video: move ipuv3 files to subdirectory

[sbabic at denx.de]

> Place ipuv3 files and headers in custom driver subdirectory.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 04/17] imx6: dts: add 'u-boot, dm-pre-reloc' to soc and ipu nodes

[sbabic at denx.de]

> u-boot,dm-pre-reloc is required for reserving video memory
> when binding DM_VIDEO driver.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 09/10] board: tbs2910: Convert sata to ahci driver model

[sbabic at denx.de]

> While at it, also configure 64-bit LBA support.
> Signed-off-by: Soeren Moch <smoch@web.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 02/10] board: tbs2910: Remove efi loader support in defconfig to reduce u-boot size

[sbabic at denx.de]

> Signed-off-by: Soeren Moch <smoch@web.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 18/22] config: colibri_vf: enable mtd partitions via dt

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Use device tree to set MTD partitions of the NAND chip.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,07/17] imx6: ge_bx50v3: convert to DM_VIDEO

[sbabic at denx.de]

> Enable DM_VIDEO in defconfig.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,15/17] imx6: wandboard: convert to DM_PMIC

[sbabic at denx.de]

> Enable DM_PMIC_PFUZE100 driver and add PMIC description to DTS.
> Rework power_init_board() code.
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,03/10] board: tbs2910: Add device tree

[sbabic at denx.de]

> ... as preparation for additional driver model coonversions.
> We use CONFIG_OF_EMBED here to keep u-boot.imx as final binary name. So we
> maintain compatibility with the original TBS u-boot and available HOWTOs
> for u-boot updates.
> Signed-off-by: Soeren Moch <smoch@web.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 09/22] configs: colibri_vf: disable obscure options

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Disable more obscure options to save another 26 KB in preparation of
> the upcoming driver model migration.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 10/10] board: tbs2910: Convert mmc to driver model

[sbabic at denx.de]

> So we don't need to duplicate settings from the device tree in the board file.
> Signed-off-by: Soeren Moch <smoch@web.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 07/22] configs: move CONFIG_MXC_OCOTP to Kconfig

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> While commit 3e020f03e94f ("driver: misc: add MXC_OCOTP Kconfig entry")
> introduced a Kconfig entry it did not actually migrate all
> configurations to using it.
> As CONFIG_MXC_OCOTP was in mx{6/7}_common.h enable it by default on
> those architectures. Additionally, also enable it on ARCH_IMX8M and
> ARCH_VF610 where all current members enabled it through their legacy
> configuration header files.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 16/22] colibri_vf: enable user debug by default

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Let the kernel print some debug messages when a user program
> crashes due to an exception.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Otavio Salvador]

Hello everyone,

On Wed, Feb 27, 2019 at 10:44 PM Fabio Estevam <festevam@gmail.com> wrote:
> On Wed, Jan 2, 2019 at 4:59 AM Baruch Siach <baruch@tkos.co.il> wrote:
> > Use a single '=' to test string equality for compatibility with non-bash
> > shells. Otherwise, if /bin/sh is dash, build fails:
> >
> > ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
> > ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
> > ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
> > ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
> > WARNING './spl/u-boot-spl-ddr.bin' not found, resulting binary is not-functional
> >
> > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
>
> I don't see this patch applied yet.
>
> Do we have other solution?

This is still broken and the proposed patch does fix it. We should get
this merged for 2019.04 release.

Please Stefano, consider this for release (be it through your branch
for directly by Tom).

Best Regards,

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9 9981-7854          Mobile: +1 (347) 903-9750

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Stefano Babic]

Hi Otavio,

On 01/04/19 15:20, Otavio Salvador wrote:
> Hello everyone,
> 
> On Wed, Feb 27, 2019 at 10:44 PM Fabio Estevam <festevam@gmail.com> wrote:
>> On Wed, Jan 2, 2019 at 4:59 AM Baruch Siach <baruch@tkos.co.il> wrote:
>>> Use a single '=' to test string equality for compatibility with non-bash
>>> shells. Otherwise, if /bin/sh is dash, build fails:
>>>
>>> ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
>>> ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
>>> ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
>>> ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
>>> WARNING './spl/u-boot-spl-ddr.bin' not found, resulting binary is not-functional
>>>
>>> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
>>
>> I don't see this patch applied yet.
>>
>> Do we have other solution?
> 
> This is still broken and the proposed patch does fix it. We should get
> this merged for 2019.04 release.
> 
> Please Stefano, consider this for release (be it through your branch
> for directly by Tom).
> 

The thing is in which conditions this is broken and why it should be
fixed here and in this way. Yes, I admit, I have not pondered this as a
big issue - it could be also fixed replacing dash with bash on
Debian-like distros, and I guess also on not-debian. And I am quite sure
we cannot ensure compatibility with all possible shell that a customer
will try , from csh to some exotic variant. Why is this so important to
be rapidely fixed here ?

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Fabio Estevam]

Hi Stefano,

On Mon, Apr 1, 2019 at 10:46 AM Stefano Babic <sbabic@denx.de> wrote:

> The thing is in which conditions this is broken and why it should be
> fixed here and in this way. Yes, I admit, I have not pondered this as a
> big issue - it could be also fixed replacing dash with bash on
> Debian-like distros, and I guess also on not-debian. And I am quite sure
> we cannot ensure compatibility with all possible shell that a customer
> will try , from csh to some exotic variant. Why is this so important to
> be rapidely fixed here ?

On my Ubuntu 18.04 host I cannot build U-Boot for imx8mq-evk without
this patch, so it would be really nice if we could get Baruch's or any
other solution that fixes this issue.

Thanks

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Otavio Salvador]

On Mon, Apr 1, 2019 at 10:46 AM Stefano Babic <sbabic@denx.de> wrote:
> > This is still broken and the proposed patch does fix it. We should get
> > this merged for 2019.04 release.
> >
> > Please Stefano, consider this for release (be it through your branch
> > for directly by Tom).
> >
>
> The thing is in which conditions this is broken and why it should be
> fixed here and in this way. Yes, I admit, I have not pondered this as a
> big issue - it could be also fixed replacing dash with bash on
> Debian-like distros, and I guess also on not-debian. And I am quite sure
> we cannot ensure compatibility with all possible shell that a customer
> will try , from csh to some exotic variant. Why is this so important to
> be rapidely fixed here ?

The dash uses POSIX syntax and it failing on this is a bad signal.
Asking people to change the default system shell to build U-Boot is no
sense.

We cannot ensure compatibility, for sure, but using bashism makes it
worse and non POSIX compatible.

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9 9981-7854          Mobile: +1 (347) 903-9750

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Stefano Babic]

Hi Fabio,

On 01/04/19 15:49, Fabio Estevam wrote:
> Hi Stefano,
> 
> On Mon, Apr 1, 2019 at 10:46 AM Stefano Babic <sbabic@denx.de> wrote:
> 
>> The thing is in which conditions this is broken and why it should be
>> fixed here and in this way. Yes, I admit, I have not pondered this as a
>> big issue - it could be also fixed replacing dash with bash on
>> Debian-like distros, and I guess also on not-debian. And I am quite sure
>> we cannot ensure compatibility with all possible shell that a customer
>> will try , from csh to some exotic variant. Why is this so important to
>> be rapidely fixed here ?
> 
> On my Ubuntu 18.04 host I cannot build U-Boot for imx8mq-evk without
> this patch, so it would be really nice if we could get Baruch's or any
> other solution that fixes this issue.

Well, it looks like too much because I have 18.04, too, and I can build.
I cannot say that Ubuntu users cannot build u-boot anymore.
I guess you have /bin/sh -> dash, and /bin/sh -> bash solves the
problem, too. Or using update-alternatives, as we are in Ubuntu. I can
imagine it is disturbing in docker because a further step in
docker-compose to set up the shell is required, too.
As far as I know, default is dash (but was not dash default a long of
time ago ? I wonder this has become an issue recently, I have missed
something in the between). Nevertheless, I am still missing why this is
so important to push here when the user can set the shell and build
without issues. And travis works, too, it is also based on Ubuntu :
trusty, quite old, but I was convinced that dash was the default in
Ubuntu since a long time.

Maybe I am missing the point here...(to be honest: I put the patch in
"Changes requested" a lot of time ago and I have forgotten about it..)

Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Tom Rini]

On Mon, Apr 01, 2019 at 03:46:20PM +0200, Stefano Babic wrote:
> Hi Otavio,
> 
> On 01/04/19 15:20, Otavio Salvador wrote:
> > Hello everyone,
> > 
> > On Wed, Feb 27, 2019 at 10:44 PM Fabio Estevam <festevam@gmail.com> wrote:
> >> On Wed, Jan 2, 2019 at 4:59 AM Baruch Siach <baruch@tkos.co.il> wrote:
> >>> Use a single '=' to test string equality for compatibility with non-bash
> >>> shells. Otherwise, if /bin/sh is dash, build fails:
> >>>
> >>> ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
> >>> ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
> >>> ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
> >>> ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
> >>> WARNING './spl/u-boot-spl-ddr.bin' not found, resulting binary is not-functional
> >>>
> >>> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> >>
> >> I don't see this patch applied yet.
> >>
> >> Do we have other solution?
> > 
> > This is still broken and the proposed patch does fix it. We should get
> > this merged for 2019.04 release.
> > 
> > Please Stefano, consider this for release (be it through your branch
> > for directly by Tom).
> > 
> 
> The thing is in which conditions this is broken and why it should be
> fixed here and in this way. Yes, I admit, I have not pondered this as a
> big issue - it could be also fixed replacing dash with bash on
> Debian-like distros, and I guess also on not-debian. And I am quite sure
> we cannot ensure compatibility with all possible shell that a customer
> will try , from csh to some exotic variant. Why is this so important to
> be rapidely fixed here ?

The script says it uses /bin/sh and not /bin/bash, so you cannot do
bashism in there.

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190401/cc0f4eec/attachment.sig>

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Fabio Estevam]

Hi Stefano,

On Mon, Apr 1, 2019 at 11:06 AM Stefano Babic <sbabic@denx.de> wrote:

> Well, it looks like too much because I have 18.04, too, and I can build.
> I cannot say that Ubuntu users cannot build u-boot anymore.
> I guess you have /bin/sh -> dash, and /bin/sh -> bash solves the
> problem, too. Or using update-alternatives, as we are in Ubuntu. I can
> imagine it is disturbing in docker because a further step in
> docker-compose to set up the shell is required, too.
> As far as I know, default is dash (but was not dash default a long of
> time ago ? I wonder this has become an issue recently, I have missed
> something in the between). Nevertheless, I am still missing why this is
> so important to push here when the user can set the shell and build
> without issues. And travis works, too, it is also based on Ubuntu :

Travis does not report an error, but Travis does not try to generate a
real 'flash.bin' with the required DDR, HDMI and ATF firmwares.

The error comes when we try to generate flash.bin with all these firmwares.

Without Baruch's patch I can not generate a flash.bin that can boot on
im8mq-evk, so that's why I see the lack of this patch as a big issue.

Thanks

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism

[Stefano Babic]

Hi Fabio, Otavio,

On 01/04/19 16:14, Fabio Estevam wrote:
> Hi Stefano,
> 
> On Mon, Apr 1, 2019 at 11:06 AM Stefano Babic <sbabic@denx.de> wrote:
> 
>> Well, it looks like too much because I have 18.04, too, and I can build.
>> I cannot say that Ubuntu users cannot build u-boot anymore.
>> I guess you have /bin/sh -> dash, and /bin/sh -> bash solves the
>> problem, too. Or using update-alternatives, as we are in Ubuntu. I can
>> imagine it is disturbing in docker because a further step in
>> docker-compose to set up the shell is required, too.
>> As far as I know, default is dash (but was not dash default a long of
>> time ago ? I wonder this has become an issue recently, I have missed
>> something in the between). Nevertheless, I am still missing why this is
>> so important to push here when the user can set the shell and build
>> without issues. And travis works, too, it is also based on Ubuntu :
> 
> Travis does not report an error, but Travis does not try to generate a
> real 'flash.bin' with the required DDR, HDMI and ATF firmwares.
> 
> The error comes when we try to generate flash.bin with all these firmwares.
> 
> Without Baruch's patch I can not generate a flash.bin that can boot on
> im8mq-evk, so that's why I see the lack of this patch as a big issue.
> 

Ok - convinced. I pick it up.

Regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [imx-next PATCH v1 00/14] imx: Fully convert HSC|DDC K+P i.MX53 based boards to use DM/DTS

[Lukasz Majewski]

This patch series converts HSC and DDC to solely use Driver Model and
Device Tree.
(As a side effect the "removal warnings" are not present anymore).

Some notable changes:
- Converting ehci-mx5 to DM
- CONFIG_USB_EHCI_MX5 to Kconfig
- Use of esdhc with DM
- Cleanup of config

This patch series applies on top of u-boot-imx -next branch
SHA1: 9648463488735e13328f8738c56251e1fb941e51


Lukasz Majewski (14):
  ARM: Remove HSC|DDC ETH PHY reset code after switching to DM/DTS
  DTS: Add esdhc3 device tree description tuning for HSC|DDC boards
  ARM: Enable CONFIG_DM_MMC and CONFIG_DM_BLK on HSC and DDC boards
  ARM: defconfig: Move CONFIG_FSL_ESDHC to Kconfig
  ARM: Remove non DM/DTS esdhc3 code from HSC|DDC board related files
  ARM: kp_imx53: config: Do not use ${boardtype} to setup update wic
    file
  DTS: Provide USB host DTS description for i.MX53 devices
  DTS: Enable USB host support (including regulators) on HSC|DDC boards
  ARM: Remove EHCI specific code from HSC|DDC board file
  USB: DM: Convert i.MX5 ehci code to driver model
  ARM: defconfig: kp_imx53: Enable DM_USB support on HSC|DDC boards
  ARM: config: Remove not needed CONFIG_MXC_USB_PORT define
  Convert CONFIG_USB_EHCI_MX5 to Kconfig
  boot.src: Provide dsa_core.blacklist bootarg when booting via NFS

 arch/arm/dts/imx53-kp.dts         |  59 +++++++++++++++++++++-
 arch/arm/dts/imx53.dtsi           |  10 ++++
 arch/arm/mach-imx/mx5/Kconfig     |   4 ++
 board/k+p/bootscripts/tpcboot.cmd |   7 +++
 board/k+p/kp_imx53/kp_imx53.c     |  70 --------------------------
 configs/kp_imx53_defconfig        |   3 ++
 configs/m53menlo_defconfig        |   1 +
 configs/mx51evk_defconfig         |   1 +
 configs/mx53loco_defconfig        |   1 +
 configs/mx53ppd_defconfig         |   1 +
 configs/usbarmory_defconfig       |   1 +
 drivers/usb/host/Kconfig          |   7 +++
 drivers/usb/host/ehci-mx5.c       | 103 ++++++++++++++++++++++++++++++++++++++
 include/configs/kp_imx53.h        |   9 +---
 include/configs/m53menlo.h        |   1 -
 include/configs/mx51evk.h         |   1 -
 include/configs/mx53cx9020.h      |   1 -
 include/configs/mx53loco.h        |   1 -
 include/configs/mx53ppd.h         |   1 -
 include/configs/usbarmory.h       |   1 -
 scripts/config_whitelist.txt      |   1 -
 21 files changed, 197 insertions(+), 87 deletions(-)

-- 
2.11.0

[U-Boot] [imx-next PATCH v1 01/14] ARM: Remove HSC|DDC ETH PHY reset code after switching to DM/DTS

[Lukasz Majewski]

After commit efd0b791069a ("eth: dm: fec: Add gpio phy reset binding")
the in-board file definition of ETH PHY reset can be removed.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 board/k+p/kp_imx53/kp_imx53.c | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c
index a12ab9107f..3f21d0b4af 100644
--- a/board/k+p/kp_imx53/kp_imx53.c
+++ b/board/k+p/kp_imx53/kp_imx53.c
@@ -20,7 +20,6 @@
 #include "kp_id_rev.h"
 
 #define VBUS_PWR_EN IMX_GPIO_NR(7, 8)
-#define PHY_nRST IMX_GPIO_NR(7, 6)
 #define BOOSTER_OFF IMX_GPIO_NR(2, 23)
 #define LCD_BACKLIGHT IMX_GPIO_NR(1, 1)
 #define KEY1 IMX_GPIO_NR(2, 26)
@@ -211,17 +210,6 @@ int board_init(void)
 	return 0;
 }
 
-void eth_phy_reset(void)
-{
-	gpio_request(PHY_nRST, "PHY_nRST");
-	gpio_direction_output(PHY_nRST, 1);
-	udelay(50);
-	gpio_set_value(PHY_nRST, 0);
-	udelay(400);
-	gpio_set_value(PHY_nRST, 1);
-	udelay(50);
-}
-
 void board_disable_display(void)
 {
 	gpio_request(LCD_BACKLIGHT, "LCD_BACKLIGHT");
@@ -258,8 +246,6 @@ int board_late_init(void)
 	if (ret)
 		printf("Error %d reading EEPROM content!\n", ret);
 
-	eth_phy_reset();
-
 	show_eeprom();
 	read_board_id();
 
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 02/14] DTS: Add esdhc3 device tree description tuning for HSC|DDC boards

[Lukasz Majewski]

In this commit the esdhc3 controller is enabled as well as it is remaped
to mmc0 to not break legacy code.

The pinctrl setup (e.g. 0x1e4) is the same as one from in-board file
definition.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 arch/arm/dts/imx53-kp.dts | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/dts/imx53-kp.dts b/arch/arm/dts/imx53-kp.dts
index 3ce4445c18..a551fc945b 100644
--- a/arch/arm/dts/imx53-kp.dts
+++ b/arch/arm/dts/imx53-kp.dts
@@ -17,6 +17,18 @@
 	chosen {
 		stdout-path = &uart2;
 	};
+
+	aliases {
+		mmc0 = &esdhc3;
+	};
+};
+
+&esdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esdhc3>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
 };
 
 &fec {
@@ -61,6 +73,21 @@
 	pinctrl-0 = <&pinctrl_hog>;
 
 	imx53-kp {
+		pinctrl_esdhc3: esdhc3grp {
+			fsl,pins = <
+				MX53_PAD_PATA_DATA8__ESDHC3_DAT0        0x1d4
+				MX53_PAD_PATA_DATA9__ESDHC3_DAT1        0x1d4
+				MX53_PAD_PATA_DATA10__ESDHC3_DAT2       0x1d4
+				MX53_PAD_PATA_DATA11__ESDHC3_DAT3       0x1d4
+				MX53_PAD_PATA_DATA0__ESDHC3_DAT4        0x1d4
+				MX53_PAD_PATA_DATA1__ESDHC3_DAT5        0x1d4
+				MX53_PAD_PATA_DATA2__ESDHC3_DAT6        0x1d4
+				MX53_PAD_PATA_DATA3__ESDHC3_DAT7        0x1d4
+				MX53_PAD_PATA_RESET_B__ESDHC3_CMD       0x1e4
+				MX53_PAD_PATA_IORDY__ESDHC3_CLK         0x1d4
+			>;
+		};
+
 		pinctrl_eth: ethgrp {
 			fsl,pins = <
 				MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 03/14] ARM: Enable CONFIG_DM_MMC and CONFIG_DM_BLK on HSC and DDC boards

[Lukasz Majewski]

This commit enables DM_MMC and DM_BLK on imx53 based HSC and DDC boards.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 arch/arm/mach-imx/mx5/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index 29051c40f3..cbffdaeed1 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -27,6 +27,8 @@ config TARGET_KP_IMX53
 	select DM_I2C
 	select DM_PMIC
 	select DM_SERIAL
+	select DM_MMC
+	select BLK
 	select MX53
 	imply CMD_DM
 
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 04/14] ARM: defconfig: Move CONFIG_FSL_ESDHC to Kconfig

[Lukasz Majewski]

The CONFIG_FSL_ESDHC is now enabled and defined in Kconfig, not in
include/configs/kp_imx53.h

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 configs/kp_imx53_defconfig | 1 +
 include/configs/kp_imx53.h | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig
index cfe96fcce5..4be67d1736 100644
--- a/configs/kp_imx53_defconfig
+++ b/configs/kp_imx53_defconfig
@@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx53-kp"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
 CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
+CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
 CONFIG_FEC_MXC=y
diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h
index 3ea75fa120..f82dcd8426 100644
--- a/include/configs/kp_imx53.h
+++ b/include/configs/kp_imx53.h
@@ -16,7 +16,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
 
 /* MMC Configs */
-#define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_ESDHC_NUM	1
 
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 05/14] ARM: Remove non DM/DTS esdhc3 code from HSC|DDC board related files

[Lukasz Majewski]

After switching to DM/DTS support of esdhc3 - the code in this patch
can be removed.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 board/k+p/kp_imx53/kp_imx53.c | 46 -------------------------------------------
 include/configs/kp_imx53.h    |  4 ----
 2 files changed, 50 deletions(-)

diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c
index 3f21d0b4af..f4d0ad0ef6 100644
--- a/board/k+p/kp_imx53/kp_imx53.c
+++ b/board/k+p/kp_imx53/kp_imx53.c
@@ -13,8 +13,6 @@
 #include <asm/arch/iomux-mx53.h>
 #include <asm/arch/clock.h>
 #include <asm/gpio.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
 #include <power/pmic.h>
 #include <fsl_pmic.h>
 #include "kp_id_rev.h"
@@ -53,50 +51,6 @@ int board_ehci_hcd_init(int port)
 }
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[] = {
-	{MMC_SDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	return 1; /* eMMC is always present */
-}
-
-#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
-				 PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
-				 PAD_CTL_DSE_HIGH)
-
-int board_mmc_init(bd_t *bis)
-{
-	int ret;
-
-	static const iomux_v3_cfg_t sd3_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-			     SD_CMD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
-	};
-
-	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads));
-
-	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-#endif
-
 static int power_init(void)
 {
 	struct udevice *dev;
diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h
index f82dcd8426..ca6ab0fabc 100644
--- a/include/configs/kp_imx53.h
+++ b/include/configs/kp_imx53.h
@@ -15,10 +15,6 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
 
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
-#define CONFIG_SYS_FSL_ESDHC_NUM	1
-
 /* USB Configs */
 #define CONFIG_USB_EHCI_MX5
 #define CONFIG_MXC_USB_PORT	1
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 06/14] ARM: kp_imx53: config: Do not use ${boardtype} to setup update wic file

[Lukasz Majewski]

After unification of the rootfs for both HSC and DDC devices, only one,
common wic file is necessary - without the distinction of specific board.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 include/configs/kp_imx53.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h
index ca6ab0fabc..9bbf590b72 100644
--- a/include/configs/kp_imx53.h
+++ b/include/configs/kp_imx53.h
@@ -52,7 +52,7 @@
 	       "setexpr blkc ${blkc} + 1; " \
 	       "mmc write ${loadaddr} 0x2 ${blkc}" \
 	"; fi\0"	  \
-	"upwic=setenv wic_file kp-image-kp${boardsoc}${boardtype}.wic; "\
+	"upwic=setenv wic_file kp-image-kp${boardsoc}.wic; "\
 	       "if tftp ${loadaddr} ${wic_file}; then " \
 	       "setexpr blkc ${filesize} / 0x200; " \
 	       "setexpr blkc ${blkc} + 1; " \
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 07/14] DTS: Provide USB host DTS description for i.MX53 devices

[Lukasz Majewski]

This code has been ported from Linux kernel - tag v5.1-rc2.
The difference from the kernel is the removal of:
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;

properties, which are not needed for correct u-boot operation (as PHY
setup is done in ehci-mx5.c file itself).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 arch/arm/dts/imx53.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index 0fd4acc6f5..5ba6174789 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -35,6 +35,7 @@
 		mmc1 = &esdhc2;
 		mmc2 = &esdhc3;
 		mmc3 = &esdhc4;
+		usb1 = &usbh1;
 	};
 
 	tzic: tz-interrupt-controller at fffc000 {
@@ -136,6 +137,15 @@
 				status = "disabled";
 			};
 
+			usbh1: usb at 53f80200 {
+				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+				reg = <0x53f80200 0x0200>;
+				interrupts = <14>;
+				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+				dr_mode = "host";
+				status = "disabled";
+			};
+
 			clks: ccm at 53fd4000{
 				compatible = "fsl,imx53-ccm";
 				reg = <0x53fd4000 0x4000>;
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 08/14] DTS: Enable USB host support (including regulators) on HSC|DDC boards

[Lukasz Majewski]

This commit enables the support for K&P's HSC|DDC imx53 based boards.
It was also necessary to provide device tree description for regulators
to avoid board specific code definition.

The GPIO pin description responsible for VBUS control has been moved from
"hog" group to usbh1 dedicated one.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 arch/arm/dts/imx53-kp.dts | 32 ++++++++++++++++++++++++++++++--
 1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/imx53-kp.dts b/arch/arm/dts/imx53-kp.dts
index a551fc945b..af4ab5d9f8 100644
--- a/arch/arm/dts/imx53-kp.dts
+++ b/arch/arm/dts/imx53-kp.dts
@@ -21,6 +21,22 @@
 	aliases {
 		mmc0 = &esdhc3;
 	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usbh1_vbus: regulator-usbh1-vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usbh1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+
 };
 
 &esdhc3 {
@@ -109,8 +125,6 @@
 			fsl,pins = <
 				/* PHY RESET */
 				MX53_PAD_PATA_DA_0__GPIO7_6 0x182
-				/* VBUS_PWR_EN */
-				MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
 				/* BOOSTER_OFF */
 				MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
 				/* LCD BACKLIGHT */
@@ -158,6 +172,13 @@
 				MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
 			>;
 		};
+
+		pinctrl_usbh1: usbh1grp {
+			fsl,pins = <
+				/* VBUS_PWR_EN */
+				MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
+			>;
+		};
 	};
 };
 
@@ -166,3 +187,10 @@
 	pinctrl-0 = <&pinctrl_uart2>;
 	status = "okay";
 };
+
+&usbh1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbh1>;
+	vbus-supply = <&reg_usbh1_vbus>;
+	status = "okay";
+};
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 09/14] ARM: Remove EHCI specific code from HSC|DDC board file

[Lukasz Majewski]

As EHCI on i.MX5 has been converted to driver model, the board specific
code, necessary for VBUS USB power supply setup is not needed anymore.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 board/k+p/kp_imx53/kp_imx53.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c
index f4d0ad0ef6..57d97153dd 100644
--- a/board/k+p/kp_imx53/kp_imx53.c
+++ b/board/k+p/kp_imx53/kp_imx53.c
@@ -17,7 +17,6 @@
 #include <fsl_pmic.h>
 #include "kp_id_rev.h"
 
-#define VBUS_PWR_EN IMX_GPIO_NR(7, 8)
 #define BOOSTER_OFF IMX_GPIO_NR(2, 23)
 #define LCD_BACKLIGHT IMX_GPIO_NR(1, 1)
 #define KEY1 IMX_GPIO_NR(2, 26)
@@ -42,15 +41,6 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-#ifdef CONFIG_USB_EHCI_MX5
-int board_ehci_hcd_init(int port)
-{
-	gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN");
-	gpio_direction_output(VBUS_PWR_EN, 1);
-	return 0;
-}
-#endif
-
 static int power_init(void)
 {
 	struct udevice *dev;
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 10/14] USB: DM: Convert i.MX5 ehci code to driver model

[Lukasz Majewski]

This commit converts i.MX5's EHCI USB host driver to driver model (DM_USB).
It is a straightforward conversion (to reuse as much code as possible),
based on ehci-mx6.c code.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 drivers/usb/host/ehci-mx5.c | 103 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 103 insertions(+)

diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index 60f1470860..0b32728c57 100644
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -12,6 +12,8 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
+#include <dm.h>
+#include <power/regulator.h>
 
 #include "ehci.h"
 
@@ -223,6 +225,7 @@ __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
 	mdelay(50);
 }
 
+#if !CONFIG_IS_ENABLED(DM_USB)
 static const struct ehci_ops mx5_ehci_ops = {
 	.powerup_fixup		= mx5_ehci_powerup_fixup,
 };
@@ -267,3 +270,103 @@ int ehci_hcd_stop(int index)
 {
 	return 0;
 }
+#else /* CONFIG_IS_ENABLED(DM_USB) */
+struct ehci_mx5_priv_data {
+	struct ehci_ctrl ctrl;
+	struct usb_ehci *ehci;
+	struct udevice *vbus_supply;
+	enum usb_init_type init_type;
+	int portnr;
+};
+
+static const struct ehci_ops mx5_ehci_ops = {
+	.powerup_fixup		= mx5_ehci_powerup_fixup,
+};
+
+static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+{
+	struct usb_platdata *plat = dev_get_platdata(dev);
+	const char *mode;
+
+	mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
+	if (mode) {
+		if (strcmp(mode, "peripheral") == 0)
+			plat->init_type = USB_INIT_DEVICE;
+		else if (strcmp(mode, "host") == 0)
+			plat->init_type = USB_INIT_HOST;
+		else
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int ehci_usb_probe(struct udevice *dev)
+{
+	struct usb_platdata *plat = dev_get_platdata(dev);
+	struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
+	struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
+	enum usb_init_type type = plat->init_type;
+	struct ehci_hccr *hccr;
+	struct ehci_hcor *hcor;
+	int ret;
+
+	set_usboh3_clk();
+	enable_usboh3_clk(true);
+	set_usb_phy_clk();
+	enable_usb_phy1_clk(true);
+	enable_usb_phy2_clk(true);
+	mdelay(1);
+
+	priv->ehci = ehci;
+	priv->portnr = dev->seq;
+	priv->init_type = type;
+
+	ret = device_get_supply_regulator(dev, "vbus-supply",
+					  &priv->vbus_supply);
+	if (ret)
+		debug("%s: No vbus supply\n", dev->name);
+
+	if (!ret && priv->vbus_supply) {
+		ret = regulator_set_enable(priv->vbus_supply,
+					   (type == USB_INIT_DEVICE) ?
+					   false : true);
+		if (ret) {
+			puts("Error enabling VBUS supply\n");
+			return ret;
+		}
+	}
+
+	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	hcor = (struct ehci_hcor *)((uint32_t)hccr +
+			HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
+	setbits_le32(&ehci->usbmode, CM_HOST);
+
+	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+	setbits_le32(&ehci->portsc, USB_EN);
+
+	mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
+	mdelay(10);
+
+	return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
+			     priv->init_type);
+}
+
+static const struct udevice_id mx5_usb_ids[] = {
+	{ .compatible = "fsl,imx53-usb" },
+	{ }
+};
+
+U_BOOT_DRIVER(usb_mx5) = {
+	.name	= "ehci_mx5",
+	.id	= UCLASS_USB,
+	.of_match = mx5_usb_ids,
+	.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+	.probe	= ehci_usb_probe,
+	.remove = ehci_deregister,
+	.ops	= &ehci_usb_ops,
+	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
+	.priv_auto_alloc_size = sizeof(struct ehci_mx5_priv_data),
+	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif /* !CONFIG_IS_ENABLED(DM_USB) */
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 11/14] ARM: defconfig: kp_imx53: Enable DM_USB support on HSC|DDC boards

[Lukasz Majewski]

This commit enables the DM_USB on HSC|DDC i.MX53 based boards.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 arch/arm/mach-imx/mx5/Kconfig | 2 ++
 configs/kp_imx53_defconfig    | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index cbffdaeed1..bde37bb97e 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -29,6 +29,8 @@ config TARGET_KP_IMX53
 	select DM_SERIAL
 	select DM_MMC
 	select BLK
+	select DM_USB
+	select DM_REGULATOR
 	select MX53
 	imply CMD_DM
 
diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig
index 4be67d1736..45227c26d2 100644
--- a/configs/kp_imx53_defconfig
+++ b/configs/kp_imx53_defconfig
@@ -40,6 +40,7 @@ CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX5=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_DM_PMIC_MC34708=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_CONS_INDEX=2
 CONFIG_MXC_UART=y
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 12/14] ARM: config: Remove not needed CONFIG_MXC_USB_PORT define

[Lukasz Majewski]

After i.MX5's EHCI conversion to DM, the CONFIG_MXC_USB_PORT is not needed
anymore and should be removed.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 include/configs/kp_imx53.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h
index 9bbf590b72..d09608df35 100644
--- a/include/configs/kp_imx53.h
+++ b/include/configs/kp_imx53.h
@@ -17,7 +17,6 @@
 
 /* USB Configs */
 #define CONFIG_USB_EHCI_MX5
-#define CONFIG_MXC_USB_PORT	1
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 13/14] Convert CONFIG_USB_EHCI_MX5 to Kconfig

[Lukasz Majewski]

This converts the following to Kconfig:
   CONFIG_USB_EHCI_MX5

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---

 configs/kp_imx53_defconfig   | 1 +
 configs/m53menlo_defconfig   | 1 +
 configs/mx51evk_defconfig    | 1 +
 configs/mx53loco_defconfig   | 1 +
 configs/mx53ppd_defconfig    | 1 +
 configs/usbarmory_defconfig  | 1 +
 drivers/usb/host/Kconfig     | 7 +++++++
 include/configs/kp_imx53.h   | 1 -
 include/configs/m53menlo.h   | 1 -
 include/configs/mx51evk.h    | 1 -
 include/configs/mx53cx9020.h | 1 -
 include/configs/mx53loco.h   | 1 -
 include/configs/mx53ppd.h    | 1 -
 include/configs/usbarmory.h  | 1 -
 scripts/config_whitelist.txt | 1 -
 15 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig
index 45227c26d2..225be66019 100644
--- a/configs/kp_imx53_defconfig
+++ b/configs/kp_imx53_defconfig
@@ -45,4 +45,5 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_CONS_INDEX=2
 CONFIG_MXC_UART=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index e830b2c92e..e10cb8ed8d 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -58,6 +58,7 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_RTC_M41T62=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index dc0b3b3f77..78aa89d651 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -26,6 +26,7 @@ CONFIG_MII=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index 776fc8bab4..caf04ad894 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -26,6 +26,7 @@ CONFIG_DWC_AHSATA=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MII=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index 2a6183b77b..2379ab8c66 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -37,6 +37,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MII=y
 CONFIG_RTC_S35392A=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index b1f872405b..46f9996e18 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -15,4 +15,5 @@ CONFIG_CMD_USB=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
 CONFIG_OF_LIBFDT=y
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 0fbc115801..1c2212f547 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -132,6 +132,13 @@ config USB_EHCI_MARVELL
 	---help---
 	  Enables support for the on-chip EHCI controller on MVEBU SoCs.
 
+config USB_EHCI_MX5
+	bool "Support for i.MX5 on-chip EHCI USB controller"
+	depends on ARCH_MX5
+	default n
+	help
+	  Enables support for the on-chip EHCI controller on i.MX5 SoCs.
+
 config USB_EHCI_MX6
 	bool "Support for i.MX6 on-chip EHCI USB controller"
 	depends on ARCH_MX6
diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h
index d09608df35..a252e9003d 100644
--- a/include/configs/kp_imx53.h
+++ b/include/configs/kp_imx53.h
@@ -16,7 +16,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
 
 /* USB Configs */
-#define CONFIG_USB_EHCI_MX5
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 84d061339e..82842d8426 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -118,7 +118,6 @@
  * USB
  */
 #ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_MX5
 #define CONFIG_MXC_USB_PORT		1
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS		0
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 9bf9773c69..f5fd01de22 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -61,7 +61,6 @@
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
 /* USB Configs */
-#define CONFIG_USB_EHCI_MX5
 #define CONFIG_MXC_USB_PORT	1
 #define CONFIG_MXC_USB_PORTSC	PORT_PTS_ULPI
 #define CONFIG_MXC_USB_FLAGS	MXC_EHCI_POWER_PINS_ENABLED
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index 1e3ea88b77..9bf5d9169b 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h
@@ -41,7 +41,6 @@
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
 /* USB Configs */
-#define CONFIG_USB_EHCI_MX5
 #define CONFIG_MXC_USB_PORT	1
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 2d18f05423..4f179081a8 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -38,7 +38,6 @@
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
 /* USB Configs */
-#define CONFIG_USB_EHCI_MX5
 #define CONFIG_MXC_USB_PORT	1
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index f002324fdd..2d6715cba2 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h
@@ -37,7 +37,6 @@
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
 /* USB Configs */
-#define CONFIG_USB_EHCI_MX5
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_USB_ETHER_MCS7830
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index 270f325a55..128f02db66 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -31,7 +31,6 @@
 #define CONFIG_SYS_FSL_ESDHC_NUM	1
 
 /* USB */
-#define CONFIG_USB_EHCI_MX5
 #define CONFIG_MXC_USB_PORT	1
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index f1fc131f53..5d39191027 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4509,7 +4509,6 @@ CONFIG_USB_EHCI_BASE_LIST
 CONFIG_USB_EHCI_EXYNOS
 CONFIG_USB_EHCI_FARADAY
 CONFIG_USB_EHCI_KIRKWOOD
-CONFIG_USB_EHCI_MX5
 CONFIG_USB_EHCI_MXC
 CONFIG_USB_EHCI_MXS
 CONFIG_USB_EHCI_SPEAR
-- 
2.11.0

[U-Boot] [imx-next PATCH v1 14/14] boot.src: Provide dsa_core.blacklist bootarg when booting via NFS

[Lukasz Majewski]

This setup is a bit special as Linux kernel (4.19) is not supporting
in-kernel NFS rootfs mount and Distributed Switch Architecture (DSA)
operation.

For that reason it was necessary to provide a bootarg to allow userspace
enable it afterwards if needed.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

---

 board/k+p/bootscripts/tpcboot.cmd | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/board/k+p/bootscripts/tpcboot.cmd b/board/k+p/bootscripts/tpcboot.cmd
index 0576e81140..b81494dd1b 100644
--- a/board/k+p/bootscripts/tpcboot.cmd
+++ b/board/k+p/bootscripts/tpcboot.cmd
@@ -27,6 +27,12 @@ setenv miscadj "
 if test '${boardsoc}' = 'imx53'; then
        setenv bootargs '${bootargs} di=${dig_in} key1=${key1}';
 fi;"
+setenv nfsadj "
+if test '${boardsoc}' = 'imx53'; then
+   if test '${boardtype}' = 'hsc'; then
+       setenv bootargs '${bootargs} dsa_core.blacklist=yes';
+   fi;
+fi;"
 setenv boot_fitImage "
 	setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb';
 	setenv itbcfg "\"#\${fdt_conf}\"";
@@ -72,6 +78,7 @@ setenv boot_nfs "
 if run download_kernel; then
 	run nfsargs;
 	run addip;
+	run nfsadj;
 	setenv bootargs '${bootargs}' console=${console};
 
 	run boot_fitImage;
-- 
2.11.0

[U-Boot] [PATCH] imx8qxp: mek: enable dm-spl for pm

[Peng Fan]

Ping..

Thanks,
Peng

> Hi Stefano,
> 
> Are you fine with this patch?
> 
> Thanks,
> Peng.
> 
> > -----Original Message-----
> > From: Peng Fan
> > Sent: 2019年3月7日 20:44
> > To: sbabic at denx.de; festevam at gmail.com
> > Cc: dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de; Peng Fan
> > <peng.fan@nxp.com>
> > Subject: [PATCH] imx8qxp: mek: enable dm-spl for pm
> >
> > with u-boot,dm-spl added for imx8qx-pm node, and SPL_SIMPLE_BUS
> > enabled, the bind and probe code in board file could be removed.
> >
> > Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi |  5 +++++
> >  board/freescale/imx8qxp_mek/spl.c        | 15 ---------------
> >  configs/imx8qxp_mek_defconfig            |  2 +-
> >  3 files changed, 6 insertions(+), 16 deletions(-)
> >
> > diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> > b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> > index 5d50eb028e..201559008c 100644
> > --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> > +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> > @@ -3,6 +3,11 @@
> >   * Copyright 2018 NXP
> >   */
> >
> > +&{/imx8qx-pm} {
> > +
> > +	u-boot,dm-spl;
> > +};
> > +
> >  &mu {
> >  	u-boot,dm-spl;
> >  };
> > diff --git a/board/freescale/imx8qxp_mek/spl.c
> > b/board/freescale/imx8qxp_mek/spl.c
> > index 95ce9f37e8..51f323811a 100644
> > --- a/board/freescale/imx8qxp_mek/spl.c
> > +++ b/board/freescale/imx8qxp_mek/spl.c
> > @@ -27,21 +27,6 @@ void spl_board_init(void)
> >  			continue;
> >  	}
> >
> > -	offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
> > "nxp,imx8-pd");
> > -	while (offset != -FDT_ERR_NOTFOUND) {
> > -		lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
> > -			       NULL, true);
> > -		offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
> > -						       "nxp,imx8-pd");
> > -	}
> > -
> > -	uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
> > -
> > -	for (; dev; uclass_find_next_device(&dev)) {
> > -		if (device_probe(dev))
> > -			continue;
> > -	}
> > -
> >  	arch_cpu_init();
> >
> >  	board_early_init_f();
> > diff --git a/configs/imx8qxp_mek_defconfig
> > b/configs/imx8qxp_mek_defconfig index a94998b8b5..915d8812ad 100644
> > --- a/configs/imx8qxp_mek_defconfig
> > +++ b/configs/imx8qxp_mek_defconfig
> > @@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x80020000
> > CONFIG_SPL_GPIO_SUPPORT=y  CONFIG_SPL_LIBCOMMON_SUPPORT=y
> > CONFIG_SPL_LIBGENERIC_SUPPORT=y
> > -CONFIG_SYS_MALLOC_F_LEN=0x2000
> > +CONFIG_SYS_MALLOC_F_LEN=0x4000
> >  CONFIG_TARGET_IMX8QXP_MEK=y
> >  CONFIG_SPL_MMC_SUPPORT=y
> >  CONFIG_SPL_SERIAL_SUPPORT=y
> > --
> > 2.16.4

[U-Boot] [PATCH RESEND 10/10] imx: support i.MX8QM MEK board

[Peng Fan]

Hi Stefano, Fabio

Any comments on this patchset?

Thanks,
Peng.

> -----Original Message-----
> From: Peng Fan [mailto:peng.fan at nxp.com]
> Sent: 2019年3月5日 10:33
> To: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>
> Cc: u-boot at lists.denx.de; van.freenix at gmail.com; dl-uboot-imx
> <uboot-imx@nxp.com>; Peng Fan <peng.fan@nxp.com>
> Subject: [PATCH RESEND 10/10] imx: support i.MX8QM MEK board
> 
> Add i.MX8QM MEK board support.
> Included a basic dts, enabled SPL FIT
> 
> Boot log as below:
> U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
> Normal Boot Trying to boot from MMC2_2
> 
> U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
> 
> CPU:   NXP i.MX8QM RevB A53 at 142933 MHz
> 
> Model: Freescale i.MX8QM MEK
> Board: iMX8QM MEK
> Build: SCFW 9330215b
> Boot:  SD1
> DRAM:  6 GiB
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1
> Loading Environment from MMC... *** Warning - bad CRC, using default
> environment
> 
> In:    serial at 5a060000
> Out:   serial at 5a060000
> Err:   serial at 5a060000
> Net:
> Error: ethernet at 5b040000 address not set.
> eth-1: ethernet at 5b040000
> Hit any key to stop autoboot:  0
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/dts/Makefile                   |   4 +-
>  arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 112 +++++++++++++++++++
>  arch/arm/dts/fsl-imx8qm-mek.dts         | 184
> ++++++++++++++++++++++++++++++++
>  arch/arm/mach-imx/imx8/Kconfig          |   6 ++
>  board/freescale/imx8qm_mek/Kconfig      |  14 +++
>  board/freescale/imx8qm_mek/MAINTAINERS  |   6 ++
>  board/freescale/imx8qm_mek/Makefile     |   8 ++
>  board/freescale/imx8qm_mek/README       |  57 ++++++++++
>  board/freescale/imx8qm_mek/imx8qm_mek.c | 157
> +++++++++++++++++++++++++++
> board/freescale/imx8qm_mek/imximage.cfg |  19 ++++
>  board/freescale/imx8qm_mek/spl.c        |  75 +++++++++++++
>  configs/imx8qm_mek_defconfig            |  75 +++++++++++++
>  include/configs/imx8qm_mek.h            | 176
> ++++++++++++++++++++++++++++++
>  13 files changed, 892 insertions(+), 1 deletion(-)  create mode 100644
> arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
>  create mode 100644 arch/arm/dts/fsl-imx8qm-mek.dts  create mode
> 100644 board/freescale/imx8qm_mek/Kconfig
>  create mode 100644 board/freescale/imx8qm_mek/MAINTAINERS
>  create mode 100644 board/freescale/imx8qm_mek/Makefile
>  create mode 100644 board/freescale/imx8qm_mek/README  create mode
> 100644 board/freescale/imx8qm_mek/imx8qm_mek.c
>  create mode 100644 board/freescale/imx8qm_mek/imximage.cfg
>  create mode 100644 board/freescale/imx8qm_mek/spl.c  create mode
> 100644 configs/imx8qm_mek_defconfig  create mode 100644
> include/configs/imx8qm_mek.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> 2a040b20a5..954d595391 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -486,7 +486,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
> 
>  dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
> 
> -dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
> +dtb-$(CONFIG_ARCH_IMX8) += \
> +	fsl-imx8qxp-mek.dtb \
> +	fsl-imx8qm-mek.dtb \
> 
>  dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
> 
> diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
> b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
> new file mode 100644
> index 0000000000..5d50eb028e
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
> @@ -0,0 +1,112 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +&mu {
> +	u-boot,dm-spl;
> +};
> +
> +&clk {
> +	u-boot,dm-spl;
> +};
> +
> +&iomuxc {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio0 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio1 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio2 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio3 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio4 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio5 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio6 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio7 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_conn {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_conn_sdch0 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_conn_sdch1 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_conn_sdch2 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio0 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio1 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio2 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio3 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio4 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio5 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio6 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio7 {
> +	u-boot,dm-spl;
> +};
> +
> +&lpuart0 {
> +	u-boot,dm-spl;
> +};
> +
> +&usdhc1 {
> +	u-boot,dm-spl;
> +};
> +
> +&usdhc2 {
> +	u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts
> b/arch/arm/dts/fsl-imx8qm-mek.dts new file mode 100644 index
> 0000000000..63908ba6bf
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8qm-mek.dts
> @@ -0,0 +1,184 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2017-2018 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "fsl-imx8qm.dtsi"
> +#include "fsl-imx8qm-mek-u-boot.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX8QM MEK";
> +	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
> +
> +	chosen {
> +		bootargs = "console=ttyLP0,115200
> earlycon=lpuart32,0x5a060000,115200";
> +		stdout-path = &lpuart0;
> +	};
> +
> +	reg_usdhc2_vmmc: usdhc2_vmmc {
> +		compatible = "regulator-fixed";
> +		regulator-name = "sw-3p3-sd1";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
> +		off-on-delay = <4800>;
> +		enable-active-high;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog>;
> +
> +	imx8qm-mek {
> +		pinctrl_hog: hoggrp {
> +			fsl,pins = <
> +				SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0
> 	0x0600004c
> +				SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25	0x0600004c
> +				SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31	0x0600004c
> +			>;
> +		};
> +
> +		pinctrl_fec1: fec1grp {
> +			fsl,pins = <
> +				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD
> 	0x000014a0
> +				SC_P_ENET0_MDC_CONN_ENET0_MDC
> 	0x06000020
> +				SC_P_ENET0_MDIO_CONN_ENET0_MDIO
> 	0x06000020
> +
> 	SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL
> 	0x00000061
> +				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC
> 	0x00000061
> +				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0
> 	0x00000061
> +				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1
> 	0x00000061
> +				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2
> 	0x00000061
> +				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3
> 	0x00000061
> +				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC
> 	0x00000061
> +
> 	SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL
> 	0x00000061
> +				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0
> 	0x00000061
> +				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1
> 	0x00000061
> +				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2
> 	0x00000061
> +				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3
> 	0x00000061
> +			>;
> +		};
> +
> +		pinctrl_fec2: fec2grp {
> +			fsl,pins = <
> +				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD
> 	0x000014a0
> +
> 	SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL
> 	0x00000060
> +				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC
> 	0x00000060
> +				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0
> 	0x00000060
> +				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1
> 	0x00000060
> +				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2
> 	0x00000060
> +				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3
> 	0x00000060
> +				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC
> 	0x00000060
> +
> 	SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL
> 	0x00000060
> +				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0
> 	0x00000060
> +				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1
> 	0x00000060
> +				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2
> 	0x00000060
> +				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3
> 	0x00000060
> +			>;
> +		};
> +
> +		pinctrl_lpuart0: lpuart0grp {
> +			fsl,pins = <
> +				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
> +				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
> +			>;
> +		};
> +
> +		pinctrl_usdhc1: usdhc1grp {
> +			fsl,pins = <
> +				SC_P_EMMC0_CLK_CONN_EMMC0_CLK
> 	0x06000041
> +				SC_P_EMMC0_CMD_CONN_EMMC0_CMD
> 	0x00000021
> +				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0
> 	0x00000021
> +				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1
> 	0x00000021
> +				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2
> 	0x00000021
> +				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3
> 	0x00000021
> +				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4
> 	0x00000021
> +				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5
> 	0x00000021
> +				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6
> 	0x00000021
> +				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7
> 	0x00000021
> +				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE
> 	0x00000041
> +				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B
> 	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc2_gpio: usdhc2grpgpio {
> +			fsl,pins = <
> +				SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021
> +				SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021
> +				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07
> 	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc2: usdhc2grp {
> +			fsl,pins = <
> +				SC_P_USDHC1_CLK_CONN_USDHC1_CLK
> 	0x06000041
> +				SC_P_USDHC1_CMD_CONN_USDHC1_CMD
> 	0x00000021
> +				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0
> 	0x00000021
> +				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1
> 	0x00000021
> +				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2
> 	0x00000021
> +				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3
> 	0x00000021
> +				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT
> 	0x00000021
> +			>;
> +		};
> +	};
> +};
> +
> +&usdhc1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc1>;
> +	bus-width = <8>;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +&usdhc2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	bus-width = <4>;
> +	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
> +	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
> +	vmmc-supply = <&reg_usdhc2_vmmc>;
> +	status = "okay";
> +};
> +
> +&fec1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec1>;
> +	phy-mode = "rgmii-txid";
> +	phy-handle = <&ethphy0>;
> +	fsl,magic-packet;
> +	fsl,rgmii_rxc_dly;
> +	status = "okay";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy0: ethernet-phy at 0 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <0>;
> +			at803x,eee-disabled;
> +			at803x,vddio-1p8v;
> +		};
> +
> +		ethphy1: ethernet-phy at 1 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <1>;
> +			at803x,eee-disabled;
> +			at803x,vddio-1p8v;
> +			status = "disabled";
> +		};
> +	};
> +};
> +
> +&lpuart0 { /* console */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpuart0>;
> +	status = "okay";
> +};
> +
> +&gpio1 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/mach-imx/imx8/Kconfig
> b/arch/arm/mach-imx/imx8/Kconfig index 4336a8c236..c32f7dbb61 100644
> --- a/arch/arm/mach-imx/imx8/Kconfig
> +++ b/arch/arm/mach-imx/imx8/Kconfig
> @@ -32,8 +32,14 @@ config TARGET_IMX8QXP_MEK
>  	select BOARD_LATE_INIT
>  	select IMX8QXP
> 
> +config TARGET_IMX8QM_MEK
> +	bool "Support i.MX8QM MEK board"
> +	select BOARD_LATE_INIT
> +	select IMX8QM
> +
>  endchoice
> 
>  source "board/freescale/imx8qxp_mek/Kconfig"
> +source "board/freescale/imx8qm_mek/Kconfig"
> 
>  endif
> diff --git a/board/freescale/imx8qm_mek/Kconfig
> b/board/freescale/imx8qm_mek/Kconfig
> new file mode 100644
> index 0000000000..93d7d5f9c5
> --- /dev/null
> +++ b/board/freescale/imx8qm_mek/Kconfig
> @@ -0,0 +1,14 @@
> +if TARGET_IMX8QM_MEK
> +
> +config SYS_BOARD
> +	default "imx8qm_mek"
> +
> +config SYS_VENDOR
> +	default "freescale"
> +
> +config SYS_CONFIG_NAME
> +	default "imx8qm_mek"
> +
> +source "board/freescale/common/Kconfig"
> +
> +endif
> diff --git a/board/freescale/imx8qm_mek/MAINTAINERS
> b/board/freescale/imx8qm_mek/MAINTAINERS
> new file mode 100644
> index 0000000000..115830df19
> --- /dev/null
> +++ b/board/freescale/imx8qm_mek/MAINTAINERS
> @@ -0,0 +1,6 @@
> +i.MX8QM MEK BOARD
> +M:	Peng Fan <peng.fan@nxp.com>
> +S:	Maintained
> +F:	board/freescale/imx8qm_mek/
> +F:	include/configs/imx8qm_mek.h
> +F:	configs/imx8qm_mek_defconfig
> diff --git a/board/freescale/imx8qm_mek/Makefile
> b/board/freescale/imx8qm_mek/Makefile
> new file mode 100644
> index 0000000000..bc9a1260bd
> --- /dev/null
> +++ b/board/freescale/imx8qm_mek/Makefile
> @@ -0,0 +1,8 @@
> +#
> +# Copyright 2018 NXP
> +#
> +# SPDX-License-Identifier:	GPL-2.0+
> +#
> +
> +obj-y += imx8qm_mek.o
> +obj-$(CONFIG_SPL_BUILD) += spl.o
> diff --git a/board/freescale/imx8qm_mek/README
> b/board/freescale/imx8qm_mek/README
> new file mode 100644
> index 0000000000..c3523801ae
> --- /dev/null
> +++ b/board/freescale/imx8qm_mek/README
> @@ -0,0 +1,57 @@
> +U-Boot for the NXP i.MX8QM EVK board
> +
> +Quick Start
> +===========
> +
> +- Build the ARM Trusted firmware binary
> +- Get scfw_tcm.bin and ahab-container.img
> +- Build U-Boot
> +- Flash the binary into the SD card
> +- Boot
> +
> +Get and Build the ARM Trusted firmware
> +======================================
> +
> +$ git clone https://source.codeaurora.org/external/imx/imx-atf
> +$ cd imx-atf/
> +$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga $
> +make PLAT=imx8qm bl31
> +
> +Get scfw_tcm.bin and ahab-container.img
> ==============================
> +
> +$ wget
> +https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
> +$ chmod +x imx-sc-firmware-1.1.bin
> +$ ./imx-sc-firmware-1.1.bin
> +$ wget
> https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
> +$ chmod +x firmware-imx-8.0.bin
> +$ ./firmware-imx-8.0.bin
> +
> +Copy the following binaries to U-Boot folder:
> +
> +$ cp imx-atf/build/imx8qm/release/bl31.bin .
> +$ cp u-boot/u-boot.bin .
> +
> +Copy the following firmwares U-Boot folder :
> +
> +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
> +$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin	.
> +
> +Build U-Boot
> +============
> +$ export ATF_LOAD_ADDR=0x80000000
> +$ export BL33_LOAD_ADDR=0x80020000
> +$ make imx8qm_mek_defconfig
> +$ make flash.bin
> +$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984
> +
> +Flash the binary into the SD card
> +=================================
> +
> +Burn the flash.bin binary to SD card offset 32KB:
> +
> +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
> +
> +Boot
> +====
> +Set Boot switch SW2: 1100.
> diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c
> b/board/freescale/imx8qm_mek/imx8qm_mek.c
> new file mode 100644
> index 0000000000..e69efc4dd6
> --- /dev/null
> +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c
> @@ -0,0 +1,157 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#include <common.h>
> +#include <errno.h>
> +#include <linux/libfdt.h>
> +#include <environment.h>
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sci/sci.h>
> +#include <asm/arch/imx8-pins.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/sys_proto.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN <<
> PADRING_CONFIG_SHIFT) | \
> +			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) |
> \
> +			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +static iomux_cfg_t uart0_pads[] = {
> +	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), };
> +
> +static void setup_iomux_uart(void)
> +{
> +	imx8_iomux_setup_multiple_pads(uart0_pads,
> ARRAY_SIZE(uart0_pads)); }
> +
> +int board_early_init_f(void)
> +{
> +	int ret;
> +	/* Set UART0 clock root to 80 MHz */
> +	sc_pm_clock_rate_t rate = 80000000;
> +
> +	/* Power up UART0 */
> +	ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0,
> SC_PM_PW_MODE_ON);
> +	if (ret)
> +		return ret;
> +
> +	ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable UART0 clock root */
> +	ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
> +	if (ret)
> +		return ret;
> +
> +	setup_iomux_uart();
> +
> +	sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5,
> SC_PM_PW_MODE_ON);
> +
> +	return 0;
> +}
> +
> +#if IS_ENABLED(CONFIG_DM_GPIO)
> +static void board_gpio_init(void)
> +{
> +	/* TODO */
> +}
> +#else
> +static inline void board_gpio_init(void) {} #endif
> +
> +#if IS_ENABLED(CONFIG_FEC_MXC)
> +#include <miiphy.h>
> +
> +int board_phy_config(struct phy_device *phydev) {
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> +	if (phydev->drv->config)
> +		phydev->drv->config(phydev);
> +
> +	return 0;
> +}
> +#endif
> +
> +void build_info(void)
> +{
> +	u32 sc_build = 0, sc_commit = 0;
> +
> +	/* Get SCFW build and commit id */
> +	sc_misc_build_info(-1, &sc_build, &sc_commit);
> +	if (!sc_build) {
> +		printf("SCFW does not support build info\n");
> +		sc_commit = 0; /* Display 0 when the build info is not supported*/
> +	}
> +	printf("Build: SCFW %x\n", sc_commit); }
> +
> +int checkboard(void)
> +{
> +	puts("Board: iMX8QM MEK\n");
> +
> +	build_info();
> +	print_bootinfo();
> +
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	/* Power up base board */
> +	sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1,
> SC_PM_PW_MODE_ON);
> +
> +	board_gpio_init();
> +
> +	return 0;
> +}
> +
> +void detail_board_ddr_info(void)
> +{
> +	puts("\nDDR    ");
> +}
> +
> +/*
> + * Board specific reset that is system reset.
> + */
> +void reset_cpu(ulong addr)
> +{
> +	/* TODO */
> +}
> +
> +#ifdef CONFIG_OF_BOARD_SETUP
> +int ft_board_setup(void *blob, bd_t *bd) {
> +	return 0;
> +}
> +#endif
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> +	return devno;
> +}
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +	env_set("board_name", "MEK");
> +	env_set("board_rev", "iMX8QM");
> +#endif
> +
> +	return 0;
> +}
> diff --git a/board/freescale/imx8qm_mek/imximage.cfg
> b/board/freescale/imx8qm_mek/imximage.cfg
> new file mode 100644
> index 0000000000..7dc6b93eb5
> --- /dev/null
> +++ b/board/freescale/imx8qm_mek/imximage.cfg
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#define __ASSEMBLY__
> +
> +/* Boot from SD, sector size 0x400 */
> +BOOT_FROM SD 0x400
> +/* SoC type IMX8QM */
> +SOC_TYPE IMX8QM
> +/* Append seco container image */
> +APPEND mx8qm-ahab-container.img
> +/* Create the 2nd container */
> +CONTAINER
> +/* Add scfw image with exec attribute */ IMAGE SCU
> +mx8qm-mek-scfw-tcm.bin
> +/* Add ATF image with exec attribute */ IMAGE A35 spl/u-boot-spl.bin
> +0x00100000
> diff --git a/board/freescale/imx8qm_mek/spl.c
> b/board/freescale/imx8qm_mek/spl.c
> new file mode 100644
> index 0000000000..95ce9f37e8
> --- /dev/null
> +++ b/board/freescale/imx8qm_mek/spl.c
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright 2018 NXP
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <spl.h>
> +#include <dm/uclass.h>
> +#include <dm/device.h>
> +#include <dm/uclass-internal.h>
> +#include <dm/device-internal.h>
> +#include <dm/lists.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void spl_board_init(void)
> +{
> +	struct udevice *dev;
> +	int offset;
> +
> +	uclass_find_first_device(UCLASS_MISC, &dev);
> +
> +	for (; dev; uclass_find_next_device(&dev)) {
> +		if (device_probe(dev))
> +			continue;
> +	}
> +
> +	offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
> "nxp,imx8-pd");
> +	while (offset != -FDT_ERR_NOTFOUND) {
> +		lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
> +			       NULL, true);
> +		offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
> +						       "nxp,imx8-pd");
> +	}
> +
> +	uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
> +
> +	for (; dev; uclass_find_next_device(&dev)) {
> +		if (device_probe(dev))
> +			continue;
> +	}
> +
> +	arch_cpu_init();
> +
> +	board_early_init_f();
> +
> +	timer_init();
> +
> +	preloader_console_init();
> +
> +	puts("Normal Boot\n");
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name) {
> +	/* Just empty function now - can't decide what to choose */
> +	debug("%s: %s\n", __func__, name);
> +
> +	return 0;
> +}
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> +	/* Clear global data */
> +	memset((void *)gd, 0, sizeof(gd_t));
> +
> +	/* Clear the BSS. */
> +	memset(__bss_start, 0, __bss_end - __bss_start);
> +
> +	board_init_r(NULL, 0);
> +}
> diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
> new file mode 100644 index 0000000000..238d44d1f5
> --- /dev/null
> +++ b/configs/imx8qm_mek_defconfig
> @@ -0,0 +1,75 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMX8=y
> +CONFIG_SYS_TEXT_BASE=0x80020000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_TARGET_IMX8QM_MEK=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_SPL=y
> +CONFIG_NR_DRAM_BANKS=3
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> +CONFIG_FIT=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_m
> ek/imximage.cfg"
> +CONFIG_BOOTDELAY=3
> +CONFIG_LOG=y
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SPL_POWER_SUPPORT=y
> +CONFIG_SPL_POWER_DOMAIN=y
> +CONFIG_SPL_WATCHDOG_SUPPORT=y
> +CONFIG_CMD_CPU=y
> +# CONFIG_CMD_IMPORTENV is not set
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_DM=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_CLK=y
> +CONFIG_CLK_IMX8=y
> +CONFIG_CPU=y
> +CONFIG_DM_GPIO=y
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_PCA953X=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_IMX_LPI2C=y
> +CONFIG_I2C_MUX=y
> +CONFIG_I2C_MUX_PCA954x=y
> +CONFIG_MISC=y
> +CONFIG_DM_MMC=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ADDR_ENABLE=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_DM_ETH=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_FEC_MXC_SHARE_MDIO=y
> +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMX8=y
> +CONFIG_POWER_DOMAIN=y
> +CONFIG_IMX8_POWER_DOMAIN=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_SPL_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_SPL_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_FSL_LPUART=y
> +CONFIG_SPL_TINY_MEMSET=y
> +# CONFIG_EFI_LOADER is not set
> diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
> new file mode 100644 index 0000000000..02c5d1c054
> --- /dev/null
> +++ b/include/configs/imx8qm_mek.h
> @@ -0,0 +1,176 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#ifndef __IMX8QM_MEK_H
> +#define __IMX8QM_MEK_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_TEXT_BASE				0x0
> +#define CONFIG_SPL_MAX_SIZE				(124 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
> 	0x800
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION		0
> +
> +#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
> +#define CONFIG_SPL_STACK		0x013E000
> +#define CONFIG_SPL_BSS_START_ADDR	0x00128000
> +#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
> +#define CONFIG_SYS_SPL_MALLOC_START	0x00120000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x3000	/* 12 KB */
> +#define CONFIG_SERIAL_LPUART_BASE	0x5a060000
> +#define CONFIG_SYS_ICACHE_OFF
> +#define CONFIG_SYS_DCACHE_OFF
> +#define CONFIG_MALLOC_F_ADDR		0x00120000
> +
> +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
> +
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> +
> +#define CONFIG_OF_EMBED
> +#endif
> +
> +#define CONFIG_REMAKE_ELF
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +/* Flat Device Tree Definitions */
> +#define CONFIG_OF_BOARD_SETUP
> +
> +#undef CONFIG_CMD_EXPORTENV
> +#undef CONFIG_CMD_IMPORTENV
> +#undef CONFIG_CMD_IMLS
> +
> +#undef CONFIG_CMD_CRC32
> +#undef CONFIG_BOOTM_NETBSD
> +
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR       0
> +#define USDHC1_BASE_ADDR                0x5B010000
> +#define USDHC2_BASE_ADDR                0x5B020000
> +#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
> +
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS		\
> +	"script=boot.scr\0" \
> +	"image=Image\0" \
> +	"panel=NULL\0" \
> +	"console=ttyLP0,${baudrate}
> earlycon=lpuart32,0x5a060000,${baudrate}\0" \
> +	"fdt_addr=0x83000000\0"			\
> +	"fdt_high=0xffffffffffffffff\0"		\
> +	"boot_fdt=try\0" \
> +	"fdt_file=fsl-imx8qxp-mek.dtb\0" \
> +	"initrd_addr=0x83800000\0"		\
> +	"initrd_high=0xffffffffffffffff\0" \
> +	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> +	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> +	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> +	"mmcautodetect=yes\0" \
> +	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
> +	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> ${script};\0" \
> +	"bootscript=echo Running bootscript from mmc ...; " \
> +		"source\0" \
> +	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> ${image}\0" \
> +	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0"
> \
> +	"mmcboot=echo Booting from mmc ...; " \
> +		"run mmcargs; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +			"if run loadfdt; then " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"else " \
> +			"echo wait for boot; " \
> +		"fi;\0" \
> +	"netargs=setenv bootargs console=${console} " \
> +		"root=/dev/nfs " \
> +		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> +	"netboot=echo Booting from net ...; " \
> +		"run netargs;  " \
> +		"if test ${ip_dyn} = yes; then " \
> +			"setenv get_cmd dhcp; " \
> +		"else " \
> +			"setenv get_cmd tftp; " \
> +		"fi; " \
> +		"${get_cmd} ${loadaddr} ${image}; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"else " \
> +			"booti; " \
> +		"fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> +	   "mmc dev ${mmcdev}; if mmc rescan; then " \
> +		   "if run loadbootscript; then " \
> +			   "run bootscript; " \
> +		   "else " \
> +			   "if run loadimage; then " \
> +				   "run mmcboot; " \
> +			   "else run netboot; " \
> +			   "fi; " \
> +		   "fi; " \
> +	   "else booti ${loadaddr} - ${fdt_addr}; fi"
> +
> +/* Link Definitions */
> +#define CONFIG_LOADADDR			0x80280000
> +
> +#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_SP_ADDR         0x80200000
> +
> +/* Default environment is in SD */
> +#define CONFIG_ENV_SIZE			0x1000
> +#define CONFIG_ENV_OFFSET		(64 * SZ_64K)
> +#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
> +
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
> +
> +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
> */
> +#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
> +#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2
> */
> +#define CONFIG_SYS_FSL_USDHC_NUM	2
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024))
> * 1024)
> +
> +#define CONFIG_SYS_SDRAM_BASE		0x80000000
> +#define PHYS_SDRAM_1			0x80000000
> +#define PHYS_SDRAM_2			0x880000000
> +#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
> +#define PHYS_SDRAM_2_SIZE		0x100000000	/* 4 GB */
> +
> +/* Serial */
> +#define CONFIG_BAUDRATE			115200
> +
> +/* Monitor Command Prompt */
> +#define CONFIG_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
> +#define CONFIG_SYS_CBSIZE              2048
> +#define CONFIG_SYS_MAXARGS             64
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> +					sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +/* Generic Timer Definitions */
> +#define COUNTER_FREQUENCY		8000000	/* 8MHz */
> +
> +/* Networking */
> +#define CONFIG_FEC_XCV_TYPE		RGMII
> +#define FEC_QUIRK_ENET_MAC
> +
> +#endif /* __IMX8QM_MEK_H */
> --
> 2.16.4

[U-Boot] [PATCH v2 00/14] colibri-imx6ull device tree enablement and driver model conversion

[Marcel Ziswiler]

This series addresses some shortcomings, enables/introduces device tree
support and converts all except video to using the driver model. This is
fully tested both running our latest downstream BSP as well as the
mainline Linux kernel.

This series is available together with my previous series addressing
Apalis and Colibri iMX6 as well as Colibri Vybrid aka VF50/VF61 on our
git server [1].

[1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next

Changes in v2:
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.

Gerard Salvatella (1):
  tdx-cfg-block: add support for new colibri iMX6ull skus

Marcel Ziswiler (9):
  colibri-imx6ull: fix ethernet phy power on
  colibri-imx6ull: configuration clean-up
  colibri-imx6ull: migrate pinctrl and regulators to dtb/dm
  colibri-imx6ull: migrate mmc to using driver model
  colibri-imx6ull: migrate usb to using driver model
  colibri-imx6ull: migrate fec to using driver model
  ARM: dts: colibri-imx6ull: fix uart-has-rtscts property
  ARM: dts: colibri-imx6ull: add osc32k_32k_out pinctrl
  ARM: dts: colibri-imx6ull: update device tree

Philippe Schenker (1):
  board: imx6ull: Add disable PMIC_STBY_REQ

Stefan Agner (3):
  tdx-cfg-block: simplify i.MX 6 module detection
  colibri-imx6ull: set module variant depending on config block
  apalis/colibri_imx6/imx6ull: make sure loadaddr does not collide

 arch/arm/dts/imx6ull-colibri.dts              | 170 ++++++++-----
 arch/arm/dts/imx6ull-pinfunc.h                |  26 +-
 .../toradex/colibri-imx6ull/colibri-imx6ull.c | 225 +++---------------
 board/toradex/common/tdx-cfg-block.c          |  70 ++++--
 board/toradex/common/tdx-cfg-block.h          |   3 +
 configs/colibri-imx6ull_defconfig             |  18 +-
 include/configs/apalis_imx6.h                 |   4 +-
 include/configs/colibri-imx6ull.h             |  14 +-
 include/configs/colibri_imx6.h                |   4 +-
 9 files changed, 227 insertions(+), 307 deletions(-)

-- 
2.20.1

[U-Boot] [PATCH v2 01/14] tdx-cfg-block: add support for new colibri iMX6ull skus

[Marcel Ziswiler]

From: Gerard Salvatella <gerard.salvatella@toradex.com>

Add support for new Colibri iMX6ULL SKUs.

While at it also checkpatch fix the whole files.

Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 board/toradex/common/tdx-cfg-block.c | 62 +++++++++++++++++++++-------
 board/toradex/common/tdx-cfg-block.h |  3 ++
 2 files changed, 50 insertions(+), 15 deletions(-)

diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index b90077bedc..3b73421243 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (c) 2016 Toradex, Inc.
+ * Copyright (c) 2016-2019 Toradex, Inc.
  */
 
 #include <common.h>
@@ -98,6 +98,9 @@ const char * const toradex_modules[] = {
 	[40] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth IT",
 	[41] = "Colibri iMX7 Dual 512MB EPDC",
 	[42] = "Apalis TK1 4GB",
+	[43] = "Colibri T20 512MB IT SETEK",
+	[44] = "Colibri iMX6ULL 512MB IT",
+	[45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth",
 };
 
 #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
@@ -299,22 +302,47 @@ static int get_cfgblock_interactive(void)
 			else
 				tdx_hw_tag.prodid = APALIS_IMX6D;
 #else
-		if (it == 'y' || it == 'Y')
-			if (is_cpu_type(MXC_CPU_MX6DL))
+		char wb = 'n';
+
+		if (it == 'y' || it == 'Y') {
+			if (is_cpu_type(MXC_CPU_MX6DL)) {
 				tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT;
-			else
+			} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 				tdx_hw_tag.prodid = COLIBRI_IMX6S_IT;
-		else
-			if (is_cpu_type(MXC_CPU_MX6DL))
+			} else {
+				sprintf(message, "Does the module have WiFi /" \
+						 " Bluetooth? [y/N] ");
+				len = cli_readline(message);
+				wb = console_buffer[0];
+				if (wb == 'y' || wb == 'Y')
+					tdx_hw_tag.prodid =
+						COLIBRI_IMX6ULL_WIFI_BT_IT;
+				else
+					tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
+			}
+		} else {
+			if (is_cpu_type(MXC_CPU_MX6DL)) {
 				tdx_hw_tag.prodid = COLIBRI_IMX6DL;
-			else
+			} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 				tdx_hw_tag.prodid = COLIBRI_IMX6S;
+			} else {
+				sprintf(message, "Does the module have WiFi /" \
+						 " Bluetooth? [y/N] ");
+				len = cli_readline(message);
+				wb = console_buffer[0];
+				if (wb == 'y' || wb == 'Y')
+					tdx_hw_tag.prodid =
+						COLIBRI_IMX6ULL_WIFI_BT;
+				else
+					tdx_hw_tag.prodid = COLIBRI_IMX6ULL;
+			}
+		}
 #endif /* CONFIG_MACH_TYPE */
-	} else if (!strcmp("imx7d", soc)) {
+	} else if (!strcmp("imx7d", soc))
 		tdx_hw_tag.prodid = COLIBRI_IMX7D;
-	} else if (!strcmp("imx7s", soc)) {
+	else if (!strcmp("imx7s", soc))
 		tdx_hw_tag.prodid = COLIBRI_IMX7S;
-	} else if (!strcmp("tegra20", soc)) {
+	else if (!strcmp("tegra20", soc)) {
 		if (it == 'y' || it == 'Y')
 			if (gd->ram_size == 0x10000000)
 				tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT;
@@ -330,8 +358,9 @@ static int get_cfgblock_interactive(void)
 			tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ;
 		else
 			tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ;
+	}
 #ifdef CONFIG_MACH_TYPE
-	} else if (!strcmp("tegra30", soc)) {
+	else if (!strcmp("tegra30", soc)) {
 		if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) {
 			if (it == 'y' || it == 'Y')
 				tdx_hw_tag.prodid = APALIS_T30_IT;
@@ -346,8 +375,9 @@ static int get_cfgblock_interactive(void)
 			else
 				tdx_hw_tag.prodid = COLIBRI_T30;
 		}
+	}
 #endif /* CONFIG_MACH_TYPE */
-	} else if (!strcmp("tegra124", soc)) {
+	else if (!strcmp("tegra124", soc)) {
 		tdx_hw_tag.prodid = APALIS_TK1_2GB;
 	} else if (!strcmp("vf500", soc)) {
 		if (it == 'y' || it == 'Y')
@@ -373,7 +403,7 @@ static int get_cfgblock_interactive(void)
 	tdx_hw_tag.ver_minor = console_buffer[2] - '0';
 	tdx_hw_tag.ver_assembly = console_buffer[3] - 'A';
 
-	if (cpu_is_pxa27x() && (tdx_hw_tag.ver_major == 1))
+	if (cpu_is_pxa27x() && tdx_hw_tag.ver_major == 1)
 		tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ -
 				       COLIBRI_PXA270_V1_312MHZ);
 
@@ -441,7 +471,8 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc,
 		 * On NAND devices, recreation is only allowed if the page is
 		 * empty (config block invalid...)
 		 */
-		printf("NAND erase block %d need to be erased before creating a Toradex config block\n",
+		printf("NAND erase block %d need to be erased before creating" \
+		       " a Toradex config block\n",
 		       CONFIG_TDX_CFG_BLOCK_OFFSET /
 		       get_nand_dev_by_index(0)->erasesize);
 		goto out;
@@ -450,7 +481,8 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc,
 		 * On NOR devices, recreation is only allowed if the sector is
 		 * empty and write protection is off (config block invalid...)
 		 */
-		printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n",
+		printf("NOR sector at offset 0x%02x need to be erased and " \
+		       "unprotected before creating a Toradex config block\n",
 		       CONFIG_TDX_CFG_BLOCK_OFFSET);
 		goto out;
 #else
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index da60e789a7..961bb4394f 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -61,6 +61,9 @@ enum {
 	COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */
 	COLIBRI_IMX7D_EPDC,
 	APALIS_TK1_4GB,
+	COLIBRI_T20_512MB_IT_SETEK,
+	COLIBRI_IMX6ULL_IT,
+	COLIBRI_IMX6ULL_WIFI_BT, /* 45 */
 };
 
 extern const char * const toradex_modules[];
-- 
2.20.1

[U-Boot] [PATCH v2 02/14] tdx-cfg-block: simplify i.MX 6 module detection

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Use CONFIG_TARGET_... at compile time to differentiate between
Apalis iMX6, Colibri iMX6 and Colibri iMX6ULL. Avoid code
duplication by moving question about Wi-Fi / Bluetooth before
IT/non-IT decision.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 board/toradex/common/tdx-cfg-block.c | 68 ++++++++++++++--------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index 3b73421243..71ff40cfad 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -280,6 +280,9 @@ static int get_cfgblock_interactive(void)
 	char it = 'n';
 	int len;
 
+	/* Unknown module by default */
+	tdx_hw_tag.prodid = 0;
+
 	if (cpu_is_pxa27x())
 		sprintf(message, "Is the module the 312 MHz version? [y/N] ");
 	else
@@ -290,54 +293,49 @@ static int get_cfgblock_interactive(void)
 
 	soc = env_get("soc");
 	if (!strcmp("mx6", soc)) {
-#ifdef CONFIG_MACH_TYPE
-		if (it == 'y' || it == 'Y')
+#ifdef CONFIG_TARGET_APALIS_IMX6
+		if (it == 'y' || it == 'Y') {
 			if (is_cpu_type(MXC_CPU_MX6Q))
 				tdx_hw_tag.prodid = APALIS_IMX6Q_IT;
 			else
 				tdx_hw_tag.prodid = APALIS_IMX6D_IT;
-		else
+		} else {
 			if (is_cpu_type(MXC_CPU_MX6Q))
 				tdx_hw_tag.prodid = APALIS_IMX6Q;
 			else
 				tdx_hw_tag.prodid = APALIS_IMX6D;
-#else
-		char wb = 'n';
-
+		}
+#elif CONFIG_TARGET_COLIBRI_IMX6
 		if (it == 'y' || it == 'Y') {
-			if (is_cpu_type(MXC_CPU_MX6DL)) {
+			if (is_cpu_type(MXC_CPU_MX6DL))
 				tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT;
-			} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+			else if (is_cpu_type(MXC_CPU_MX6SOLO))
 				tdx_hw_tag.prodid = COLIBRI_IMX6S_IT;
-			} else {
-				sprintf(message, "Does the module have WiFi /" \
-						 " Bluetooth? [y/N] ");
-				len = cli_readline(message);
-				wb = console_buffer[0];
-				if (wb == 'y' || wb == 'Y')
-					tdx_hw_tag.prodid =
-						COLIBRI_IMX6ULL_WIFI_BT_IT;
-				else
-					tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
-			}
 		} else {
-			if (is_cpu_type(MXC_CPU_MX6DL)) {
+			if (is_cpu_type(MXC_CPU_MX6DL))
 				tdx_hw_tag.prodid = COLIBRI_IMX6DL;
-			} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+			else if (is_cpu_type(MXC_CPU_MX6SOLO))
 				tdx_hw_tag.prodid = COLIBRI_IMX6S;
-			} else {
-				sprintf(message, "Does the module have WiFi /" \
-						 " Bluetooth? [y/N] ");
-				len = cli_readline(message);
-				wb = console_buffer[0];
-				if (wb == 'y' || wb == 'Y')
-					tdx_hw_tag.prodid =
-						COLIBRI_IMX6ULL_WIFI_BT;
-				else
-					tdx_hw_tag.prodid = COLIBRI_IMX6ULL;
-			}
 		}
-#endif /* CONFIG_MACH_TYPE */
+#elif CONFIG_TARGET_COLIBRI_IMX6ULL
+		char wb = 'n';
+
+		sprintf(message, "Does the module have Wi-Fi / Bluetooth? " \
+				 "[y/N] ");
+		len = cli_readline(message);
+		wb = console_buffer[0];
+		if (it == 'y' || it == 'Y') {
+			if (wb == 'y' || wb == 'Y')
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
+		} else {
+			if (wb == 'y' || wb == 'Y')
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL;
+		}
+#endif
 	} else if (!strcmp("imx7d", soc))
 		tdx_hw_tag.prodid = COLIBRI_IMX7D;
 	else if (!strcmp("imx7s", soc))
@@ -389,7 +387,9 @@ static int get_cfgblock_interactive(void)
 			tdx_hw_tag.prodid = COLIBRI_VF61_IT;
 		else
 			tdx_hw_tag.prodid = COLIBRI_VF61;
-	} else {
+	}
+
+	if (!tdx_hw_tag.prodid) {
 		printf("Module type not detectable due to unknown SoC\n");
 		return -1;
 	}
-- 
2.20.1

[U-Boot] [PATCH v2 03/14] colibri-imx6ull: set module variant depending on config block

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Using CPU temperature grading as a discriminator if the Wi-Fi /
Bluetooth chip is populated is no longer possible due to upcoming
SKUs. Set variant to -wifi only if a valid config block is present
and the product id mentions a SKU with Wi-Fi / Bluetooth.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 board/toradex/colibri-imx6ull/colibri-imx6ull.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index fcb49a0718..fe60b8e870 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -29,6 +29,7 @@
 #include <usb.h>
 #include <usb/ehci-ci.h>
 #include "../common/tdx-common.h"
+#include "../common/tdx-cfg-block.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -317,10 +318,15 @@ static const struct boot_mode board_boot_modes[] = {
 
 int board_late_init(void)
 {
-	int minc, maxc;
-
-	if (get_cpu_temp_grade(&minc, &maxc) != TEMP_COMMERCIAL)
+#ifdef CONFIG_TDX_CFG_BLOCK
+	/*
+	 * If we have a valid config block and it says we are a module with
+	 * Wi-Fi/Bluetooth make sure we use the -wifi device tree.
+	 */
+	if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT ||
+	    tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT)
 		env_set("variant", "-wifi");
+#endif
 
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
-- 
2.20.1

[U-Boot] [PATCH v2 04/14] apalis/colibri_imx6/imx6ull: make sure loadaddr does not collide

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Currently $loadaddr and $fdt_addr_r point to the same address. This
might be not ideal for some distro boot scripts which make use of
$loadaddr after loading the device tree.

Make sure the two variables point to two different addresses. Moving
$loadaddr is not entirly trivial since it is defined in mx6_common.h.
Move $fdt_addr_r and $ramdisk_addr_r by 1MiB, which should be enough
for scripts.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 include/configs/apalis_imx6.h     | 4 ++--
 include/configs/colibri-imx6ull.h | 4 ++--
 include/configs/colibri_imx6.h    | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 96169f55f0..91054d8c05 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -138,12 +138,12 @@
 
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0x20000000\0" \
-	"fdt_addr_r=0x12000000\0" \
+	"fdt_addr_r=0x12100000\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"kernel_addr_r=0x11000000\0" \
 	"pxefile_addr_r=0x17100000\0" \
-	"ramdisk_addr_r=0x12100000\0" \
+	"ramdisk_addr_r=0x12200000\0" \
 	"scriptaddr=0x17000000\0"
 
 #define NFS_BOOTCMD \
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index 7cf550cf9e..31248b14a1 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -48,12 +48,12 @@
 
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0x10000000\0" \
-	"fdt_addr_r=0x82000000\0" \
+	"fdt_addr_r=0x82100000\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"kernel_addr_r=0x81000000\0" \
 	"pxefile_addr_r=0x87100000\0" \
-	"ramdisk_addr_r=0x82100000\0" \
+	"ramdisk_addr_r=0x82200000\0" \
 	"scriptaddr=0x87000000\0"
 
 #define NFS_BOOTCMD \
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 803c9be064..fecea95d32 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -128,12 +128,12 @@
 
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0x10000000\0" \
-	"fdt_addr_r=0x12000000\0" \
+	"fdt_addr_r=0x12100000\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"kernel_addr_r=0x11000000\0" \
 	"pxefile_addr_r=0x17100000\0" \
-	"ramdisk_addr_r=0x12100000\0" \
+	"ramdisk_addr_r=0x12200000\0" \
 	"scriptaddr=0x17000000\0"
 
 #define NFS_BOOTCMD \
-- 
2.20.1

[U-Boot] [PATCH v2 05/14] colibri-imx6ull: fix ethernet phy power on

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Just give the new Ethernet PHY power save mode circuitry time to settle.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>

---

Changes in v2: None

 board/toradex/colibri-imx6ull/colibri-imx6ull.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index fe60b8e870..b6f45edb86 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -263,6 +263,9 @@ static int setup_fec(void)
 			IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
 			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 
+	/* give new Ethernet PHY power save mode circuitry time to settle */
+	mdelay(300);
+
 	return 0;
 }
 
-- 
2.20.1

[U-Boot] [PATCH v2 06/14] board: imx6ull: Add disable PMIC_STBY_REQ

[Marcel Ziswiler]

From: Philippe Schenker <philippe.schenker@toradex.com>

Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the
SOC to request for a lower voltage during sleep. This is necessary
because the voltage is changing too slow for the SOC to wake up
properly.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 board/toradex/colibri-imx6ull/colibri-imx6ull.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index b6f45edb86..f1d5cc6655 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -50,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
 		PAD_CTL_DSE_48ohm)
 
+#define MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR 0x2290040
+
 #define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
 
 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
@@ -331,6 +333,14 @@ int board_late_init(void)
 		env_set("variant", "-wifi");
 #endif
 
+	/*
+	 * Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the
+	 * SOC to request for a lower voltage during sleep. This is necessary
+	 * because the voltage is changing too slow for the SOC to wake up
+	 * properly.
+	 */
+	__raw_writel(0x8080, MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR);
+
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
-- 
2.20.1

[U-Boot] [PATCH v2 07/14] colibri-imx6ull: configuration clean-up

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Drop disabling SPL_SYS_THUMB_BUILD as we anyway do not use SPL.
Enbale CRC32 verify, USB SDP and EFI loader support.
Drop CMD_GPT and disabling RANDOM_UUID.
Do savedefconfig which drops USB_FUNCTION_SDP.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 configs/colibri-imx6ull_defconfig | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index dfe6ec1ce7..b19b3b7fb2 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
-# CONFIG_SPL_SYS_THUMB_BUILD is not set
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_COLIBRI_IMX6ULL=y
@@ -18,19 +17,20 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
+# CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_ASKENV=y
+CONFIG_CRC32_VERIFY=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_NAND_TORTURE=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
@@ -73,8 +73,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_SDP=y
 CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_FDT_FIXUP_PARTITIONS=y
-# CONFIG_EFI_LOADER is not set
-- 
2.20.1

[U-Boot] [PATCH v2 08/14] colibri-imx6ull: migrate pinctrl and regulators to dtb/dm

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate pinctrl and regulators to device tree resp. driver model:
Ethernet, NAND and UART.
Drop BOARD_EARLY_INIT_F as it is anyway no longer used.
Enable CMD_DM, CMD_MTD, CMD_REGULATOR and DM_REGULATOR_FIXED.
While at it also update copyright period.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 .../toradex/colibri-imx6ull/colibri-imx6ull.c | 82 ++-----------------
 configs/colibri-imx6ull_defconfig             |  5 +-
 2 files changed, 10 insertions(+), 77 deletions(-)

diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index f1d5cc6655..8493b1dfdd 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -1,8 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2018 Toradex AG
+ * Copyright (C) 2018-2019 Toradex AG
  */
 #include <common.h>
+
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/imx-regs.h>
@@ -14,7 +15,6 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/io.h>
-#include <common.h>
 #include <dm.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <fdt_support.h>
@@ -28,25 +28,16 @@
 #include <netdev.h>
 #include <usb.h>
 #include <usb/ehci-ci.h>
+
 #include "../common/tdx-common.h"
 #include "../common/tdx-cfg-block.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-#define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_40ohm)
-
-#define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm)
-
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
 		PAD_CTL_DSE_48ohm)
 
@@ -65,13 +56,6 @@ int dram_init(void)
 	return 0;
 }
 
-static iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_UART1_TX_DATA__UART1_DTE_RX	| MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_UART1_RX_DATA__UART1_DTE_TX	| MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_UART1_RTS_B__UART1_DTE_CTS	| MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_UART1_CTS_B__UART1_DTE_RTS	| MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 #ifdef CONFIG_FSL_ESDHC
 static iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_SD1_CLK__USDHC1_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -90,31 +74,12 @@ static iomux_v3_cfg_t const usb_cdet_pads[] = {
 };
 
 #ifdef CONFIG_NAND_MXS
-static iomux_v3_cfg_t const gpmi_pads[] = {
-	MX6_PAD_NAND_DATA00__RAWNAND_DATA00	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA01__RAWNAND_DATA01	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA02__RAWNAND_DATA02	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA03__RAWNAND_DATA03	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA04__RAWNAND_DATA04	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_RE_B__RAWNAND_RE_B		| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_WE_B__RAWNAND_WE_B		| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_READY_B__RAWNAND_READY_B	| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
-};
-
 static void setup_gpmi_nand(void)
 {
-	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
-
 	setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
 			  (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
 }
-#endif
+#endif /* CONFIG_NAND_MXS */
 
 #ifdef CONFIG_VIDEO_MXS
 static iomux_v3_cfg_t const lcd_pads[] = {
@@ -170,31 +135,6 @@ static int setup_lcd(void)
 }
 #endif
 
-#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const fec2_pads[] = {
-	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2		| MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
-	MX6_PAD_GPIO1_IO06__ENET2_MDIO			| MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
-	MX6_PAD_GPIO1_IO07__ENET2_MDC			| MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
-	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00		| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01		| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER		| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN		| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_fec(void)
-{
-	imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
-}
-#endif
-
-static void setup_iomux_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
 #ifdef CONFIG_FSL_ESDHC
 
 #define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 0)
@@ -247,20 +187,17 @@ int board_mmc_init(bd_t *bis)
 #endif
 
 #ifdef CONFIG_FEC_MXC
-
 static int setup_fec(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int ret;
 
-	setup_iomux_fec();
-
 	/* provide the PHY clock from the i.MX 6 */
 	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
 	if (ret)
 		return ret;
 
-	/* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */
+	/* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */
 	clrsetbits_le32(&iomuxc_regs->gpr[1],
 			IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
 			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
@@ -277,14 +214,7 @@ int board_phy_config(struct phy_device *phydev)
 		phydev->drv->config(phydev);
 	return 0;
 }
-#endif
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-
-	return 0;
-}
+#endif /* CONFIG_FEC_MXC */
 
 int board_init(void)
 {
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index b19b3b7fb2..ce2c09338d 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -15,7 +15,6 @@ CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOUNCE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
@@ -24,9 +23,11 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CRC32_VERIFY=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_DFU=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_NAND_TORTURE=y
 CONFIG_CMD_USB=y
@@ -34,6 +35,7 @@ CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx6ull-bcb),1536k(u-boot1)ro,1536k(u-boot2)ro,512k(u-boot-env),-(ubi)"
@@ -63,6 +65,7 @@ CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
-- 
2.20.1

[U-Boot] [PATCH v2 09/14] colibri-imx6ull: migrate mmc to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate MMC to using driver model.
Migrate USDHC to using pinctrl.
While at it also add GPIO1_IO03__OSC32K_32K_OUT pin muxing.
While at it also update copyright period.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts              | 15 +++-
 .../toradex/colibri-imx6ull/colibri-imx6ull.c | 70 -------------------
 configs/colibri-imx6ull_defconfig             |  1 +
 include/configs/colibri-imx6ull.h             |  6 +-
 4 files changed, 17 insertions(+), 75 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 95c67be438..0d416ebd10 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2019 Toradex AG
  */
 
 /dts-v1/;
@@ -11,6 +11,10 @@
 	model = "Toradex Colibri iMX6ULL";
 	compatible = "toradex,imx6ull-colibri", "fsl,imx6ull";
 
+	aliases {
+		mmc0 = &usdhc1;
+	};
+
 	chosen {
 		stdout-path = &uart1;
 	};
@@ -190,10 +194,18 @@
 	dr_mode = "host";
 };
 
+/* Colibri MMC */
 &usdhc1 {
 	assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
 	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
 	assigned-clock-rates = <0>, <198000000>;
+	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
 };
 
 &iomuxc {
@@ -547,4 +559,3 @@
 		>;
 	};
 };
-
diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index 8493b1dfdd..c9af44e30e 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -18,11 +18,9 @@
 #include <dm.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <fdt_support.h>
-#include <fsl_esdhc.h>
 #include <imx_thermal.h>
 #include <jffs2/load_kernel.h>
 #include <linux/sizes.h>
-#include <mmc.h>
 #include <miiphy.h>
 #include <mtd_node.h>
 #include <netdev.h>
@@ -34,10 +32,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
 		PAD_CTL_DSE_48ohm)
 
@@ -56,19 +50,6 @@ int dram_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_FSL_ESDHC
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-	MX6_PAD_SD1_CLK__USDHC1_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_CMD__USDHC1_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA0__USDHC1_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA1__USDHC1_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA2__USDHC1_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA3__USDHC1_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
-	MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-#endif
-
 static iomux_v3_cfg_t const usb_cdet_pads[] = {
 	MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
@@ -135,57 +116,6 @@ static int setup_lcd(void)
 }
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
-
-#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 0)
-
-static struct fsl_esdhc_cfg usdhc_cfg[] = {
-	{USDHC1_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC1_BASE_ADDR:
-		ret = !gpio_get_value(USDHC1_CD_GPIO);
-		break;
-	}
-
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int i, ret;
-
-	/* USDHC1 is mmc0 */
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
-							 ARRAY_SIZE(usdhc1_pads));
-			gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
-			gpio_direction_input(USDHC1_CD_GPIO);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-				"(%d) than supported by the board\n", i + 1);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_FEC_MXC
 static int setup_fec(void)
 {
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index ce2c09338d..69305323f2 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -50,6 +50,7 @@ CONFIG_DFU_NAND=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_NAND=y
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index 31248b14a1..7a7a70e457 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2019 Toradex AG
  *
  * Configuration settings for the Colibri iMX6ULL module.
  *
@@ -30,7 +30,7 @@
 /* ENET1 */
 #define IMX_FEC_BASE			ENET2_BASE_ADDR
 
-/* MMC Config*/
+/* MMC Config */
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_USDHC_NUM	1
 
@@ -182,4 +182,4 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #endif
 
-#endif
+#endif /* __COLIBRI_IMX6ULL_CONFIG_H */
-- 
2.20.1

[U-Boot] [PATCH v2 10/14] colibri-imx6ull: migrate usb to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate USB to using driver model.
Add USBH_PEN GPIO regulator.
While at it also add alias e.g. as required for UMS.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts              | 24 ++++++++++
 .../toradex/colibri-imx6ull/colibri-imx6ull.c | 48 -------------------
 configs/colibri-imx6ull_defconfig             |  1 +
 3 files changed, 25 insertions(+), 48 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 0d416ebd10..91e48aab61 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -13,6 +13,7 @@
 
 	aliases {
 		mmc0 = &usdhc1;
+		usb0 = &usbotg1; /* required for ums */
 	};
 
 	chosen {
@@ -35,6 +36,13 @@
 		regulator-max-microvolt = <3300000>;
 	};
 
+	reg_5v0: regulator-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
 	reg_sd1_vmmc: regulator-sd1-vmmc {
 		compatible = "regulator-gpio";
 		gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
@@ -47,6 +55,17 @@
 		states = <1800000 0x1 3300000 0x0>;
 		vin-supply = <&reg_module_3v3>;
 	};
+
+	reg_usbh_vbus: regulator-usbh-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh_reg>;
+		regulator-name = "VCC_USB[1-4]";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
+		vin-supply = <&reg_5v0>;
+	};
 };
 
 &adc1 {
@@ -183,15 +202,20 @@
 	fsl,dte-mode;
 };
 
+/* Colibri USBC */
 &usbotg1 {
 	dr_mode = "otg";
 	srp-disable;
 	hnp-disable;
 	adp-disable;
+	status = "okay";
 };
 
+/* Colibri USBH */
 &usbotg2 {
 	dr_mode = "host";
+	vbus-supply = <&reg_usbh_vbus>;
+	status = "okay";
 };
 
 /* Colibri MMC */
diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index c9af44e30e..21addaf6ed 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -24,8 +24,6 @@
 #include <miiphy.h>
 #include <mtd_node.h>
 #include <netdev.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
 
 #include "../common/tdx-common.h"
 #include "../common/tdx-cfg-block.h"
@@ -41,8 +39,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
 
-#define USB_CDET_GPIO	IMX_GPIO_NR(7, 14)
-
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -50,10 +46,6 @@ int dram_init(void)
 	return 0;
 }
 
-static iomux_v3_cfg_t const usb_cdet_pads[] = {
-	MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
 #ifdef CONFIG_NAND_MXS
 static void setup_gpmi_nand(void)
 {
@@ -163,11 +155,6 @@ int board_init(void)
 	setup_lcd();
 #endif
 
-#ifdef CONFIG_USB_EHCI_MX6
-	imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
-	gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
-#endif
-
 	return 0;
 }
 
@@ -241,41 +228,6 @@ int ft_board_setup(void *blob, bd_t *bd)
 }
 #endif
 
-#ifdef CONFIG_USB_EHCI_MX6
-static iomux_v3_cfg_t const usb_otg2_pads[] = {
-		MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_ehci_hcd_init(int port)
-{
-	switch (port) {
-	case 0:
-		break;
-	case 1:
-		imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
-						 ARRAY_SIZE(usb_otg2_pads));
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-int board_usb_phy_mode(int port)
-{
-	switch (port) {
-	case 0:
-		if (gpio_get_value(USB_CDET_GPIO))
-			return USB_INIT_DEVICE;
-		else
-			return USB_INIT_HOST;
-	case 1:
-	default:
-		return USB_INIT_HOST;
-	}
-}
-#endif
-
 static struct mxc_serial_platdata mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART1_BASE,
 	.use_dte = 1,
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index 69305323f2..0440b4ed94 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -71,6 +71,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-- 
2.20.1

[U-Boot] [PATCH v2 11/14] colibri-imx6ull: migrate fec to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate Ethernet FEC to using driver model.
Drop PHY_MICREL_KSZ90X1 which slipped in from Apalis iMX6.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts  | 31 ++++++++++++++++---------------
 configs/colibri-imx6ull_defconfig |  3 +--
 include/configs/colibri-imx6ull.h |  4 ----
 3 files changed, 17 insertions(+), 21 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 91e48aab61..2f8865c29c 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -80,6 +80,7 @@
 	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
 };
 
+/* Ethernet */
 &fec2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet2>;
@@ -233,6 +234,21 @@
 };
 
 &iomuxc {
+	pinctrl_enet2: enet2-grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
+			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+		>;
+	};
+
 	pinctrl_gpio1: gpio1-grp {
 		fsl,pins = <
 			MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00	0x74 /* SODIMM 55 */
@@ -295,21 +311,6 @@
 		>;
 	};
 
-	pinctrl_enet2: enet2-grp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
-			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
-			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
-			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
-			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
-		>;
-	};
-
 	pinctrl_ecspi1_cs: ecspi1-cs-grp {
 		fsl,pins = <
 			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x000a0
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index 0440b4ed94..a24c87f321 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -58,9 +58,8 @@ CONFIG_NAND_MXS=y
 CONFIG_NAND_MXS_DT=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_PHYLIB=y
-CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index 7a7a70e457..fc39e807b6 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -19,10 +19,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
 
 /* Network */
-#define CONFIG_FEC_XCV_TYPE             RMII
-#define CONFIG_ETHPRIME                 "FEC"
-#define CONFIG_FEC_MXC_PHYADDR		0
-
 #define CONFIG_IP_DEFRAG
 #define CONFIG_TFTP_BLOCKSIZE		16352
 #define CONFIG_TFTP_TSIZE
-- 
2.20.1

[U-Boot] [PATCH v2 12/14] ARM: dts: colibri-imx6ull: fix uart-has-rtscts property

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Remove vendor pre-fix fsl, from uart-has-rtscts property.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 2f8865c29c..f05c72eb2c 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -182,21 +182,24 @@
 	status = "disabled";
 };
 
+/* Colibri UART_A */
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
-	fsl,uart-has-rtscts;
+	uart-has-rtscts;
 	fsl,dte-mode;
 	status = "okay";
 };
 
+/* Colibri UART_B */
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart2>;
-	fsl,uart-has-rtscts;
+	uart-has-rtscts;
 	fsl,dte-mode;
 };
 
+/* Colibri UART_C */
 &uart5 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart5>;
-- 
2.20.1

[U-Boot] [PATCH v2 13/14] ARM: dts: colibri-imx6ull: add osc32k_32k_out pinctrl

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Add GPIO1_IO03__OSC32K_32K_OUT pin muxing.
While at it also fix indentation of pinfunc header file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts |  2 ++
 arch/arm/dts/imx6ull-pinfunc.h   | 26 ++++++++++++++------------
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index f05c72eb2c..84f70deaa1 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -524,6 +524,8 @@
 			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
 			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
 			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x17059
+
+			MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT	0x14
 		>;
 	};
 };
diff --git a/arch/arm/dts/imx6ull-pinfunc.h b/arch/arm/dts/imx6ull-pinfunc.h
index fca003680b..7770ed39f6 100644
--- a/arch/arm/dts/imx6ull-pinfunc.h
+++ b/arch/arm/dts/imx6ull-pinfunc.h
@@ -14,6 +14,8 @@
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>
  */
+#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT                     0x0068 0x02f4 0x0000 0x3 0x0
+
 #define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08                    0x00E4 0x0370 0x0000 0x9 0x0
 #define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09                    0x00E8 0x0374 0x0000 0x9 0x0
 #define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10                       0x00EC 0x0378 0x0000 0x9 0x0
@@ -41,17 +43,17 @@
 #define MX6UL_PAD_LCD_DATA17__EPDC_GDSP                          0x015C 0x03E8 0x0000 0x9 0x0
 #define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1                         0x016C 0x03F8 0x0000 0x9 0x0
 
-#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2                          0x01D4 0x0460 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3                        0x01D8 0x0464 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1                         0x01DC 0x0468 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1                             0x01E0 0x046C 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK                      0x01E4 0x0470 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK                      0x01E8 0x0474 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS                          0x01EC 0x0478 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK                         0x01F0 0x047C 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS                          0x01F4 0x0480 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK                         0x01F8 0x0484 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0                        0x01FC 0x0488 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA07__ESAI_T0                             0x0200 0x048C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2                         0x01D4 0x0460 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3                       0x01D8 0x0464 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1                        0x01DC 0x0468 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1                            0x01E0 0x046C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK                     0x01E4 0x0470 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK                     0x01E8 0x0474 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS                         0x01EC 0x0478 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK                        0x01F0 0x047C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS                         0x01F4 0x0480 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK                        0x01F8 0x0484 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0                       0x01FC 0x0488 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA07__ESAI_T0                            0x0200 0x048C 0x0000 0x9 0x0
 
 #endif /* __DTS_IMX6ULL_PINFUNC_H */
-- 
2.20.1

[U-Boot] [PATCH v2 14/14] ARM: dts: colibri-imx6ull: update device tree

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Fix compatible node to use regular Toradex notation.
Annotate device tree with standard Colibri pin muxing comments.
Use open-drain I2C pin muxings.
Alphabetically re-order iomuxc nodes.
Rename 	snvs-ad7879-int-grp touch interrupt node as per Linux device tree.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts | 91 ++++++++++++++++++--------------
 1 file changed, 52 insertions(+), 39 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 84f70deaa1..4196cbdf22 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -9,7 +9,7 @@
 
 / {
 	model = "Toradex Colibri iMX6ULL";
-	compatible = "toradex,imx6ull-colibri", "fsl,imx6ull";
+	compatible = "toradex,colibri-imx6ull", "fsl,imx6ull";
 
 	aliases {
 		mmc0 = &usdhc1;
@@ -100,6 +100,7 @@
 	};
 };
 
+/* NAND */
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
@@ -110,21 +111,28 @@
 	status = "okay";
 };
 
+/*
+ * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
 &i2c1 {
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
-	scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+	sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 };
 
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
 &i2c2 {
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2>;
 	pinctrl-1 = <&pinctrl_i2c2_gpio>;
-	sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
-	scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+	sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
 	ad7879 at 2c {
@@ -150,24 +158,28 @@
 		     &pinctrl_lcdif_ctrl>;
 };
 
+/* PWM <A> */
 &pwm4 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm4>;
 	#pwm-cells = <3>;
 };
 
+/* PWM <B> */
 &pwm5 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm5>;
 	#pwm-cells = <3>;
 };
 
+/* PWM <C> */
 &pwm6 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm6>;
 	#pwm-cells = <3>;
 };
 
+/* PWM <D> */
 &pwm7 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm7>;
@@ -237,6 +249,13 @@
 };
 
 &iomuxc {
+	pinctrl_can_int: canint-grp {
+		fsl,pins = <
+			/* SODIMM 73 */
+			MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04	0X14
+		>;
+	};
+
 	pinctrl_enet2: enet2-grp {
 		fsl,pins = <
 			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
@@ -252,6 +271,33 @@
 		>;
 	};
 
+	pinctrl_ecspi1_cs: ecspi1-cs-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x000a0
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x000a0
+			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x000a0
+			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x100a0
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2-grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX	0x1b020
+			MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX	0x1b020
+		>;
+	};
+
+	pinctrl_gpio_bl_on: gpio-bl-on-grp {
+		fsl,pins = <
+			MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x000a0
+		>;
+	};
+
 	pinctrl_gpio1: gpio1-grp {
 		fsl,pins = <
 			MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00	0x74 /* SODIMM 55 */
@@ -308,39 +354,6 @@
 		>;
 	};
 
-	pinctrl_can_int: canint-grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04	0X14 /* SODIMM 73 */
-		>;
-	};
-
-	pinctrl_ecspi1_cs: ecspi1-cs-grp {
-		fsl,pins = <
-			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x000a0
-		>;
-	};
-
-	pinctrl_ecspi1: ecspi1-grp {
-		fsl,pins = <
-			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x000a0
-			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x000a0
-			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x100a0
-		>;
-	};
-
-	pinctrl_flexcan2: flexcan2-grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX	0x1b020
-			MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX	0x1b020
-		>;
-	};
-
-	pinctrl_gpio_bl_on: gpio-bl-on-grp {
-		fsl,pins = <
-			MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x000a0
-		>;
-	};
-
 	pinctrl_gpmi_nand: gpmi-nand-grp {
 		fsl,pins = <
 			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x100a9
@@ -553,7 +566,7 @@
 		>;
 	};
 
-	pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */
+	pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
 		fsl,pins = <
 			MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x1b0b0
 		>;
-- 
2.20.1

[U-Boot] [PATCH v2 0/5] colibri imx8qxp 2gb wb it v1.0b module support

[Marcel Ziswiler]

This series fixes the i.MX 8QXP SCFW API header file, adds support for
more lpuart instances, cleans-up and extends the Toradex SKU handling
and last but not least introduces support for the Toradex Colibri
iMX8QXP 2GB WB IT V1.0B module.

This series is available together with my previous series addressing
Apalis and Colibri iMX6 as well as Colibri Vybrid aka VF50/VF61 and
Colibri iMX6ULL on our git server [1].

[1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next

Changes in v2:
- Added Peng and Igor's reviewed-by.
- Added Peng and Igor's reviewed-by.
- Added Igor's reviewed-by.
- Added Igor's reviewed-by.
- Changed imx-atf git clone command to include initial branch
  information as suggested by Igor.
- Sorted board file includes alphabetically as suggested by Igor.
- Got rid of SPL configuration in legacy header file as suggested by
  Igor and the whole use of SPL on i.MX 8X anyway neither works well
  nor makes any much sense at all.

Marcel Ziswiler (5):
  misc: imx8: remove duplicates from scfw api
  arm: dts: imx8dx: add lpuart1, lpuart2, lpuart3
  board: toradex: tdx-cfg-block: clean-up sku handling
  board: toradex: tdx-cfg-block: add new skus
  board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

 arch/arm/dts/Makefile                         |   4 +-
 arch/arm/dts/fsl-imx8dx.dtsi                  |  54 +++
 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi  | 112 ++++++
 arch/arm/dts/fsl-imx8qxp-colibri.dts          | 328 ++++++++++++++++++
 arch/arm/include/asm/arch-imx8/sci/sci.h      |   4 -
 arch/arm/mach-imx/imx8/Kconfig                |   6 +
 board/toradex/colibri-imx8qxp/Kconfig         |  30 ++
 board/toradex/colibri-imx8qxp/MAINTAINERS     |   9 +
 board/toradex/colibri-imx8qxp/Makefile        |   7 +
 board/toradex/colibri-imx8qxp/README          |  66 ++++
 .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 212 +++++++++++
 board/toradex/colibri-imx8qxp/imximage.cfg    |  24 ++
 board/toradex/common/tdx-cfg-block.c          |  19 +-
 board/toradex/common/tdx-cfg-block.h          |  29 +-
 configs/colibri-imx8qxp_defconfig             |  53 +++
 include/configs/colibri-imx8qxp.h             | 214 ++++++++++++
 16 files changed, 1152 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
 create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts
 create mode 100644 board/toradex/colibri-imx8qxp/Kconfig
 create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS
 create mode 100644 board/toradex/colibri-imx8qxp/Makefile
 create mode 100644 board/toradex/colibri-imx8qxp/README
 create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
 create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg
 create mode 100644 configs/colibri-imx8qxp_defconfig
 create mode 100644 include/configs/colibri-imx8qxp.h

-- 
2.20.1

[U-Boot] [PATCH v2 1/5] misc: imx8: remove duplicates from scfw api

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Remove duplicate function declarations from the SCFW API header file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Peng and Igor's reviewed-by.

 arch/arm/include/asm/arch-imx8/sci/sci.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h
index d1621669e2..97377697f0 100644
--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
@@ -62,10 +62,6 @@ int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
 			 sc_pm_clock_rate_t *rate);
 int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
 			 sc_pm_clock_rate_t *rate);
-int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
-			 sc_pm_clock_rate_t *rate);
-int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
-			 sc_pm_clock_rate_t *rate);
 int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
 		       sc_bool_t enable, sc_bool_t autog);
 
-- 
2.20.1

[U-Boot] [PATCH v2 2/5] arm: dts: imx8dx: add lpuart1, lpuart2, lpuart3

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Add support for lpuart1, lpuart2 and lpuart3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Peng and Igor's reviewed-by.

 arch/arm/dts/fsl-imx8dx.dtsi | 54 ++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
index 3b1a2a20e3..715abb413d 100644
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -236,6 +236,21 @@
 				power-domains = <&pd_dma>;
 				wakeup-irq = <225>;
 			};
+			pd_dma_lpuart1: PD_DMA_UART1 {
+				reg = <SC_R_UART_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpuart2: PD_DMA_UART2 {
+				reg = <SC_R_UART_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpuart3: PD_DMA_UART3 {
+				reg = <SC_R_UART_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
 		};
 	};
 
@@ -402,6 +417,45 @@
 		status = "disabled";
 	};
 
+	lpuart1: serial at 5a070000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a070000 0x0 0x1000>;
+		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_UART1_CLK>,
+			 <&clk IMX8QXP_UART1_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpuart1>;
+		status = "disabled";
+	};
+
+	lpuart2: serial at 5a080000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a080000 0x0 0x1000>;
+		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_UART2_CLK>,
+			 <&clk IMX8QXP_UART2_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpuart2>;
+		status = "disabled";
+	};
+
+	lpuart3: serial at 5a090000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a090000 0x0 0x1000>;
+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_UART3_CLK>,
+			 <&clk IMX8QXP_UART3_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpuart3>;
+		status = "disabled";
+	};
+
 	usdhc1: usdhc at 5b010000 {
 		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
 		interrupt-parent = <&gic>;
-- 
2.20.1

[U-Boot] [PATCH v2 3/5] board: toradex: tdx-cfg-block: clean-up sku handling

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Clean-up handling of several SKUs.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 board/toradex/common/tdx-cfg-block.c | 12 ++++++++----
 board/toradex/common/tdx-cfg-block.h | 22 ++++++++++++----------
 2 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index 71ff40cfad..7e529afc7f 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -6,7 +6,9 @@
 #include <common.h>
 #include "tdx-cfg-block.h"
 
-#if defined(CONFIG_TARGET_APALIS_IMX6) || defined(CONFIG_TARGET_COLIBRI_IMX6)
+#if defined(CONFIG_TARGET_APALIS_IMX6) || \
+	defined(CONFIG_TARGET_COLIBRI_IMX6) || \
+	defined(CONFIG_TARGET_COLIBRI_IMX8QXP)
 #include <asm/arch/sys_proto.h>
 #else
 #define is_cpu_type(cpu) (0)
@@ -92,10 +94,10 @@ const char * const toradex_modules[] = {
 	[34] = "Apalis TK1 2GB",
 	[35] = "Apalis iMX6 Dual 1GB IT",
 	[36] = "Colibri iMX6ULL 256MB",
-	[37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / Bluetooth",
-	[38] = "Colibri iMX8X",
+	[37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT",
+	[38] = "Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT",
 	[39] = "Colibri iMX7 Dual 1GB (eMMC)",
-	[40] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth IT",
+	[40] = "Colibri iMX6ULL 512MB Wi-Fi / BT IT",
 	[41] = "Colibri iMX7 Dual 512MB EPDC",
 	[42] = "Apalis TK1 4GB",
 	[43] = "Colibri T20 512MB IT SETEK",
@@ -340,6 +342,8 @@ static int get_cfgblock_interactive(void)
 		tdx_hw_tag.prodid = COLIBRI_IMX7D;
 	else if (!strcmp("imx7s", soc))
 		tdx_hw_tag.prodid = COLIBRI_IMX7S;
+	else if (is_cpu_type(MXC_CPU_IMX8QXP))
+		tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT;
 	else if (!strcmp("tegra20", soc)) {
 		if (it == 'y' || it == 'Y')
 			if (gd->ram_size == 0x10000000)
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index 961bb4394f..b20b522e1d 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -25,42 +25,44 @@ enum {
 	COLIBRI_PXA270_V1_520MHZ,
 	COLIBRI_PXA320,
 	COLIBRI_PXA300,
-	COLIBRI_PXA310,
+	COLIBRI_PXA310, /* 5 */
 	COLIBRI_PXA320_IT,
 	COLIBRI_PXA300_XT,
 	COLIBRI_PXA270_312MHZ,
 	COLIBRI_PXA270_520MHZ,
-	COLIBRI_VF50, /* not currently on sale */
-	COLIBRI_VF61,
+	COLIBRI_VF50, /* 10 */
+	COLIBRI_VF61, /* not currently on sale */
 	COLIBRI_VF61_IT,
 	COLIBRI_VF50_IT,
 	COLIBRI_IMX6S,
-	COLIBRI_IMX6DL,
+	COLIBRI_IMX6DL, /* 15 */
 	COLIBRI_IMX6S_IT,
 	COLIBRI_IMX6DL_IT,
+	/* 18 */
+	/* 19 */
 	COLIBRI_T20_256MB = 20,
 	COLIBRI_T20_512MB,
 	COLIBRI_T20_512MB_IT,
 	COLIBRI_T30,
 	COLIBRI_T20_256MB_IT,
-	APALIS_T30_2GB,
+	APALIS_T30_2GB, /* 25 */
 	APALIS_T30_1GB,
 	APALIS_IMX6Q,
 	APALIS_IMX6Q_IT,
 	APALIS_IMX6D,
-	COLIBRI_T30_IT,
+	COLIBRI_T30_IT, /* 30 */
 	APALIS_T30_IT,
 	COLIBRI_IMX7S,
 	COLIBRI_IMX7D,
 	APALIS_TK1_2GB,
-	APALIS_IMX6D_IT,
+	APALIS_IMX6D_IT, /* 35 */
 	COLIBRI_IMX6ULL,
-	APALIS_IMX8QM, /* 37 */
-	COLIBRI_IMX8X,
+	APALIS_IMX8QM_WIFI_BT_IT,
+	COLIBRI_IMX8QXP_WIFI_BT_IT,
 	COLIBRI_IMX7D_EMMC,
 	COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */
 	COLIBRI_IMX7D_EPDC,
-	APALIS_TK1_4GB,
+	APALIS_TK1_4GB, /* not currently on sale */
 	COLIBRI_T20_512MB_IT_SETEK,
 	COLIBRI_IMX6ULL_IT,
 	COLIBRI_IMX6ULL_WIFI_BT, /* 45 */
-- 
2.20.1

[U-Boot] [PATCH v2 4/5] board: toradex: tdx-cfg-block: add new skus

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Add all the latest new SKUs:
- Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT
- Apalis iMX8 QuadMax 4GB IT
- Apalis iMX8 QuadPlus 2GB Wi-Fi / BT
- Apalis iMX8 QuadPlus 2GB",
- Colibri iMX8 QuadXPlus 2GB IT
- Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth
- Colibri iMX8 DualX 1GB

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v2:
- Added Igor's reviewed-by.

 board/toradex/common/tdx-cfg-block.c | 7 +++++++
 board/toradex/common/tdx-cfg-block.h | 7 +++++++
 2 files changed, 14 insertions(+)

diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index 7e529afc7f..f69c4433b2 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -103,6 +103,13 @@ const char * const toradex_modules[] = {
 	[43] = "Colibri T20 512MB IT SETEK",
 	[44] = "Colibri iMX6ULL 512MB IT",
 	[45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth",
+	[46] = "Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT",
+	[47] = "Apalis iMX8 QuadMax 4GB IT",
+	[48] = "Apalis iMX8 QuadPlus 2GB Wi-Fi / BT",
+	[49] = "Apalis iMX8 QuadPlus 2GB",
+	[50] = "Colibri iMX8 QuadXPlus 2GB IT",
+	[51] = "Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth",
+	[52] = "Colibri iMX8 DualX 1GB",
 };
 
 #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index b20b522e1d..bfdc8b7f70 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -66,6 +66,13 @@ enum {
 	COLIBRI_T20_512MB_IT_SETEK,
 	COLIBRI_IMX6ULL_IT,
 	COLIBRI_IMX6ULL_WIFI_BT, /* 45 */
+	APALIS_IMX8QXP_WIFI_BT_IT,
+	APALIS_IMX8QM_IT,
+	APALIS_IMX8QP_WIFI_BT,
+	APALIS_IMX8QP,
+	COLIBRI_IMX8QXP_IT, /* 50 */
+	COLIBRI_IMX8DX_WIFI_BT,
+	COLIBRI_IMX8DX,
 };
 
 extern const char * const toradex_modules[];
-- 
2.20.1

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

This commit adds initial support for the Toradex Colibri iMX8QXP 2GB WB
IT V1.0B module. Unlike the V1.0A early access samples exclusively
booting from SD card, they are now strapped to boot from eFuses which
are factory fused to properly boot from their on-module eMMC. U-Boot
supports either booting from the on-module eMMC or may be used for
recovery purpose using the universal update utility (uuu) aka mfgtools
3.0.

Functionality wise the following is known to be working:
- eMMC and MMC/SD card
- Ethernet
- GPIOs
- I2C

Unfortunately, there is no USB functionality for the i.MX 8QXP as of
yet.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

Changes in v2:
- Changed imx-atf git clone command to include initial branch
  information as suggested by Igor.
- Sorted board file includes alphabetically as suggested by Igor.
- Got rid of SPL configuration in legacy header file as suggested by
  Igor and the whole use of SPL on i.MX 8X anyway neither works well
  nor makes any much sense at all.

 arch/arm/dts/Makefile                         |   4 +-
 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi  | 112 ++++++
 arch/arm/dts/fsl-imx8qxp-colibri.dts          | 328 ++++++++++++++++++
 arch/arm/mach-imx/imx8/Kconfig                |   6 +
 board/toradex/colibri-imx8qxp/Kconfig         |  30 ++
 board/toradex/colibri-imx8qxp/MAINTAINERS     |   9 +
 board/toradex/colibri-imx8qxp/Makefile        |   7 +
 board/toradex/colibri-imx8qxp/README          |  66 ++++
 .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 212 +++++++++++
 board/toradex/colibri-imx8qxp/imximage.cfg    |  24 ++
 configs/colibri-imx8qxp_defconfig             |  53 +++
 include/configs/colibri-imx8qxp.h             | 214 ++++++++++++
 12 files changed, 1064 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
 create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts
 create mode 100644 board/toradex/colibri-imx8qxp/Kconfig
 create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS
 create mode 100644 board/toradex/colibri-imx8qxp/Makefile
 create mode 100644 board/toradex/colibri-imx8qxp/README
 create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
 create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg
 create mode 100644 configs/colibri-imx8qxp_defconfig
 create mode 100644 include/configs/colibri-imx8qxp.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 13d1d67624..2a551d42a4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -559,7 +559,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
 
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
 
-dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_IMX8) += \
+	fsl-imx8qxp-colibri.dtb \
+	fsl-imx8qxp-mek.dtb
 
 dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
 
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
new file mode 100644
index 0000000000..f8686befdf
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-spl;
+};
+
+&gpio0 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&gpio6 {
+	u-boot,dm-spl;
+};
+
+&gpio7 {
+	u-boot,dm-spl;
+};
+
+&lpuart3 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts
new file mode 100644
index 0000000000..0c20edf2cf
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+#include "fsl-imx8qxp-colibri-u-boot.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX8QXP";
+	compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";
+
+	chosen {
+		bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
+		stdout-path = &lpuart3;
+	};
+
+	reg_usbh_vbus: regulator-usbh-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh1_reg>;
+		regulator-name = "usbh_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
+
+	colibri-imx8qxp {
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
+				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
+			>;
+		};
+
+		pinctrl_lpuart3: lpuart3grp {
+			fsl,pins = <
+				SC_P_FLEXCAN2_RX_ADMA_UART3_RX	0x06000020
+				SC_P_FLEXCAN2_TX_ADMA_UART3_TX	0x06000020
+			>;
+		};
+
+		pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
+			fsl,pins = <
+				SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */
+				SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x00000020 /* CTS */
+				SC_P_SAI1_RXC_LSIO_GPIO0_IO30		0x00000020 /* RTS */
+				SC_P_CSI_RESET_LSIO_GPIO3_IO03		0x00000020 /* DSR */
+				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x00000020 /* DCD */
+				SC_P_CSI_EN_LSIO_GPIO3_IO02		0x00000020 /* RI */
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0 /* Use pads in 3.3V mode */
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0 /* Use pads in 3.3V mode */
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000061
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000061
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000061
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000061
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000061
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000061
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000061
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x00000061
+			>;
+		};
+
+		pinctrl_gpio_bl_on: gpio-bl-on {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12	0x00000040
+			>;
+		};
+
+		pinctrl_hog0: hog0grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0 /* Use pads in 3.3V mode */
+			>;
+		};
+
+		pinctrl_hog1: hog1grp {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10	0x00000020 /*  45 */
+				SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02	0x06000020 /*  65 */
+					SC_P_CSI_D07_CI_PI_D09		0x00000061
+				SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11	0x00000020 /*  69 */
+				SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13		0x00000020 /*  73 */
+				SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x00000020 /*  79 */
+					SC_P_CSI_D02_CI_PI_D04		0x00000061
+				SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03	0x06000020 /*  85 */
+					SC_P_CSI_D06_CI_PI_D08		0x00000061
+				SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x00000020 /*  95 */
+				SC_P_SAI0_RXD_LSIO_GPIO0_IO27		0x00000020 /*  97 */
+					SC_P_CSI_D03_CI_PI_D05		0x00000061
+				SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x00000020 /*  99 */
+				SC_P_SAI0_TXFS_LSIO_GPIO0_IO28		0x00000020 /* 101 */
+					SC_P_CSI_D00_CI_PI_D02		0x00000061
+				SC_P_SAI0_TXD_LSIO_GPIO0_IO25		0x00000020 /* 103 */
+					SC_P_CSI_D01_CI_PI_D03		0x00000061
+				SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x00000020 /* 105 */
+				SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20	0x00000020 /* 107 */
+				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x00000020 /* 127 */
+				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x00000020 /* 131 */
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x00000020 /* 133 */
+				SC_P_CSI_PCLK_LSIO_GPIO3_IO00		0x00000020 /*  96 */
+				SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21	0x00000020 /*  98 */
+				SC_P_SAI1_RXFS_LSIO_GPIO0_IO31		0x00000020 /* 100 */
+				SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22		0x00000020 /* 102 */
+				SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23	0x00000020 /* 104 */
+				SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24	0x00000020 /* 106 */
+			>;
+		};
+
+		pinctrl_hog2: hog2grp {
+			fsl,pins = <
+				SC_P_CSI_MCLK_LSIO_GPIO3_IO01		0x00000020 /*  75 */
+				SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14	0x00000020 /*  77 */
+				SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15	0x00000020 /*  89 */
+				SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16	0x00000020 /*  93 */
+			>;
+		};
+
+		/* Off Module I2C */
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021
+				SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021
+			>;
+		};
+
+		/*INT*/
+		pinctrl_usb3503a: usb3503a-grp {
+			fsl,pins = <
+				SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061
+			>;
+		};
+
+		pinctrl_usbc_det: usbc-det {
+			fsl,pins = <
+				SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040
+			>;
+		};
+
+		pinctrl_usbh1_reg: usbh1-reg {
+			fsl,pins = <
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000040
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09	0x06000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+	};
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&lpuart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&fec1 {
+	phy-handle = <&ethphy0>;
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy at 2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			max-speed = <100>;
+			reg = <2>;
+		};
+	};
+};
+
+&i2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	bus-width = <8>;
+	non-removable;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	status = "okay";
+};
+
+&usdhc2 {
+	bus-width = <4>;
+	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	status = "okay";
+};
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index f76a139684..feea07f135 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -22,6 +22,11 @@ choice
 	prompt "i.MX8 board select"
 	optional
 
+config TARGET_COLIBRI_IMX8QXP
+	bool "Support Colibri iMX8QXP module"
+	select BOARD_LATE_INIT
+	select IMX8QXP
+
 config TARGET_IMX8QXP_MEK
 	bool "Support i.MX8QXP MEK board"
 	select BOARD_LATE_INIT
@@ -30,5 +35,6 @@ config TARGET_IMX8QXP_MEK
 endchoice
 
 source "board/freescale/imx8qxp_mek/Kconfig"
+source "board/toradex/colibri-imx8qxp/Kconfig"
 
 endif
diff --git a/board/toradex/colibri-imx8qxp/Kconfig b/board/toradex/colibri-imx8qxp/Kconfig
new file mode 100644
index 0000000000..340fe72816
--- /dev/null
+++ b/board/toradex/colibri-imx8qxp/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_COLIBRI_IMX8QXP
+
+config SYS_BOARD
+	default "colibri-imx8qxp"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "colibri-imx8qxp"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/colibri-imx8qxp/MAINTAINERS b/board/toradex/colibri-imx8qxp/MAINTAINERS
new file mode 100644
index 0000000000..39a9eb79b7
--- /dev/null
+++ b/board/toradex/colibri-imx8qxp/MAINTAINERS
@@ -0,0 +1,9 @@
+Colibri iMX8QXP
+M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+S:	Maintained
+F:	arch/arm/dts/fsl-imx8qxp-colibri.dts
+F:	arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
+F:	board/toradex/colibri-imx8qxp/
+F:	configs/colibri-imx8qxp_defconfig
+F:	include/configs/colibri-imx8qxp.h
diff --git a/board/toradex/colibri-imx8qxp/Makefile b/board/toradex/colibri-imx8qxp/Makefile
new file mode 100644
index 0000000000..f6342e1dca
--- /dev/null
+++ b/board/toradex/colibri-imx8qxp/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2019 Toradex
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += colibri-imx8qxp.o
diff --git a/board/toradex/colibri-imx8qxp/README b/board/toradex/colibri-imx8qxp/README
new file mode 100644
index 0000000000..e68d183fe6
--- /dev/null
+++ b/board/toradex/colibri-imx8qxp/README
@@ -0,0 +1,66 @@
+U-Boot for the Toradex Colibri iMX8QXP V1.0B module
+
+Quick Start
+===========
+
+- Build the ARM trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Load U-Boot binary using uuu
+- Flash U-Boot binary into the eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware
+======================================
+
+$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
+$ cd imx-atf/
+$ make PLAT=imx8qxp bl31
+
+Get scfw_tcm.bin and ahab-container.img
+=======================================
+
+$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
+$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-tcm.bin
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin
+$ chmod +x firmware-imx-7.6.bin
+$ ./firmware-imx-7.6.bin
+
+Copy the following binaries to the U-Boot folder:
+
+$ cp imx-atf/build/imx8qxp/release/bl31.bin .
+$ cp u-boot/u-boot.bin .
+
+Copy the following firmware to the U-Boot folder:
+
+$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
+
+Build U-Boot
+============
+
+$ make colibri-imx8qxp_defconfig
+$ make u-boot-dtb.imx
+
+Load the U-Boot Binary Using UUU
+================================
+
+Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
+
+https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
+
+Put the module into USB recovery aka serial downloader mode, connect USB device
+to your host and execute uuu:
+
+sudo ./uuu u-boot/u-boot-dtb.imx
+
+Flash the U-Boot Binary into the eMMC
+=====================================
+
+Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
+
+load mmc 1:1 $loadaddr u-boot-dtb.imx
+setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+mmc dev 0 1
+mmc write ${loadaddr} 0x0 ${blkcnt}
+
+Boot
diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
new file mode 100644
index 0000000000..9aa0f096d2
--- /dev/null
+++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Toradex
+ */
+
+#include <common.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/video.h>
+#include <dm.h>
+#include <environment.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <i2c.h>
+#include <linux/libfdt.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <power-domain.h>
+#include <usb.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart3_pads[] = {
+	SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
+	/* Transceiver FORCEOFF# signal, mux to use pullup */
+	SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate;
+	sc_err_t err = 0;
+
+	/*
+	 * This works around that having only UART3 up the baudrate is 1.2M
+	 * instead of 115.2k. Set UART0 clock root to 80 MHz
+	 */
+	rate = 80000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	/* Power up UART3 */
+	err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3, SC_PM_PW_MODE_ON);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	/* Set UART3 clock root to 80 MHz */
+	rate = 80000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER, &rate);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	/* Enable UART3 clock root */
+	err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER, true, false);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#undef CONFIG_MXC_GPIO /* TODO */
+#ifdef CONFIG_MXC_GPIO
+#define IOEXP_RESET IMX_GPIO_NR(1, 1)
+
+static iomux_cfg_t board_gpios[] = {
+	SC_P_SPI2_SDO | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+	SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | \
+		MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+static void board_gpio_init(void)
+{
+	struct gpio_desc desc;
+	int ret;
+
+	ret = dm_gpio_lookup_name("gpio@1a_3", &desc);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc, "bb_per_rst_b");
+	if (ret)
+		return;
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc, 0);
+	udelay(50);
+	dm_gpio_set_value(&desc, 1);
+
+	imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
+
+	/* enable i2c port expander assert reset line */
+	gpio_request(IOEXP_RESET, "ioexp_rst");
+	gpio_direction_output(IOEXP_RESET, 1);
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+void build_info(void)
+{
+	u32 sc_build = 0, sc_commit = 0;
+
+	/* Get SCFW build and commit id */
+	sc_misc_build_info(-1, &sc_build, &sc_commit);
+	if (!sc_build) {
+		printf("SCFW does not support build info\n");
+		sc_commit = 0; /* Display 0 if build info not supported */
+	}
+	printf("Build: SCFW %x\n", sc_commit);
+}
+
+int checkboard(void)
+{
+	puts("Model: Toradex Colibri iMX8X\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	board_gpio_init();
+
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+	/* TODO */
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/* TODO move to common */
+	env_set("board_name", "Colibri iMX8QXP");
+	env_set("board_rev", "v1.0");
+#endif
+
+	return 0;
+}
diff --git a/board/toradex/colibri-imx8qxp/imximage.cfg b/board/toradex/colibri-imx8qxp/imximage.cfg
new file mode 100644
index 0000000000..ce9e66c64d
--- /dev/null
+++ b/board/toradex/colibri-imx8qxp/imximage.cfg
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Toradex
+ *
+ * Refer doc/README.imx8image for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM EMMC_FASTBOOT 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-colibri-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig
new file mode 100644
index 0000000000..d697546ed7
--- /dev/null
+++ b/configs/colibri-imx8qxp_defconfig
@@ -0,0 +1,53 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_COLIBRI_IMX8QXP=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8qxp/imximage.cfg"
+CONFIG_LOG=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_DM_THERMAL=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/colibri-imx8qxp.h b/include/configs/colibri-imx8qxp.h
new file mode 100644
index 0000000000..33cbcb44a9
--- /dev/null
+++ b/include/configs/colibri-imx8qxp.h
@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Toradex
+ */
+
+#ifndef __COLIBRI_IMX8QXP_H
+#define __COLIBRI_IMX8QXP_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define USDHC1_BASE_ADDR		0x5B010000
+#define USDHC2_BASE_ADDR		0x5B020000
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE		4096
+#define CONFIG_TFTP_TSIZE
+
+#define CONFIG_IPADDR			192.168.10.2
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_SERVERIP			192.168.10.1
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"fdt_addr_r=0x84000000\0" \
+	"kernel_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x84100000\0"
+
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
+/* Boot M4 */
+#define M4_BOOT_ENV \
+	"m4_0_image=m4_0.bin\0" \
+	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+		"${m4_0_image}\0" \
+	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+
+#define MFG_NAND_PARTITION ""
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc g_mass_storage.stall=0 " \
+		"g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \
+		"g_mass_storage.idProduct=0x37FF " \
+		"g_mass_storage.iSerialNumber=\"\" "\
+		MFG_NAND_PARTITION \
+		"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off " \
+		"clk_ignore_unused "\
+		"\0" \
+	"initrd_addr=0x83800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \
+		"${fdt_addr};\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	AHAB_ENV \
+	BOOTENV \
+	CONFIG_MFG_ENV_SETTINGS \
+	M4_BOOT_ENV \
+	MEM_LAYOUT_ENV_SETTINGS \
+	"boot_fdt=try\0" \
+	"bootscript=echo Running bootscript from mmc ...; source\0" \
+	"console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200\0" \
+	"fdt_addr=0x83000000\0"			\
+	"fdt_file=fsl-imx8qxp-colibri-eval-v3.dtb\0" \
+	"fdt_high=0xffffffffffffffff\0"		\
+	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+	"image=Image\0" \
+	"initrd_addr=0x83800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+		"${script};\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=PARTUUID=${uuid} rootwait " \
+	"mmcautodetect=yes\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run finduuid; run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
+		"nfsroot=${serverip}:${nfsroot},v3,tcp video=imxdpufb5:off " \
+		"video=imxdpufb6:off video=imxdpufb7:off\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0" \
+	"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
+		"colibri-imx8qxp/${fdt_file}; booti ${loadaddr} - " \
+		"${fdt_addr}\0" \
+	"panel=NULL\0" \
+	"script=boot.scr\0" \
+	"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
+
+#define CONFIG_SYS_MEMTEST_START	0x88000000
+#define CONFIG_SYS_MEMTEST_END		0x89000000
+
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
+					 CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		1
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* On Colibri iMX8 USDHC1 is eMMC, USDHC2 is 4-bit SD */
+#define CONFIG_SYS_MMC_ENV_DEV		0		 /* USDHC1 eMMC */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_NR_DRAM_BANKS		3
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
+#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 GB */
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
+#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */
+
+#endif /* __COLIBRI_IMX8QXP_H */
-- 
2.20.1

[U-Boot] [PATCH v2 05/14] colibri-imx6ull: fix ethernet phy power on

[Igor Opaniuk]

Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

On Tue, Apr 9, 2019 at 5:28 PM Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Just give the new Ethernet PHY power save mode circuitry time to settle.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
>
> ---
>
> Changes in v2: None
>
>  board/toradex/colibri-imx6ull/colibri-imx6ull.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
> index fe60b8e870..b6f45edb86 100644
> --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
> +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
> @@ -263,6 +263,9 @@ static int setup_fec(void)
>                         IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
>                         IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
>
> +       /* give new Ethernet PHY power save mode circuitry time to settle */
> +       mdelay(300);
> +
>         return 0;
>  }
>
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot



-- 
Best regards - Freundliche Grüsse - Meilleures salutations

Senior Development Engineer,
Igor Opaniuk

Toradex AG
Altsagenstrasse 5 | 6048 Horw/Luzern | Switzerland | T: +41 41 500 48
00 (main line)

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Igor Opaniuk]

Hi Marcel,

Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Some minor comments below (can be addressed in different patch):

On Tue, Apr 9, 2019 at 5:34 PM Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> This commit adds initial support for the Toradex Colibri iMX8QXP 2GB WB
> IT V1.0B module. Unlike the V1.0A early access samples exclusively
> booting from SD card, they are now strapped to boot from eFuses which
> are factory fused to properly boot from their on-module eMMC. U-Boot
> supports either booting from the on-module eMMC or may be used for
> recovery purpose using the universal update utility (uuu) aka mfgtools
> 3.0.
>
> Functionality wise the following is known to be working:
> - eMMC and MMC/SD card
> - Ethernet
> - GPIOs
> - I2C
>
> Unfortunately, there is no USB functionality for the i.MX 8QXP as of
> yet.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v2:
> - Changed imx-atf git clone command to include initial branch
>   information as suggested by Igor.
> - Sorted board file includes alphabetically as suggested by Igor.
> - Got rid of SPL configuration in legacy header file as suggested by
>   Igor and the whole use of SPL on i.MX 8X anyway neither works well
>   nor makes any much sense at all.
>
>  arch/arm/dts/Makefile                         |   4 +-
>  arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi  | 112 ++++++
>  arch/arm/dts/fsl-imx8qxp-colibri.dts          | 328 ++++++++++++++++++
>  arch/arm/mach-imx/imx8/Kconfig                |   6 +
>  board/toradex/colibri-imx8qxp/Kconfig         |  30 ++
>  board/toradex/colibri-imx8qxp/MAINTAINERS     |   9 +
>  board/toradex/colibri-imx8qxp/Makefile        |   7 +
>  board/toradex/colibri-imx8qxp/README          |  66 ++++
>  .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 212 +++++++++++
>  board/toradex/colibri-imx8qxp/imximage.cfg    |  24 ++
>  configs/colibri-imx8qxp_defconfig             |  53 +++
>  include/configs/colibri-imx8qxp.h             | 214 ++++++++++++
>  12 files changed, 1064 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
>  create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts
>  create mode 100644 board/toradex/colibri-imx8qxp/Kconfig
>  create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS
>  create mode 100644 board/toradex/colibri-imx8qxp/Makefile
>  create mode 100644 board/toradex/colibri-imx8qxp/README
>  create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
>  create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg
>  create mode 100644 configs/colibri-imx8qxp_defconfig
>  create mode 100644 include/configs/colibri-imx8qxp.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 13d1d67624..2a551d42a4 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -559,7 +559,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
>
>  dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
>
> -dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
> +dtb-$(CONFIG_ARCH_IMX8) += \
> +       fsl-imx8qxp-colibri.dtb \
> +       fsl-imx8qxp-mek.dtb
>
>  dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
>
> diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> new file mode 100644
> index 0000000000..f8686befdf
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> @@ -0,0 +1,112 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR X11
> +/*
> + * Copyright 2019 Toradex AG
> + */
> +
> +&mu {
> +       u-boot,dm-spl;
> +};
> +
> +&clk {
> +       u-boot,dm-spl;
> +};
> +
> +&iomuxc {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_lsio {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio0 {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio1 {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio2 {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio3 {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio4 {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio5 {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio6 {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio7 {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_conn {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_conn_sdch0 {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_conn_sdch1 {
> +       u-boot,dm-spl;
> +};
> +
> +&pd_conn_sdch2 {
> +       u-boot,dm-spl;
> +};
> +
> +&gpio0 {
> +       u-boot,dm-spl;
> +};
> +
> +&gpio1 {
> +       u-boot,dm-spl;
> +};
> +
> +&gpio2 {
> +       u-boot,dm-spl;
> +};
> +
> +&gpio3 {
> +       u-boot,dm-spl;
> +};
> +
> +&gpio4 {
> +       u-boot,dm-spl;
> +};
> +
> +&gpio5 {
> +       u-boot,dm-spl;
> +};
> +
> +&gpio6 {
> +       u-boot,dm-spl;
> +};
> +
> +&gpio7 {
> +       u-boot,dm-spl;
> +};
> +
> +&lpuart3 {
> +       u-boot,dm-spl;
> +};
> +
> +&usdhc1 {
> +       u-boot,dm-spl;
> +};
> +
> +&usdhc2 {
> +       u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts
> new file mode 100644
> index 0000000000..0c20edf2cf
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts
> @@ -0,0 +1,328 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR X11
> +/*
> + * Copyright 2019 Toradex AG
> + */
> +
> +/dts-v1/;
> +
> +#include "fsl-imx8qxp.dtsi"
> +#include "fsl-imx8qxp-colibri-u-boot.dtsi"
> +
> +/ {
> +       model = "Toradex Colibri iMX8QXP";
> +       compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";
> +
> +       chosen {
> +               bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
> +               stdout-path = &lpuart3;
> +       };
> +
> +       reg_usbh_vbus: regulator-usbh-vbus {
> +               compatible = "regulator-fixed";
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&pinctrl_usbh1_reg>;
> +               regulator-name = "usbh_vbus";
> +               regulator-min-microvolt = <5000000>;
> +               regulator-max-microvolt = <5000000>;
> +               gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
> +       };
> +};
> +
> +&iomuxc {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
> +
> +       colibri-imx8qxp {
> +               pinctrl_lpuart0: lpuart0grp {
> +                       fsl,pins = <
> +                               SC_P_UART0_RX_ADMA_UART0_RX     0x06000020
> +                               SC_P_UART0_TX_ADMA_UART0_TX     0x06000020
> +                       >;
> +               };
> +
> +               pinctrl_lpuart3: lpuart3grp {
> +                       fsl,pins = <
> +                               SC_P_FLEXCAN2_RX_ADMA_UART3_RX  0x06000020
> +                               SC_P_FLEXCAN2_TX_ADMA_UART3_TX  0x06000020
> +                       >;
> +               };
> +
> +               pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
> +                       fsl,pins = <
> +                               SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */
> +                               SC_P_SAI1_RXD_LSIO_GPIO0_IO29           0x00000020 /* CTS */
> +                               SC_P_SAI1_RXC_LSIO_GPIO0_IO30           0x00000020 /* RTS */
> +                               SC_P_CSI_RESET_LSIO_GPIO3_IO03          0x00000020 /* DSR */
> +                               SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22        0x00000020 /* DCD */
> +                               SC_P_CSI_EN_LSIO_GPIO3_IO02             0x00000020 /* RI */
> +                       >;
> +               };
> +
> +               pinctrl_fec1: fec1grp {
> +                       fsl,pins = <
> +                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD      0x000014a0 /* Use pads in 3.3V mode */
> +                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD      0x000014a0 /* Use pads in 3.3V mode */
> +                               SC_P_ENET0_MDC_CONN_ENET0_MDC                   0x06000020
> +                               SC_P_ENET0_MDIO_CONN_ENET0_MDIO                 0x06000020
> +                               SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
> +                               SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT     0x06000061
> +                               SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0     0x00000061
> +                               SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1     0x00000061
> +                               SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
> +                               SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0     0x00000061
> +                               SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1     0x00000061
> +                               SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER     0x00000061
> +                       >;
> +               };
> +
> +               pinctrl_gpio_bl_on: gpio-bl-on {
> +                       fsl,pins = <
> +                               SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12       0x00000040
> +                       >;
> +               };
> +
> +               pinctrl_hog0: hog0grp {
> +                       fsl,pins = <
> +                               SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD  0x000514a0 /* Use pads in 3.3V mode */
> +                       >;
> +               };
> +
> +               pinctrl_hog1: hog1grp {
> +                       fsl,pins = <
> +                               SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10       0x00000020 /*  45 */
> +                               SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02   0x06000020 /*  65 */
> +                                       SC_P_CSI_D07_CI_PI_D09          0x00000061
> +                               SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11       0x00000020 /*  69 */
> +                               SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13         0x00000020 /*  73 */
> +                               SC_P_SAI0_TXC_LSIO_GPIO0_IO26           0x00000020 /*  79 */
> +                                       SC_P_CSI_D02_CI_PI_D04          0x00000061
> +                               SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03    0x06000020 /*  85 */
> +                                       SC_P_CSI_D06_CI_PI_D08          0x00000061
> +                               SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17        0x00000020 /*  95 */
> +                               SC_P_SAI0_RXD_LSIO_GPIO0_IO27           0x00000020 /*  97 */
> +                                       SC_P_CSI_D03_CI_PI_D05          0x00000061
> +                               SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18       0x00000020 /*  99 */
> +                               SC_P_SAI0_TXFS_LSIO_GPIO0_IO28          0x00000020 /* 101 */
> +                                       SC_P_CSI_D00_CI_PI_D02          0x00000061
> +                               SC_P_SAI0_TXD_LSIO_GPIO0_IO25           0x00000020 /* 103 */
> +                                       SC_P_CSI_D01_CI_PI_D03          0x00000061

I seems that in 20 lines above alignment is broken a bit.

> +                               SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19       0x00000020 /* 105 */
> +                               SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20       0x00000020 /* 107 */
> +                               SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05        0x00000020 /* 127 */
> +                               SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06        0x00000020 /* 131 */
> +                               SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04        0x00000020 /* 133 */
> +                               SC_P_CSI_PCLK_LSIO_GPIO3_IO00           0x00000020 /*  96 */
> +                               SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21       0x00000020 /*  98 */
> +                               SC_P_SAI1_RXFS_LSIO_GPIO0_IO31          0x00000020 /* 100 */
> +                               SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22         0x00000020 /* 102 */
> +                               SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23       0x00000020 /* 104 */
> +                               SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24       0x00000020 /* 106 */
> +                       >;
> +               };
> +
> +               pinctrl_hog2: hog2grp {
> +                       fsl,pins = <
> +                               SC_P_CSI_MCLK_LSIO_GPIO3_IO01           0x00000020 /*  75 */
> +                               SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14       0x00000020 /*  77 */
> +                               SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15       0x00000020 /*  89 */
> +                               SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16        0x00000020 /*  93 */
> +                       >;
> +               };
> +
> +               /* Off Module I2C */
> +               pinctrl_i2c1: i2c1grp {
> +                       fsl,pins = <
> +                               SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL   0x06000021
> +                               SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA   0x06000021
> +                       >;
> +               };
> +
> +               /*INT*/
> +               pinctrl_usb3503a: usb3503a-grp {
> +                       fsl,pins = <
> +                               SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061
> +                       >;
> +               };
> +
> +               pinctrl_usbc_det: usbc-det {
> +                       fsl,pins = <
> +                               SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09      0x06000040
> +                       >;
> +               };
> +
> +               pinctrl_usbh1_reg: usbh1-reg {
> +                       fsl,pins = <
> +                               SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03        0x06000040
> +                       >;
> +               };
> +
> +               pinctrl_usdhc1: usdhc1grp {
> +                       fsl,pins = <
> +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000041
> +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD           0x00000021
> +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0       0x00000021
> +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1       0x00000021
> +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2       0x00000021
> +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3       0x00000021
> +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4       0x00000021
> +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
> +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
> +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
> +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000041
> +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000021
> +                       >;
> +               };
> +
> +               pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> +                       fsl,pins = <
> +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000041
> +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD           0x00000021
> +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0       0x00000021
> +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1       0x00000021
> +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2       0x00000021
> +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3       0x00000021
> +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4       0x00000021
> +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
> +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
> +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
> +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000041
> +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000021
> +                       >;
> +               };
> +
> +               pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> +                       fsl,pins = <
> +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000041
> +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD           0x00000021
> +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0       0x00000021
> +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1       0x00000021
> +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2       0x00000021
> +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3       0x00000021
> +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4       0x00000021
> +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
> +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
> +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
> +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000041
> +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000021
> +                       >;
> +               };
> +
> +               pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> +                       fsl,pins = <
> +                               SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09       0x06000021
> +                       >;
> +               };
> +
> +               pinctrl_usdhc2: usdhc2grp {
> +                       fsl,pins = <
> +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000041
> +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000021
> +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000021
> +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000021
> +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000021
> +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000021
> +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
> +                       >;
> +               };
> +
> +               pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> +                       fsl,pins = <
> +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000041
> +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000021
> +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000021
> +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000021
> +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000021
> +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000021
> +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
> +                       >;
> +               };
> +
> +               pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> +                       fsl,pins = <
> +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000041
> +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000021
> +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000021
> +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000021
> +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000021
> +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000021
> +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
> +                       >;
> +               };
> +       };
> +};
> +
> +&lpuart0 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_lpuart0>;
> +       status = "okay";
> +};
> +
> +&lpuart3 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
> +       status = "okay";
> +};
> +
> +&gpio0 {
> +       status = "okay";
> +};
> +
> +&gpio1 {
> +       status = "okay";
> +};
> +
> +&gpio3 {
> +       status = "okay";
> +};
> +
> +&gpio4 {
> +       status = "okay";
> +};
> +
> +&fec1 {
> +       phy-handle = <&ethphy0>;
> +       phy-mode = "rmii";
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_fec1>;
> +       status = "okay";
> +
> +       mdio {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               ethphy0: ethernet-phy at 2 {
> +                       compatible = "ethernet-phy-ieee802.3-c22";
> +                       max-speed = <100>;
> +                       reg = <2>;
> +               };
> +       };
> +};
> +
> +&i2c1 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       clock-frequency = <100000>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_i2c1>;
> +       status = "okay";
> +};
> +
> +&usdhc1 {
> +       bus-width = <8>;
> +       non-removable;
> +       pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +       pinctrl-0 = <&pinctrl_usdhc1>;
> +       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> +       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> +       status = "okay";
> +};
> +
> +&usdhc2 {
> +       bus-width = <4>;
> +       cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
> +       pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> +       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> +       status = "okay";
> +};
> diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
> index f76a139684..feea07f135 100644
> --- a/arch/arm/mach-imx/imx8/Kconfig
> +++ b/arch/arm/mach-imx/imx8/Kconfig
> @@ -22,6 +22,11 @@ choice
>         prompt "i.MX8 board select"
>         optional
>
> +config TARGET_COLIBRI_IMX8QXP
> +       bool "Support Colibri iMX8QXP module"
> +       select BOARD_LATE_INIT
> +       select IMX8QXP
> +
>  config TARGET_IMX8QXP_MEK
>         bool "Support i.MX8QXP MEK board"
>         select BOARD_LATE_INIT
> @@ -30,5 +35,6 @@ config TARGET_IMX8QXP_MEK
>  endchoice
>
>  source "board/freescale/imx8qxp_mek/Kconfig"
> +source "board/toradex/colibri-imx8qxp/Kconfig"
>
>  endif
> diff --git a/board/toradex/colibri-imx8qxp/Kconfig b/board/toradex/colibri-imx8qxp/Kconfig
> new file mode 100644
> index 0000000000..340fe72816
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/Kconfig
> @@ -0,0 +1,30 @@
> +if TARGET_COLIBRI_IMX8QXP
> +
> +config SYS_BOARD
> +       default "colibri-imx8qxp"
> +
> +config SYS_VENDOR
> +       default "toradex"
> +
> +config SYS_CONFIG_NAME
> +       default "colibri-imx8qxp"
> +
> +config TDX_CFG_BLOCK
> +       default y
> +
> +config TDX_HAVE_MMC
> +       default y
> +
> +config TDX_CFG_BLOCK_DEV
> +       default "0"
> +
> +config TDX_CFG_BLOCK_PART
> +       default "1"
> +
> +# Toradex config block in eMMC, at the end of 1st "boot sector"
> +config TDX_CFG_BLOCK_OFFSET
> +       default "-512"
> +
> +source "board/toradex/common/Kconfig"
> +
> +endif
> diff --git a/board/toradex/colibri-imx8qxp/MAINTAINERS b/board/toradex/colibri-imx8qxp/MAINTAINERS
> new file mode 100644
> index 0000000000..39a9eb79b7
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/MAINTAINERS
> @@ -0,0 +1,9 @@
> +Colibri iMX8QXP
> +M:     Marcel Ziswiler <marcel.ziswiler@toradex.com>
> +W:     http://developer.toradex.com/software/linux/linux-software
> +S:     Maintained
> +F:     arch/arm/dts/fsl-imx8qxp-colibri.dts
> +F:     arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> +F:     board/toradex/colibri-imx8qxp/
> +F:     configs/colibri-imx8qxp_defconfig
> +F:     include/configs/colibri-imx8qxp.h
> diff --git a/board/toradex/colibri-imx8qxp/Makefile b/board/toradex/colibri-imx8qxp/Makefile
> new file mode 100644
> index 0000000000..f6342e1dca
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright 2019 Toradex
> +#
> +# SPDX-License-Identifier:     GPL-2.0+

SPDX line should be in the beginning of the file.

> +#
> +
> +obj-y += colibri-imx8qxp.o
> diff --git a/board/toradex/colibri-imx8qxp/README b/board/toradex/colibri-imx8qxp/README
> new file mode 100644
> index 0000000000..e68d183fe6
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/README
> @@ -0,0 +1,66 @@
> +U-Boot for the Toradex Colibri iMX8QXP V1.0B module
> +
> +Quick Start
> +===========
> +
> +- Build the ARM trusted firmware binary
> +- Get scfw_tcm.bin and ahab-container.img
> +- Build U-Boot
> +- Load U-Boot binary using uuu
> +- Flash U-Boot binary into the eMMC
> +- Boot
> +
> +Get and Build the ARM Trusted Firmware
> +======================================
> +
> +$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
> +$ cd imx-atf/
> +$ make PLAT=imx8qxp bl31
> +
> +Get scfw_tcm.bin and ahab-container.img
> +=======================================
> +
> +$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
> +$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-tcm.bin
> +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin
> +$ chmod +x firmware-imx-7.6.bin
> +$ ./firmware-imx-7.6.bin
> +
> +Copy the following binaries to the U-Boot folder:
> +
> +$ cp imx-atf/build/imx8qxp/release/bl31.bin .
> +$ cp u-boot/u-boot.bin .
> +
> +Copy the following firmware to the U-Boot folder:
> +
> +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
> +
> +Build U-Boot
> +============
> +
> +$ make colibri-imx8qxp_defconfig
> +$ make u-boot-dtb.imx
> +
> +Load the U-Boot Binary Using UUU
> +================================
> +
> +Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
> +
> +https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
> +
> +Put the module into USB recovery aka serial downloader mode, connect USB device
> +to your host and execute uuu:
> +
> +sudo ./uuu u-boot/u-boot-dtb.imx
> +
> +Flash the U-Boot Binary into the eMMC
> +=====================================
> +
> +Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
> +
> +load mmc 1:1 $loadaddr u-boot-dtb.imx
> +setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
> +mmc dev 0 1
> +mmc write ${loadaddr} 0x0 ${blkcnt}
> +
> +Boot
> diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> new file mode 100644
> index 0000000000..9aa0f096d2
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> @@ -0,0 +1,212 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 Toradex
> + */
> +
> +#include <common.h>
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx8-pins.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/sci/sci.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/mach-imx/video.h>
> +#include <dm.h>
> +#include <environment.h>
> +#include <errno.h>
> +#include <fdt_support.h>
> +#include <fsl_esdhc.h>
> +#include <fsl_ifc.h>
> +#include <i2c.h>
> +#include <linux/libfdt.h>
> +#include <malloc.h>
> +#include <netdev.h>
> +#include <power-domain.h>
> +#include <usb.h>
> +
> +#include "../common/tdx-cfg-block.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define GPIO_PAD_CTRL  ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
> +                        (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +                        (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +                        (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define UART_PAD_CTRL  ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
> +                        (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +                        (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +                        (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +static iomux_cfg_t uart3_pads[] = {
> +       SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
> +       SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
> +       /* Transceiver FORCEOFF# signal, mux to use pullup */
> +       SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static void setup_iomux_uart(void)
> +{
> +       imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
> +}
> +
> +int board_early_init_f(void)
> +{
> +       sc_pm_clock_rate_t rate;
> +       sc_err_t err = 0;
> +
> +       /*
> +        * This works around that having only UART3 up the baudrate is 1.2M
> +        * instead of 115.2k. Set UART0 clock root to 80 MHz
> +        */
> +       rate = 80000000;
> +       err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
> +       if (err != SC_ERR_NONE)
> +               return 0;
> +
> +       /* Power up UART3 */
> +       err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3, SC_PM_PW_MODE_ON);
> +       if (err != SC_ERR_NONE)
> +               return 0;
> +
> +       /* Set UART3 clock root to 80 MHz */
> +       rate = 80000000;
> +       err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER, &rate);
> +       if (err != SC_ERR_NONE)
> +               return 0;
> +
> +       /* Enable UART3 clock root */
> +       err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER, true, false);
> +       if (err != SC_ERR_NONE)
> +               return 0;
> +
> +       setup_iomux_uart();
> +
> +       return 0;
> +}
> +
> +#undef CONFIG_MXC_GPIO /* TODO */
> +#ifdef CONFIG_MXC_GPIO
> +#define IOEXP_RESET IMX_GPIO_NR(1, 1)
> +
> +static iomux_cfg_t board_gpios[] = {
> +       SC_P_SPI2_SDO | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
> +       SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | \
> +               MUX_PAD_CTRL(GPIO_PAD_CTRL),
> +};
> +
> +static void board_gpio_init(void)
> +{
> +       struct gpio_desc desc;
> +       int ret;
> +
> +       ret = dm_gpio_lookup_name("gpio at 1a_3", &desc);
> +       if (ret)
> +               return;
> +
> +       ret = dm_gpio_request(&desc, "bb_per_rst_b");
> +       if (ret)
> +               return;
> +
> +       dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
> +       dm_gpio_set_value(&desc, 0);
> +       udelay(50);
> +       dm_gpio_set_value(&desc, 1);
> +
> +       imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
> +
> +       /* enable i2c port expander assert reset line */
> +       gpio_request(IOEXP_RESET, "ioexp_rst");
> +       gpio_direction_output(IOEXP_RESET, 1);
> +}
> +#else
> +static inline void board_gpio_init(void) {}
> +#endif
> +
> +#if IS_ENABLED(CONFIG_FEC_MXC)
> +#include <miiphy.h>
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> +       if (phydev->drv->config)
> +               phydev->drv->config(phydev);
> +
> +       return 0;
> +}
> +#endif
> +
> +void build_info(void)
> +{
> +       u32 sc_build = 0, sc_commit = 0;
> +
> +       /* Get SCFW build and commit id */
> +       sc_misc_build_info(-1, &sc_build, &sc_commit);
> +       if (!sc_build) {
> +               printf("SCFW does not support build info\n");
> +               sc_commit = 0; /* Display 0 if build info not supported */
> +       }
> +       printf("Build: SCFW %x\n", sc_commit);
> +}
> +
> +int checkboard(void)
> +{
> +       puts("Model: Toradex Colibri iMX8X\n");
> +
> +       build_info();
> +       print_bootinfo();
> +
> +       return 0;
> +}
> +
> +int board_init(void)
> +{
> +       board_gpio_init();
> +
> +       return 0;
> +}
> +
> +void detail_board_ddr_info(void)
> +{
> +       puts("\nDDR    ");
> +}
> +
> +/*
> + * Board specific reset that is system reset.
> + */
> +void reset_cpu(ulong addr)
> +{
> +       /* TODO */
> +}
> +
> +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
> +int ft_board_setup(void *blob, bd_t *bd)
> +{
> +       return ft_common_board_setup(blob, bd);
> +}
> +#endif
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> +       return devno;
> +}
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +/* TODO move to common */
> +       env_set("board_name", "Colibri iMX8QXP");
> +       env_set("board_rev", "v1.0");
> +#endif
> +
> +       return 0;
> +}
> diff --git a/board/toradex/colibri-imx8qxp/imximage.cfg b/board/toradex/colibri-imx8qxp/imximage.cfg
> new file mode 100644
> index 0000000000..ce9e66c64d
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/imximage.cfg
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 Toradex
> + *
> + * Refer doc/README.imx8image for more details about how-to configure
> + * and create imx8image boot image
> + */
> +
> +#define __ASSEMBLY__
> +
> +/* Boot from SD, sector size 0x400 */
> +BOOT_FROM EMMC_FASTBOOT 0x400
> +/* SoC type IMX8QX */
> +SOC_TYPE IMX8QX
> +/* Append seco container image */
> +APPEND ahab-container.img
> +/* Create the 2nd container */
> +CONTAINER
> +/* Add scfw image with exec attribute */
> +IMAGE SCU mx8qx-colibri-scfw-tcm.bin
> +/* Add ATF image with exec attribute */
> +IMAGE A35 bl31.bin 0x80000000
> +/* Add U-Boot image with load attribute */
> +DATA A35 u-boot-dtb.bin 0x80020000
> diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig
> new file mode 100644
> index 0000000000..d697546ed7
> --- /dev/null
> +++ b/configs/colibri-imx8qxp_defconfig
> @@ -0,0 +1,53 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMX8=y
> +CONFIG_SYS_TEXT_BASE=0x80020000
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_TARGET_COLIBRI_IMX8QXP=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_NR_DRAM_BANKS=3
> +CONFIG_FIT=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8qxp/imximage.cfg"
> +CONFIG_LOG=y
> +CONFIG_VERSION_VARIABLE=y
> +# CONFIG_DISPLAY_BOARDINFO is not set
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_CMD_CPU=y
> +# CONFIG_CMD_IMPORTENV is not set
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_DM=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_UUID=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_CLK_IMX8=y
> +CONFIG_CPU=y
> +CONFIG_DM_GPIO=y
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_IMX_LPI2C=y
> +CONFIG_MISC=y
> +CONFIG_DM_MMC=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ADDR_ENABLE=y
> +CONFIG_PHY_MICREL=y
> +CONFIG_DM_ETH=y
> +CONFIG_FEC_MXC_SHARE_MDIO=y
> +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX8=y
> +CONFIG_POWER_DOMAIN=y
> +CONFIG_IMX8_POWER_DOMAIN=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_FSL_LPUART=y
> +CONFIG_DM_THERMAL=y
> +# CONFIG_EFI_LOADER is not set
> diff --git a/include/configs/colibri-imx8qxp.h b/include/configs/colibri-imx8qxp.h
> new file mode 100644
> index 0000000000..33cbcb44a9
> --- /dev/null
> +++ b/include/configs/colibri-imx8qxp.h
> @@ -0,0 +1,214 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 Toradex
> + */
> +
> +#ifndef __COLIBRI_IMX8QXP_H
> +#define __COLIBRI_IMX8QXP_H
> +
> +#include <asm/arch/imx-regs.h>
> +#include <linux/sizes.h>
> +
> +#define CONFIG_REMAKE_ELF
> +
> +#define CONFIG_DISPLAY_BOARDINFO_LATE
> +
> +#undef CONFIG_CMD_EXPORTENV
> +#undef CONFIG_CMD_IMPORTENV
> +#undef CONFIG_CMD_IMLS
> +
> +#undef CONFIG_CMD_CRC32
> +#undef CONFIG_BOOTM_NETBSD
> +
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR      0
> +#define USDHC1_BASE_ADDR               0x5B010000
> +#define USDHC2_BASE_ADDR               0x5B020000
> +#define CONFIG_SUPPORT_EMMC_BOOT       /* eMMC specific */
> +
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +
> +#define FEC_QUIRK_ENET_MAC
> +
> +#define CONFIG_IP_DEFRAG
> +#define CONFIG_TFTP_BLOCKSIZE          4096

4096 can be replaced with SZ_4K (from include/linux/sizes.h)

> +#define CONFIG_TFTP_TSIZE
> +
> +#define CONFIG_IPADDR                  192.168.10.2
> +#define CONFIG_NETMASK                 255.255.255.0
> +#define CONFIG_SERVERIP                        192.168.10.1
> +
> +#define MEM_LAYOUT_ENV_SETTINGS \
> +       "fdt_addr_r=0x84000000\0" \
> +       "kernel_addr_r=0x82000000\0" \
> +       "ramdisk_addr_r=0x84100000\0"
> +
> +#ifdef CONFIG_AHAB_BOOT
> +#define AHAB_ENV "sec_boot=yes\0"
> +#else
> +#define AHAB_ENV "sec_boot=no\0"
> +#endif
> +
> +/* Boot M4 */
> +#define M4_BOOT_ENV \
> +       "m4_0_image=m4_0.bin\0" \
> +       "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
> +               "${m4_0_image}\0" \
> +       "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
> +
> +#define MFG_NAND_PARTITION ""
> +
> +#define BOOT_TARGET_DEVICES(func) \
> +       func(MMC, mmc, 0) \
> +       func(MMC, mmc, 1) \
> +       func(DHCP, dhcp, na)
> +#include <config_distro_bootcmd.h>
> +#undef BOOTENV_RUN_NET_USB_START
> +#define BOOTENV_RUN_NET_USB_START ""
> +
> +#define CONFIG_MFG_ENV_SETTINGS \
> +       "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
> +               "rdinit=/linuxrc g_mass_storage.stall=0 " \
> +               "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \
> +               "g_mass_storage.idProduct=0x37FF " \
> +               "g_mass_storage.iSerialNumber=\"\" "\
> +               MFG_NAND_PARTITION \
> +               "video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off " \
> +               "clk_ignore_unused "\
> +               "\0" \
> +       "initrd_addr=0x83800000\0" \
> +       "initrd_high=0xffffffff\0" \
> +       "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \
> +               "${fdt_addr};\0" \
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +       AHAB_ENV \
> +       BOOTENV \
> +       CONFIG_MFG_ENV_SETTINGS \
> +       M4_BOOT_ENV \
> +       MEM_LAYOUT_ENV_SETTINGS \
> +       "boot_fdt=try\0" \
> +       "bootscript=echo Running bootscript from mmc ...; source\0" \
> +       "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200\0" \
> +       "fdt_addr=0x83000000\0"                 \
> +       "fdt_file=fsl-imx8qxp-colibri-eval-v3.dtb\0" \
> +       "fdt_high=0xffffffffffffffff\0"         \
> +       "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
> +       "image=Image\0" \
> +       "initrd_addr=0x83800000\0"              \
> +       "initrd_high=0xffffffffffffffff\0" \
> +       "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
> +               "${script};\0" \
> +       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> +       "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> +       "mmcargs=setenv bootargs console=${console},${baudrate} " \
> +               "root=PARTUUID=${uuid} rootwait " \
> +       "mmcautodetect=yes\0" \
> +       "mmcboot=echo Booting from mmc ...; " \
> +               "run finduuid; run mmcargs; " \
> +               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +                       "if run loadfdt; then " \
> +                               "booti ${loadaddr} - ${fdt_addr}; " \
> +                       "else " \
> +                               "echo WARN: Cannot load the DT; " \
> +                       "fi; " \
> +               "else " \
> +                       "echo wait for boot; " \
> +               "fi;\0" \
> +       "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
> +       "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> +       "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
> +               "nfsroot=${serverip}:${nfsroot},v3,tcp video=imxdpufb5:off " \
> +               "video=imxdpufb6:off video=imxdpufb7:off\0" \
> +       "netboot=echo Booting from net ...; " \
> +               "run netargs; " \
> +               "if test ${ip_dyn} = yes; then " \
> +                       "setenv get_cmd dhcp; " \
> +               "else " \
> +                       "setenv get_cmd tftp; " \
> +               "fi; " \
> +               "${get_cmd} ${loadaddr} ${image}; " \
> +               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +                       "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> +                               "booti ${loadaddr} - ${fdt_addr}; " \
> +                       "else " \
> +                               "echo WARN: Cannot load the DT; " \
> +                       "fi; " \
> +               "else " \
> +                       "booti; " \
> +               "fi;\0" \
> +       "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
> +               "colibri-imx8qxp/${fdt_file}; booti ${loadaddr} - " \
> +               "${fdt_addr}\0" \
> +       "panel=NULL\0" \
> +       "script=boot.scr\0" \
> +       "video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
> +
> +#undef CONFIG_BOOTCOMMAND
> +#define CONFIG_BOOTCOMMAND \
> +          "mmc dev ${mmcdev}; if mmc rescan; then " \
> +                  "if run loadbootscript; then " \
> +                          "run bootscript; " \
> +                  "else " \
> +                          "if run loadimage; then " \
> +                                  "run mmcboot; " \
> +                          "else run netboot; " \
> +                          "fi; " \
> +                  "fi; " \
> +          "else booti ${loadaddr} - ${fdt_addr}; fi"
> +
> +/* Link Definitions */
> +#define CONFIG_LOADADDR                        0x80280000
> +
> +#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_SP_ADDR                0x80200000
> +
> +#define CONFIG_SYS_MEMTEST_START       0x88000000
> +#define CONFIG_SYS_MEMTEST_END         0x89000000
> +
> +/* Environment in eMMC, before config block at the end of 1st "boot sector" */
> +#define CONFIG_ENV_SIZE                        (8 * 1024)

 (8 * 1024) can be replaced with SZ_8K (from include/linux/sizes.h)

> +#define CONFIG_ENV_OFFSET              (-CONFIG_ENV_SIZE + \
> +                                        CONFIG_TDX_CFG_BLOCK_OFFSET)
> +#define CONFIG_SYS_MMC_ENV_DEV         0
> +#define CONFIG_SYS_MMC_ENV_PART                1
> +
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART   1
> +
> +/* On Colibri iMX8 USDHC1 is eMMC, USDHC2 is 4-bit SD */
> +#define CONFIG_SYS_MMC_ENV_DEV         0                /* USDHC1 eMMC */
> +#define CONFIG_SYS_FSL_USDHC_NUM       2
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN          ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
> +
> +#define CONFIG_SYS_SDRAM_BASE          0x80000000
> +#define CONFIG_NR_DRAM_BANKS           3
> +#define PHYS_SDRAM_1                   0x80000000
> +#define PHYS_SDRAM_2                   0x880000000
> +#define PHYS_SDRAM_1_SIZE              0x80000000      /* 2 GB */
0x80000000 can be replaced with SZ_2G (from include/linux/sizes.h)
> +#define PHYS_SDRAM_2_SIZE              0x00000000      /* 0 GB */
> +
> +/* Serial */
> +#define CONFIG_BAUDRATE                        115200
> +
> +/* Monitor Command Prompt */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
> +#define CONFIG_SYS_CBSIZE              2048

Same as above

> +#define CONFIG_SYS_MAXARGS             64
> +#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
> +                                       sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +/* Generic Timer Definitions */
> +#define COUNTER_FREQUENCY              8000000 /* 8MHz */
> +
> +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
> +#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */
Same as above
> +
> +#endif /* __COLIBRI_IMX8QXP_H */
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot



-- 
Best regards - Freundliche Grüsse - Meilleures salutations

Igor Opaniuk

mailto: igor.opaniuk at gmail.com
skype: igor.opanyuk
+380 (93) 836 40 67
http://ua.linkedin.com/in/iopaniuk

[U-Boot] [PATCH 1/8] imx: sip: add call_imx_sip_ret2

[Peng Fan]

This function will be used by i.MX8 fuse driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/mach-imx/sys_proto.h |  3 +++
 arch/arm/mach-imx/sip.c                   | 22 ++++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index d0f866b630..4925dd7894 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -134,4 +134,7 @@ int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 
 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
 			   unsigned long reg1, unsigned long reg2);
+unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
+				unsigned long *reg1, unsigned long reg2,
+				unsigned long reg3);
 #endif
diff --git a/arch/arm/mach-imx/sip.c b/arch/arm/mach-imx/sip.c
index 813c2ae5e1..968e7cf309 100644
--- a/arch/arm/mach-imx/sip.c
+++ b/arch/arm/mach-imx/sip.c
@@ -20,3 +20,25 @@ unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
 
 	return regs.regs[0];
 }
+
+/*
+ * Do an SMC call to return 2 registers by having reg1 passed in by reference
+ */
+unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
+				unsigned long *reg1, unsigned long reg2,
+				unsigned long reg3)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = id;
+	regs.regs[1] = reg0;
+	regs.regs[2] = *reg1;
+	regs.regs[3] = reg2;
+	regs.regs[4] = reg3;
+
+	smc_call(&regs);
+
+	*reg1 = regs.regs[1];
+
+	return regs.regs[0];
+}
-- 
2.16.4

[U-Boot] [PATCH 2/8] imx8: fuse: add fuse driver

[Peng Fan]

Add fuse write for i.MX8

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/misc/imx8/Makefile |  1 +
 drivers/misc/imx8/fuse.c   | 86 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 87 insertions(+)
 create mode 100644 drivers/misc/imx8/fuse.c

diff --git a/drivers/misc/imx8/Makefile b/drivers/misc/imx8/Makefile
index ee05893cbb..48fdb5b61c 100644
--- a/drivers/misc/imx8/Makefile
+++ b/drivers/misc/imx8/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-y += scu_api.o scu.o
+obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c
new file mode 100644
index 0000000000..29d2256a22
--- /dev/null
+++ b/drivers/misc/imx8/fuse.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <console.h>
+#include <errno.h>
+#include <fuse.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FSL_ECC_WORD_START_1	 0x10
+#define FSL_ECC_WORD_END_1	 0x10F
+
+#ifdef CONFIG_IMX8QXP
+#define FSL_ECC_WORD_START_2	 0x220
+#define FSL_ECC_WORD_END_2	 0x31F
+
+#define FSL_QXP_FUSE_GAP_START	 0x110
+#define FSL_QXP_FUSE_GAP_END	 0x21F
+#endif
+
+#define FSL_SIP_OTP_READ             0xc200000A
+#define FSL_SIP_OTP_WRITE            0xc200000B
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	return fuse_sense(bank, word, val);
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	unsigned long ret = 0, value = 0;
+
+	if (bank != 0) {
+		printf("Invalid bank argument, ONLY bank 0 is supported\n");
+		return -EINVAL;
+	}
+
+	ret = call_imx_sip_ret2(FSL_SIP_OTP_READ, (unsigned long)word, &value,
+				0, 0);
+	*val = (u32)value;
+
+	return ret;
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	if (bank != 0) {
+		printf("Invalid bank argument, ONLY bank 0 is supported\n");
+		return -EINVAL;
+	}
+
+	if (IS_ENABLED(CONFIG_IMX8QXP)) {
+		if (word >= FSL_QXP_FUSE_GAP_START &&
+		    word <= FSL_QXP_FUSE_GAP_END) {
+			printf("Invalid word argument for this SoC\n");
+			return -EINVAL;
+		}
+	}
+
+	if ((word >= FSL_ECC_WORD_START_1 && word <= FSL_ECC_WORD_END_1) ||
+	    (word >= FSL_ECC_WORD_START_2 && word <= FSL_ECC_WORD_END_2)) {
+		puts("Warning: Words in this index range have ECC protection\n"
+		     "and can only be programmed once per word. Individual bit\n"
+		     "operations will be rejected after the first one.\n"
+		     "\n\n Really program this word? <y/N>\n");
+
+		if (!confirm_yesno()) {
+			puts("Word programming aborted\n");
+			return -EPERM;
+		}
+	}
+
+	return call_imx_sip(FSL_SIP_OTP_WRITE, (unsigned long)word,
+			    (unsigned long)val, 0);
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	printf("Override fuse to i.MX8 in u-boot is forbidden\n");
+	return -EPERM;
+}
-- 
2.16.4

[U-Boot] [PATCH 3/8] imx8qxp: mek: Enable CMD_FUSE

[Peng Fan]

Enable CMD_FUSE for i.MX8QXP MEK

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 configs/imx8qxp_mek_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index a94998b8b5..14e9da386a 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMPORTENV is not set
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-- 
2.16.4

[U-Boot] [PATCH 4/8] misc: imx8: add sc_misc_get_temp

[Peng Fan]

Add sc_misc_get_temp to support get temperature

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8/sci/sci.h          |  2 ++
 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h |  1 +
 drivers/misc/imx8/scu_api.c                       | 28 +++++++++++++++++++++++
 3 files changed, 31 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h
index d1621669e2..ccf45d71f7 100644
--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
@@ -76,6 +76,8 @@ void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
 void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
 void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
 int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
+int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
+		     s16 *celsius, s8 *tenths);
 
 /* RM API */
 sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
index 5d17b553d7..3629eb68d7 100644
--- a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
@@ -26,5 +26,6 @@
 #define SC_MISC_REL_CONTAINER	2U	/* Release container */
 
 typedef u8 sc_misc_boot_status_t;
+typedef u8 sc_misc_temp_t;
 
 #endif /* SC_MISC_API_H */
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index d9c4d5d784..031bc0048b 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -273,6 +273,34 @@ int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val)
 	return 0;
 }
 
+int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
+		     s16 *celsius, s8 *tenths)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	int size = sizeof(struct sc_rpc_msg_s);
+	struct sc_rpc_msg_s msg;
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = (u8)SC_RPC_SVC_MISC;
+	RPC_FUNC(&msg) = (u8)MISC_FUNC_GET_TEMP;
+	RPC_U16(&msg, 0U) = (u16)resource;
+	RPC_U8(&msg, 2U) = (u8)temp;
+	RPC_SIZE(&msg) = 2U;
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret < 0)
+		return ret;
+
+	if (celsius)
+		*celsius = RPC_I16(&msg, 0U);
+
+	if (tenths)
+		*tenths = RPC_I8(&msg, 2U);
+
+	return 0;
+}
+
 /* RM */
 sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
 {
-- 
2.16.4

[U-Boot] [PATCH 5/8] thermal: add i.MX8 thermal driver

[Peng Fan]

Add i.MX8 thermal driver to support get temperature from SCU.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/thermal/Kconfig           |   9 ++
 drivers/thermal/Makefile          |   1 +
 drivers/thermal/imx_scu_thermal.c | 203 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 213 insertions(+)
 create mode 100644 drivers/thermal/imx_scu_thermal.c

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index a71b9be5fb..bdf8dc6fef 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -17,6 +17,15 @@ config IMX_THERMAL
           cpufreq is used as the cooling device to throttle CPUs when the
           passive trip is crossed.
 
+config IMX_SCU_THERMAL
+	bool "Temperature sensor driver for NXP i.MX8"
+	depends on ARCH_IMX8
+	help
+	  Support for Temperature sensors on NXP i.MX8.
+	  It supports one critical trip point and one passive trip point. The
+	  boot is hold to the cool device to throttle CPUs when the passive
+	  trip is crossed
+
 config TI_DRA7_THERMAL
         bool "Temperature sensor driver for TI dra7xx SOCs"
         help
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index cc75e387e4..ef2929d180 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -5,4 +5,5 @@
 
 obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o
 obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_IMX_SCU_THERMAL) += imx_scu_thermal.o
 obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o
diff --git a/drivers/thermal/imx_scu_thermal.c b/drivers/thermal/imx_scu_thermal.c
new file mode 100644
index 0000000000..7e17377b69
--- /dev/null
+++ b/drivers/thermal/imx_scu_thermal.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <config.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <thermal.h>
+#include <dm/device-internal.h>
+#include <dm/device.h>
+#include <asm/arch/sci/sci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct imx_sc_thermal_plat {
+	int critical;
+	int alert;
+	int polling_delay;
+	int id;
+	bool zone_node;
+};
+
+static int read_temperature(struct udevice *dev, int *temp)
+{
+	s16 celsius;
+	s8 tenths;
+	int ret;
+
+	sc_rsrc_t *sensor_rsrc = (sc_rsrc_t *)dev_get_driver_data(dev);
+
+	struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+
+	if (!temp)
+		return -EINVAL;
+
+	ret = sc_misc_get_temp(-1, sensor_rsrc[pdata->id], SC_C_TEMP,
+			       &celsius, &tenths);
+	if (ret) {
+		printf("Error: get temperature failed! (error = %d)\n", ret);
+		return ret;
+	}
+
+	*temp = celsius * 1000 + tenths * 100;
+
+	return 0;
+}
+
+int imx_sc_thermal_get_temp(struct udevice *dev, int *temp)
+{
+	struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+	int cpu_temp = 0;
+	int ret;
+
+	ret = read_temperature(dev, &cpu_temp);
+	if (ret)
+		return ret;
+
+	while (cpu_temp >= pdata->alert) {
+		printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)",
+		       cpu_temp, pdata->alert, pdata->critical);
+		puts(" waiting...\n");
+		mdelay(pdata->polling_delay);
+		ret = read_temperature(dev, &cpu_temp);
+		if (ret)
+			return ret;
+	}
+
+	*temp = cpu_temp / 1000;
+
+	return 0;
+}
+
+static const struct dm_thermal_ops imx_sc_thermal_ops = {
+	.get_temp	= imx_sc_thermal_get_temp,
+};
+
+static int imx_sc_thermal_probe(struct udevice *dev)
+{
+	debug("%s dev name %s\n", __func__, dev->name);
+	return 0;
+}
+
+static int imx_sc_thermal_bind(struct udevice *dev)
+{
+	struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+	int reg, ret;
+	int offset;
+	const char *name;
+	const void *prop;
+
+	debug("%s dev name %s\n", __func__, dev->name);
+
+	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "compatible",
+			   NULL);
+	if (!prop)
+		return 0;
+
+	pdata->zone_node = 1;
+
+	reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "tsens-num", 0);
+	if (reg == 0) {
+		printf("%s: no temp sensor number provided!\n", __func__);
+		return -EINVAL;
+	}
+
+	offset = fdt_subnode_offset(gd->fdt_blob, 0, "thermal-zones");
+	fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
+		/* Bind the subnode to this driver */
+		name = fdt_get_name(gd->fdt_blob, offset, NULL);
+
+		ret = device_bind_with_driver_data(dev, dev->driver, name,
+						   dev->driver_data,
+						   offset_to_ofnode(offset),
+						   NULL);
+		if (ret)
+			printf("Error binding driver '%s': %d\n",
+			       dev->driver->name, ret);
+	}
+	return 0;
+}
+
+static int imx_sc_thermal_ofdata_to_platdata(struct udevice *dev)
+{
+	struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+	struct fdtdec_phandle_args args;
+	const char *type;
+	int ret;
+	int trips_np;
+
+	debug("%s dev name %s\n", __func__, dev->name);
+
+	if (pdata->zone_node)
+		return 0;
+
+	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
+					     "thermal-sensors",
+					     "#thermal-sensor-cells",
+					     0, 0, &args);
+	if (ret)
+		return ret;
+
+	if (args.node != dev_of_offset(dev->parent))
+		return -EFAULT;
+
+	if (args.args_count >= 1)
+		pdata->id = args.args[0];
+	else
+		pdata->id = 0;
+
+	debug("args.args_count %d, id %d\n", args.args_count, pdata->id);
+
+	pdata->polling_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+					      "polling-delay", 1000);
+
+	trips_np = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
+				      "trips");
+	fdt_for_each_subnode(trips_np, gd->fdt_blob, trips_np) {
+		type = fdt_getprop(gd->fdt_blob, trips_np, "type", NULL);
+		if (type) {
+			if (strcmp(type, "critical") == 0) {
+				pdata->critical = fdtdec_get_int(gd->fdt_blob,
+								 trips_np,
+								 "temperature",
+								 85);
+			} else if (strcmp(type, "passive") == 0) {
+				pdata->alert = fdtdec_get_int(gd->fdt_blob,
+							      trips_np,
+							      "temperature",
+							      80);
+			}
+		}
+	}
+
+	debug("id %d polling_delay %d, critical %d, alert %d\n", pdata->id,
+	      pdata->polling_delay, pdata->critical, pdata->alert);
+
+	return 0;
+}
+
+static const sc_rsrc_t imx8qxp_sensor_rsrc[] = {
+	SC_R_SYSTEM, SC_R_DRC_0, SC_R_PMIC_0,
+	SC_R_PMIC_1, SC_R_PMIC_2,
+};
+
+static const struct udevice_id imx_sc_thermal_ids[] = {
+	{ .compatible = "nxp,imx8qxp-sc-tsens", .data =
+		(ulong)&imx8qxp_sensor_rsrc, },
+	{ }
+};
+
+U_BOOT_DRIVER(imx_sc_thermal) = {
+	.name	= "imx_sc_thermal",
+	.id	= UCLASS_THERMAL,
+	.ops	= &imx_sc_thermal_ops,
+	.of_match = imx_sc_thermal_ids,
+	.bind = imx_sc_thermal_bind,
+	.probe	= imx_sc_thermal_probe,
+	.ofdata_to_platdata = imx_sc_thermal_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct imx_sc_thermal_plat),
+	.flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.16.4

[U-Boot] [PATCH 6/8] imx8: cpu: get temperature when print cpu desc

[Peng Fan]

Read the temperature when print cpu inforation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8/cpu.c | 35 +++++++++++++++++++++++++++++++++--
 1 file changed, 33 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 4bbc956f9d..25b010489b 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -11,6 +11,7 @@
 #include <dm/lists.h>
 #include <dm/uclass.h>
 #include <errno.h>
+#include <thermal.h>
 #include <asm/arch/sci/sci.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch-imx/cpu.h>
@@ -571,15 +572,45 @@ const char *get_core_name(void)
 		return "?";
 }
 
+#if defined(CONFIG_IMX_SCU_THERMAL)
+static int cpu_imx_get_temp(void)
+{
+	struct udevice *thermal_dev;
+	int cpu_tmp, ret;
+
+	ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0",
+					&thermal_dev);
+
+	if (!ret) {
+		ret = thermal_get_temp(thermal_dev, &cpu_tmp);
+		if (ret)
+			return 0xdeadbeef;
+	} else {
+		return 0xdeadbeef;
+	}
+
+	return cpu_tmp;
+}
+#endif
+
 int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
 {
 	struct cpu_imx_platdata *plat = dev_get_platdata(dev);
+	int ret;
 
 	if (size < 100)
 		return -ENOSPC;
 
-	snprintf(buf, size, "NXP i.MX8%s Rev%s %s@%u MHz\n",
-		 plat->type, plat->rev, plat->name, plat->freq_mhz);
+	ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
+		       plat->type, plat->rev, plat->name, plat->freq_mhz);
+
+	if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
+		buf = buf + ret;
+		size = size - ret;
+		ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
+	}
+
+	snprintf(buf + ret, size - ret, "\n");
 
 	return 0;
 }
-- 
2.16.4

[U-Boot] [PATCH 7/8] imx: imx8dx/qxp: enable thermal

[Peng Fan]

Add thermal dts node
Enable thermal in defconfig

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/dts/fsl-imx8dx.dtsi  | 56 +++++++++++++++++++++++++++++++++++++++++++
 configs/imx8qxp_mek_defconfig |  2 ++
 2 files changed, 58 insertions(+)

diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
index 3b1a2a20e3..1c163afdcd 100644
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	model = "Freescale i.MX8DX";
@@ -489,6 +490,61 @@
 		power-domains = <&pd_conn_enet1>;
 		status = "disabled";
 	};
+
+	tsens: thermal-sensor {
+		compatible = "nxp,imx8qxp-sc-tsens";
+		/* number of the temp sensor on the chip */
+		tsens-num = <2>;
+		#thermal-sensor-cells = <1>;
+	};
+
+	thermal_zones: thermal-zones {
+		/* cpu thermal */
+		cpu-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			/*the slope and offset of the temp sensor */
+			thermal-sensors = <&tsens 0>;
+			trips {
+				cpu_alert0: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit0: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		drc-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tsens 1>;
+			status = "disabled";
+			trips {
+				drc_alert0: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				drc_crit0: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
 };
 
 &A35_0 {
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index 14e9da386a..f0da489645 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -73,5 +73,7 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
 CONFIG_SPL_TINY_MEMSET=y
 # CONFIG_EFI_LOADER is not set
-- 
2.16.4

[U-Boot] [PATCH 8/8] imx8: mek: move HUSH_PARSER to defconfig

[Peng Fan]

Move HUSH_PARSER to defconfig, otherwise meet
"
=> run netboot
Booting from net ...
Unknown command 'if' - try 'help'
Unknown command 'then' - try 'help'
Unknown command 'else' - try 'help'
Unknown command 'fi' - try 'help'
Unknown command '0x80280000' - try 'help'
Unknown command 'if' - try 'help'
Unknown command 'then' - try 'help'
Unknown command 'then' - try 'help'
Unknown command 'else' - try 'help'
Unknown command 'fi' - try 'help'
Unknown command 'else' - try 'help'
Unknown command 'fi' - try 'help'
"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 configs/imx8qxp_mek_defconfig | 1 +
 include/configs/imx8qxp_mek.h | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index f0da489645..38f0ff0bf3 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -23,6 +23,7 @@ CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMPORTENV is not set
 CONFIG_CMD_CLK=y
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index 312e30dc6c..1cff18e05e 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -159,7 +159,6 @@
 #define CONFIG_BAUDRATE			115200
 
 /* Monitor Command Prompt */
-#define CONFIG_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #define CONFIG_SYS_CBSIZE              2048
 #define CONFIG_SYS_MAXARGS             64
-- 
2.16.4

[U-Boot] [PATCH] ARM: imx: Fix typo in select option for ZMX25

[Chris Packham]

Correct CPU_ARM926EJS1 to CPU_ARM926EJS.

Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
---

 arch/arm/mach-imx/mx2/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mx2/Kconfig b/arch/arm/mach-imx/mx2/Kconfig
index ea308fccab02..30a331ae43b7 100644
--- a/arch/arm/mach-imx/mx2/Kconfig
+++ b/arch/arm/mach-imx/mx2/Kconfig
@@ -17,7 +17,7 @@ config TARGET_MX25PDK
 config TARGET_ZMX25
 	bool "Support zmx25"
 	select BOARD_LATE_INIT
-	select CPU_ARM926EJS1
+	select CPU_ARM926EJS
 
 endchoice
 
-- 
2.21.0

[U-Boot] [PATCH] imx: add lowlevel init for ARM64

[Peng Fan]

Sometimes we met SERROR, but only to catch it when Linux boots up.
Let's enable catching in U-Boot to catch it ealier and ease debug.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/Makefile   |  2 +-
 arch/arm/mach-imx/lowlevel.S | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-imx/lowlevel.S

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index c3ed62aed6..37675d0558 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -204,7 +204,7 @@ endif
 
 targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
 
-obj-$(CONFIG_ARM64) += sip.o
+obj-$(CONFIG_ARM64) += lowlevel.o sip.o
 
 obj-$(CONFIG_MX5) += mx5/
 obj-$(CONFIG_MX6) += mx6/
diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-imx/lowlevel.S
new file mode 100644
index 0000000000..158fdb7d87
--- /dev/null
+++ b/arch/arm/mach-imx/lowlevel.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+	mrs	x0, CurrentEL
+	cmp	x0, #8
+	b.eq	1f
+	ret
+1:
+	msr daifclr, #4
+
+	/* set HCR_EL2.AMO to catch SERROR */
+	mrs	x0, hcr_el2
+	orr	x0, x0, #0x20
+	msr	hcr_el2, x0
+	isb
+	ret
+ENDPROC(lowlevel_init)
-- 
2.16.4

[U-Boot] [PATCH v2 1/2] ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration

[Ludwig Zenz]

From: Ludwig Zenz <lzenz@dh-electronics.de>

The four x16 DDR3 are wired in T-topology. From NXP AN4467:
'Although not required, T-Topologies may also benefit from performing
Write Leveling as there are package delays on both the processor and DDR
devices that can be de-skewed by performing Write Leveling. Therefore,
Freescale recommends determining Write Leveling calibration parameters
for all boards, regardless of topology used.'
That is why write level calibration is also done.

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>
---
 board/dhelectronics/dh_imx6/dh_imx6_spl.c | 32 +++++++++++++++++++++++++------
 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index 04e9eab272a..bbd2dc26828 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -482,6 +482,29 @@ static void setup_iomux_usb(void)
 	SETUP_IOMUX_PADS(usb_pads);
 }
 
+/* Perform DDR DRAM calibration */
+static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+	int ret = 0;
+
+#ifdef CONFIG_MX6_DDRCAL
+	udelay(100);
+	ret = mmdc_do_write_level_calibration(sysinfo);
+	if (ret) {
+		printf("DDR3: Write level calibration error [%d]\n", ret);
+		return ret;
+	}
+
+	ret = mmdc_do_dqs_calibration(sysinfo);
+	if (ret) {
+		printf("DDR3: DQS calibration error [%d]\n", ret);
+		return ret;
+	}
+#endif /* CONFIG_MX6_DDRCAL */
+
+	return ret;
+}
+
 
 /* DRAM */
 static void dhcom_spl_dram_init(void)
@@ -509,8 +532,7 @@ static void dhcom_spl_dram_init(void)
 		}
 
 		/* Perform DDR DRAM calibration */
-		udelay(100);
-		mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
+		spl_dram_perform_cal(&dhcom_ddr_64bit);
 
 	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
 		mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
@@ -528,8 +550,7 @@ static void dhcom_spl_dram_init(void)
 		}
 
 		/* Perform DDR DRAM calibration */
-		udelay(100);
-		mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
+		spl_dram_perform_cal(&dhcom_ddr_64bit);
 
 	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 		mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
@@ -552,8 +573,7 @@ static void dhcom_spl_dram_init(void)
 		}
 
 		/* Perform DDR DRAM calibration */
-		udelay(100);
-		mmdc_do_dqs_calibration(&dhcom_ddr_32bit);
+		spl_dram_perform_cal(&dhcom_ddr_32bit);
 	}
 }
 
-- 
2.11.0

[U-Boot] [PATCH] imx: 8qxp_mek: fix fdt_file and console

[Peng Fan]

Fix fdt_file and console to boot upstream Linux Kernel.

Upstream linux use imx8qxp-mek.dtb, and pass lpuart32 to earlycon
will not work for i.MX8QXP, only need to pass earlycon,
check drivers/tty/serial/earlycon.c,
" /* Just 'earlycon' is a valid param for devicetree and ACPI SPCR. */ "

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/configs/imx8qxp_mek.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index 1cff18e05e..5c83505ff0 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -65,11 +65,11 @@
 	"script=boot.scr\0" \
 	"image=Image\0" \
 	"panel=NULL\0" \
-	"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
+	"console=ttyLP0,${baudrate} earlycon\0" \
 	"fdt_addr=0x83000000\0"			\
 	"fdt_high=0xffffffffffffffff\0"		\
 	"boot_fdt=try\0" \
-	"fdt_file=fsl-imx8qxp-mek.dtb\0" \
+	"fdt_file=imx8qxp-mek.dtb\0" \
 	"initrd_addr=0x83800000\0"		\
 	"initrd_high=0xffffffffffffffff\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
-- 
2.16.4

[U-Boot] [PATCH] imx: 8qxp_mek: fix fdt_file and console

[Fabio Estevam]

On Mon, Apr 15, 2019 at 9:01 AM Peng Fan <peng.fan@nxp.com> wrote:
>
> Fix fdt_file and console to boot upstream Linux Kernel.
>
> Upstream linux use imx8qxp-mek.dtb, and pass lpuart32 to earlycon
> will not work for i.MX8QXP, only need to pass earlycon,
> check drivers/tty/serial/earlycon.c,
> " /* Just 'earlycon' is a valid param for devicetree and ACPI SPCR. */ "
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH] ARM: imx: Fix typo in select option for ZMX25

[Fabio Estevam]

On Sat, Apr 13, 2019 at 5:22 AM Chris Packham <judge.packham@gmail.com> wrote:
>
> Correct CPU_ARM926EJS1 to CPU_ARM926EJS.
>
> Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
> Signed-off-by: Chris Packham <judge.packham@gmail.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH] ARM: imx: Fix typo in select option for ZMX25

[Stefano Babic]

On 13/04/19 10:21, Chris Packham wrote:
> Correct CPU_ARM926EJS1 to CPU_ARM926EJS.
> 
> Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
> ---
> 
>  arch/arm/mach-imx/mx2/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/mx2/Kconfig b/arch/arm/mach-imx/mx2/Kconfig
> index ea308fccab02..30a331ae43b7 100644
> --- a/arch/arm/mach-imx/mx2/Kconfig
> +++ b/arch/arm/mach-imx/mx2/Kconfig
> @@ -17,7 +17,7 @@ config TARGET_MX25PDK
>  config TARGET_ZMX25
>  	bool "Support zmx25"
>  	select BOARD_LATE_INIT
> -	select CPU_ARM926EJS1
> +	select CPU_ARM926EJS
>  
>  endchoice
>  
> 

Reviewed-by : Stefano Babiy <sbabic@denx.de>

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 10/14] colibri-imx6ull: migrate usb to using driver model

[Igor Opaniuk]

Hi Marcel,

Just found out that to be able to use usbotg1 also in host mode this
change should be introduced:
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -220,7 +220,7 @@

 /* Colibri USBC */
 &usbotg1 {
-       dr_mode = "otg";
+       dr_mode = "host";
        srp-disable;
        hnp-disable;
        adp-disable;

Without (tested with USB pendrive):
Colibri iMX6ULL # usb start
starting USB...
USB0:   USB1:   USB EHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 1 for devices... 2 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found


With (tested with USB pendrive):
Colibri iMX6ULL # usb start
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB EHCI 1.00
scanning bus 0 for devices... 2 USB Device(s) found
scanning bus 1 for devices... 2 USB Device(s) found
       scanning usb for storage devices... 1 Storage Device(s) found

On Tue, Apr 9, 2019 at 5:31 PM Marcel Ziswiler <marcel@ziswiler.com> wrote:
>
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Migrate USB to using driver model.
> Add USBH_PEN GPIO regulator.
> While at it also add alias e.g. as required for UMS.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
>
> ---
>
> Changes in v2:
> - Added Igor's reviewed-by.
>
>  arch/arm/dts/imx6ull-colibri.dts              | 24 ++++++++++
>  .../toradex/colibri-imx6ull/colibri-imx6ull.c | 48 -------------------
>  configs/colibri-imx6ull_defconfig             |  1 +
>  3 files changed, 25 insertions(+), 48 deletions(-)
>
> diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
> index 0d416ebd10..91e48aab61 100644
> --- a/arch/arm/dts/imx6ull-colibri.dts
> +++ b/arch/arm/dts/imx6ull-colibri.dts
> @@ -13,6 +13,7 @@
>
>         aliases {
>                 mmc0 = &usdhc1;
> +               usb0 = &usbotg1; /* required for ums */
>         };
>
>         chosen {
> @@ -35,6 +36,13 @@
>                 regulator-max-microvolt = <3300000>;
>         };
>
> +       reg_5v0: regulator-5v0 {
> +               compatible = "regulator-fixed";
> +               regulator-name = "5V";
> +               regulator-min-microvolt = <5000000>;
> +               regulator-max-microvolt = <5000000>;
> +       };
> +
>         reg_sd1_vmmc: regulator-sd1-vmmc {
>                 compatible = "regulator-gpio";
>                 gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
> @@ -47,6 +55,17 @@
>                 states = <1800000 0x1 3300000 0x0>;
>                 vin-supply = <&reg_module_3v3>;
>         };
> +
> +       reg_usbh_vbus: regulator-usbh-vbus {
> +               compatible = "regulator-fixed";
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&pinctrl_usbh_reg>;
> +               regulator-name = "VCC_USB[1-4]";
> +               regulator-min-microvolt = <5000000>;
> +               regulator-max-microvolt = <5000000>;
> +               gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
> +               vin-supply = <&reg_5v0>;
> +       };
>  };
>
>  &adc1 {
> @@ -183,15 +202,20 @@
>         fsl,dte-mode;
>  };
>
> +/* Colibri USBC */
>  &usbotg1 {
>         dr_mode = "otg";
>         srp-disable;
>         hnp-disable;
>         adp-disable;
> +       status = "okay";
>  };
>
> +/* Colibri USBH */
>  &usbotg2 {
>         dr_mode = "host";
> +       vbus-supply = <&reg_usbh_vbus>;
> +       status = "okay";
>  };
>
>  /* Colibri MMC */
> diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
> index c9af44e30e..21addaf6ed 100644
> --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
> +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
> @@ -24,8 +24,6 @@
>  #include <miiphy.h>
>  #include <mtd_node.h>
>  #include <netdev.h>
> -#include <usb.h>
> -#include <usb/ehci-ci.h>
>
>  #include "../common/tdx-common.h"
>  #include "../common/tdx-cfg-block.h"
> @@ -41,8 +39,6 @@ DECLARE_GLOBAL_DATA_PTR;
>
>  #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
>
> -#define USB_CDET_GPIO  IMX_GPIO_NR(7, 14)
> -
>  int dram_init(void)
>  {
>         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> @@ -50,10 +46,6 @@ int dram_init(void)
>         return 0;
>  }
>
> -static iomux_v3_cfg_t const usb_cdet_pads[] = {
> -       MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
> -};
> -
>  #ifdef CONFIG_NAND_MXS
>  static void setup_gpmi_nand(void)
>  {
> @@ -163,11 +155,6 @@ int board_init(void)
>         setup_lcd();
>  #endif
>
> -#ifdef CONFIG_USB_EHCI_MX6
> -       imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
> -       gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
> -#endif
> -
>         return 0;
>  }
>
> @@ -241,41 +228,6 @@ int ft_board_setup(void *blob, bd_t *bd)
>  }
>  #endif
>
> -#ifdef CONFIG_USB_EHCI_MX6
> -static iomux_v3_cfg_t const usb_otg2_pads[] = {
> -               MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
> -};
> -
> -int board_ehci_hcd_init(int port)
> -{
> -       switch (port) {
> -       case 0:
> -               break;
> -       case 1:
> -               imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
> -                                                ARRAY_SIZE(usb_otg2_pads));
> -               break;
> -       default:
> -               return -EINVAL;
> -       }
> -       return 0;
> -}
> -
> -int board_usb_phy_mode(int port)
> -{
> -       switch (port) {
> -       case 0:
> -               if (gpio_get_value(USB_CDET_GPIO))
> -                       return USB_INIT_DEVICE;
> -               else
> -                       return USB_INIT_HOST;
> -       case 1:
> -       default:
> -               return USB_INIT_HOST;
> -       }
> -}
> -#endif
> -
>  static struct mxc_serial_platdata mxc_serial_plat = {
>         .reg = (struct mxc_uart *)UART1_BASE,
>         .use_dte = 1,
> diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
> index 69305323f2..0440b4ed94 100644
> --- a/configs/colibri-imx6ull_defconfig
> +++ b/configs/colibri-imx6ull_defconfig
> @@ -71,6 +71,7 @@ CONFIG_DM_REGULATOR_FIXED=y
>  CONFIG_DM_SERIAL=y
>  CONFIG_MXC_UART=y
>  CONFIG_USB=y
> +CONFIG_DM_USB=y
>  CONFIG_USB_GADGET=y
>  CONFIG_USB_GADGET_MANUFACTURER="Toradex"
>  CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot



-- 
Best regards - Freundliche Grüsse - Meilleures salutations

Senior Development Engineer,
Igor Opaniuk

Toradex AG
Altsagenstrasse 5 | 6048 Horw/Luzern | Switzerland | T: +41 41 500 48
00 (main line)

[U-Boot] [PATCH] imx: i.MX8MQ: clear ocotp error bit

[Peng Fan]

In case ocotp error bit is set, clear it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8m/soc.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 11251c5f9a..7ec39b3e47 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -169,6 +169,7 @@ static void imx_set_wdog_powerdown(bool enable)
 
 int arch_cpu_init(void)
 {
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 	/*
 	 * Init timer at very early state, because sscg pll setting
 	 * will use it
@@ -180,6 +181,12 @@ int arch_cpu_init(void)
 		imx_set_wdog_powerdown(false);
 	}
 
+	if (is_imx8mq()) {
+		clock_enable(CCGR_OCOTP, 1);
+		if (readl(&ocotp->ctrl) & 0x200)
+			writel(0x200, &ocotp->ctrl_clr);
+	}
+
 	return 0;
 }
 
-- 
2.16.4

[U-Boot] [PATCH 1/2] mxc_ocotp: Update redundancy banks for mx7ulp B0

[Peng Fan]

From: Ye Li <ye.li@nxp.com>

On mx7ulp B0, beside bank 0 and 1, the fuse bank 9, 10, 28 are changed to
Redundancy mode not ECC, so they can support to program different bits of
a word in multiple times.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/misc/mxc_ocotp.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index f84fe88db1..33ea31135c 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -354,13 +354,17 @@ static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
 
 	/* Only bank 0 and 1 are redundancy mode, others are ECC mode */
 	if (bank != 0 && bank != 1) {
-		ret = fuse_sense(bank, word, &val);
-		if (ret)
-			return ret;
-
-		if (val != 0) {
-			printf("mxc_ocotp: The word has been programmed, no more write\n");
-			return -EPERM;
+		if ((soc_rev() < CHIP_REV_2_0) ||
+		    ((soc_rev() >= CHIP_REV_2_0) &&
+		    bank != 9 && bank != 10 && bank != 28)) {
+			ret = fuse_sense(bank, word, &val);
+			if (ret)
+				return ret;
+
+			if (val != 0) {
+				printf("mxc_ocotp: The word has been programmed, no more write\n");
+				return -EPERM;
+			}
 		}
 	}
 #endif
-- 
2.16.4

[U-Boot] [PATCH 2/2] mxc_ocotp: Disable fuse sense for imx8mq B1

[Peng Fan]

From: Ye Li <ye.li@nxp.com>

On iMX8MQ Rev B1, reading from fuse box is not allowed. The
OCOTP_READ_FUSE_DATA register is tied to magic number 0xff0055aa
for chip rev. So u-boot has to disable the fuse sense function for it.

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/misc/mxc_ocotp.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 33ea31135c..1b945e9727 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -321,6 +321,11 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
 	struct ocotp_regs *regs;
 	int ret;
 
+	if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) {
+		printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__);
+		return -EPERM;
+	}
+
 	ret = prepare_read(&regs, bank, word, val, __func__);
 	if (ret)
 		return ret;
-- 
2.16.4

[U-Boot] [PATCH v3] ARM: dts: i.MX6Q: fix avoid_unnecessary_addr_size warnings

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Re-synced the device tree with Linux 5.0.

This fixes the following warnings:

w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
 port at 2/endpoint at 0:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
 port at 2/endpoint at 1:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
 port at 2/endpoint at 2:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
 port at 2/endpoint at 3:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
 port at 2/endpoint at 4:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
 port at 3/endpoint at 1:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
 port at 3/endpoint at 2:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
 port at 3/endpoint at 3:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
 port at 3/endpoint at 4:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 2/endpoint at 0: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 2/endpoint at 0: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 2/endpoint at 1: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 2/endpoint at 1: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 2/endpoint at 2: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 2/endpoint at 2: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 2/endpoint at 3: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 2/endpoint at 3: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 2/endpoint at 4: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 2/endpoint at 4: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 3/endpoint at 1: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 3/endpoint at 1: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 3/endpoint at 2: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 3/endpoint at 2: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 3/endpoint at 3: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 3/endpoint at 3: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 3/endpoint at 4: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu at 2800000/port at 3/endpoint at 4: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 Failed prerequisite 'avoid_default_addr_size'

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>

---

Changes in v3:
- Added Fabio and Lukasz' reviewed-by tags.

Changes in v2:
- Re-synced the device tree with Linux 5.0 as suggested by Fabio.

 arch/arm/dts/imx6q.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
index ab1716b6b0..d038f41170 100644
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@@ -202,6 +202,7 @@
 				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
 			clock-names = "bus", "core";
 			power-domains = <&pd_pu>;
+			#cooling-cells = <2>;
 		};
 
 		ipu2: ipu at 2800000 {
@@ -234,6 +235,8 @@
 			};
 
 			ipu2_di0: port at 2 {
+				#address-cells = <1>;
+				#size-cells = <0>;
 				reg = <2>;
 
 				ipu2_di0_disp0: endpoint at 0 {
@@ -262,6 +265,8 @@
 			};
 
 			ipu2_di1: port at 3 {
+				#address-cells = <1>;
+				#size-cells = <0>;
 				reg = <3>;
 
 				ipu2_di1_hdmi: endpoint at 1 {
-- 
2.20.1

[U-Boot] [PATCH v3 00/14] colibri-imx6ull device tree enablement and driver model conversion

[Marcel Ziswiler]

This series addresses some shortcomings, enables/introduces device tree
support and converts all except video to using the driver model. This is
fully tested both running our latest downstream BSP as well as the
mainline Linux kernel.

This series is available together with my previous series addressing
Apalis and Colibri iMX6 as well as Colibri Vybrid aka VF50/VF61 on our
git server [1].

[1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next

Changes in v3:
- Fixed issue with host mode as pointed out by Igor.

Changes in v2:
- Added Igor's reviewed-by tag.

Gerard Salvatella (1):
  tdx-cfg-block: add support for new colibri iMX6ull skus

Marcel Ziswiler (9):
  colibri-imx6ull: fix ethernet phy power on
  colibri-imx6ull: configuration clean-up
  colibri-imx6ull: migrate pinctrl and regulators to dtb/dm
  colibri-imx6ull: migrate mmc to using driver model
  colibri-imx6ull: migrate usb to using driver model
  colibri-imx6ull: migrate fec to using driver model
  ARM: dts: colibri-imx6ull: fix uart-has-rtscts property
  ARM: dts: colibri-imx6ull: add osc32k_32k_out pinctrl
  ARM: dts: colibri-imx6ull: update device tree

Philippe Schenker (1):
  board: imx6ull: Add disable PMIC_STBY_REQ

Stefan Agner (3):
  tdx-cfg-block: simplify i.MX 6 module detection
  colibri-imx6ull: set module variant depending on config block
  apalis/colibri_imx6/imx6ull: make sure loadaddr does not collide

 arch/arm/dts/imx6ull-colibri.dts              | 172 ++++++++-----
 arch/arm/dts/imx6ull-pinfunc.h                |  26 +-
 .../toradex/colibri-imx6ull/colibri-imx6ull.c | 225 +++---------------
 board/toradex/common/tdx-cfg-block.c          |  70 ++++--
 board/toradex/common/tdx-cfg-block.h          |   3 +
 configs/colibri-imx6ull_defconfig             |  18 +-
 include/configs/apalis_imx6.h                 |   4 +-
 include/configs/colibri-imx6ull.h             |  14 +-
 include/configs/colibri_imx6.h                |   4 +-
 9 files changed, 228 insertions(+), 308 deletions(-)

-- 
2.20.1

[U-Boot] [PATCH v3 01/14] tdx-cfg-block: add support for new colibri iMX6ull skus

[Marcel Ziswiler]

From: Gerard Salvatella <gerard.salvatella@toradex.com>

Add support for new Colibri iMX6ULL SKUs.

While at it also checkpatch fix the whole files.

Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 board/toradex/common/tdx-cfg-block.c | 62 +++++++++++++++++++++-------
 board/toradex/common/tdx-cfg-block.h |  3 ++
 2 files changed, 50 insertions(+), 15 deletions(-)

diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index b90077bedc..3b73421243 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (c) 2016 Toradex, Inc.
+ * Copyright (c) 2016-2019 Toradex, Inc.
  */
 
 #include <common.h>
@@ -98,6 +98,9 @@ const char * const toradex_modules[] = {
 	[40] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth IT",
 	[41] = "Colibri iMX7 Dual 512MB EPDC",
 	[42] = "Apalis TK1 4GB",
+	[43] = "Colibri T20 512MB IT SETEK",
+	[44] = "Colibri iMX6ULL 512MB IT",
+	[45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth",
 };
 
 #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
@@ -299,22 +302,47 @@ static int get_cfgblock_interactive(void)
 			else
 				tdx_hw_tag.prodid = APALIS_IMX6D;
 #else
-		if (it == 'y' || it == 'Y')
-			if (is_cpu_type(MXC_CPU_MX6DL))
+		char wb = 'n';
+
+		if (it == 'y' || it == 'Y') {
+			if (is_cpu_type(MXC_CPU_MX6DL)) {
 				tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT;
-			else
+			} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 				tdx_hw_tag.prodid = COLIBRI_IMX6S_IT;
-		else
-			if (is_cpu_type(MXC_CPU_MX6DL))
+			} else {
+				sprintf(message, "Does the module have WiFi /" \
+						 " Bluetooth? [y/N] ");
+				len = cli_readline(message);
+				wb = console_buffer[0];
+				if (wb == 'y' || wb == 'Y')
+					tdx_hw_tag.prodid =
+						COLIBRI_IMX6ULL_WIFI_BT_IT;
+				else
+					tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
+			}
+		} else {
+			if (is_cpu_type(MXC_CPU_MX6DL)) {
 				tdx_hw_tag.prodid = COLIBRI_IMX6DL;
-			else
+			} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 				tdx_hw_tag.prodid = COLIBRI_IMX6S;
+			} else {
+				sprintf(message, "Does the module have WiFi /" \
+						 " Bluetooth? [y/N] ");
+				len = cli_readline(message);
+				wb = console_buffer[0];
+				if (wb == 'y' || wb == 'Y')
+					tdx_hw_tag.prodid =
+						COLIBRI_IMX6ULL_WIFI_BT;
+				else
+					tdx_hw_tag.prodid = COLIBRI_IMX6ULL;
+			}
+		}
 #endif /* CONFIG_MACH_TYPE */
-	} else if (!strcmp("imx7d", soc)) {
+	} else if (!strcmp("imx7d", soc))
 		tdx_hw_tag.prodid = COLIBRI_IMX7D;
-	} else if (!strcmp("imx7s", soc)) {
+	else if (!strcmp("imx7s", soc))
 		tdx_hw_tag.prodid = COLIBRI_IMX7S;
-	} else if (!strcmp("tegra20", soc)) {
+	else if (!strcmp("tegra20", soc)) {
 		if (it == 'y' || it == 'Y')
 			if (gd->ram_size == 0x10000000)
 				tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT;
@@ -330,8 +358,9 @@ static int get_cfgblock_interactive(void)
 			tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ;
 		else
 			tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ;
+	}
 #ifdef CONFIG_MACH_TYPE
-	} else if (!strcmp("tegra30", soc)) {
+	else if (!strcmp("tegra30", soc)) {
 		if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) {
 			if (it == 'y' || it == 'Y')
 				tdx_hw_tag.prodid = APALIS_T30_IT;
@@ -346,8 +375,9 @@ static int get_cfgblock_interactive(void)
 			else
 				tdx_hw_tag.prodid = COLIBRI_T30;
 		}
+	}
 #endif /* CONFIG_MACH_TYPE */
-	} else if (!strcmp("tegra124", soc)) {
+	else if (!strcmp("tegra124", soc)) {
 		tdx_hw_tag.prodid = APALIS_TK1_2GB;
 	} else if (!strcmp("vf500", soc)) {
 		if (it == 'y' || it == 'Y')
@@ -373,7 +403,7 @@ static int get_cfgblock_interactive(void)
 	tdx_hw_tag.ver_minor = console_buffer[2] - '0';
 	tdx_hw_tag.ver_assembly = console_buffer[3] - 'A';
 
-	if (cpu_is_pxa27x() && (tdx_hw_tag.ver_major == 1))
+	if (cpu_is_pxa27x() && tdx_hw_tag.ver_major == 1)
 		tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ -
 				       COLIBRI_PXA270_V1_312MHZ);
 
@@ -441,7 +471,8 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc,
 		 * On NAND devices, recreation is only allowed if the page is
 		 * empty (config block invalid...)
 		 */
-		printf("NAND erase block %d need to be erased before creating a Toradex config block\n",
+		printf("NAND erase block %d need to be erased before creating" \
+		       " a Toradex config block\n",
 		       CONFIG_TDX_CFG_BLOCK_OFFSET /
 		       get_nand_dev_by_index(0)->erasesize);
 		goto out;
@@ -450,7 +481,8 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc,
 		 * On NOR devices, recreation is only allowed if the sector is
 		 * empty and write protection is off (config block invalid...)
 		 */
-		printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n",
+		printf("NOR sector at offset 0x%02x need to be erased and " \
+		       "unprotected before creating a Toradex config block\n",
 		       CONFIG_TDX_CFG_BLOCK_OFFSET);
 		goto out;
 #else
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index da60e789a7..961bb4394f 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -61,6 +61,9 @@ enum {
 	COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */
 	COLIBRI_IMX7D_EPDC,
 	APALIS_TK1_4GB,
+	COLIBRI_T20_512MB_IT_SETEK,
+	COLIBRI_IMX6ULL_IT,
+	COLIBRI_IMX6ULL_WIFI_BT, /* 45 */
 };
 
 extern const char * const toradex_modules[];
-- 
2.20.1

[U-Boot] [PATCH v3 02/14] tdx-cfg-block: simplify i.MX 6 module detection

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Use CONFIG_TARGET_... at compile time to differentiate between
Apalis iMX6, Colibri iMX6 and Colibri iMX6ULL. Avoid code
duplication by moving question about Wi-Fi / Bluetooth before
IT/non-IT decision.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 board/toradex/common/tdx-cfg-block.c | 68 ++++++++++++++--------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index 3b73421243..71ff40cfad 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -280,6 +280,9 @@ static int get_cfgblock_interactive(void)
 	char it = 'n';
 	int len;
 
+	/* Unknown module by default */
+	tdx_hw_tag.prodid = 0;
+
 	if (cpu_is_pxa27x())
 		sprintf(message, "Is the module the 312 MHz version? [y/N] ");
 	else
@@ -290,54 +293,49 @@ static int get_cfgblock_interactive(void)
 
 	soc = env_get("soc");
 	if (!strcmp("mx6", soc)) {
-#ifdef CONFIG_MACH_TYPE
-		if (it == 'y' || it == 'Y')
+#ifdef CONFIG_TARGET_APALIS_IMX6
+		if (it == 'y' || it == 'Y') {
 			if (is_cpu_type(MXC_CPU_MX6Q))
 				tdx_hw_tag.prodid = APALIS_IMX6Q_IT;
 			else
 				tdx_hw_tag.prodid = APALIS_IMX6D_IT;
-		else
+		} else {
 			if (is_cpu_type(MXC_CPU_MX6Q))
 				tdx_hw_tag.prodid = APALIS_IMX6Q;
 			else
 				tdx_hw_tag.prodid = APALIS_IMX6D;
-#else
-		char wb = 'n';
-
+		}
+#elif CONFIG_TARGET_COLIBRI_IMX6
 		if (it == 'y' || it == 'Y') {
-			if (is_cpu_type(MXC_CPU_MX6DL)) {
+			if (is_cpu_type(MXC_CPU_MX6DL))
 				tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT;
-			} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+			else if (is_cpu_type(MXC_CPU_MX6SOLO))
 				tdx_hw_tag.prodid = COLIBRI_IMX6S_IT;
-			} else {
-				sprintf(message, "Does the module have WiFi /" \
-						 " Bluetooth? [y/N] ");
-				len = cli_readline(message);
-				wb = console_buffer[0];
-				if (wb == 'y' || wb == 'Y')
-					tdx_hw_tag.prodid =
-						COLIBRI_IMX6ULL_WIFI_BT_IT;
-				else
-					tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
-			}
 		} else {
-			if (is_cpu_type(MXC_CPU_MX6DL)) {
+			if (is_cpu_type(MXC_CPU_MX6DL))
 				tdx_hw_tag.prodid = COLIBRI_IMX6DL;
-			} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+			else if (is_cpu_type(MXC_CPU_MX6SOLO))
 				tdx_hw_tag.prodid = COLIBRI_IMX6S;
-			} else {
-				sprintf(message, "Does the module have WiFi /" \
-						 " Bluetooth? [y/N] ");
-				len = cli_readline(message);
-				wb = console_buffer[0];
-				if (wb == 'y' || wb == 'Y')
-					tdx_hw_tag.prodid =
-						COLIBRI_IMX6ULL_WIFI_BT;
-				else
-					tdx_hw_tag.prodid = COLIBRI_IMX6ULL;
-			}
 		}
-#endif /* CONFIG_MACH_TYPE */
+#elif CONFIG_TARGET_COLIBRI_IMX6ULL
+		char wb = 'n';
+
+		sprintf(message, "Does the module have Wi-Fi / Bluetooth? " \
+				 "[y/N] ");
+		len = cli_readline(message);
+		wb = console_buffer[0];
+		if (it == 'y' || it == 'Y') {
+			if (wb == 'y' || wb == 'Y')
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
+		} else {
+			if (wb == 'y' || wb == 'Y')
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL;
+		}
+#endif
 	} else if (!strcmp("imx7d", soc))
 		tdx_hw_tag.prodid = COLIBRI_IMX7D;
 	else if (!strcmp("imx7s", soc))
@@ -389,7 +387,9 @@ static int get_cfgblock_interactive(void)
 			tdx_hw_tag.prodid = COLIBRI_VF61_IT;
 		else
 			tdx_hw_tag.prodid = COLIBRI_VF61;
-	} else {
+	}
+
+	if (!tdx_hw_tag.prodid) {
 		printf("Module type not detectable due to unknown SoC\n");
 		return -1;
 	}
-- 
2.20.1

[U-Boot] [PATCH v3 03/14] colibri-imx6ull: set module variant depending on config block

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Using CPU temperature grading as a discriminator if the Wi-Fi /
Bluetooth chip is populated is no longer possible due to upcoming
SKUs. Set variant to -wifi only if a valid config block is present
and the product id mentions a SKU with Wi-Fi / Bluetooth.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 board/toradex/colibri-imx6ull/colibri-imx6ull.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index fcb49a0718..fe60b8e870 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -29,6 +29,7 @@
 #include <usb.h>
 #include <usb/ehci-ci.h>
 #include "../common/tdx-common.h"
+#include "../common/tdx-cfg-block.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -317,10 +318,15 @@ static const struct boot_mode board_boot_modes[] = {
 
 int board_late_init(void)
 {
-	int minc, maxc;
-
-	if (get_cpu_temp_grade(&minc, &maxc) != TEMP_COMMERCIAL)
+#ifdef CONFIG_TDX_CFG_BLOCK
+	/*
+	 * If we have a valid config block and it says we are a module with
+	 * Wi-Fi/Bluetooth make sure we use the -wifi device tree.
+	 */
+	if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT ||
+	    tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT)
 		env_set("variant", "-wifi");
+#endif
 
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
-- 
2.20.1

[U-Boot] [PATCH v3 04/14] apalis/colibri_imx6/imx6ull: make sure loadaddr does not collide

[Marcel Ziswiler]

From: Stefan Agner <stefan.agner@toradex.com>

Currently $loadaddr and $fdt_addr_r point to the same address. This
might be not ideal for some distro boot scripts which make use of
$loadaddr after loading the device tree.

Make sure the two variables point to two different addresses. Moving
$loadaddr is not entirly trivial since it is defined in mx6_common.h.
Move $fdt_addr_r and $ramdisk_addr_r by 1MiB, which should be enough
for scripts.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 include/configs/apalis_imx6.h     | 4 ++--
 include/configs/colibri-imx6ull.h | 4 ++--
 include/configs/colibri_imx6.h    | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 96169f55f0..91054d8c05 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -138,12 +138,12 @@
 
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0x20000000\0" \
-	"fdt_addr_r=0x12000000\0" \
+	"fdt_addr_r=0x12100000\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"kernel_addr_r=0x11000000\0" \
 	"pxefile_addr_r=0x17100000\0" \
-	"ramdisk_addr_r=0x12100000\0" \
+	"ramdisk_addr_r=0x12200000\0" \
 	"scriptaddr=0x17000000\0"
 
 #define NFS_BOOTCMD \
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index 7cf550cf9e..31248b14a1 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -48,12 +48,12 @@
 
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0x10000000\0" \
-	"fdt_addr_r=0x82000000\0" \
+	"fdt_addr_r=0x82100000\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"kernel_addr_r=0x81000000\0" \
 	"pxefile_addr_r=0x87100000\0" \
-	"ramdisk_addr_r=0x82100000\0" \
+	"ramdisk_addr_r=0x82200000\0" \
 	"scriptaddr=0x87000000\0"
 
 #define NFS_BOOTCMD \
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 803c9be064..fecea95d32 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -128,12 +128,12 @@
 
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0x10000000\0" \
-	"fdt_addr_r=0x12000000\0" \
+	"fdt_addr_r=0x12100000\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"kernel_addr_r=0x11000000\0" \
 	"pxefile_addr_r=0x17100000\0" \
-	"ramdisk_addr_r=0x12100000\0" \
+	"ramdisk_addr_r=0x12200000\0" \
 	"scriptaddr=0x17000000\0"
 
 #define NFS_BOOTCMD \
-- 
2.20.1

[U-Boot] [PATCH v3 05/14] colibri-imx6ull: fix ethernet phy power on

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Just give the new Ethernet PHY power save mode circuitry time to settle.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by tag.

 board/toradex/colibri-imx6ull/colibri-imx6ull.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index fe60b8e870..b6f45edb86 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -263,6 +263,9 @@ static int setup_fec(void)
 			IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
 			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 
+	/* give new Ethernet PHY power save mode circuitry time to settle */
+	mdelay(300);
+
 	return 0;
 }
 
-- 
2.20.1

[U-Boot] [PATCH v3 06/14] board: imx6ull: Add disable PMIC_STBY_REQ

[Marcel Ziswiler]

From: Philippe Schenker <philippe.schenker@toradex.com>

Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the
SOC to request for a lower voltage during sleep. This is necessary
because the voltage is changing too slow for the SOC to wake up
properly.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 board/toradex/colibri-imx6ull/colibri-imx6ull.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index b6f45edb86..f1d5cc6655 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -50,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
 		PAD_CTL_DSE_48ohm)
 
+#define MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR 0x2290040
+
 #define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
 
 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
@@ -331,6 +333,14 @@ int board_late_init(void)
 		env_set("variant", "-wifi");
 #endif
 
+	/*
+	 * Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the
+	 * SOC to request for a lower voltage during sleep. This is necessary
+	 * because the voltage is changing too slow for the SOC to wake up
+	 * properly.
+	 */
+	__raw_writel(0x8080, MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR);
+
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
-- 
2.20.1

[U-Boot] [PATCH v3 07/14] colibri-imx6ull: configuration clean-up

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Drop disabling SPL_SYS_THUMB_BUILD as we anyway do not use SPL.
Enbale CRC32 verify, USB SDP and EFI loader support.
Drop CMD_GPT and disabling RANDOM_UUID.
Do savedefconfig which drops USB_FUNCTION_SDP.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 configs/colibri-imx6ull_defconfig | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index dfe6ec1ce7..b19b3b7fb2 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
-# CONFIG_SPL_SYS_THUMB_BUILD is not set
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_COLIBRI_IMX6ULL=y
@@ -18,19 +17,20 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
+# CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_ASKENV=y
+CONFIG_CRC32_VERIFY=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_NAND_TORTURE=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
@@ -73,8 +73,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_SDP=y
 CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_FDT_FIXUP_PARTITIONS=y
-# CONFIG_EFI_LOADER is not set
-- 
2.20.1

[U-Boot] [PATCH v3 08/14] colibri-imx6ull: migrate pinctrl and regulators to dtb/dm

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate pinctrl and regulators to device tree resp. driver model:
Ethernet, NAND and UART.
Drop BOARD_EARLY_INIT_F as it is anyway no longer used.
Enable CMD_DM, CMD_MTD, CMD_REGULATOR and DM_REGULATOR_FIXED.
While at it also update copyright period.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 .../toradex/colibri-imx6ull/colibri-imx6ull.c | 82 ++-----------------
 configs/colibri-imx6ull_defconfig             |  5 +-
 2 files changed, 10 insertions(+), 77 deletions(-)

diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index f1d5cc6655..8493b1dfdd 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -1,8 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2018 Toradex AG
+ * Copyright (C) 2018-2019 Toradex AG
  */
 #include <common.h>
+
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/imx-regs.h>
@@ -14,7 +15,6 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/io.h>
-#include <common.h>
 #include <dm.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <fdt_support.h>
@@ -28,25 +28,16 @@
 #include <netdev.h>
 #include <usb.h>
 #include <usb/ehci-ci.h>
+
 #include "../common/tdx-common.h"
 #include "../common/tdx-cfg-block.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-#define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_40ohm)
-
-#define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm)
-
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
 		PAD_CTL_DSE_48ohm)
 
@@ -65,13 +56,6 @@ int dram_init(void)
 	return 0;
 }
 
-static iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_UART1_TX_DATA__UART1_DTE_RX	| MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_UART1_RX_DATA__UART1_DTE_TX	| MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_UART1_RTS_B__UART1_DTE_CTS	| MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_UART1_CTS_B__UART1_DTE_RTS	| MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 #ifdef CONFIG_FSL_ESDHC
 static iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_SD1_CLK__USDHC1_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -90,31 +74,12 @@ static iomux_v3_cfg_t const usb_cdet_pads[] = {
 };
 
 #ifdef CONFIG_NAND_MXS
-static iomux_v3_cfg_t const gpmi_pads[] = {
-	MX6_PAD_NAND_DATA00__RAWNAND_DATA00	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA01__RAWNAND_DATA01	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA02__RAWNAND_DATA02	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA03__RAWNAND_DATA03	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA04__RAWNAND_DATA04	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_RE_B__RAWNAND_RE_B		| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_WE_B__RAWNAND_WE_B		| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NAND_READY_B__RAWNAND_READY_B	| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
-};
-
 static void setup_gpmi_nand(void)
 {
-	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
-
 	setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
 			  (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
 }
-#endif
+#endif /* CONFIG_NAND_MXS */
 
 #ifdef CONFIG_VIDEO_MXS
 static iomux_v3_cfg_t const lcd_pads[] = {
@@ -170,31 +135,6 @@ static int setup_lcd(void)
 }
 #endif
 
-#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const fec2_pads[] = {
-	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2		| MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
-	MX6_PAD_GPIO1_IO06__ENET2_MDIO			| MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
-	MX6_PAD_GPIO1_IO07__ENET2_MDC			| MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
-	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00		| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01		| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER		| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN		| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_fec(void)
-{
-	imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
-}
-#endif
-
-static void setup_iomux_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
 #ifdef CONFIG_FSL_ESDHC
 
 #define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 0)
@@ -247,20 +187,17 @@ int board_mmc_init(bd_t *bis)
 #endif
 
 #ifdef CONFIG_FEC_MXC
-
 static int setup_fec(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int ret;
 
-	setup_iomux_fec();
-
 	/* provide the PHY clock from the i.MX 6 */
 	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
 	if (ret)
 		return ret;
 
-	/* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */
+	/* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */
 	clrsetbits_le32(&iomuxc_regs->gpr[1],
 			IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
 			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
@@ -277,14 +214,7 @@ int board_phy_config(struct phy_device *phydev)
 		phydev->drv->config(phydev);
 	return 0;
 }
-#endif
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-
-	return 0;
-}
+#endif /* CONFIG_FEC_MXC */
 
 int board_init(void)
 {
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index b19b3b7fb2..ce2c09338d 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -15,7 +15,6 @@ CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOUNCE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
@@ -24,9 +23,11 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CRC32_VERIFY=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_DFU=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_NAND_TORTURE=y
 CONFIG_CMD_USB=y
@@ -34,6 +35,7 @@ CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx6ull-bcb),1536k(u-boot1)ro,1536k(u-boot2)ro,512k(u-boot-env),-(ubi)"
@@ -63,6 +65,7 @@ CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
-- 
2.20.1

[U-Boot] [PATCH v3 09/14] colibri-imx6ull: migrate mmc to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate MMC to using driver model.
Migrate USDHC to using pinctrl.
While at it also add GPIO1_IO03__OSC32K_32K_OUT pin muxing.
While at it also update copyright period.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts              | 15 +++-
 .../toradex/colibri-imx6ull/colibri-imx6ull.c | 70 -------------------
 configs/colibri-imx6ull_defconfig             |  1 +
 include/configs/colibri-imx6ull.h             |  6 +-
 4 files changed, 17 insertions(+), 75 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 95c67be438..0d416ebd10 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2019 Toradex AG
  */
 
 /dts-v1/;
@@ -11,6 +11,10 @@
 	model = "Toradex Colibri iMX6ULL";
 	compatible = "toradex,imx6ull-colibri", "fsl,imx6ull";
 
+	aliases {
+		mmc0 = &usdhc1;
+	};
+
 	chosen {
 		stdout-path = &uart1;
 	};
@@ -190,10 +194,18 @@
 	dr_mode = "host";
 };
 
+/* Colibri MMC */
 &usdhc1 {
 	assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
 	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
 	assigned-clock-rates = <0>, <198000000>;
+	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
 };
 
 &iomuxc {
@@ -547,4 +559,3 @@
 		>;
 	};
 };
-
diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index 8493b1dfdd..c9af44e30e 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -18,11 +18,9 @@
 #include <dm.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <fdt_support.h>
-#include <fsl_esdhc.h>
 #include <imx_thermal.h>
 #include <jffs2/load_kernel.h>
 #include <linux/sizes.h>
-#include <mmc.h>
 #include <miiphy.h>
 #include <mtd_node.h>
 #include <netdev.h>
@@ -34,10 +32,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
 		PAD_CTL_DSE_48ohm)
 
@@ -56,19 +50,6 @@ int dram_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_FSL_ESDHC
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-	MX6_PAD_SD1_CLK__USDHC1_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_CMD__USDHC1_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA0__USDHC1_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA1__USDHC1_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA2__USDHC1_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA3__USDHC1_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
-	MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-#endif
-
 static iomux_v3_cfg_t const usb_cdet_pads[] = {
 	MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
@@ -135,57 +116,6 @@ static int setup_lcd(void)
 }
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
-
-#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 0)
-
-static struct fsl_esdhc_cfg usdhc_cfg[] = {
-	{USDHC1_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC1_BASE_ADDR:
-		ret = !gpio_get_value(USDHC1_CD_GPIO);
-		break;
-	}
-
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int i, ret;
-
-	/* USDHC1 is mmc0 */
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
-							 ARRAY_SIZE(usdhc1_pads));
-			gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
-			gpio_direction_input(USDHC1_CD_GPIO);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-				"(%d) than supported by the board\n", i + 1);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_FEC_MXC
 static int setup_fec(void)
 {
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index ce2c09338d..69305323f2 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -50,6 +50,7 @@ CONFIG_DFU_NAND=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_NAND=y
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index 31248b14a1..7a7a70e457 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2019 Toradex AG
  *
  * Configuration settings for the Colibri iMX6ULL module.
  *
@@ -30,7 +30,7 @@
 /* ENET1 */
 #define IMX_FEC_BASE			ENET2_BASE_ADDR
 
-/* MMC Config*/
+/* MMC Config */
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_USDHC_NUM	1
 
@@ -182,4 +182,4 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #endif
 
-#endif
+#endif /* __COLIBRI_IMX6ULL_CONFIG_H */
-- 
2.20.1

[U-Boot] [PATCH v3 10/14] colibri-imx6ull: migrate usb to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate USB to using driver model.
Add USBH_PEN GPIO regulator.
While at it also add alias e.g. as required for UMS.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3:
- Fixed issue with host mode as pointed out by Igor.

Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts              | 26 +++++++++-
 .../toradex/colibri-imx6ull/colibri-imx6ull.c | 48 -------------------
 configs/colibri-imx6ull_defconfig             |  1 +
 3 files changed, 26 insertions(+), 49 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 0d416ebd10..42ae70deff 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -13,6 +13,7 @@
 
 	aliases {
 		mmc0 = &usdhc1;
+		usb0 = &usbotg1; /* required for ums */
 	};
 
 	chosen {
@@ -35,6 +36,13 @@
 		regulator-max-microvolt = <3300000>;
 	};
 
+	reg_5v0: regulator-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
 	reg_sd1_vmmc: regulator-sd1-vmmc {
 		compatible = "regulator-gpio";
 		gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
@@ -47,6 +55,17 @@
 		states = <1800000 0x1 3300000 0x0>;
 		vin-supply = <&reg_module_3v3>;
 	};
+
+	reg_usbh_vbus: regulator-usbh-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh_reg>;
+		regulator-name = "VCC_USB[1-4]";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
+		vin-supply = <&reg_5v0>;
+	};
 };
 
 &adc1 {
@@ -183,15 +202,20 @@
 	fsl,dte-mode;
 };
 
+/* Colibri USBC */
 &usbotg1 {
-	dr_mode = "otg";
+	dr_mode = "host";
 	srp-disable;
 	hnp-disable;
 	adp-disable;
+	status = "okay";
 };
 
+/* Colibri USBH */
 &usbotg2 {
 	dr_mode = "host";
+	vbus-supply = <&reg_usbh_vbus>;
+	status = "okay";
 };
 
 /* Colibri MMC */
diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index c9af44e30e..21addaf6ed 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -24,8 +24,6 @@
 #include <miiphy.h>
 #include <mtd_node.h>
 #include <netdev.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
 
 #include "../common/tdx-common.h"
 #include "../common/tdx-cfg-block.h"
@@ -41,8 +39,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
 
-#define USB_CDET_GPIO	IMX_GPIO_NR(7, 14)
-
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -50,10 +46,6 @@ int dram_init(void)
 	return 0;
 }
 
-static iomux_v3_cfg_t const usb_cdet_pads[] = {
-	MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
 #ifdef CONFIG_NAND_MXS
 static void setup_gpmi_nand(void)
 {
@@ -163,11 +155,6 @@ int board_init(void)
 	setup_lcd();
 #endif
 
-#ifdef CONFIG_USB_EHCI_MX6
-	imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
-	gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
-#endif
-
 	return 0;
 }
 
@@ -241,41 +228,6 @@ int ft_board_setup(void *blob, bd_t *bd)
 }
 #endif
 
-#ifdef CONFIG_USB_EHCI_MX6
-static iomux_v3_cfg_t const usb_otg2_pads[] = {
-		MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_ehci_hcd_init(int port)
-{
-	switch (port) {
-	case 0:
-		break;
-	case 1:
-		imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
-						 ARRAY_SIZE(usb_otg2_pads));
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-int board_usb_phy_mode(int port)
-{
-	switch (port) {
-	case 0:
-		if (gpio_get_value(USB_CDET_GPIO))
-			return USB_INIT_DEVICE;
-		else
-			return USB_INIT_HOST;
-	case 1:
-	default:
-		return USB_INIT_HOST;
-	}
-}
-#endif
-
 static struct mxc_serial_platdata mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART1_BASE,
 	.use_dte = 1,
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index 69305323f2..0440b4ed94 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -71,6 +71,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-- 
2.20.1

[U-Boot] [PATCH v3 11/14] colibri-imx6ull: migrate fec to using driver model

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Migrate Ethernet FEC to using driver model.
Drop PHY_MICREL_KSZ90X1 which slipped in from Apalis iMX6.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts  | 31 ++++++++++++++++---------------
 configs/colibri-imx6ull_defconfig |  3 +--
 include/configs/colibri-imx6ull.h |  4 ----
 3 files changed, 17 insertions(+), 21 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 42ae70deff..adb10ac8ca 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -80,6 +80,7 @@
 	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
 };
 
+/* Ethernet */
 &fec2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet2>;
@@ -233,6 +234,21 @@
 };
 
 &iomuxc {
+	pinctrl_enet2: enet2-grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
+			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+		>;
+	};
+
 	pinctrl_gpio1: gpio1-grp {
 		fsl,pins = <
 			MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00	0x74 /* SODIMM 55 */
@@ -295,21 +311,6 @@
 		>;
 	};
 
-	pinctrl_enet2: enet2-grp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
-			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
-			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
-			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
-			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
-		>;
-	};
-
 	pinctrl_ecspi1_cs: ecspi1-cs-grp {
 		fsl,pins = <
 			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x000a0
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index 0440b4ed94..a24c87f321 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -58,9 +58,8 @@ CONFIG_NAND_MXS=y
 CONFIG_NAND_MXS_DT=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_PHYLIB=y
-CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index 7a7a70e457..fc39e807b6 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -19,10 +19,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
 
 /* Network */
-#define CONFIG_FEC_XCV_TYPE             RMII
-#define CONFIG_ETHPRIME                 "FEC"
-#define CONFIG_FEC_MXC_PHYADDR		0
-
 #define CONFIG_IP_DEFRAG
 #define CONFIG_TFTP_BLOCKSIZE		16352
 #define CONFIG_TFTP_TSIZE
-- 
2.20.1

[U-Boot] [PATCH v3 12/14] ARM: dts: colibri-imx6ull: fix uart-has-rtscts property

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Remove vendor pre-fix fsl, from uart-has-rtscts property.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index adb10ac8ca..6a2a934dff 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -182,21 +182,24 @@
 	status = "disabled";
 };
 
+/* Colibri UART_A */
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
-	fsl,uart-has-rtscts;
+	uart-has-rtscts;
 	fsl,dte-mode;
 	status = "okay";
 };
 
+/* Colibri UART_B */
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart2>;
-	fsl,uart-has-rtscts;
+	uart-has-rtscts;
 	fsl,dte-mode;
 };
 
+/* Colibri UART_C */
 &uart5 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart5>;
-- 
2.20.1

[U-Boot] [PATCH v3 13/14] ARM: dts: colibri-imx6ull: add osc32k_32k_out pinctrl

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Add GPIO1_IO03__OSC32K_32K_OUT pin muxing.
While at it also fix indentation of pinfunc header file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts |  2 ++
 arch/arm/dts/imx6ull-pinfunc.h   | 26 ++++++++++++++------------
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 6a2a934dff..a827e9ceeb 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -524,6 +524,8 @@
 			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
 			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
 			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x17059
+
+			MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT	0x14
 		>;
 	};
 };
diff --git a/arch/arm/dts/imx6ull-pinfunc.h b/arch/arm/dts/imx6ull-pinfunc.h
index fca003680b..7770ed39f6 100644
--- a/arch/arm/dts/imx6ull-pinfunc.h
+++ b/arch/arm/dts/imx6ull-pinfunc.h
@@ -14,6 +14,8 @@
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>
  */
+#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT                     0x0068 0x02f4 0x0000 0x3 0x0
+
 #define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08                    0x00E4 0x0370 0x0000 0x9 0x0
 #define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09                    0x00E8 0x0374 0x0000 0x9 0x0
 #define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10                       0x00EC 0x0378 0x0000 0x9 0x0
@@ -41,17 +43,17 @@
 #define MX6UL_PAD_LCD_DATA17__EPDC_GDSP                          0x015C 0x03E8 0x0000 0x9 0x0
 #define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1                         0x016C 0x03F8 0x0000 0x9 0x0
 
-#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2                          0x01D4 0x0460 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3                        0x01D8 0x0464 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1                         0x01DC 0x0468 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1                             0x01E0 0x046C 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK                      0x01E4 0x0470 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK                      0x01E8 0x0474 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS                          0x01EC 0x0478 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK                         0x01F0 0x047C 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS                          0x01F4 0x0480 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK                         0x01F8 0x0484 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0                        0x01FC 0x0488 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA07__ESAI_T0                             0x0200 0x048C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2                         0x01D4 0x0460 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3                       0x01D8 0x0464 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1                        0x01DC 0x0468 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1                            0x01E0 0x046C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK                     0x01E4 0x0470 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK                     0x01E8 0x0474 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS                         0x01EC 0x0478 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK                        0x01F0 0x047C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS                         0x01F4 0x0480 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK                        0x01F8 0x0484 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0                       0x01FC 0x0488 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA07__ESAI_T0                            0x0200 0x048C 0x0000 0x9 0x0
 
 #endif /* __DTS_IMX6ULL_PINFUNC_H */
-- 
2.20.1

[U-Boot] [PATCH v3 14/14] ARM: dts: colibri-imx6ull: update device tree

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Fix compatible node to use regular Toradex notation.
Annotate device tree with standard Colibri pin muxing comments.
Use open-drain I2C pin muxings.
Alphabetically re-order iomuxc nodes.
Rename snvs-ad7879-int-grp touch interrupt node as per Linux device tree.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

---

Changes in v3: None
Changes in v2:
- Added Igor's reviewed-by.

 arch/arm/dts/imx6ull-colibri.dts | 91 ++++++++++++++++++--------------
 1 file changed, 52 insertions(+), 39 deletions(-)

diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index a827e9ceeb..6c847ab792 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -9,7 +9,7 @@
 
 / {
 	model = "Toradex Colibri iMX6ULL";
-	compatible = "toradex,imx6ull-colibri", "fsl,imx6ull";
+	compatible = "toradex,colibri-imx6ull", "fsl,imx6ull";
 
 	aliases {
 		mmc0 = &usdhc1;
@@ -100,6 +100,7 @@
 	};
 };
 
+/* NAND */
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
@@ -110,21 +111,28 @@
 	status = "okay";
 };
 
+/*
+ * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
 &i2c1 {
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
-	scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+	sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 };
 
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
 &i2c2 {
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2>;
 	pinctrl-1 = <&pinctrl_i2c2_gpio>;
-	sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
-	scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+	sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
 	ad7879 at 2c {
@@ -150,24 +158,28 @@
 		     &pinctrl_lcdif_ctrl>;
 };
 
+/* PWM <A> */
 &pwm4 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm4>;
 	#pwm-cells = <3>;
 };
 
+/* PWM <B> */
 &pwm5 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm5>;
 	#pwm-cells = <3>;
 };
 
+/* PWM <C> */
 &pwm6 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm6>;
 	#pwm-cells = <3>;
 };
 
+/* PWM <D> */
 &pwm7 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm7>;
@@ -237,6 +249,13 @@
 };
 
 &iomuxc {
+	pinctrl_can_int: canint-grp {
+		fsl,pins = <
+			/* SODIMM 73 */
+			MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04	0X14
+		>;
+	};
+
 	pinctrl_enet2: enet2-grp {
 		fsl,pins = <
 			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
@@ -252,6 +271,33 @@
 		>;
 	};
 
+	pinctrl_ecspi1_cs: ecspi1-cs-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x000a0
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x000a0
+			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x000a0
+			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x100a0
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2-grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX	0x1b020
+			MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX	0x1b020
+		>;
+	};
+
+	pinctrl_gpio_bl_on: gpio-bl-on-grp {
+		fsl,pins = <
+			MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x000a0
+		>;
+	};
+
 	pinctrl_gpio1: gpio1-grp {
 		fsl,pins = <
 			MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00	0x74 /* SODIMM 55 */
@@ -308,39 +354,6 @@
 		>;
 	};
 
-	pinctrl_can_int: canint-grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04	0X14 /* SODIMM 73 */
-		>;
-	};
-
-	pinctrl_ecspi1_cs: ecspi1-cs-grp {
-		fsl,pins = <
-			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x000a0
-		>;
-	};
-
-	pinctrl_ecspi1: ecspi1-grp {
-		fsl,pins = <
-			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x000a0
-			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x000a0
-			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x100a0
-		>;
-	};
-
-	pinctrl_flexcan2: flexcan2-grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX	0x1b020
-			MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX	0x1b020
-		>;
-	};
-
-	pinctrl_gpio_bl_on: gpio-bl-on-grp {
-		fsl,pins = <
-			MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x000a0
-		>;
-	};
-
 	pinctrl_gpmi_nand: gpmi-nand-grp {
 		fsl,pins = <
 			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x100a9
@@ -553,7 +566,7 @@
 		>;
 	};
 
-	pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */
+	pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
 		fsl,pins = <
 			MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x1b0b0
 		>;
-- 
2.20.1

[U-Boot] [PATCH] ddr: imx8m: hide i.MX8M DDR options from device driver entry

[Peng Fan]

Use one menu to hide the several i.MX8M DDR options from device
driver entry.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/ddr/imx/imx8m/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig
index 71f466f5ec..a83b0f43d7 100644
--- a/drivers/ddr/imx/imx8m/Kconfig
+++ b/drivers/ddr/imx/imx8m/Kconfig
@@ -1,3 +1,6 @@
+menu "i.MX8M DDR controllers"
+	depends on ARCH_IMX8M
+
 config IMX8M_DRAM
 	bool "imx8m dram"
 
@@ -20,3 +23,4 @@ config SAVED_DRAM_TIMING_BASE
 	  info into memory for low power use. OCRAM_S is used for this
 	  purpose on i.MX8MM.
 	default 0x180000
+endmenu
-- 
2.16.4

[U-Boot] [PATCH 6/8] imx8: cpu: get temperature when print cpu desc

[Stefano Babic]

Hi Peng,

On 12/04/19 09:55, Peng Fan wrote:
> Read the temperature when print cpu inforation.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/mach-imx/imx8/cpu.c | 35 +++++++++++++++++++++++++++++++++--
>  1 file changed, 33 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
> index 4bbc956f9d..25b010489b 100644
> --- a/arch/arm/mach-imx/imx8/cpu.c
> +++ b/arch/arm/mach-imx/imx8/cpu.c
> @@ -11,6 +11,7 @@
>  #include <dm/lists.h>
>  #include <dm/uclass.h>
>  #include <errno.h>
> +#include <thermal.h>
>  #include <asm/arch/sci/sci.h>
>  #include <asm/arch/sys_proto.h>
>  #include <asm/arch-imx/cpu.h>
> @@ -571,15 +572,45 @@ const char *get_core_name(void)
>  		return "?";
>  }
>  
> +#if defined(CONFIG_IMX_SCU_THERMAL)
> +static int cpu_imx_get_temp(void)
> +{

This generates a warning when CONFIG_IMX_SCU_THERMAL is not set, because
it is called later:

> +	struct udevice *thermal_dev;
> +	int cpu_tmp, ret;
> +
> +	ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0",
> +					&thermal_dev);
> +
> +	if (!ret) {
> +		ret = thermal_get_temp(thermal_dev, &cpu_tmp);
> +		if (ret)
> +			return 0xdeadbeef;
> +	} else {
> +		return 0xdeadbeef;
> +	}
> +
> +	return cpu_tmp;
> +}
> +#endif
> +
>  int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
>  {
>  	struct cpu_imx_platdata *plat = dev_get_platdata(dev);
> +	int ret;
>  
>  	if (size < 100)
>  		return -ENOSPC;
>  
> -	snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n",
> -		 plat->type, plat->rev, plat->name, plat->freq_mhz);
> +	ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
> +		       plat->type, plat->rev, plat->name, plat->freq_mhz);
> +
> +	if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
> +		buf = buf + ret;
> +		size = size - ret;
> +		ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
                                                        ^--- here it is
referenced.

Regards,
Stefano

> +	}
> +
> +	snprintf(buf + ret, size - ret, "\n");
>  
>  	return 0;
>  }
> 


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Stefano Babic]

Hi Marcel,

On 09/04/19 17:25, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> This commit adds initial support for the Toradex Colibri iMX8QXP 2GB WB
> IT V1.0B module. Unlike the V1.0A early access samples exclusively
> booting from SD card, they are now strapped to boot from eFuses which
> are factory fused to properly boot from their on-module eMMC. U-Boot
> supports either booting from the on-module eMMC or may be used for
> recovery purpose using the universal update utility (uuu) aka mfgtools
> 3.0.
> 
> Functionality wise the following is known to be working:
> - eMMC and MMC/SD card
> - Ethernet
> - GPIOs
> - I2C
> 
> Unfortunately, there is no USB functionality for the i.MX 8QXP as of
> yet.
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> ---
> 

I merged the series and build locally (fine), but Travis complains and
stops with error:

+cc1: fatal error: opening output file spl/u-boot-spl.cfgout: No such
file or directory
+compilation terminated.

Can you take a look at it ?

Regards,
Stefano

> Changes in v2:
> - Changed imx-atf git clone command to include initial branch
>   information as suggested by Igor.
> - Sorted board file includes alphabetically as suggested by Igor.
> - Got rid of SPL configuration in legacy header file as suggested by
>   Igor and the whole use of SPL on i.MX 8X anyway neither works well
>   nor makes any much sense at all.
> 
>  arch/arm/dts/Makefile                         |   4 +-
>  arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi  | 112 ++++++
>  arch/arm/dts/fsl-imx8qxp-colibri.dts          | 328 ++++++++++++++++++
>  arch/arm/mach-imx/imx8/Kconfig                |   6 +
>  board/toradex/colibri-imx8qxp/Kconfig         |  30 ++
>  board/toradex/colibri-imx8qxp/MAINTAINERS     |   9 +
>  board/toradex/colibri-imx8qxp/Makefile        |   7 +
>  board/toradex/colibri-imx8qxp/README          |  66 ++++
>  .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 212 +++++++++++
>  board/toradex/colibri-imx8qxp/imximage.cfg    |  24 ++
>  configs/colibri-imx8qxp_defconfig             |  53 +++
>  include/configs/colibri-imx8qxp.h             | 214 ++++++++++++
>  12 files changed, 1064 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
>  create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts
>  create mode 100644 board/toradex/colibri-imx8qxp/Kconfig
>  create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS
>  create mode 100644 board/toradex/colibri-imx8qxp/Makefile
>  create mode 100644 board/toradex/colibri-imx8qxp/README
>  create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
>  create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg
>  create mode 100644 configs/colibri-imx8qxp_defconfig
>  create mode 100644 include/configs/colibri-imx8qxp.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 13d1d67624..2a551d42a4 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -559,7 +559,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
>  
>  dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
>  
> -dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
> +dtb-$(CONFIG_ARCH_IMX8) += \
> +	fsl-imx8qxp-colibri.dtb \
> +	fsl-imx8qxp-mek.dtb
>  
>  dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
>  
> diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> new file mode 100644
> index 0000000000..f8686befdf
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> @@ -0,0 +1,112 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR X11
> +/*
> + * Copyright 2019 Toradex AG
> + */
> +
> +&mu {
> +	u-boot,dm-spl;
> +};
> +
> +&clk {
> +	u-boot,dm-spl;
> +};
> +
> +&iomuxc {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio0 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio1 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio2 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio3 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio4 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio5 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio6 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_lsio_gpio7 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_conn {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_conn_sdch0 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_conn_sdch1 {
> +	u-boot,dm-spl;
> +};
> +
> +&pd_conn_sdch2 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio0 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio1 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio2 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio3 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio4 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio5 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio6 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio7 {
> +	u-boot,dm-spl;
> +};
> +
> +&lpuart3 {
> +	u-boot,dm-spl;
> +};
> +
> +&usdhc1 {
> +	u-boot,dm-spl;
> +};
> +
> +&usdhc2 {
> +	u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts
> new file mode 100644
> index 0000000000..0c20edf2cf
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts
> @@ -0,0 +1,328 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR X11
> +/*
> + * Copyright 2019 Toradex AG
> + */
> +
> +/dts-v1/;
> +
> +#include "fsl-imx8qxp.dtsi"
> +#include "fsl-imx8qxp-colibri-u-boot.dtsi"
> +
> +/ {
> +	model = "Toradex Colibri iMX8QXP";
> +	compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";
> +
> +	chosen {
> +		bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
> +		stdout-path = &lpuart3;
> +	};
> +
> +	reg_usbh_vbus: regulator-usbh-vbus {
> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_usbh1_reg>;
> +		regulator-name = "usbh_vbus";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
> +
> +	colibri-imx8qxp {
> +		pinctrl_lpuart0: lpuart0grp {
> +			fsl,pins = <
> +				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
> +				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
> +			>;
> +		};
> +
> +		pinctrl_lpuart3: lpuart3grp {
> +			fsl,pins = <
> +				SC_P_FLEXCAN2_RX_ADMA_UART3_RX	0x06000020
> +				SC_P_FLEXCAN2_TX_ADMA_UART3_TX	0x06000020
> +			>;
> +		};
> +
> +		pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
> +			fsl,pins = <
> +				SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */
> +				SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x00000020 /* CTS */
> +				SC_P_SAI1_RXC_LSIO_GPIO0_IO30		0x00000020 /* RTS */
> +				SC_P_CSI_RESET_LSIO_GPIO3_IO03		0x00000020 /* DSR */
> +				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x00000020 /* DCD */
> +				SC_P_CSI_EN_LSIO_GPIO3_IO02		0x00000020 /* RI */
> +			>;
> +		};
> +
> +		pinctrl_fec1: fec1grp {
> +			fsl,pins = <
> +				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0 /* Use pads in 3.3V mode */
> +				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0 /* Use pads in 3.3V mode */
> +				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
> +				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
> +				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000061
> +				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000061
> +				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000061
> +				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000061
> +				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000061
> +				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000061
> +				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000061
> +				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x00000061
> +			>;
> +		};
> +
> +		pinctrl_gpio_bl_on: gpio-bl-on {
> +			fsl,pins = <
> +				SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12	0x00000040
> +			>;
> +		};
> +
> +		pinctrl_hog0: hog0grp {
> +			fsl,pins = <
> +				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0 /* Use pads in 3.3V mode */
> +			>;
> +		};
> +
> +		pinctrl_hog1: hog1grp {
> +			fsl,pins = <
> +				SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10	0x00000020 /*  45 */
> +				SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02	0x06000020 /*  65 */
> +					SC_P_CSI_D07_CI_PI_D09		0x00000061
> +				SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11	0x00000020 /*  69 */
> +				SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13		0x00000020 /*  73 */
> +				SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x00000020 /*  79 */
> +					SC_P_CSI_D02_CI_PI_D04		0x00000061
> +				SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03	0x06000020 /*  85 */
> +					SC_P_CSI_D06_CI_PI_D08		0x00000061
> +				SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x00000020 /*  95 */
> +				SC_P_SAI0_RXD_LSIO_GPIO0_IO27		0x00000020 /*  97 */
> +					SC_P_CSI_D03_CI_PI_D05		0x00000061
> +				SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x00000020 /*  99 */
> +				SC_P_SAI0_TXFS_LSIO_GPIO0_IO28		0x00000020 /* 101 */
> +					SC_P_CSI_D00_CI_PI_D02		0x00000061
> +				SC_P_SAI0_TXD_LSIO_GPIO0_IO25		0x00000020 /* 103 */
> +					SC_P_CSI_D01_CI_PI_D03		0x00000061
> +				SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x00000020 /* 105 */
> +				SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20	0x00000020 /* 107 */
> +				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x00000020 /* 127 */
> +				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x00000020 /* 131 */
> +				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x00000020 /* 133 */
> +				SC_P_CSI_PCLK_LSIO_GPIO3_IO00		0x00000020 /*  96 */
> +				SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21	0x00000020 /*  98 */
> +				SC_P_SAI1_RXFS_LSIO_GPIO0_IO31		0x00000020 /* 100 */
> +				SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22		0x00000020 /* 102 */
> +				SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23	0x00000020 /* 104 */
> +				SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24	0x00000020 /* 106 */
> +			>;
> +		};
> +
> +		pinctrl_hog2: hog2grp {
> +			fsl,pins = <
> +				SC_P_CSI_MCLK_LSIO_GPIO3_IO01		0x00000020 /*  75 */
> +				SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14	0x00000020 /*  77 */
> +				SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15	0x00000020 /*  89 */
> +				SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16	0x00000020 /*  93 */
> +			>;
> +		};
> +
> +		/* Off Module I2C */
> +		pinctrl_i2c1: i2c1grp {
> +			fsl,pins = <
> +				SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021
> +				SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021
> +			>;
> +		};
> +
> +		/*INT*/
> +		pinctrl_usb3503a: usb3503a-grp {
> +			fsl,pins = <
> +				SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061
> +			>;
> +		};
> +
> +		pinctrl_usbc_det: usbc-det {
> +			fsl,pins = <
> +				SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040
> +			>;
> +		};
> +
> +		pinctrl_usbh1_reg: usbh1-reg {
> +			fsl,pins = <
> +				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000040
> +			>;
> +		};
> +
> +		pinctrl_usdhc1: usdhc1grp {
> +			fsl,pins = <
> +				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
> +				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
> +				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
> +				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
> +				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
> +				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
> +				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
> +				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
> +				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
> +				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
> +				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
> +				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> +			fsl,pins = <
> +				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
> +				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
> +				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
> +				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
> +				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
> +				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
> +				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
> +				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
> +				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
> +				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
> +				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
> +				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> +			fsl,pins = <
> +				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
> +				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
> +				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
> +				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
> +				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
> +				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
> +				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
> +				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
> +				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
> +				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
> +				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
> +				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> +			fsl,pins = <
> +				SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09	0x06000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc2: usdhc2grp {
> +			fsl,pins = <
> +				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
> +				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
> +				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
> +				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
> +				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
> +				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
> +				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> +			fsl,pins = <
> +				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
> +				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
> +				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
> +				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
> +				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
> +				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
> +				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> +			fsl,pins = <
> +				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
> +				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
> +				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
> +				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
> +				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
> +				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
> +				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
> +			>;
> +		};
> +	};
> +};
> +
> +&lpuart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpuart0>;
> +	status = "okay";
> +};
> +
> +&lpuart3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
> +	status = "okay";
> +};
> +
> +&gpio0 {
> +	status = "okay";
> +};
> +
> +&gpio1 {
> +	status = "okay";
> +};
> +
> +&gpio3 {
> +	status = "okay";
> +};
> +
> +&gpio4 {
> +	status = "okay";
> +};
> +
> +&fec1 {
> +	phy-handle = <&ethphy0>;
> +	phy-mode = "rmii";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec1>;
> +	status = "okay";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy0: ethernet-phy at 2 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			max-speed = <100>;
> +			reg = <2>;
> +		};
> +	};
> +};
> +
> +&i2c1 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c1>;
> +	status = "okay";
> +};
> +
> +&usdhc1 {
> +	bus-width = <8>;
> +	non-removable;
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc1>;
> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> +	status = "okay";
> +};
> +
> +&usdhc2 {
> +	bus-width = <4>;
> +	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> +	status = "okay";
> +};
> diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
> index f76a139684..feea07f135 100644
> --- a/arch/arm/mach-imx/imx8/Kconfig
> +++ b/arch/arm/mach-imx/imx8/Kconfig
> @@ -22,6 +22,11 @@ choice
>  	prompt "i.MX8 board select"
>  	optional
>  
> +config TARGET_COLIBRI_IMX8QXP
> +	bool "Support Colibri iMX8QXP module"
> +	select BOARD_LATE_INIT
> +	select IMX8QXP
> +
>  config TARGET_IMX8QXP_MEK
>  	bool "Support i.MX8QXP MEK board"
>  	select BOARD_LATE_INIT
> @@ -30,5 +35,6 @@ config TARGET_IMX8QXP_MEK
>  endchoice
>  
>  source "board/freescale/imx8qxp_mek/Kconfig"
> +source "board/toradex/colibri-imx8qxp/Kconfig"
>  
>  endif
> diff --git a/board/toradex/colibri-imx8qxp/Kconfig b/board/toradex/colibri-imx8qxp/Kconfig
> new file mode 100644
> index 0000000000..340fe72816
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/Kconfig
> @@ -0,0 +1,30 @@
> +if TARGET_COLIBRI_IMX8QXP
> +
> +config SYS_BOARD
> +	default "colibri-imx8qxp"
> +
> +config SYS_VENDOR
> +	default "toradex"
> +
> +config SYS_CONFIG_NAME
> +	default "colibri-imx8qxp"
> +
> +config TDX_CFG_BLOCK
> +	default y
> +
> +config TDX_HAVE_MMC
> +	default y
> +
> +config TDX_CFG_BLOCK_DEV
> +	default "0"
> +
> +config TDX_CFG_BLOCK_PART
> +	default "1"
> +
> +# Toradex config block in eMMC, at the end of 1st "boot sector"
> +config TDX_CFG_BLOCK_OFFSET
> +	default "-512"
> +
> +source "board/toradex/common/Kconfig"
> +
> +endif
> diff --git a/board/toradex/colibri-imx8qxp/MAINTAINERS b/board/toradex/colibri-imx8qxp/MAINTAINERS
> new file mode 100644
> index 0000000000..39a9eb79b7
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/MAINTAINERS
> @@ -0,0 +1,9 @@
> +Colibri iMX8QXP
> +M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
> +W:	http://developer.toradex.com/software/linux/linux-software
> +S:	Maintained
> +F:	arch/arm/dts/fsl-imx8qxp-colibri.dts
> +F:	arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> +F:	board/toradex/colibri-imx8qxp/
> +F:	configs/colibri-imx8qxp_defconfig
> +F:	include/configs/colibri-imx8qxp.h
> diff --git a/board/toradex/colibri-imx8qxp/Makefile b/board/toradex/colibri-imx8qxp/Makefile
> new file mode 100644
> index 0000000000..f6342e1dca
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright 2019 Toradex
> +#
> +# SPDX-License-Identifier:	GPL-2.0+
> +#
> +
> +obj-y += colibri-imx8qxp.o
> diff --git a/board/toradex/colibri-imx8qxp/README b/board/toradex/colibri-imx8qxp/README
> new file mode 100644
> index 0000000000..e68d183fe6
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/README
> @@ -0,0 +1,66 @@
> +U-Boot for the Toradex Colibri iMX8QXP V1.0B module
> +
> +Quick Start
> +===========
> +
> +- Build the ARM trusted firmware binary
> +- Get scfw_tcm.bin and ahab-container.img
> +- Build U-Boot
> +- Load U-Boot binary using uuu
> +- Flash U-Boot binary into the eMMC
> +- Boot
> +
> +Get and Build the ARM Trusted Firmware
> +======================================
> +
> +$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
> +$ cd imx-atf/
> +$ make PLAT=imx8qxp bl31
> +
> +Get scfw_tcm.bin and ahab-container.img
> +=======================================
> +
> +$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
> +$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-tcm.bin
> +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin
> +$ chmod +x firmware-imx-7.6.bin
> +$ ./firmware-imx-7.6.bin
> +
> +Copy the following binaries to the U-Boot folder:
> +
> +$ cp imx-atf/build/imx8qxp/release/bl31.bin .
> +$ cp u-boot/u-boot.bin .
> +
> +Copy the following firmware to the U-Boot folder:
> +
> +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
> +
> +Build U-Boot
> +============
> +
> +$ make colibri-imx8qxp_defconfig
> +$ make u-boot-dtb.imx
> +
> +Load the U-Boot Binary Using UUU
> +================================
> +
> +Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
> +
> +https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
> +
> +Put the module into USB recovery aka serial downloader mode, connect USB device
> +to your host and execute uuu:
> +
> +sudo ./uuu u-boot/u-boot-dtb.imx
> +
> +Flash the U-Boot Binary into the eMMC
> +=====================================
> +
> +Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
> +
> +load mmc 1:1 $loadaddr u-boot-dtb.imx
> +setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
> +mmc dev 0 1
> +mmc write ${loadaddr} 0x0 ${blkcnt}
> +
> +Boot
> diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> new file mode 100644
> index 0000000000..9aa0f096d2
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> @@ -0,0 +1,212 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 Toradex
> + */
> +
> +#include <common.h>
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx8-pins.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/sci/sci.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/mach-imx/video.h>
> +#include <dm.h>
> +#include <environment.h>
> +#include <errno.h>
> +#include <fdt_support.h>
> +#include <fsl_esdhc.h>
> +#include <fsl_ifc.h>
> +#include <i2c.h>
> +#include <linux/libfdt.h>
> +#include <malloc.h>
> +#include <netdev.h>
> +#include <power-domain.h>
> +#include <usb.h>
> +
> +#include "../common/tdx-cfg-block.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
> +			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
> +			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +static iomux_cfg_t uart3_pads[] = {
> +	SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	/* Transceiver FORCEOFF# signal, mux to use pullup */
> +	SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static void setup_iomux_uart(void)
> +{
> +	imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
> +}
> +
> +int board_early_init_f(void)
> +{
> +	sc_pm_clock_rate_t rate;
> +	sc_err_t err = 0;
> +
> +	/*
> +	 * This works around that having only UART3 up the baudrate is 1.2M
> +	 * instead of 115.2k. Set UART0 clock root to 80 MHz
> +	 */
> +	rate = 80000000;
> +	err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
> +	if (err != SC_ERR_NONE)
> +		return 0;
> +
> +	/* Power up UART3 */
> +	err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3, SC_PM_PW_MODE_ON);
> +	if (err != SC_ERR_NONE)
> +		return 0;
> +
> +	/* Set UART3 clock root to 80 MHz */
> +	rate = 80000000;
> +	err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER, &rate);
> +	if (err != SC_ERR_NONE)
> +		return 0;
> +
> +	/* Enable UART3 clock root */
> +	err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER, true, false);
> +	if (err != SC_ERR_NONE)
> +		return 0;
> +
> +	setup_iomux_uart();
> +
> +	return 0;
> +}
> +
> +#undef CONFIG_MXC_GPIO /* TODO */
> +#ifdef CONFIG_MXC_GPIO
> +#define IOEXP_RESET IMX_GPIO_NR(1, 1)
> +
> +static iomux_cfg_t board_gpios[] = {
> +	SC_P_SPI2_SDO | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
> +	SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | \
> +		MUX_PAD_CTRL(GPIO_PAD_CTRL),
> +};
> +
> +static void board_gpio_init(void)
> +{
> +	struct gpio_desc desc;
> +	int ret;
> +
> +	ret = dm_gpio_lookup_name("gpio at 1a_3", &desc);
> +	if (ret)
> +		return;
> +
> +	ret = dm_gpio_request(&desc, "bb_per_rst_b");
> +	if (ret)
> +		return;
> +
> +	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
> +	dm_gpio_set_value(&desc, 0);
> +	udelay(50);
> +	dm_gpio_set_value(&desc, 1);
> +
> +	imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
> +
> +	/* enable i2c port expander assert reset line */
> +	gpio_request(IOEXP_RESET, "ioexp_rst");
> +	gpio_direction_output(IOEXP_RESET, 1);
> +}
> +#else
> +static inline void board_gpio_init(void) {}
> +#endif
> +
> +#if IS_ENABLED(CONFIG_FEC_MXC)
> +#include <miiphy.h>
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> +	if (phydev->drv->config)
> +		phydev->drv->config(phydev);
> +
> +	return 0;
> +}
> +#endif
> +
> +void build_info(void)
> +{
> +	u32 sc_build = 0, sc_commit = 0;
> +
> +	/* Get SCFW build and commit id */
> +	sc_misc_build_info(-1, &sc_build, &sc_commit);
> +	if (!sc_build) {
> +		printf("SCFW does not support build info\n");
> +		sc_commit = 0; /* Display 0 if build info not supported */
> +	}
> +	printf("Build: SCFW %x\n", sc_commit);
> +}
> +
> +int checkboard(void)
> +{
> +	puts("Model: Toradex Colibri iMX8X\n");
> +
> +	build_info();
> +	print_bootinfo();
> +
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	board_gpio_init();
> +
> +	return 0;
> +}
> +
> +void detail_board_ddr_info(void)
> +{
> +	puts("\nDDR    ");
> +}
> +
> +/*
> + * Board specific reset that is system reset.
> + */
> +void reset_cpu(ulong addr)
> +{
> +	/* TODO */
> +}
> +
> +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
> +int ft_board_setup(void *blob, bd_t *bd)
> +{
> +	return ft_common_board_setup(blob, bd);
> +}
> +#endif
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> +	return devno;
> +}
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +/* TODO move to common */
> +	env_set("board_name", "Colibri iMX8QXP");
> +	env_set("board_rev", "v1.0");
> +#endif
> +
> +	return 0;
> +}
> diff --git a/board/toradex/colibri-imx8qxp/imximage.cfg b/board/toradex/colibri-imx8qxp/imximage.cfg
> new file mode 100644
> index 0000000000..ce9e66c64d
> --- /dev/null
> +++ b/board/toradex/colibri-imx8qxp/imximage.cfg
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 Toradex
> + *
> + * Refer doc/README.imx8image for more details about how-to configure
> + * and create imx8image boot image
> + */
> +
> +#define __ASSEMBLY__
> +
> +/* Boot from SD, sector size 0x400 */
> +BOOT_FROM EMMC_FASTBOOT 0x400
> +/* SoC type IMX8QX */
> +SOC_TYPE IMX8QX
> +/* Append seco container image */
> +APPEND ahab-container.img
> +/* Create the 2nd container */
> +CONTAINER
> +/* Add scfw image with exec attribute */
> +IMAGE SCU mx8qx-colibri-scfw-tcm.bin
> +/* Add ATF image with exec attribute */
> +IMAGE A35 bl31.bin 0x80000000
> +/* Add U-Boot image with load attribute */
> +DATA A35 u-boot-dtb.bin 0x80020000
> diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig
> new file mode 100644
> index 0000000000..d697546ed7
> --- /dev/null
> +++ b/configs/colibri-imx8qxp_defconfig
> @@ -0,0 +1,53 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMX8=y
> +CONFIG_SYS_TEXT_BASE=0x80020000
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_TARGET_COLIBRI_IMX8QXP=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_NR_DRAM_BANKS=3
> +CONFIG_FIT=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8qxp/imximage.cfg"
> +CONFIG_LOG=y
> +CONFIG_VERSION_VARIABLE=y
> +# CONFIG_DISPLAY_BOARDINFO is not set
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_CMD_CPU=y
> +# CONFIG_CMD_IMPORTENV is not set
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_DM=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_UUID=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_CLK_IMX8=y
> +CONFIG_CPU=y
> +CONFIG_DM_GPIO=y
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_IMX_LPI2C=y
> +CONFIG_MISC=y
> +CONFIG_DM_MMC=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ADDR_ENABLE=y
> +CONFIG_PHY_MICREL=y
> +CONFIG_DM_ETH=y
> +CONFIG_FEC_MXC_SHARE_MDIO=y
> +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX8=y
> +CONFIG_POWER_DOMAIN=y
> +CONFIG_IMX8_POWER_DOMAIN=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_FSL_LPUART=y
> +CONFIG_DM_THERMAL=y
> +# CONFIG_EFI_LOADER is not set
> diff --git a/include/configs/colibri-imx8qxp.h b/include/configs/colibri-imx8qxp.h
> new file mode 100644
> index 0000000000..33cbcb44a9
> --- /dev/null
> +++ b/include/configs/colibri-imx8qxp.h
> @@ -0,0 +1,214 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 Toradex
> + */
> +
> +#ifndef __COLIBRI_IMX8QXP_H
> +#define __COLIBRI_IMX8QXP_H
> +
> +#include <asm/arch/imx-regs.h>
> +#include <linux/sizes.h>
> +
> +#define CONFIG_REMAKE_ELF
> +
> +#define CONFIG_DISPLAY_BOARDINFO_LATE
> +
> +#undef CONFIG_CMD_EXPORTENV
> +#undef CONFIG_CMD_IMPORTENV
> +#undef CONFIG_CMD_IMLS
> +
> +#undef CONFIG_CMD_CRC32
> +#undef CONFIG_BOOTM_NETBSD
> +
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR	0
> +#define USDHC1_BASE_ADDR		0x5B010000
> +#define USDHC2_BASE_ADDR		0x5B020000
> +#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
> +
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +
> +#define FEC_QUIRK_ENET_MAC
> +
> +#define CONFIG_IP_DEFRAG
> +#define CONFIG_TFTP_BLOCKSIZE		4096
> +#define CONFIG_TFTP_TSIZE
> +
> +#define CONFIG_IPADDR			192.168.10.2
> +#define CONFIG_NETMASK			255.255.255.0
> +#define CONFIG_SERVERIP			192.168.10.1
> +
> +#define MEM_LAYOUT_ENV_SETTINGS \
> +	"fdt_addr_r=0x84000000\0" \
> +	"kernel_addr_r=0x82000000\0" \
> +	"ramdisk_addr_r=0x84100000\0"
> +
> +#ifdef CONFIG_AHAB_BOOT
> +#define AHAB_ENV "sec_boot=yes\0"
> +#else
> +#define AHAB_ENV "sec_boot=no\0"
> +#endif
> +
> +/* Boot M4 */
> +#define M4_BOOT_ENV \
> +	"m4_0_image=m4_0.bin\0" \
> +	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
> +		"${m4_0_image}\0" \
> +	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
> +
> +#define MFG_NAND_PARTITION ""
> +
> +#define BOOT_TARGET_DEVICES(func) \
> +	func(MMC, mmc, 0) \
> +	func(MMC, mmc, 1) \
> +	func(DHCP, dhcp, na)
> +#include <config_distro_bootcmd.h>
> +#undef BOOTENV_RUN_NET_USB_START
> +#define BOOTENV_RUN_NET_USB_START ""
> +
> +#define CONFIG_MFG_ENV_SETTINGS \
> +	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
> +		"rdinit=/linuxrc g_mass_storage.stall=0 " \
> +		"g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \
> +		"g_mass_storage.idProduct=0x37FF " \
> +		"g_mass_storage.iSerialNumber=\"\" "\
> +		MFG_NAND_PARTITION \
> +		"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off " \
> +		"clk_ignore_unused "\
> +		"\0" \
> +	"initrd_addr=0x83800000\0" \
> +	"initrd_high=0xffffffff\0" \
> +	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \
> +		"${fdt_addr};\0" \
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +	AHAB_ENV \
> +	BOOTENV \
> +	CONFIG_MFG_ENV_SETTINGS \
> +	M4_BOOT_ENV \
> +	MEM_LAYOUT_ENV_SETTINGS \
> +	"boot_fdt=try\0" \
> +	"bootscript=echo Running bootscript from mmc ...; source\0" \
> +	"console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200\0" \
> +	"fdt_addr=0x83000000\0"			\
> +	"fdt_file=fsl-imx8qxp-colibri-eval-v3.dtb\0" \
> +	"fdt_high=0xffffffffffffffff\0"		\
> +	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
> +	"image=Image\0" \
> +	"initrd_addr=0x83800000\0"		\
> +	"initrd_high=0xffffffffffffffff\0" \
> +	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
> +		"${script};\0" \
> +	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> +	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> +	"mmcargs=setenv bootargs console=${console},${baudrate} " \
> +		"root=PARTUUID=${uuid} rootwait " \
> +	"mmcautodetect=yes\0" \
> +	"mmcboot=echo Booting from mmc ...; " \
> +		"run finduuid; run mmcargs; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +			"if run loadfdt; then " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"else " \
> +			"echo wait for boot; " \
> +		"fi;\0" \
> +	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
> +	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> +	"netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
> +		"nfsroot=${serverip}:${nfsroot},v3,tcp video=imxdpufb5:off " \
> +		"video=imxdpufb6:off video=imxdpufb7:off\0" \
> +	"netboot=echo Booting from net ...; " \
> +		"run netargs; " \
> +		"if test ${ip_dyn} = yes; then " \
> +			"setenv get_cmd dhcp; " \
> +		"else " \
> +			"setenv get_cmd tftp; " \
> +		"fi; " \
> +		"${get_cmd} ${loadaddr} ${image}; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"else " \
> +			"booti; " \
> +		"fi;\0" \
> +	"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
> +		"colibri-imx8qxp/${fdt_file}; booti ${loadaddr} - " \
> +		"${fdt_addr}\0" \
> +	"panel=NULL\0" \
> +	"script=boot.scr\0" \
> +	"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
> +
> +#undef CONFIG_BOOTCOMMAND
> +#define CONFIG_BOOTCOMMAND \
> +	   "mmc dev ${mmcdev}; if mmc rescan; then " \
> +		   "if run loadbootscript; then " \
> +			   "run bootscript; " \
> +		   "else " \
> +			   "if run loadimage; then " \
> +				   "run mmcboot; " \
> +			   "else run netboot; " \
> +			   "fi; " \
> +		   "fi; " \
> +	   "else booti ${loadaddr} - ${fdt_addr}; fi"
> +
> +/* Link Definitions */
> +#define CONFIG_LOADADDR			0x80280000
> +
> +#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
> +
> +#define CONFIG_SYS_MEMTEST_START	0x88000000
> +#define CONFIG_SYS_MEMTEST_END		0x89000000
> +
> +/* Environment in eMMC, before config block at the end of 1st "boot sector" */
> +#define CONFIG_ENV_SIZE			(8 * 1024)
> +#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
> +					 CONFIG_TDX_CFG_BLOCK_OFFSET)
> +#define CONFIG_SYS_MMC_ENV_DEV		0
> +#define CONFIG_SYS_MMC_ENV_PART		1
> +
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
> +
> +/* On Colibri iMX8 USDHC1 is eMMC, USDHC2 is 4-bit SD */
> +#define CONFIG_SYS_MMC_ENV_DEV		0		 /* USDHC1 eMMC */
> +#define CONFIG_SYS_FSL_USDHC_NUM	2
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
> +
> +#define CONFIG_SYS_SDRAM_BASE		0x80000000
> +#define CONFIG_NR_DRAM_BANKS		3
> +#define PHYS_SDRAM_1			0x80000000
> +#define PHYS_SDRAM_2			0x880000000
> +#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
> +#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 GB */
> +
> +/* Serial */
> +#define CONFIG_BAUDRATE			115200
> +
> +/* Monitor Command Prompt */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> +#define CONFIG_SYS_CBSIZE		2048
> +#define CONFIG_SYS_MAXARGS		64
> +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> +					sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +/* Generic Timer Definitions */
> +#define COUNTER_FREQUENCY		8000000	/* 8MHz */
> +
> +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
> +#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */
> +
> +#endif /* __COLIBRI_IMX8QXP_H */
> 


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Marcel Ziswiler]

Hi Stefano

On Thu, 2019-04-25 at 12:48 +0200, Stefano Babic wrote:
> Hi Marcel,
> 
> On 09/04/19 17:25, Marcel Ziswiler wrote:
> > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > 
> > This commit adds initial support for the Toradex Colibri iMX8QXP
> > 2GB WB
> > IT V1.0B module. Unlike the V1.0A early access samples exclusively
> > booting from SD card, they are now strapped to boot from eFuses
> > which
> > are factory fused to properly boot from their on-module eMMC. U-
> > Boot
> > supports either booting from the on-module eMMC or may be used for
> > recovery purpose using the universal update utility (uuu) aka
> > mfgtools
> > 3.0.
> > 
> > Functionality wise the following is known to be working:
> > - eMMC and MMC/SD card
> > - Ethernet
> > - GPIOs
> > - I2C
> > 
> > Unfortunately, there is no USB functionality for the i.MX 8QXP as
> > of
> > yet.
> > 
> > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > 
> > ---
> > 
> 
> I merged the series and build locally (fine), but Travis complains
> and
> stops with error:
> 
> +cc1: fatal error: opening output file spl/u-boot-spl.cfgout: No such
> file or directory
> +compilation terminated.
> 
> Can you take a look at it ?

Sure, looks like Peng's commit caceb739ea07 ("imx: build flash.bin for
i.MX8") takes SPL for granted while my patchset currently avoids it.

BTW: I still don't believe SPL makes much sense on i.MX 8X given all
the other proprietary parts involved in booting. Plus currently SPL
actually breaks the USB serial downloader aka recovery mode using the
universal update utility (uuu) aka mfgtools 3.0.

> Regards,
> Stefano

Cheers

Marcel

> > Changes in v2:
> > - Changed imx-atf git clone command to include initial branch
> >   information as suggested by Igor.
> > - Sorted board file includes alphabetically as suggested by Igor.
> > - Got rid of SPL configuration in legacy header file as suggested
> > by
> >   Igor and the whole use of SPL on i.MX 8X anyway neither works
> > well
> >   nor makes any much sense at all.
> > 
> >  arch/arm/dts/Makefile                         |   4 +-
> >  arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi  | 112 ++++++
> >  arch/arm/dts/fsl-imx8qxp-colibri.dts          | 328
> > ++++++++++++++++++
> >  arch/arm/mach-imx/imx8/Kconfig                |   6 +
> >  board/toradex/colibri-imx8qxp/Kconfig         |  30 ++
> >  board/toradex/colibri-imx8qxp/MAINTAINERS     |   9 +
> >  board/toradex/colibri-imx8qxp/Makefile        |   7 +
> >  board/toradex/colibri-imx8qxp/README          |  66 ++++
> >  .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 212 +++++++++++
> >  board/toradex/colibri-imx8qxp/imximage.cfg    |  24 ++
> >  configs/colibri-imx8qxp_defconfig             |  53 +++
> >  include/configs/colibri-imx8qxp.h             | 214 ++++++++++++
> >  12 files changed, 1064 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> >  create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts
> >  create mode 100644 board/toradex/colibri-imx8qxp/Kconfig
> >  create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS
> >  create mode 100644 board/toradex/colibri-imx8qxp/Makefile
> >  create mode 100644 board/toradex/colibri-imx8qxp/README
> >  create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> >  create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg
> >  create mode 100644 configs/colibri-imx8qxp_defconfig
> >  create mode 100644 include/configs/colibri-imx8qxp.h
> > 
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 13d1d67624..2a551d42a4 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -559,7 +559,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
> >  
> >  dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
> >  
> > -dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
> > +dtb-$(CONFIG_ARCH_IMX8) += \
> > +	fsl-imx8qxp-colibri.dtb \
> > +	fsl-imx8qxp-mek.dtb
> >  
> >  dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
> >  
> > diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..f8686befdf
> > --- /dev/null
> > +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > @@ -0,0 +1,112 @@
> > +// SPDX-License-Identifier: GPL-2.0+ OR X11
> > +/*
> > + * Copyright 2019 Toradex AG
> > + */
> > +
> > +&mu {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&clk {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&iomuxc {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio0 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio1 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio2 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio3 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio4 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio5 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio6 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio7 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_conn {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_conn_sdch0 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_conn_sdch1 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&pd_conn_sdch2 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&gpio0 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&gpio1 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&gpio2 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&gpio3 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&gpio4 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&gpio5 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&gpio6 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&gpio7 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&lpuart3 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&usdhc1 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&usdhc2 {
> > +	u-boot,dm-spl;
> > +};
> > diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts
> > b/arch/arm/dts/fsl-imx8qxp-colibri.dts
> > new file mode 100644
> > index 0000000000..0c20edf2cf
> > --- /dev/null
> > +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts
> > @@ -0,0 +1,328 @@
> > +// SPDX-License-Identifier: GPL-2.0+ OR X11
> > +/*
> > + * Copyright 2019 Toradex AG
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "fsl-imx8qxp.dtsi"
> > +#include "fsl-imx8qxp-colibri-u-boot.dtsi"
> > +
> > +/ {
> > +	model = "Toradex Colibri iMX8QXP";
> > +	compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";
> > +
> > +	chosen {
> > +		bootargs = "console=ttyLP3,115200
> > earlycon=lpuart32,0x5a090000,115200";
> > +		stdout-path = &lpuart3;
> > +	};
> > +
> > +	reg_usbh_vbus: regulator-usbh-vbus {
> > +		compatible = "regulator-fixed";
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&pinctrl_usbh1_reg>;
> > +		regulator-name = "usbh_vbus";
> > +		regulator-min-microvolt = <5000000>;
> > +		regulator-max-microvolt = <5000000>;
> > +		gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
> > +	};
> > +};
> > +
> > +&iomuxc {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
> > +
> > +	colibri-imx8qxp {
> > +		pinctrl_lpuart0: lpuart0grp {
> > +			fsl,pins = <
> > +				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
> > +				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
> > +			>;
> > +		};
> > +
> > +		pinctrl_lpuart3: lpuart3grp {
> > +			fsl,pins = <
> > +				SC_P_FLEXCAN2_RX_ADMA_UART3_RX	0x0
> > 6000020
> > +				SC_P_FLEXCAN2_TX_ADMA_UART3_TX	0x0
> > 6000020
> > +			>;
> > +		};
> > +
> > +		pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
> > +			fsl,pins = <
> > +				SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00
> > 0x00000020 /* DTR */
> > +				SC_P_SAI1_RXD_LSIO_GPIO0_IO29		
> > 0x00000020 /* CTS */
> > +				SC_P_SAI1_RXC_LSIO_GPIO0_IO30		
> > 0x00000020 /* RTS */
> > +				SC_P_CSI_RESET_LSIO_GPIO3_IO03		
> > 0x00000020 /* DSR */
> > +				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x0
> > 0000020 /* DCD */
> > +				SC_P_CSI_EN_LSIO_GPIO3_IO02		0x0
> > 0000020 /* RI */
> > +			>;
> > +		};
> > +
> > +		pinctrl_fec1: fec1grp {
> > +			fsl,pins = <
> > +				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_
> > PAD	0x000014a0 /* Use pads in 3.3V mode */
> > +				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_
> > PAD	0x000014a0 /* Use pads in 3.3V mode */
> > +				SC_P_ENET0_MDC_CONN_ENET0_MDC		
> > 	0x06000020
> > +				SC_P_ENET0_MDIO_CONN_ENET0_MDIO		
> > 	0x06000020
> > +				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMI
> > I_TX_CTL	0x00000061
> > +				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M
> > _OUT	0x06000061
> > +				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_
> > TXD0	0x00000061
> > +				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_
> > TXD1	0x00000061
> > +				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMI
> > I_RX_CTL	0x00000061
> > +				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_
> > RXD0	0x00000061
> > +				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_
> > RXD1	0x00000061
> > +				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_R
> > X_ER	0x00000061
> > +			>;
> > +		};
> > +
> > +		pinctrl_gpio_bl_on: gpio-bl-on {
> > +			fsl,pins = <
> > +				SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12	0x0
> > 0000040
> > +			>;
> > +		};
> > +
> > +		pinctrl_hog0: hog0grp {
> > +			fsl,pins = <
> > +				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	
> > 0x000514a0 /* Use pads in 3.3V mode */
> > +			>;
> > +		};
> > +
> > +		pinctrl_hog1: hog1grp {
> > +			fsl,pins = <
> > +				SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10	0x0
> > 0000020 /*  45 */
> > +				SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02	
> > 0x06000020 /*  65 */
> > +					SC_P_CSI_D07_CI_PI_D09		
> > 0x00000061
> > +				SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11	0x0
> > 0000020 /*  69 */
> > +				SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13		
> > 0x00000020 /*  73 */
> > +				SC_P_SAI0_TXC_LSIO_GPIO0_IO26		
> > 0x00000020 /*  79 */
> > +					SC_P_CSI_D02_CI_PI_D04		
> > 0x00000061
> > +				SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03	
> > 0x06000020 /*  85 */
> > +					SC_P_CSI_D06_CI_PI_D08		
> > 0x00000061
> > +				SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x0
> > 0000020 /*  95 */
> > +				SC_P_SAI0_RXD_LSIO_GPIO0_IO27		
> > 0x00000020 /*  97 */
> > +					SC_P_CSI_D03_CI_PI_D05		
> > 0x00000061
> > +				SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x0
> > 0000020 /*  99 */
> > +				SC_P_SAI0_TXFS_LSIO_GPIO0_IO28		
> > 0x00000020 /* 101 */
> > +					SC_P_CSI_D00_CI_PI_D02		
> > 0x00000061
> > +				SC_P_SAI0_TXD_LSIO_GPIO0_IO25		
> > 0x00000020 /* 103 */
> > +					SC_P_CSI_D01_CI_PI_D03		
> > 0x00000061
> > +				SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x0
> > 0000020 /* 105 */
> > +				SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20	0x0
> > 0000020 /* 107 */
> > +				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x0
> > 0000020 /* 127 */
> > +				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x0
> > 0000020 /* 131 */
> > +				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x0
> > 0000020 /* 133 */
> > +				SC_P_CSI_PCLK_LSIO_GPIO3_IO00		
> > 0x00000020 /*  96 */
> > +				SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21	0x0
> > 0000020 /*  98 */
> > +				SC_P_SAI1_RXFS_LSIO_GPIO0_IO31		
> > 0x00000020 /* 100 */
> > +				SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22		
> > 0x00000020 /* 102 */
> > +				SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23	0x0
> > 0000020 /* 104 */
> > +				SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24	0x0
> > 0000020 /* 106 */
> > +			>;
> > +		};
> > +
> > +		pinctrl_hog2: hog2grp {
> > +			fsl,pins = <
> > +				SC_P_CSI_MCLK_LSIO_GPIO3_IO01		
> > 0x00000020 /*  75 */
> > +				SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14	0x0
> > 0000020 /*  77 */
> > +				SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15	0x0
> > 0000020 /*  89 */
> > +				SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16	0x0
> > 0000020 /*  93 */
> > +			>;
> > +		};
> > +
> > +		/* Off Module I2C */
> > +		pinctrl_i2c1: i2c1grp {
> > +			fsl,pins = <
> > +				SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	
> > 0x06000021
> > +				SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	
> > 0x06000021
> > +			>;
> > +		};
> > +
> > +		/*INT*/
> > +		pinctrl_usb3503a: usb3503a-grp {
> > +			fsl,pins = <
> > +				SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04
> > 0x00000061
> > +			>;
> > +		};
> > +
> > +		pinctrl_usbc_det: usbc-det {
> > +			fsl,pins = <
> > +				SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_I
> > O09	0x06000040
> > +			>;
> > +		};
> > +
> > +		pinctrl_usbh1_reg: usbh1-reg {
> > +			fsl,pins = <
> > +				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x0
> > 6000040
> > +			>;
> > +		};
> > +
> > +		pinctrl_usdhc1: usdhc1grp {
> > +			fsl,pins = <
> > +				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		
> > 0x06000041
> > +				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		
> > 0x00000021
> > +				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x0
> > 0000021
> > +				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x0
> > 0000041
> > +				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	
> > 0x00000021
> > +			>;
> > +		};
> > +
> > +		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> > +			fsl,pins = <
> > +				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		
> > 0x06000041
> > +				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		
> > 0x00000021
> > +				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x0
> > 0000021
> > +				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x0
> > 0000041
> > +				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	
> > 0x00000021
> > +			>;
> > +		};
> > +
> > +		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> > +			fsl,pins = <
> > +				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		
> > 0x06000041
> > +				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		
> > 0x00000021
> > +				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x0
> > 0000021
> > +				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x0
> > 0000021
> > +				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x0
> > 0000041
> > +				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	
> > 0x00000021
> > +			>;
> > +		};
> > +
> > +		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> > +			fsl,pins = <
> > +				SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09	0x0
> > 6000021
> > +			>;
> > +		};
> > +
> > +		pinctrl_usdhc2: usdhc2grp {
> > +			fsl,pins = <
> > +				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		
> > 0x06000041
> > +				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		
> > 0x00000021
> > +				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x0
> > 0000021
> > +				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x0
> > 0000021
> > +				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x0
> > 0000021
> > +				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x0
> > 0000021
> > +				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT
> > 	0x00000021
> > +			>;
> > +		};
> > +
> > +		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> > +			fsl,pins = <
> > +				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		
> > 0x06000041
> > +				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		
> > 0x00000021
> > +				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x0
> > 0000021
> > +				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x0
> > 0000021
> > +				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x0
> > 0000021
> > +				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x0
> > 0000021
> > +				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT
> > 	0x00000021
> > +			>;
> > +		};
> > +
> > +		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> > +			fsl,pins = <
> > +				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		
> > 0x06000041
> > +				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		
> > 0x00000021
> > +				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x0
> > 0000021
> > +				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x0
> > 0000021
> > +				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x0
> > 0000021
> > +				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x0
> > 0000021
> > +				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT
> > 	0x00000021
> > +			>;
> > +		};
> > +	};
> > +};
> > +
> > +&lpuart0 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_lpuart0>;
> > +	status = "okay";
> > +};
> > +
> > +&lpuart3 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
> > +	status = "okay";
> > +};
> > +
> > +&gpio0 {
> > +	status = "okay";
> > +};
> > +
> > +&gpio1 {
> > +	status = "okay";
> > +};
> > +
> > +&gpio3 {
> > +	status = "okay";
> > +};
> > +
> > +&gpio4 {
> > +	status = "okay";
> > +};
> > +
> > +&fec1 {
> > +	phy-handle = <&ethphy0>;
> > +	phy-mode = "rmii";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_fec1>;
> > +	status = "okay";
> > +
> > +	mdio {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		ethphy0: ethernet-phy at 2 {
> > +			compatible = "ethernet-phy-ieee802.3-c22";
> > +			max-speed = <100>;
> > +			reg = <2>;
> > +		};
> > +	};
> > +};
> > +
> > +&i2c1 {
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> > +	clock-frequency = <100000>;
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_i2c1>;
> > +	status = "okay";
> > +};
> > +
> > +&usdhc1 {
> > +	bus-width = <8>;
> > +	non-removable;
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc1>;
> > +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> > +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> > +	status = "okay";
> > +};
> > +
> > +&usdhc2 {
> > +	bus-width = <4>;
> > +	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> > +	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> > +	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> > +	status = "okay";
> > +};
> > diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-
> > imx/imx8/Kconfig
> > index f76a139684..feea07f135 100644
> > --- a/arch/arm/mach-imx/imx8/Kconfig
> > +++ b/arch/arm/mach-imx/imx8/Kconfig
> > @@ -22,6 +22,11 @@ choice
> >  	prompt "i.MX8 board select"
> >  	optional
> >  
> > +config TARGET_COLIBRI_IMX8QXP
> > +	bool "Support Colibri iMX8QXP module"
> > +	select BOARD_LATE_INIT
> > +	select IMX8QXP
> > +
> >  config TARGET_IMX8QXP_MEK
> >  	bool "Support i.MX8QXP MEK board"
> >  	select BOARD_LATE_INIT
> > @@ -30,5 +35,6 @@ config TARGET_IMX8QXP_MEK
> >  endchoice
> >  
> >  source "board/freescale/imx8qxp_mek/Kconfig"
> > +source "board/toradex/colibri-imx8qxp/Kconfig"
> >  
> >  endif
> > diff --git a/board/toradex/colibri-imx8qxp/Kconfig
> > b/board/toradex/colibri-imx8qxp/Kconfig
> > new file mode 100644
> > index 0000000000..340fe72816
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/Kconfig
> > @@ -0,0 +1,30 @@
> > +if TARGET_COLIBRI_IMX8QXP
> > +
> > +config SYS_BOARD
> > +	default "colibri-imx8qxp"
> > +
> > +config SYS_VENDOR
> > +	default "toradex"
> > +
> > +config SYS_CONFIG_NAME
> > +	default "colibri-imx8qxp"
> > +
> > +config TDX_CFG_BLOCK
> > +	default y
> > +
> > +config TDX_HAVE_MMC
> > +	default y
> > +
> > +config TDX_CFG_BLOCK_DEV
> > +	default "0"
> > +
> > +config TDX_CFG_BLOCK_PART
> > +	default "1"
> > +
> > +# Toradex config block in eMMC, at the end of 1st "boot sector"
> > +config TDX_CFG_BLOCK_OFFSET
> > +	default "-512"
> > +
> > +source "board/toradex/common/Kconfig"
> > +
> > +endif
> > diff --git a/board/toradex/colibri-imx8qxp/MAINTAINERS
> > b/board/toradex/colibri-imx8qxp/MAINTAINERS
> > new file mode 100644
> > index 0000000000..39a9eb79b7
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/MAINTAINERS
> > @@ -0,0 +1,9 @@
> > +Colibri iMX8QXP
> > +M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > +W:	http://developer.toradex.com/software/linux/linux-software
> > +S:	Maintained
> > +F:	arch/arm/dts/fsl-imx8qxp-colibri.dts
> > +F:	arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > +F:	board/toradex/colibri-imx8qxp/
> > +F:	configs/colibri-imx8qxp_defconfig
> > +F:	include/configs/colibri-imx8qxp.h
> > diff --git a/board/toradex/colibri-imx8qxp/Makefile
> > b/board/toradex/colibri-imx8qxp/Makefile
> > new file mode 100644
> > index 0000000000..f6342e1dca
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/Makefile
> > @@ -0,0 +1,7 @@
> > +#
> > +# Copyright 2019 Toradex
> > +#
> > +# SPDX-License-Identifier:	GPL-2.0+
> > +#
> > +
> > +obj-y += colibri-imx8qxp.o
> > diff --git a/board/toradex/colibri-imx8qxp/README
> > b/board/toradex/colibri-imx8qxp/README
> > new file mode 100644
> > index 0000000000..e68d183fe6
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/README
> > @@ -0,0 +1,66 @@
> > +U-Boot for the Toradex Colibri iMX8QXP V1.0B module
> > +
> > +Quick Start
> > +===========
> > +
> > +- Build the ARM trusted firmware binary
> > +- Get scfw_tcm.bin and ahab-container.img
> > +- Build U-Boot
> > +- Load U-Boot binary using uuu
> > +- Flash U-Boot binary into the eMMC
> > +- Boot
> > +
> > +Get and Build the ARM Trusted Firmware
> > +======================================
> > +
> > +$ git clone -b imx_4.14.78_1.0.0_ga 
> > https://source.codeaurora.org/external/imx/imx-atf
> > +$ cd imx-atf/
> > +$ make PLAT=imx8qxp bl31
> > +
> > +Get scfw_tcm.bin and ahab-container.img
> > +=======================================
> > +
> > +$ wget 
> > https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
> > +$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-
> > tcm.bin
> > +$ wget 
> > https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin
> > +$ chmod +x firmware-imx-7.6.bin
> > +$ ./firmware-imx-7.6.bin
> > +
> > +Copy the following binaries to the U-Boot folder:
> > +
> > +$ cp imx-atf/build/imx8qxp/release/bl31.bin .
> > +$ cp u-boot/u-boot.bin .
> > +
> > +Copy the following firmware to the U-Boot folder:
> > +
> > +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
> > +
> > +Build U-Boot
> > +============
> > +
> > +$ make colibri-imx8qxp_defconfig
> > +$ make u-boot-dtb.imx
> > +
> > +Load the U-Boot Binary Using UUU
> > +================================
> > +
> > +Get the latest version of the universal update utility (uuu) aka
> > mfgtools 3.0:
> > +
> > +
> > https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
> > +
> > +Put the module into USB recovery aka serial downloader mode,
> > connect USB device
> > +to your host and execute uuu:
> > +
> > +sudo ./uuu u-boot/u-boot-dtb.imx
> > +
> > +Flash the U-Boot Binary into the eMMC
> > +=====================================
> > +
> > +Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot
> > area partition:
> > +
> > +load mmc 1:1 $loadaddr u-boot-dtb.imx
> > +setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} /
> > 0x200
> > +mmc dev 0 1
> > +mmc write ${loadaddr} 0x0 ${blkcnt}
> > +
> > +Boot
> > diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> > b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> > new file mode 100644
> > index 0000000000..9aa0f096d2
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> > @@ -0,0 +1,212 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 Toradex
> > + */
> > +
> > +#include <common.h>
> > +
> > +#include <asm/arch/clock.h>
> > +#include <asm/arch/imx8-pins.h>
> > +#include <asm/arch/iomux.h>
> > +#include <asm/arch/sci/sci.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <asm/gpio.h>
> > +#include <asm/io.h>
> > +#include <asm/mach-imx/video.h>
> > +#include <dm.h>
> > +#include <environment.h>
> > +#include <errno.h>
> > +#include <fdt_support.h>
> > +#include <fsl_esdhc.h>
> > +#include <fsl_ifc.h>
> > +#include <i2c.h>
> > +#include <linux/libfdt.h>
> > +#include <malloc.h>
> > +#include <netdev.h>
> > +#include <power-domain.h>
> > +#include <usb.h>
> > +
> > +#include "../common/tdx-cfg-block.h"
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL <<
> > PADRING_CONFIG_SHIFT) | \
> > +			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> > +			 (SC_PAD_28FDSOI_DSE_DV_HIGH <<
> > PADRING_DSE_SHIFT) | \
> > +			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> > +
> > +#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN <<
> > PADRING_CONFIG_SHIFT) | \
> > +			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> > +			 (SC_PAD_28FDSOI_DSE_DV_HIGH <<
> > PADRING_DSE_SHIFT) | \
> > +			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> > +
> > +static iomux_cfg_t uart3_pads[] = {
> > +	SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) |
> > MUX_PAD_CTRL(UART_PAD_CTRL),
> > +	SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) |
> > MUX_PAD_CTRL(UART_PAD_CTRL),
> > +	/* Transceiver FORCEOFF# signal, mux to use pullup */
> > +	SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) |
> > MUX_PAD_CTRL(UART_PAD_CTRL),
> > +};
> > +
> > +static void setup_iomux_uart(void)
> > +{
> > +	imx8_iomux_setup_multiple_pads(uart3_pads,
> > ARRAY_SIZE(uart3_pads));
> > +}
> > +
> > +int board_early_init_f(void)
> > +{
> > +	sc_pm_clock_rate_t rate;
> > +	sc_err_t err = 0;
> > +
> > +	/*
> > +	 * This works around that having only UART3 up the baudrate is
> > 1.2M
> > +	 * instead of 115.2k. Set UART0 clock root to 80 MHz
> > +	 */
> > +	rate = 80000000;
> > +	err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER,
> > &rate);
> > +	if (err != SC_ERR_NONE)
> > +		return 0;
> > +
> > +	/* Power up UART3 */
> > +	err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3,
> > SC_PM_PW_MODE_ON);
> > +	if (err != SC_ERR_NONE)
> > +		return 0;
> > +
> > +	/* Set UART3 clock root to 80 MHz */
> > +	rate = 80000000;
> > +	err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER,
> > &rate);
> > +	if (err != SC_ERR_NONE)
> > +		return 0;
> > +
> > +	/* Enable UART3 clock root */
> > +	err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER, true,
> > false);
> > +	if (err != SC_ERR_NONE)
> > +		return 0;
> > +
> > +	setup_iomux_uart();
> > +
> > +	return 0;
> > +}
> > +
> > +#undef CONFIG_MXC_GPIO /* TODO */
> > +#ifdef CONFIG_MXC_GPIO
> > +#define IOEXP_RESET IMX_GPIO_NR(1, 1)
> > +
> > +static iomux_cfg_t board_gpios[] = {
> > +	SC_P_SPI2_SDO | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
> > +	SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | \
> > +		MUX_PAD_CTRL(GPIO_PAD_CTRL),
> > +};
> > +
> > +static void board_gpio_init(void)
> > +{
> > +	struct gpio_desc desc;
> > +	int ret;
> > +
> > +	ret = dm_gpio_lookup_name("gpio at 1a_3", &desc);
> > +	if (ret)
> > +		return;
> > +
> > +	ret = dm_gpio_request(&desc, "bb_per_rst_b");
> > +	if (ret)
> > +		return;
> > +
> > +	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
> > +	dm_gpio_set_value(&desc, 0);
> > +	udelay(50);
> > +	dm_gpio_set_value(&desc, 1);
> > +
> > +	imx8_iomux_setup_multiple_pads(board_gpios,
> > ARRAY_SIZE(board_gpios));
> > +
> > +	/* enable i2c port expander assert reset line */
> > +	gpio_request(IOEXP_RESET, "ioexp_rst");
> > +	gpio_direction_output(IOEXP_RESET, 1);
> > +}
> > +#else
> > +static inline void board_gpio_init(void) {}
> > +#endif
> > +
> > +#if IS_ENABLED(CONFIG_FEC_MXC)
> > +#include <miiphy.h>
> > +
> > +int board_phy_config(struct phy_device *phydev)
> > +{
> > +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> > +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> > +
> > +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> > +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> > +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> > +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> > +
> > +	if (phydev->drv->config)
> > +		phydev->drv->config(phydev);
> > +
> > +	return 0;
> > +}
> > +#endif
> > +
> > +void build_info(void)
> > +{
> > +	u32 sc_build = 0, sc_commit = 0;
> > +
> > +	/* Get SCFW build and commit id */
> > +	sc_misc_build_info(-1, &sc_build, &sc_commit);
> > +	if (!sc_build) {
> > +		printf("SCFW does not support build info\n");
> > +		sc_commit = 0; /* Display 0 if build info not supported
> > */
> > +	}
> > +	printf("Build: SCFW %x\n", sc_commit);
> > +}
> > +
> > +int checkboard(void)
> > +{
> > +	puts("Model: Toradex Colibri iMX8X\n");
> > +
> > +	build_info();
> > +	print_bootinfo();
> > +
> > +	return 0;
> > +}
> > +
> > +int board_init(void)
> > +{
> > +	board_gpio_init();
> > +
> > +	return 0;
> > +}
> > +
> > +void detail_board_ddr_info(void)
> > +{
> > +	puts("\nDDR    ");
> > +}
> > +
> > +/*
> > + * Board specific reset that is system reset.
> > + */
> > +void reset_cpu(ulong addr)
> > +{
> > +	/* TODO */
> > +}
> > +
> > +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
> > +int ft_board_setup(void *blob, bd_t *bd)
> > +{
> > +	return ft_common_board_setup(blob, bd);
> > +}
> > +#endif
> > +
> > +int board_mmc_get_env_dev(int devno)
> > +{
> > +	return devno;
> > +}
> > +
> > +int board_late_init(void)
> > +{
> > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > +/* TODO move to common */
> > +	env_set("board_name", "Colibri iMX8QXP");
> > +	env_set("board_rev", "v1.0");
> > +#endif
> > +
> > +	return 0;
> > +}
> > diff --git a/board/toradex/colibri-imx8qxp/imximage.cfg
> > b/board/toradex/colibri-imx8qxp/imximage.cfg
> > new file mode 100644
> > index 0000000000..ce9e66c64d
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/imximage.cfg
> > @@ -0,0 +1,24 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2019 Toradex
> > + *
> > + * Refer doc/README.imx8image for more details about how-to
> > configure
> > + * and create imx8image boot image
> > + */
> > +
> > +#define __ASSEMBLY__
> > +
> > +/* Boot from SD, sector size 0x400 */
> > +BOOT_FROM EMMC_FASTBOOT 0x400
> > +/* SoC type IMX8QX */
> > +SOC_TYPE IMX8QX
> > +/* Append seco container image */
> > +APPEND ahab-container.img
> > +/* Create the 2nd container */
> > +CONTAINER
> > +/* Add scfw image with exec attribute */
> > +IMAGE SCU mx8qx-colibri-scfw-tcm.bin
> > +/* Add ATF image with exec attribute */
> > +IMAGE A35 bl31.bin 0x80000000
> > +/* Add U-Boot image with load attribute */
> > +DATA A35 u-boot-dtb.bin 0x80020000
> > diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-
> > imx8qxp_defconfig
> > new file mode 100644
> > index 0000000000..d697546ed7
> > --- /dev/null
> > +++ b/configs/colibri-imx8qxp_defconfig
> > @@ -0,0 +1,53 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_IMX8=y
> > +CONFIG_SYS_TEXT_BASE=0x80020000
> > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > +CONFIG_TARGET_COLIBRI_IMX8QXP=y
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_NR_DRAM_BANKS=3
> > +CONFIG_FIT=y
> > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-
> > imx8qxp/imximage.cfg"
> > +CONFIG_LOG=y
> > +CONFIG_VERSION_VARIABLE=y
> > +# CONFIG_DISPLAY_BOARDINFO is not set
> > +CONFIG_BOARD_EARLY_INIT_F=y
> > +CONFIG_CMD_CPU=y
> > +# CONFIG_CMD_IMPORTENV is not set
> > +CONFIG_CMD_MEMTEST=y
> > +CONFIG_CMD_CLK=y
> > +CONFIG_CMD_DM=y
> > +CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_CMD_UUID=y
> > +CONFIG_CMD_EXT4_WRITE=y
> > +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
> > +CONFIG_ENV_IS_IN_MMC=y
> > +CONFIG_CLK_IMX8=y
> > +CONFIG_CPU=y
> > +CONFIG_DM_GPIO=y
> > +CONFIG_MXC_GPIO=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SYS_I2C_IMX_LPI2C=y
> > +CONFIG_MISC=y
> > +CONFIG_DM_MMC=y
> > +CONFIG_PHYLIB=y
> > +CONFIG_PHY_ADDR_ENABLE=y
> > +CONFIG_PHY_MICREL=y
> > +CONFIG_DM_ETH=y
> > +CONFIG_FEC_MXC_SHARE_MDIO=y
> > +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
> > +CONFIG_FEC_MXC=y
> > +CONFIG_MII=y
> > +CONFIG_PINCTRL=y
> > +CONFIG_PINCTRL_IMX8=y
> > +CONFIG_POWER_DOMAIN=y
> > +CONFIG_IMX8_POWER_DOMAIN=y
> > +CONFIG_DM_REGULATOR=y
> > +CONFIG_DM_REGULATOR_FIXED=y
> > +CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_DM_SERIAL=y
> > +CONFIG_FSL_LPUART=y
> > +CONFIG_DM_THERMAL=y
> > +# CONFIG_EFI_LOADER is not set
> > diff --git a/include/configs/colibri-imx8qxp.h
> > b/include/configs/colibri-imx8qxp.h
> > new file mode 100644
> > index 0000000000..33cbcb44a9
> > --- /dev/null
> > +++ b/include/configs/colibri-imx8qxp.h
> > @@ -0,0 +1,214 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2019 Toradex
> > + */
> > +
> > +#ifndef __COLIBRI_IMX8QXP_H
> > +#define __COLIBRI_IMX8QXP_H
> > +
> > +#include <asm/arch/imx-regs.h>
> > +#include <linux/sizes.h>
> > +
> > +#define CONFIG_REMAKE_ELF
> > +
> > +#define CONFIG_DISPLAY_BOARDINFO_LATE
> > +
> > +#undef CONFIG_CMD_EXPORTENV
> > +#undef CONFIG_CMD_IMPORTENV
> > +#undef CONFIG_CMD_IMLS
> > +
> > +#undef CONFIG_CMD_CRC32
> > +#undef CONFIG_BOOTM_NETBSD
> > +
> > +#define CONFIG_FSL_ESDHC
> > +#define CONFIG_FSL_USDHC
> > +#define CONFIG_SYS_FSL_ESDHC_ADDR	0
> > +#define USDHC1_BASE_ADDR		0x5B010000
> > +#define USDHC2_BASE_ADDR		0x5B020000
> > +#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
> > +
> > +#define CONFIG_ENV_OVERWRITE
> > +
> > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > +
> > +#define FEC_QUIRK_ENET_MAC
> > +
> > +#define CONFIG_IP_DEFRAG
> > +#define CONFIG_TFTP_BLOCKSIZE		4096
> > +#define CONFIG_TFTP_TSIZE
> > +
> > +#define CONFIG_IPADDR			192.168.10.2
> > +#define CONFIG_NETMASK			255.255.255.0
> > +#define CONFIG_SERVERIP			192.168.10.1
> > +
> > +#define MEM_LAYOUT_ENV_SETTINGS \
> > +	"fdt_addr_r=0x84000000\0" \
> > +	"kernel_addr_r=0x82000000\0" \
> > +	"ramdisk_addr_r=0x84100000\0"
> > +
> > +#ifdef CONFIG_AHAB_BOOT
> > +#define AHAB_ENV "sec_boot=yes\0"
> > +#else
> > +#define AHAB_ENV "sec_boot=no\0"
> > +#endif
> > +
> > +/* Boot M4 */
> > +#define M4_BOOT_ENV \
> > +	"m4_0_image=m4_0.bin\0" \
> > +	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
> > +		"${m4_0_image}\0" \
> > +	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr}
> > 0\0" \
> > +
> > +#define MFG_NAND_PARTITION ""
> > +
> > +#define BOOT_TARGET_DEVICES(func) \
> > +	func(MMC, mmc, 0) \
> > +	func(MMC, mmc, 1) \
> > +	func(DHCP, dhcp, na)
> > +#include <config_distro_bootcmd.h>
> > +#undef BOOTENV_RUN_NET_USB_START
> > +#define BOOTENV_RUN_NET_USB_START ""
> > +
> > +#define CONFIG_MFG_ENV_SETTINGS \
> > +	"mfgtool_args=setenv bootargs console=${console},${baudrate} "
> > \
> > +		"rdinit=/linuxrc g_mass_storage.stall=0 " \
> > +		"g_mass_storage.removable=1
> > g_mass_storage.idVendor=0x066F " \
> > +		"g_mass_storage.idProduct=0x37FF " \
> > +		"g_mass_storage.iSerialNumber=\"\" "\
> > +		MFG_NAND_PARTITION \
> > +		"video=imxdpufb5:off video=imxdpufb6:off
> > video=imxdpufb7:off " \
> > +		"clk_ignore_unused "\
> > +		"\0" \
> > +	"initrd_addr=0x83800000\0" \
> > +	"initrd_high=0xffffffff\0" \
> > +	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr}
> > " \
> > +		"${fdt_addr};\0" \
> > +
> > +/* Initial environment variables */
> > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > +	AHAB_ENV \
> > +	BOOTENV \
> > +	CONFIG_MFG_ENV_SETTINGS \
> > +	M4_BOOT_ENV \
> > +	MEM_LAYOUT_ENV_SETTINGS \
> > +	"boot_fdt=try\0" \
> > +	"bootscript=echo Running bootscript from mmc ...; source\0" \
> > +	"console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200\0" \
> > +	"fdt_addr=0x83000000\0"			\
> > +	"fdt_file=fsl-imx8qxp-colibri-eval-v3.dtb\0" \
> > +	"fdt_high=0xffffffffffffffff\0"		\
> > +	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
> > +	"image=Image\0" \
> > +	"initrd_addr=0x83800000\0"		\
> > +	"initrd_high=0xffffffffffffffff\0" \
> > +	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} "
> > \
> > +		"${script};\0" \
> > +	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
> > ${fdt_file}\0" \
> > +	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > ${image}\0" \
> > +	"mmcargs=setenv bootargs console=${console},${baudrate} " \
> > +		"root=PARTUUID=${uuid} rootwait " \
> > +	"mmcautodetect=yes\0" \
> > +	"mmcboot=echo Booting from mmc ...; " \
> > +		"run finduuid; run mmcargs; " \
> > +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try;
> > then " \
> > +			"if run loadfdt; then " \
> > +				"booti ${loadaddr} - ${fdt_addr}; " \
> > +			"else " \
> > +				"echo WARN: Cannot load the DT; " \
> > +			"fi; " \
> > +		"else " \
> > +			"echo wait for boot; " \
> > +		"fi;\0" \
> > +	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
> > +	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> > +	"netargs=setenv bootargs console=${console} root=/dev/nfs
> > ip=dhcp " \
> > +		"nfsroot=${serverip}:${nfsroot},v3,tcp
> > video=imxdpufb5:off " \
> > +		"video=imxdpufb6:off video=imxdpufb7:off\0" \
> > +	"netboot=echo Booting from net ...; " \
> > +		"run netargs; " \
> > +		"if test ${ip_dyn} = yes; then " \
> > +			"setenv get_cmd dhcp; " \
> > +		"else " \
> > +			"setenv get_cmd tftp; " \
> > +		"fi; " \
> > +		"${get_cmd} ${loadaddr} ${image}; " \
> > +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try;
> > then " \
> > +			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then "
> > \
> > +				"booti ${loadaddr} - ${fdt_addr}; " \
> > +			"else " \
> > +				"echo WARN: Cannot load the DT; " \
> > +			"fi; " \
> > +		"else " \
> > +			"booti; " \
> > +		"fi;\0" \
> > +	"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp
> > ${fdt_addr} " \
> > +		"colibri-imx8qxp/${fdt_file}; booti ${loadaddr} - " \
> > +		"${fdt_addr}\0" \
> > +	"panel=NULL\0" \
> > +	"script=boot.scr\0" \
> > +	"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
> > +
> > +#undef CONFIG_BOOTCOMMAND
> > +#define CONFIG_BOOTCOMMAND \
> > +	   "mmc dev ${mmcdev}; if mmc rescan; then " \
> > +		   "if run loadbootscript; then " \
> > +			   "run bootscript; " \
> > +		   "else " \
> > +			   "if run loadimage; then " \
> > +				   "run mmcboot; " \
> > +			   "else run netboot; " \
> > +			   "fi; " \
> > +		   "fi; " \
> > +	   "else booti ${loadaddr} - ${fdt_addr}; fi"
> > +
> > +/* Link Definitions */
> > +#define CONFIG_LOADADDR			0x80280000
> > +
> > +#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
> > +
> > +#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
> > +
> > +#define CONFIG_SYS_MEMTEST_START	0x88000000
> > +#define CONFIG_SYS_MEMTEST_END		0x89000000
> > +
> > +/* Environment in eMMC, before config block at the end of 1st
> > "boot sector" */
> > +#define CONFIG_ENV_SIZE			(8 * 1024)
> > +#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
> > +					 CONFIG_TDX_CFG_BLOCK_OFFSET)
> > +#define CONFIG_SYS_MMC_ENV_DEV		0
> > +#define CONFIG_SYS_MMC_ENV_PART		1
> > +
> > +#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
> > +
> > +/* On Colibri iMX8 USDHC1 is eMMC, USDHC2 is 4-bit SD */
> > +#define CONFIG_SYS_MMC_ENV_DEV		0		 /* USDHC1
> > eMMC */
> > +#define CONFIG_SYS_FSL_USDHC_NUM	2
> > +
> > +/* Size of malloc() pool */
> > +#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32
> > * 1024)) * 1024)
> > +
> > +#define CONFIG_SYS_SDRAM_BASE		0x80000000
> > +#define CONFIG_NR_DRAM_BANKS		3
> > +#define PHYS_SDRAM_1			0x80000000
> > +#define PHYS_SDRAM_2			0x880000000
> > +#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
> > +#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 GB */
> > +
> > +/* Serial */
> > +#define CONFIG_BAUDRATE			115200
> > +
> > +/* Monitor Command Prompt */
> > +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> > +#define CONFIG_SYS_CBSIZE		2048
> > +#define CONFIG_SYS_MAXARGS		64
> > +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
> > +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> > +					sizeof(CONFIG_SYS_PROMPT) + 16)
> > +
> > +/* Generic Timer Definitions */
> > +#define COUNTER_FREQUENCY		8000000	/* 8MHz */
> > +
> > +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
> > +#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from
> > second 128MB */
> > +
> > +#endif /* __COLIBRI_IMX8QXP_H */

[U-Boot] [PATCH 6/8] imx8: cpu: get temperature when print cpu desc

[Peng Fan]

Hi Stefano.

> Subject: Re: [PATCH 6/8] imx8: cpu: get temperature when print cpu desc
> 
> Hi Peng,
> 
> On 12/04/19 09:55, Peng Fan wrote:
> > Read the temperature when print cpu inforation.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  arch/arm/mach-imx/imx8/cpu.c | 35
> +++++++++++++++++++++++++++++++++--
> >  1 file changed, 33 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/imx8/cpu.c
> > b/arch/arm/mach-imx/imx8/cpu.c index 4bbc956f9d..25b010489b 100644
> > --- a/arch/arm/mach-imx/imx8/cpu.c
> > +++ b/arch/arm/mach-imx/imx8/cpu.c
> > @@ -11,6 +11,7 @@
> >  #include <dm/lists.h>
> >  #include <dm/uclass.h>
> >  #include <errno.h>
> > +#include <thermal.h>
> >  #include <asm/arch/sci/sci.h>
> >  #include <asm/arch/sys_proto.h>
> >  #include <asm/arch-imx/cpu.h>
> > @@ -571,15 +572,45 @@ const char *get_core_name(void)
> >  		return "?";
> >  }
> >
> > +#if defined(CONFIG_IMX_SCU_THERMAL)
> > +static int cpu_imx_get_temp(void)
> > +{
> 
> This generates a warning when CONFIG_IMX_SCU_THERMAL is not set,
> because it is called later:
> 
> > +	struct udevice *thermal_dev;
> > +	int cpu_tmp, ret;
> > +
> > +	ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0",
> > +					&thermal_dev);
> > +
> > +	if (!ret) {
> > +		ret = thermal_get_temp(thermal_dev, &cpu_tmp);
> > +		if (ret)
> > +			return 0xdeadbeef;
> > +	} else {
> > +		return 0xdeadbeef;
> > +	}
> > +
> > +	return cpu_tmp;
> > +}
> > +#endif
> > +
> >  int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)  {
> >  	struct cpu_imx_platdata *plat = dev_get_platdata(dev);
> > +	int ret;
> >
> >  	if (size < 100)
> >  		return -ENOSPC;
> >
> > -	snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n",
> > -		 plat->type, plat->rev, plat->name, plat->freq_mhz);
> > +	ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
> > +		       plat->type, plat->rev, plat->name, plat->freq_mhz);
> > +
> > +	if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
> > +		buf = buf + ret;
> > +		size = size - ret;
> > +		ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
>                                                         ^---

I not able to connect my PC to verify. But just thinking,
When CONFIG_IMX_SCU_THERMAL not enabled, the compiler
should optimize the if block? Because it is just "if (0)"

Regards,
Peng.

> here it is referenced.
> 
> Regards,
> Stefano
> 
> > +	}
> > +
> > +	snprintf(buf + ret, size - ret, "\n");
> >
> >  	return 0;
> >  }
> >
> 
> 
> --
> ==============================================================
> =======
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> ==============================================================
> =======

[U-Boot] [PATCH 6/8] imx8: cpu: get temperature when print cpu desc

[Stefano Babic]

On 25/04/19 15:46, Peng Fan wrote:
> Hi Stefano.
> 
>> Subject: Re: [PATCH 6/8] imx8: cpu: get temperature when print cpu desc
>>
>> Hi Peng,
>>
>> On 12/04/19 09:55, Peng Fan wrote:
>>> Read the temperature when print cpu inforation.
>>>
>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>> ---
>>>  arch/arm/mach-imx/imx8/cpu.c | 35
>> +++++++++++++++++++++++++++++++++--
>>>  1 file changed, 33 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-imx/imx8/cpu.c
>>> b/arch/arm/mach-imx/imx8/cpu.c index 4bbc956f9d..25b010489b 100644
>>> --- a/arch/arm/mach-imx/imx8/cpu.c
>>> +++ b/arch/arm/mach-imx/imx8/cpu.c
>>> @@ -11,6 +11,7 @@
>>>  #include <dm/lists.h>
>>>  #include <dm/uclass.h>
>>>  #include <errno.h>
>>> +#include <thermal.h>
>>>  #include <asm/arch/sci/sci.h>
>>>  #include <asm/arch/sys_proto.h>
>>>  #include <asm/arch-imx/cpu.h>
>>> @@ -571,15 +572,45 @@ const char *get_core_name(void)
>>>  		return "?";
>>>  }
>>>
>>> +#if defined(CONFIG_IMX_SCU_THERMAL)
>>> +static int cpu_imx_get_temp(void)
>>> +{
>>
>> This generates a warning when CONFIG_IMX_SCU_THERMAL is not set,
>> because it is called later:
>>
>>> +	struct udevice *thermal_dev;
>>> +	int cpu_tmp, ret;
>>> +
>>> +	ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0",
>>> +					&thermal_dev);
>>> +
>>> +	if (!ret) {
>>> +		ret = thermal_get_temp(thermal_dev, &cpu_tmp);
>>> +		if (ret)
>>> +			return 0xdeadbeef;
>>> +	} else {
>>> +		return 0xdeadbeef;
>>> +	}
>>> +
>>> +	return cpu_tmp;
>>> +}
>>> +#endif
>>> +
>>>  int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)  {
>>>  	struct cpu_imx_platdata *plat = dev_get_platdata(dev);
>>> +	int ret;
>>>
>>>  	if (size < 100)
>>>  		return -ENOSPC;
>>>
>>> -	snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n",
>>> -		 plat->type, plat->rev, plat->name, plat->freq_mhz);
>>> +	ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
>>> +		       plat->type, plat->rev, plat->name, plat->freq_mhz);
>>> +
>>> +	if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
>>> +		buf = buf + ret;
>>> +		size = size - ret;
>>> +		ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
>>                                                         ^---
> 
> I not able to connect my PC to verify. But just thinking,
> When CONFIG_IMX_SCU_THERMAL not enabled, the compiler
> should optimize the if block? Because it is just "if (0)"

But if compiler optimizes the block, I should not see the warning...

Regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Stefano Babic]

Hi Marcel,

On 25/04/19 14:35, Marcel Ziswiler wrote:
> Hi Stefano
> 
> On Thu, 2019-04-25 at 12:48 +0200, Stefano Babic wrote:
>> Hi Marcel,
>>
>> On 09/04/19 17:25, Marcel Ziswiler wrote:
>>> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>>>
>>> This commit adds initial support for the Toradex Colibri iMX8QXP
>>> 2GB WB
>>> IT V1.0B module. Unlike the V1.0A early access samples exclusively
>>> booting from SD card, they are now strapped to boot from eFuses
>>> which
>>> are factory fused to properly boot from their on-module eMMC. U-
>>> Boot
>>> supports either booting from the on-module eMMC or may be used for
>>> recovery purpose using the universal update utility (uuu) aka
>>> mfgtools
>>> 3.0.
>>>
>>> Functionality wise the following is known to be working:
>>> - eMMC and MMC/SD card
>>> - Ethernet
>>> - GPIOs
>>> - I2C
>>>
>>> Unfortunately, there is no USB functionality for the i.MX 8QXP as
>>> of
>>> yet.
>>>
>>> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>>>
>>> ---
>>>
>>
>> I merged the series and build locally (fine), but Travis complains
>> and
>> stops with error:
>>
>> +cc1: fatal error: opening output file spl/u-boot-spl.cfgout: No such
>> file or directory
>> +compilation terminated.
>>
>> Can you take a look at it ?
> 
> Sure, looks like Peng's commit caceb739ea07 ("imx: build flash.bin for
> i.MX8") takes SPL for granted while my patchset currently avoids it.

It looks so, yes.

> 
> BTW: I still don't believe SPL makes much sense on i.MX 8X given all
> the other proprietary parts involved in booting.

SPL makes more sense if it is possible to detect at runtime the HW and
change the configuration - for i.MX6, this means RAMS detection, which
boot device is booting, and so on.

On i.MX8 there is a lot of proprietary parts - we lose the flexibility
of SPL, and most features are lost (or must be provided by proprietary
code). I agree that on this platform SPL makes less sense, and i.MX8
should be built independently if CONFIG_SPL is set (this is also for
i.MX6 / MX5, there are boards without SPL and using the DCD image to set
up the RAM controller).

> Plus currently SPL
> actually breaks the USB serial downloader aka recovery mode using the
> universal update utility (uuu) aka mfgtools 3.0.
> 

Regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Peng Fan]

Hi Stefano,

> Subject: Re: [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it
> v1.0b module support
> 
> Hi Marcel,
> 
> On 25/04/19 14:35, Marcel Ziswiler wrote:
> > Hi Stefano
> >
> > On Thu, 2019-04-25 at 12:48 +0200, Stefano Babic wrote:
> >> Hi Marcel,
> >>
> >> On 09/04/19 17:25, Marcel Ziswiler wrote:
> >>> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> >>>
> >>> This commit adds initial support for the Toradex Colibri iMX8QXP 2GB
> >>> WB IT V1.0B module. Unlike the V1.0A early access samples
> >>> exclusively booting from SD card, they are now strapped to boot from
> >>> eFuses which are factory fused to properly boot from their on-module
> >>> eMMC. U- Boot supports either booting from the on-module eMMC or
> may
> >>> be used for recovery purpose using the universal update utility
> >>> (uuu) aka mfgtools 3.0.
> >>>
> >>> Functionality wise the following is known to be working:
> >>> - eMMC and MMC/SD card
> >>> - Ethernet
> >>> - GPIOs
> >>> - I2C
> >>>
> >>> Unfortunately, there is no USB functionality for the i.MX 8QXP as of
> >>> yet.
> >>>
> >>> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> >>>
> >>> ---
> >>>
> >>
> >> I merged the series and build locally (fine), but Travis complains
> >> and stops with error:
> >>
> >> +cc1: fatal error: opening output file spl/u-boot-spl.cfgout: No such
> >> file or directory
> >> +compilation terminated.
> >>
> >> Can you take a look at it ?
> >
> > Sure, looks like Peng's commit caceb739ea07 ("imx: build flash.bin for
> > i.MX8") takes SPL for granted while my patchset currently avoids it.
> 
> It looks so, yes.
> 
> >
> > BTW: I still don't believe SPL makes much sense on i.MX 8X given all
> > the other proprietary parts involved in booting.
> 
> SPL makes more sense if it is possible to detect at runtime the HW and
> change the configuration - for i.MX6, this means RAMS detection, which boot
> device is booting, and so on.
> 
> On i.MX8 there is a lot of proprietary parts - we lose the flexibility of SPL, and
> most features are lost (or must be provided by proprietary code). I agree that
> on this platform SPL makes less sense, and i.MX8 should be built
> independently if CONFIG_SPL is set (this is also for
> i.MX6 / MX5, there are boards without SPL and using the DCD image to set up
> the RAM controller).


The reason we move to use SPL on i.MX8 is that we would like to avoid
bind ATF/OP-TEE/U-Boot into a flat image with hacked offset in an image.

So the bootflow now is
SPL->ATF->OPTEE->ATF->U-Boot

Without SPL, when generating flash.bin, we have to hack ATF to copy OP-TEE
image from flash.bin to the runtime location.

> 
> > Plus currently SPL
> > actually breaks the USB serial downloader aka recovery mode using the
> > universal update utility (uuu) aka mfgtools 3.0.

The usb related function for i.MX8 is not ready now. we are almost run out
of ocram with SPL DM, thinking to use OF_PLATDATA now, then move
to usb functions.

Thanks,
Peng.

> >
> 
> Regards,
> Stefano
> 
> --
> ==============================================================
> =======
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> ==============================================================
> =======

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Stefano Babic]

Hi Peng,

On 26/04/19 04:10, Peng Fan wrote:
> Hi Stefano,
> 
>> Subject: Re: [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it
>> v1.0b module support
>>
>> Hi Marcel,
>>
>> On 25/04/19 14:35, Marcel Ziswiler wrote:
>>> Hi Stefano
>>>
>>> On Thu, 2019-04-25 at 12:48 +0200, Stefano Babic wrote:
>>>> Hi Marcel,
>>>>
>>>> On 09/04/19 17:25, Marcel Ziswiler wrote:
>>>>> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>>>>>
>>>>> This commit adds initial support for the Toradex Colibri iMX8QXP 2GB
>>>>> WB IT V1.0B module. Unlike the V1.0A early access samples
>>>>> exclusively booting from SD card, they are now strapped to boot from
>>>>> eFuses which are factory fused to properly boot from their on-module
>>>>> eMMC. U- Boot supports either booting from the on-module eMMC or
>> may
>>>>> be used for recovery purpose using the universal update utility
>>>>> (uuu) aka mfgtools 3.0.
>>>>>
>>>>> Functionality wise the following is known to be working:
>>>>> - eMMC and MMC/SD card
>>>>> - Ethernet
>>>>> - GPIOs
>>>>> - I2C
>>>>>
>>>>> Unfortunately, there is no USB functionality for the i.MX 8QXP as of
>>>>> yet.
>>>>>
>>>>> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>>>>>
>>>>> ---
>>>>>
>>>>
>>>> I merged the series and build locally (fine), but Travis complains
>>>> and stops with error:
>>>>
>>>> +cc1: fatal error: opening output file spl/u-boot-spl.cfgout: No such
>>>> file or directory
>>>> +compilation terminated.
>>>>
>>>> Can you take a look at it ?
>>>
>>> Sure, looks like Peng's commit caceb739ea07 ("imx: build flash.bin for
>>> i.MX8") takes SPL for granted while my patchset currently avoids it.
>>
>> It looks so, yes.
>>
>>>
>>> BTW: I still don't believe SPL makes much sense on i.MX 8X given all
>>> the other proprietary parts involved in booting.
>>
>> SPL makes more sense if it is possible to detect at runtime the HW and
>> change the configuration - for i.MX6, this means RAMS detection, which boot
>> device is booting, and so on.
>>
>> On i.MX8 there is a lot of proprietary parts - we lose the flexibility of SPL, and
>> most features are lost (or must be provided by proprietary code). I agree that
>> on this platform SPL makes less sense, and i.MX8 should be built
>> independently if CONFIG_SPL is set (this is also for
>> i.MX6 / MX5, there are boards without SPL and using the DCD image to set up
>> the RAM controller).
> 
> 
> The reason we move to use SPL on i.MX8 is that we would like to avoid
> bind ATF/OP-TEE/U-Boot into a flat image with hacked offset in an image.
> 

It seemed I have missed some point. Thanks for clarification. This makes
sense.

> So the bootflow now is
> SPL->ATF->OPTEE->ATF->U-Boot
> 
> Without SPL, when generating flash.bin, we have to hack ATF to copy OP-TEE
> image from flash.bin to the runtime location.

Nevertheless, I understand that it is not strictly required to enable
OPTEE to boot the kernel, and in some applications a secure zone is not
required. The thing is not that SPL is used here, but to constrain all
other users like Marcel to do the same. With i.MX6, even if I strongly
suggested to do this to allow run time detection, I let boards without
SPL and with just u-boot.imx (with built-in DCD) to flow into mainline -
the board maintainer rules as he knows better where the device is used.

So I will prefer that the build assume to have SPL just if SPL is
configured and not in any case, letting boards without SPL (like this
colibri-mx8) to build.

> 
>>
>>> Plus currently SPL
>>> actually breaks the USB serial downloader aka recovery mode using the
>>> universal update utility (uuu) aka mfgtools 3.0.
> 
> The usb related function for i.MX8 is not ready now.

That is ok - it s WIP, it will be merged when ready. I agree with you,
this is *not* a reason to avoid SPL.

> we are almost run out
> of ocram with SPL DM, thinking to use OF_PLATDATA now, then move
> to usb functions.

Understood.

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Peng Fan]

Hi Stefano,

> Subject: Re: [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it
> v1.0b module support
> 
> Hi Peng,
> 
> On 26/04/19 04:10, Peng Fan wrote:
> > Hi Stefano,
> >
> >> Subject: Re: [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb
> >> wb it v1.0b module support
> >>
> >> Hi Marcel,
> >>
> >> On 25/04/19 14:35, Marcel Ziswiler wrote:
> >>> Hi Stefano
> >>>
> >>> On Thu, 2019-04-25 at 12:48 +0200, Stefano Babic wrote:
> >>>> Hi Marcel,
> >>>>
> >>>> On 09/04/19 17:25, Marcel Ziswiler wrote:
> >>>>> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> >>>>>
> >>>>> This commit adds initial support for the Toradex Colibri iMX8QXP
> >>>>> 2GB WB IT V1.0B module. Unlike the V1.0A early access samples
> >>>>> exclusively booting from SD card, they are now strapped to boot
> >>>>> from eFuses which are factory fused to properly boot from their
> >>>>> on-module eMMC. U- Boot supports either booting from the
> on-module
> >>>>> eMMC or
> >> may
> >>>>> be used for recovery purpose using the universal update utility
> >>>>> (uuu) aka mfgtools 3.0.
> >>>>>
> >>>>> Functionality wise the following is known to be working:
> >>>>> - eMMC and MMC/SD card
> >>>>> - Ethernet
> >>>>> - GPIOs
> >>>>> - I2C
> >>>>>
> >>>>> Unfortunately, there is no USB functionality for the i.MX 8QXP as
> >>>>> of yet.
> >>>>>
> >>>>> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> >>>>>
> >>>>> ---
> >>>>>
> >>>>
> >>>> I merged the series and build locally (fine), but Travis complains
> >>>> and stops with error:
> >>>>
> >>>> +cc1: fatal error: opening output file spl/u-boot-spl.cfgout: No
> >>>> +such
> >>>> file or directory
> >>>> +compilation terminated.
> >>>>
> >>>> Can you take a look at it ?
> >>>
> >>> Sure, looks like Peng's commit caceb739ea07 ("imx: build flash.bin
> >>> for
> >>> i.MX8") takes SPL for granted while my patchset currently avoids it.
> >>
> >> It looks so, yes.
> >>
> >>>
> >>> BTW: I still don't believe SPL makes much sense on i.MX 8X given all
> >>> the other proprietary parts involved in booting.
> >>
> >> SPL makes more sense if it is possible to detect at runtime the HW
> >> and change the configuration - for i.MX6, this means RAMS detection,
> >> which boot device is booting, and so on.
> >>
> >> On i.MX8 there is a lot of proprietary parts - we lose the
> >> flexibility of SPL, and most features are lost (or must be provided
> >> by proprietary code). I agree that on this platform SPL makes less
> >> sense, and i.MX8 should be built independently if CONFIG_SPL is set
> >> (this is also for
> >> i.MX6 / MX5, there are boards without SPL and using the DCD image to
> >> set up the RAM controller).
> >
> >
> > The reason we move to use SPL on i.MX8 is that we would like to avoid
> > bind ATF/OP-TEE/U-Boot into a flat image with hacked offset in an image.
> >
> 
> It seemed I have missed some point. Thanks for clarification. This makes
> sense.
> 
> > So the bootflow now is
> > SPL->ATF->OPTEE->ATF->U-Boot
> >
> > Without SPL, when generating flash.bin, we have to hack ATF to copy
> > OP-TEE image from flash.bin to the runtime location.
> 
> Nevertheless, I understand that it is not strictly required to enable OPTEE to
> boot the kernel, and in some applications a secure zone is not required. The
> thing is not that SPL is used here, but to constrain all other users like Marcel to
> do the same. With i.MX6, even if I strongly suggested to do this to allow run
> time detection, I let boards without SPL and with just u-boot.imx (with built-in
> DCD) to flow into mainline - the board maintainer rules as he knows better
> where the device is used.
> 
> So I will prefer that the build assume to have SPL just if SPL is configured and
> not in any case, letting boards without SPL (like this
> colibri-mx8) to build.

ok. Then need to think about how to bind bl31.bin and u-boot.bin,

the binded image will be copied to 0x80000000 by ROM.

Consider bl31 is 128KB now, so uboot entry could be hardcoded
to 0x80020000, and u-boot.bin is 128KB offset of the final image.

Could use binman. And then need to generate flash.bin.

Regards,
Peng.

> 
> >
> >>
> >>> Plus currently SPL
> >>> actually breaks the USB serial downloader aka recovery mode using
> >>> the universal update utility (uuu) aka mfgtools 3.0.
> >
> > The usb related function for i.MX8 is not ready now.
> 
> That is ok - it s WIP, it will be merged when ready. I agree with you, this is
> *not* a reason to avoid SPL.
> 
> > we are almost run out
> > of ocram with SPL DM, thinking to use OF_PLATDATA now, then move to
> > usb functions.
> 
> Understood.
> 
> Best regards,
> Stefano
> 
> --
> ==============================================================
> =======
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> ==============================================================
> =======

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Marcel Ziswiler]

Hi Peng and Stefano

On Fri, 2019-04-26 at 10:38 +0200, Stefano Babic wrote:
> Hi Peng,
> 
> On 26/04/19 04:10, Peng Fan wrote:
> > Hi Stefano,
> > 
> > > Subject: Re: [PATCH v2 5/5] board: toradex: add colibri imx8qxp
> > > 2gb wb it
> > > v1.0b module support
> > > 
> > > Hi Marcel,
> > > 
> > > On 25/04/19 14:35, Marcel Ziswiler wrote:
> > > > Hi Stefano
> > > > 
> > > > On Thu, 2019-04-25 at 12:48 +0200, Stefano Babic wrote:
> > > > > Hi Marcel,
> > > > > 
> > > > > On 09/04/19 17:25, Marcel Ziswiler wrote:
> > > > > > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > > > > > 
> > > > > > This commit adds initial support for the Toradex Colibri
> > > > > > iMX8QXP 2GB
> > > > > > WB IT V1.0B module. Unlike the V1.0A early access samples
> > > > > > exclusively booting from SD card, they are now strapped to
> > > > > > boot from
> > > > > > eFuses which are factory fused to properly boot from their
> > > > > > on-module
> > > > > > eMMC. U- Boot supports either booting from the on-module
> > > > > > eMMC or
> > > may
> > > > > > be used for recovery purpose using the universal update
> > > > > > utility
> > > > > > (uuu) aka mfgtools 3.0.
> > > > > > 
> > > > > > Functionality wise the following is known to be working:
> > > > > > - eMMC and MMC/SD card
> > > > > > - Ethernet
> > > > > > - GPIOs
> > > > > > - I2C
> > > > > > 
> > > > > > Unfortunately, there is no USB functionality for the i.MX
> > > > > > 8QXP as of
> > > > > > yet.
> > > > > > 
> > > > > > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com
> > > > > > >
> > > > > > 
> > > > > > ---
> > > > > > 
> > > > > 
> > > > > I merged the series and build locally (fine), but Travis
> > > > > complains
> > > > > and stops with error:
> > > > > 
> > > > > +cc1: fatal error: opening output file spl/u-boot-spl.cfgout: 
> > > > > No such
> > > > > file or directory
> > > > > +compilation terminated.
> > > > > 
> > > > > Can you take a look at it ?
> > > > 
> > > > Sure, looks like Peng's commit caceb739ea07 ("imx: build
> > > > flash.bin for
> > > > i.MX8") takes SPL for granted while my patchset currently
> > > > avoids it.
> > > 
> > > It looks so, yes.
> > > 
> > > > BTW: I still don't believe SPL makes much sense on i.MX 8X
> > > > given all
> > > > the other proprietary parts involved in booting.
> > > 
> > > SPL makes more sense if it is possible to detect at runtime the
> > > HW and
> > > change the configuration - for i.MX6, this means RAMS detection,
> > > which boot
> > > device is booting, and so on.
> > > 
> > > On i.MX8 there is a lot of proprietary parts - we lose the
> > > flexibility of SPL, and
> > > most features are lost (or must be provided by proprietary code).
> > > I agree that
> > > on this platform SPL makes less sense, and i.MX8 should be built
> > > independently if CONFIG_SPL is set (this is also for
> > > i.MX6 / MX5, there are boards without SPL and using the DCD image
> > > to set up
> > > the RAM controller).
> > 
> > The reason we move to use SPL on i.MX8 is that we would like to
> > avoid
> > bind ATF/OP-TEE/U-Boot into a flat image with hacked offset in an
> > image.
> > 
> 
> It seemed I have missed some point. Thanks for clarification. This
> makes
> sense.

OK, I was also not aware of this.

However, currently I am just happy the current tooling kinda works.
Which is we can ship stuff to customers and they may use uuu to recover
bricked modules. So far nobody is talking about OP-TEE and such
advanced use cases yet.

On the other hand enabling SPL currently does not seem to work at all
on our hardware. Neither booting from eMMC nor recovering using uuu.
That is really the main reason I decided against it at least for now.

> > So the bootflow now is
> > SPL->ATF->OPTEE->ATF->U-Boot
> > 
> > Without SPL, when generating flash.bin, we have to hack ATF to copy
> > OP-TEE
> > image from flash.bin to the runtime location.
> 
> Nevertheless, I understand that it is not strictly required to enable
> OPTEE to boot the kernel, and in some applications a secure zone is
> not
> required. The thing is not that SPL is used here, but to constrain
> all
> other users like Marcel to do the same. With i.MX6, even if I
> strongly
> suggested to do this to allow run time detection, I let boards
> without
> SPL and with just u-boot.imx (with built-in DCD) to flow into
> mainline -
> the board maintainer rules as he knows better where the device is
> used.

Thanks!

> So I will prefer that the build assume to have SPL just if SPL is
> configured and not in any case, letting boards without SPL (like this
> colibri-mx8

Colibri iMX8X that is while on the Apalis family we have the Apalis
iMX8 (e.g. with the i.MX 8QuadMax or i.MX 8QuadPlus) and the new Apalis
iMX8X with ECC RAM still in the works. Welcome to the i.MX 8 series
with the i.MX 8 and i.MX 8X families and careful with NXP's brilliant
naming scheme (;-p).

> ) to build.

Don't worry. I believe I found a fix for the issue at hand and will
send a patch shortly.

> > > > Plus currently SPL
> > > > actually breaks the USB serial downloader aka recovery mode
> > > > using the
> > > > universal update utility (uuu) aka mfgtools 3.0.
> > 
> > The usb related function for i.MX8 is not ready now.
> 
> That is ok - it s WIP, it will be merged when ready. I agree with
> you,
> this is *not* a reason to avoid SPL.

Agreed. However, it is kinda painful requiring different U-Boot
configuration flavours for regular boot vs. recovery. That said we used
to previously do this on Apalis/Colibri iMX6 as well so it is
definitely no show stopper.

> > we are almost run out
> > of ocram with SPL DM, thinking to use OF_PLATDATA now, then move
> > to usb functions.
> 
> Understood.

Yeah, I also played with OF_PLATDATA once before however was not
entirely happy with the result as of yet. I guess WIP patches welcome
(;-p).

> Best regards,
> Stefano

Cheers

Marcel

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Peng Fan]

> Subject: Re: [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it
> v1.0b module support
> 
> Hi Peng and Stefano
> 
> On Fri, 2019-04-26 at 10:38 +0200, Stefano Babic wrote:
> > Hi Peng,
> >
> > On 26/04/19 04:10, Peng Fan wrote:
> > > Hi Stefano,
> > >
> > > > Subject: Re: [PATCH v2 5/5] board: toradex: add colibri imx8qxp
> > > > 2gb wb it v1.0b module support
> > > >
> > > > Hi Marcel,
> > > >
> > > > On 25/04/19 14:35, Marcel Ziswiler wrote:
> > > > > Hi Stefano
> > > > >
> > > > > On Thu, 2019-04-25 at 12:48 +0200, Stefano Babic wrote:
> > > > > > Hi Marcel,
> > > > > >
> > > > > > On 09/04/19 17:25, Marcel Ziswiler wrote:
> > > > > > > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > > > > > >
> > > > > > > This commit adds initial support for the Toradex Colibri
> > > > > > > iMX8QXP 2GB WB IT V1.0B module. Unlike the V1.0A early
> > > > > > > access samples exclusively booting from SD card, they are
> > > > > > > now strapped to boot from eFuses which are factory fused to
> > > > > > > properly boot from their on-module eMMC. U- Boot supports
> > > > > > > either booting from the on-module eMMC or
> > > > may
> > > > > > > be used for recovery purpose using the universal update
> > > > > > > utility
> > > > > > > (uuu) aka mfgtools 3.0.
> > > > > > >
> > > > > > > Functionality wise the following is known to be working:
> > > > > > > - eMMC and MMC/SD card
> > > > > > > - Ethernet
> > > > > > > - GPIOs
> > > > > > > - I2C
> > > > > > >
> > > > > > > Unfortunately, there is no USB functionality for the i.MX
> > > > > > > 8QXP as of yet.
> > > > > > >
> > > > > > > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com
> > > > > > > >
> > > > > > >
> > > > > > > ---
> > > > > > >
> > > > > >
> > > > > > I merged the series and build locally (fine), but Travis
> > > > > > complains and stops with error:
> > > > > >
> > > > > > +cc1: fatal error: opening output file spl/u-boot-spl.cfgout:
> > > > > > No such
> > > > > > file or directory
> > > > > > +compilation terminated.
> > > > > >
> > > > > > Can you take a look at it ?
> > > > >
> > > > > Sure, looks like Peng's commit caceb739ea07 ("imx: build
> > > > > flash.bin for
> > > > > i.MX8") takes SPL for granted while my patchset currently avoids
> > > > > it.
> > > >
> > > > It looks so, yes.
> > > >
> > > > > BTW: I still don't believe SPL makes much sense on i.MX 8X given
> > > > > all the other proprietary parts involved in booting.
> > > >
> > > > SPL makes more sense if it is possible to detect at runtime the HW
> > > > and change the configuration - for i.MX6, this means RAMS
> > > > detection, which boot device is booting, and so on.
> > > >
> > > > On i.MX8 there is a lot of proprietary parts - we lose the
> > > > flexibility of SPL, and most features are lost (or must be
> > > > provided by proprietary code).
> > > > I agree that
> > > > on this platform SPL makes less sense, and i.MX8 should be built
> > > > independently if CONFIG_SPL is set (this is also for
> > > > i.MX6 / MX5, there are boards without SPL and using the DCD image
> > > > to set up the RAM controller).
> > >
> > > The reason we move to use SPL on i.MX8 is that we would like to
> > > avoid bind ATF/OP-TEE/U-Boot into a flat image with hacked offset in
> > > an image.
> > >
> >
> > It seemed I have missed some point. Thanks for clarification. This
> > makes sense.
> 
> OK, I was also not aware of this.
> 
> However, currently I am just happy the current tooling kinda works.
> Which is we can ship stuff to customers and they may use uuu to recover
> bricked modules. So far nobody is talking about OP-TEE and such advanced
> use cases yet.
> 
> On the other hand enabling SPL currently does not seem to work at all on our
> hardware. Neither booting from eMMC nor recovering using uuu.
> That is really the main reason I decided against it at least for now.

In vendor tree, we use SPL to load i.MX8 container image.
To UUU, 1st need to enable usb gadget functions in SPL, then enable container
for the 2nd image. So with uuu, it not work with upstream U-Boot now.

> 
> > > So the bootflow now is
> > > SPL->ATF->OPTEE->ATF->U-Boot
> > >
> > > Without SPL, when generating flash.bin, we have to hack ATF to copy
> > > OP-TEE image from flash.bin to the runtime location.
> >
> > Nevertheless, I understand that it is not strictly required to enable
> > OPTEE to boot the kernel, and in some applications a secure zone is
> > not required. The thing is not that SPL is used here, but to constrain
> > all other users like Marcel to do the same. With i.MX6, even if I
> > strongly suggested to do this to allow run time detection, I let
> > boards without SPL and with just u-boot.imx (with built-in DCD) to
> > flow into mainline - the board maintainer rules as he knows better
> > where the device is used.
> 
> Thanks!
> 
> > So I will prefer that the build assume to have SPL just if SPL is
> > configured and not in any case, letting boards without SPL (like this
> > colibri-mx8
> 
> Colibri iMX8X that is while on the Apalis family we have the Apalis
> iMX8 (e.g. with the i.MX 8QuadMax or i.MX 8QuadPlus) and the new Apalis
> iMX8X with ECC RAM still in the works. Welcome to the i.MX 8 series with the
> i.MX 8 and i.MX 8X families and careful with NXP's brilliant naming scheme
> (;-p).
> 
> > ) to build.
> 
> Don't worry. I believe I found a fix for the issue at hand and will send a patch
> shortly.

ok.

Regards,
Peng.

> 
> > > > > Plus currently SPL
> > > > > actually breaks the USB serial downloader aka recovery mode
> > > > > using the universal update utility (uuu) aka mfgtools 3.0.
> > >
> > > The usb related function for i.MX8 is not ready now.
> >
> > That is ok - it s WIP, it will be merged when ready. I agree with you,
> > this is *not* a reason to avoid SPL.
> 
> Agreed. However, it is kinda painful requiring different U-Boot configuration
> flavours for regular boot vs. recovery. That said we used to previously do this
> on Apalis/Colibri iMX6 as well so it is definitely no show stopper.
> 
> > > we are almost run out
> > > of ocram with SPL DM, thinking to use OF_PLATDATA now, then move to
> > > usb functions.
> >
> > Understood.
> 
> Yeah, I also played with OF_PLATDATA once before however was not entirely
> happy with the result as of yet. I guess WIP patches welcome (;-p).
> 
> > Best regards,
> > Stefano
> 
> Cheers
> 
> Marcel

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Marcel Ziswiler]

Hi Igor

Sorry, somehow I missed your comments below (;-p).

I will send out a v4 (yes there already was a v3 BTW) shortly including
the SPL resp. without SPL build fix.

On Thu, 2019-04-11 at 12:47 +0200, Igor Opaniuk wrote:
> Hi Marcel,
> 
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
> 
> Some minor comments below (can be addressed in different patch):
> 
> On Tue, Apr 9, 2019 at 5:34 PM Marcel Ziswiler <marcel@ziswiler.com>
> wrote:
> > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > 
> > This commit adds initial support for the Toradex Colibri iMX8QXP
> > 2GB WB
> > IT V1.0B module. Unlike the V1.0A early access samples exclusively
> > booting from SD card, they are now strapped to boot from eFuses
> > which
> > are factory fused to properly boot from their on-module eMMC. U-
> > Boot
> > supports either booting from the on-module eMMC or may be used for
> > recovery purpose using the universal update utility (uuu) aka
> > mfgtools
> > 3.0.
> > 
> > Functionality wise the following is known to be working:
> > - eMMC and MMC/SD card
> > - Ethernet
> > - GPIOs
> > - I2C
> > 
> > Unfortunately, there is no USB functionality for the i.MX 8QXP as
> > of
> > yet.
> > 
> > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > 
> > ---
> > 
> > Changes in v2:
> > - Changed imx-atf git clone command to include initial branch
> >   information as suggested by Igor.
> > - Sorted board file includes alphabetically as suggested by Igor.
> > - Got rid of SPL configuration in legacy header file as suggested
> > by
> >   Igor and the whole use of SPL on i.MX 8X anyway neither works
> > well
> >   nor makes any much sense at all.
> > 
> >  arch/arm/dts/Makefile                         |   4 +-
> >  arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi  | 112 ++++++
> >  arch/arm/dts/fsl-imx8qxp-colibri.dts          | 328
> > ++++++++++++++++++
> >  arch/arm/mach-imx/imx8/Kconfig                |   6 +
> >  board/toradex/colibri-imx8qxp/Kconfig         |  30 ++
> >  board/toradex/colibri-imx8qxp/MAINTAINERS     |   9 +
> >  board/toradex/colibri-imx8qxp/Makefile        |   7 +
> >  board/toradex/colibri-imx8qxp/README          |  66 ++++
> >  .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 212 +++++++++++
> >  board/toradex/colibri-imx8qxp/imximage.cfg    |  24 ++
> >  configs/colibri-imx8qxp_defconfig             |  53 +++
> >  include/configs/colibri-imx8qxp.h             | 214 ++++++++++++
> >  12 files changed, 1064 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> >  create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts
> >  create mode 100644 board/toradex/colibri-imx8qxp/Kconfig
> >  create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS
> >  create mode 100644 board/toradex/colibri-imx8qxp/Makefile
> >  create mode 100644 board/toradex/colibri-imx8qxp/README
> >  create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> >  create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg
> >  create mode 100644 configs/colibri-imx8qxp_defconfig
> >  create mode 100644 include/configs/colibri-imx8qxp.h
> > 
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 13d1d67624..2a551d42a4 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -559,7 +559,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
> > 
> >  dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
> > 
> > -dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
> > +dtb-$(CONFIG_ARCH_IMX8) += \
> > +       fsl-imx8qxp-colibri.dtb \
> > +       fsl-imx8qxp-mek.dtb
> > 
> >  dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
> > 
> > diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..f8686befdf
> > --- /dev/null
> > +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > @@ -0,0 +1,112 @@
> > +// SPDX-License-Identifier: GPL-2.0+ OR X11
> > +/*
> > + * Copyright 2019 Toradex AG
> > + */
> > +
> > +&mu {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&clk {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&iomuxc {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio0 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio1 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio2 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio3 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio4 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio5 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio6 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_lsio_gpio7 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_conn {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_conn_sdch0 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_conn_sdch1 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&pd_conn_sdch2 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&gpio0 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&gpio1 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&gpio2 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&gpio3 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&gpio4 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&gpio5 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&gpio6 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&gpio7 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&lpuart3 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&usdhc1 {
> > +       u-boot,dm-spl;
> > +};
> > +
> > +&usdhc2 {
> > +       u-boot,dm-spl;
> > +};
> > diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts
> > b/arch/arm/dts/fsl-imx8qxp-colibri.dts
> > new file mode 100644
> > index 0000000000..0c20edf2cf
> > --- /dev/null
> > +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts
> > @@ -0,0 +1,328 @@
> > +// SPDX-License-Identifier: GPL-2.0+ OR X11
> > +/*
> > + * Copyright 2019 Toradex AG
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "fsl-imx8qxp.dtsi"
> > +#include "fsl-imx8qxp-colibri-u-boot.dtsi"
> > +
> > +/ {
> > +       model = "Toradex Colibri iMX8QXP";
> > +       compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";
> > +
> > +       chosen {
> > +               bootargs = "console=ttyLP3,115200
> > earlycon=lpuart32,0x5a090000,115200";
> > +               stdout-path = &lpuart3;
> > +       };
> > +
> > +       reg_usbh_vbus: regulator-usbh-vbus {
> > +               compatible = "regulator-fixed";
> > +               pinctrl-names = "default";
> > +               pinctrl-0 = <&pinctrl_usbh1_reg>;
> > +               regulator-name = "usbh_vbus";
> > +               regulator-min-microvolt = <5000000>;
> > +               regulator-max-microvolt = <5000000>;
> > +               gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
> > +       };
> > +};
> > +
> > +&iomuxc {
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>,
> > <&pinctrl_hog2>;
> > +
> > +       colibri-imx8qxp {
> > +               pinctrl_lpuart0: lpuart0grp {
> > +                       fsl,pins = <
> > +                               SC_P_UART0_RX_ADMA_UART0_RX     0x0
> > 6000020
> > +                               SC_P_UART0_TX_ADMA_UART0_TX     0x0
> > 6000020
> > +                       >;
> > +               };
> > +
> > +               pinctrl_lpuart3: lpuart3grp {
> > +                       fsl,pins = <
> > +                               SC_P_FLEXCAN2_RX_ADMA_UART3_RX  0x0
> > 6000020
> > +                               SC_P_FLEXCAN2_TX_ADMA_UART3_TX  0x0
> > 6000020
> > +                       >;
> > +               };
> > +
> > +               pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
> > +                       fsl,pins = <
> > +                               SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_
> > IO00 0x00000020 /* DTR */
> > +                               SC_P_SAI1_RXD_LSIO_GPIO0_IO29      
> >      0x00000020 /* CTS */
> > +                               SC_P_SAI1_RXC_LSIO_GPIO0_IO30      
> >      0x00000020 /* RTS */
> > +                               SC_P_CSI_RESET_LSIO_GPIO3_IO03     
> >      0x00000020 /* DSR */
> > +                               SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22   
> >      0x00000020 /* DCD */
> > +                               SC_P_CSI_EN_LSIO_GPIO3_IO02        
> >      0x00000020 /* RI */
> > +                       >;
> > +               };
> > +
> > +               pinctrl_fec1: fec1grp {
> > +                       fsl,pins = <
> > +                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENE
> > TB0_PAD      0x000014a0 /* Use pads in 3.3V mode */
> > +                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENE
> > TB1_PAD      0x000014a0 /* Use pads in 3.3V mode */
> > +                               SC_P_ENET0_MDC_CONN_ENET0_MDC      
> >              0x06000020
> > +                               SC_P_ENET0_MDIO_CONN_ENET0_MDIO    
> >              0x06000020
> > +                               SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_
> > RGMII_TX_CTL 0x00000061
> > +                               SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCL
> > K50M_OUT     0x06000061
> > +                               SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RG
> > MII_TXD0     0x00000061
> > +                               SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RG
> > MII_TXD1     0x00000061
> > +                               SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_
> > RGMII_RX_CTL 0x00000061
> > +                               SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RG
> > MII_RXD0     0x00000061
> > +                               SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RG
> > MII_RXD1     0x00000061
> > +                               SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RM
> > II_RX_ER     0x00000061
> > +                       >;
> > +               };
> > +
> > +               pinctrl_gpio_bl_on: gpio-bl-on {
> > +                       fsl,pins = <
> > +                               SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12  
> >      0x00000040
> > +                       >;
> > +               };
> > +
> > +               pinctrl_hog0: hog0grp {
> > +                       fsl,pins = <
> > +                               SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_
> > PAD  0x000514a0 /* Use pads in 3.3V mode */
> > +                       >;
> > +               };
> > +
> > +               pinctrl_hog1: hog1grp {
> > +                       fsl,pins = <
> > +                               SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10  
> >      0x00000020 /*  45 */
> > +                               SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO
> > 02   0x06000020 /*  65 */
> > +                                       SC_P_CSI_D07_CI_PI_D09     
> >      0x00000061
> > +                               SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11  
> >      0x00000020 /*  69 */
> > +                               SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13    
> >      0x00000020 /*  73 */
> > +                               SC_P_SAI0_TXC_LSIO_GPIO0_IO26      
> >      0x00000020 /*  79 */
> > +                                       SC_P_CSI_D02_CI_PI_D04     
> >      0x00000061
> > +                               SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO0
> > 3    0x06000020 /*  85 */
> > +                                       SC_P_CSI_D06_CI_PI_D08     
> >      0x00000061
> > +                               SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17   
> >      0x00000020 /*  95 */
> > +                               SC_P_SAI0_RXD_LSIO_GPIO0_IO27      
> >      0x00000020 /*  97 */
> > +                                       SC_P_CSI_D03_CI_PI_D05     
> >      0x00000061
> > +                               SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18  
> >      0x00000020 /*  99 */
> > +                               SC_P_SAI0_TXFS_LSIO_GPIO0_IO28     
> >      0x00000020 /* 101 */
> > +                                       SC_P_CSI_D00_CI_PI_D02     
> >      0x00000061
> > +                               SC_P_SAI0_TXD_LSIO_GPIO0_IO25      
> >      0x00000020 /* 103 */
> > +                                       SC_P_CSI_D01_CI_PI_D03     
> >      0x00000061
> 
> I seems that in 20 lines above alignment is broken a bit.

No, I believe Max intentionally did it that way downstream indicating
that those SODIMM pins are each multiplexed onto two SoC balls. Toradex
does this at times to gain greater pin compatibility across our module
families.

Further comments down below taken into account. Thanks!

Cheers

Marcel

> > +                               SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19  
> >      0x00000020 /* 105 */
> > +                               SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20  
> >      0x00000020 /* 107 */
> > +                               SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05   
> >      0x00000020 /* 127 */
> > +                               SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06   
> >      0x00000020 /* 131 */
> > +                               SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04   
> >      0x00000020 /* 133 */
> > +                               SC_P_CSI_PCLK_LSIO_GPIO3_IO00      
> >      0x00000020 /*  96 */
> > +                               SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21  
> >      0x00000020 /*  98 */
> > +                               SC_P_SAI1_RXFS_LSIO_GPIO0_IO31     
> >      0x00000020 /* 100 */
> > +                               SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22    
> >      0x00000020 /* 102 */
> > +                               SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23  
> >      0x00000020 /* 104 */
> > +                               SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24  
> >      0x00000020 /* 106 */
> > +                       >;
> > +               };
> > +
> > +               pinctrl_hog2: hog2grp {
> > +                       fsl,pins = <
> > +                               SC_P_CSI_MCLK_LSIO_GPIO3_IO01      
> >      0x00000020 /*  75 */
> > +                               SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14  
> >      0x00000020 /*  77 */
> > +                               SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15  
> >      0x00000020 /*  89 */
> > +                               SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16   
> >      0x00000020 /*  93 */
> > +                       >;
> > +               };
> > +
> > +               /* Off Module I2C */
> > +               pinctrl_i2c1: i2c1grp {
> > +                       fsl,pins = <
> > +                               SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_S
> > CL   0x06000021
> > +                               SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_S
> > DA   0x06000021
> > +                       >;
> > +               };
> > +
> > +               /*INT*/
> > +               pinctrl_usb3503a: usb3503a-grp {
> > +                       fsl,pins = <
> > +                               SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_
> > IO04 0x00000061
> > +                       >;
> > +               };
> > +
> > +               pinctrl_usbc_det: usbc-det {
> > +                       fsl,pins = <
> > +                               SC_P_ENET0_REFCLK_125M_25M_LSIO_GPI
> > O5_IO09      0x06000040
> > +                       >;
> > +               };
> > +
> > +               pinctrl_usbh1_reg: usbh1-reg {
> > +                       fsl,pins = <
> > +                               SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03   
> >      0x06000040
> > +                       >;
> > +               };
> > +
> > +               pinctrl_usdhc1: usdhc1grp {
> > +                       fsl,pins = <
> > +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK      
> >      0x06000041
> > +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD      
> >      0x00000021
> > +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7  
> >      0x00000021
> > +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE
> >      0x00000041
> > +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET
> > _B   0x00000021
> > +                       >;
> > +               };
> > +
> > +               pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> > +                       fsl,pins = <
> > +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK      
> >      0x06000041
> > +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD      
> >      0x00000021
> > +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7  
> >      0x00000021
> > +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE
> >      0x00000041
> > +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET
> > _B   0x00000021
> > +                       >;
> > +               };
> > +
> > +               pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> > +                       fsl,pins = <
> > +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK      
> >      0x06000041
> > +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD      
> >      0x00000021
> > +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6  
> >      0x00000021
> > +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7  
> >      0x00000021
> > +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE
> >      0x00000041
> > +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET
> > _B   0x00000021
> > +                       >;
> > +               };
> > +
> > +               pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> > +                       fsl,pins = <
> > +                               SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09  
> >      0x06000021
> > +                       >;
> > +               };
> > +
> > +               pinctrl_usdhc2: usdhc2grp {
> > +                       fsl,pins = <
> > +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK    
> >      0x06000041
> > +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD    
> >      0x00000021
> > +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0
> >      0x00000021
> > +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1
> >      0x00000021
> > +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2
> >      0x00000021
> > +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3
> >      0x00000021
> > +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSE
> > LECT 0x00000021
> > +                       >;
> > +               };
> > +
> > +               pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> > +                       fsl,pins = <
> > +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK    
> >      0x06000041
> > +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD    
> >      0x00000021
> > +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0
> >      0x00000021
> > +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1
> >      0x00000021
> > +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2
> >      0x00000021
> > +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3
> >      0x00000021
> > +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSE
> > LECT 0x00000021
> > +                       >;
> > +               };
> > +
> > +               pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> > +                       fsl,pins = <
> > +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK    
> >      0x06000041
> > +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD    
> >      0x00000021
> > +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0
> >      0x00000021
> > +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1
> >      0x00000021
> > +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2
> >      0x00000021
> > +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3
> >      0x00000021
> > +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSE
> > LECT 0x00000021
> > +                       >;
> > +               };
> > +       };
> > +};
> > +
> > +&lpuart0 {
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&pinctrl_lpuart0>;
> > +       status = "okay";
> > +};
> > +
> > +&lpuart3 {
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
> > +       status = "okay";
> > +};
> > +
> > +&gpio0 {
> > +       status = "okay";
> > +};
> > +
> > +&gpio1 {
> > +       status = "okay";
> > +};
> > +
> > +&gpio3 {
> > +       status = "okay";
> > +};
> > +
> > +&gpio4 {
> > +       status = "okay";
> > +};
> > +
> > +&fec1 {
> > +       phy-handle = <&ethphy0>;
> > +       phy-mode = "rmii";
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&pinctrl_fec1>;
> > +       status = "okay";
> > +
> > +       mdio {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               ethphy0: ethernet-phy at 2 {
> > +                       compatible = "ethernet-phy-ieee802.3-c22";
> > +                       max-speed = <100>;
> > +                       reg = <2>;
> > +               };
> > +       };
> > +};
> > +
> > +&i2c1 {
> > +       #address-cells = <1>;
> > +       #size-cells = <0>;
> > +       clock-frequency = <100000>;
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&pinctrl_i2c1>;
> > +       status = "okay";
> > +};
> > +
> > +&usdhc1 {
> > +       bus-width = <8>;
> > +       non-removable;
> > +       pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +       pinctrl-0 = <&pinctrl_usdhc1>;
> > +       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> > +       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> > +       status = "okay";
> > +};
> > +
> > +&usdhc2 {
> > +       bus-width = <4>;
> > +       cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
> > +       pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> > +       pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
> > <&pinctrl_usdhc2_gpio>;
> > +       pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
> > <&pinctrl_usdhc2_gpio>;
> > +       status = "okay";
> > +};
> > diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-
> > imx/imx8/Kconfig
> > index f76a139684..feea07f135 100644
> > --- a/arch/arm/mach-imx/imx8/Kconfig
> > +++ b/arch/arm/mach-imx/imx8/Kconfig
> > @@ -22,6 +22,11 @@ choice
> >         prompt "i.MX8 board select"
> >         optional
> > 
> > +config TARGET_COLIBRI_IMX8QXP
> > +       bool "Support Colibri iMX8QXP module"
> > +       select BOARD_LATE_INIT
> > +       select IMX8QXP
> > +
> >  config TARGET_IMX8QXP_MEK
> >         bool "Support i.MX8QXP MEK board"
> >         select BOARD_LATE_INIT
> > @@ -30,5 +35,6 @@ config TARGET_IMX8QXP_MEK
> >  endchoice
> > 
> >  source "board/freescale/imx8qxp_mek/Kconfig"
> > +source "board/toradex/colibri-imx8qxp/Kconfig"
> > 
> >  endif
> > diff --git a/board/toradex/colibri-imx8qxp/Kconfig
> > b/board/toradex/colibri-imx8qxp/Kconfig
> > new file mode 100644
> > index 0000000000..340fe72816
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/Kconfig
> > @@ -0,0 +1,30 @@
> > +if TARGET_COLIBRI_IMX8QXP
> > +
> > +config SYS_BOARD
> > +       default "colibri-imx8qxp"
> > +
> > +config SYS_VENDOR
> > +       default "toradex"
> > +
> > +config SYS_CONFIG_NAME
> > +       default "colibri-imx8qxp"
> > +
> > +config TDX_CFG_BLOCK
> > +       default y
> > +
> > +config TDX_HAVE_MMC
> > +       default y
> > +
> > +config TDX_CFG_BLOCK_DEV
> > +       default "0"
> > +
> > +config TDX_CFG_BLOCK_PART
> > +       default "1"
> > +
> > +# Toradex config block in eMMC, at the end of 1st "boot sector"
> > +config TDX_CFG_BLOCK_OFFSET
> > +       default "-512"
> > +
> > +source "board/toradex/common/Kconfig"
> > +
> > +endif
> > diff --git a/board/toradex/colibri-imx8qxp/MAINTAINERS
> > b/board/toradex/colibri-imx8qxp/MAINTAINERS
> > new file mode 100644
> > index 0000000000..39a9eb79b7
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/MAINTAINERS
> > @@ -0,0 +1,9 @@
> > +Colibri iMX8QXP
> > +M:     Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > +W:     http://developer.toradex.com/software/linux/linux-software
> > +S:     Maintained
> > +F:     arch/arm/dts/fsl-imx8qxp-colibri.dts
> > +F:     arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
> > +F:     board/toradex/colibri-imx8qxp/
> > +F:     configs/colibri-imx8qxp_defconfig
> > +F:     include/configs/colibri-imx8qxp.h
> > diff --git a/board/toradex/colibri-imx8qxp/Makefile
> > b/board/toradex/colibri-imx8qxp/Makefile
> > new file mode 100644
> > index 0000000000..f6342e1dca
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/Makefile
> > @@ -0,0 +1,7 @@
> > +#
> > +# Copyright 2019 Toradex
> > +#
> > +# SPDX-License-Identifier:     GPL-2.0+
> 
> SPDX line should be in the beginning of the file.
> 
> > +#
> > +
> > +obj-y += colibri-imx8qxp.o
> > diff --git a/board/toradex/colibri-imx8qxp/README
> > b/board/toradex/colibri-imx8qxp/README
> > new file mode 100644
> > index 0000000000..e68d183fe6
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/README
> > @@ -0,0 +1,66 @@
> > +U-Boot for the Toradex Colibri iMX8QXP V1.0B module
> > +
> > +Quick Start
> > +===========
> > +
> > +- Build the ARM trusted firmware binary
> > +- Get scfw_tcm.bin and ahab-container.img
> > +- Build U-Boot
> > +- Load U-Boot binary using uuu
> > +- Flash U-Boot binary into the eMMC
> > +- Boot
> > +
> > +Get and Build the ARM Trusted Firmware
> > +======================================
> > +
> > +$ git clone -b imx_4.14.78_1.0.0_ga 
> > https://source.codeaurora.org/external/imx/imx-atf
> > +$ cd imx-atf/
> > +$ make PLAT=imx8qxp bl31
> > +
> > +Get scfw_tcm.bin and ahab-container.img
> > +=======================================
> > +
> > +$ wget 
> > https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
> > +$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-
> > tcm.bin
> > +$ wget 
> > https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin
> > +$ chmod +x firmware-imx-7.6.bin
> > +$ ./firmware-imx-7.6.bin
> > +
> > +Copy the following binaries to the U-Boot folder:
> > +
> > +$ cp imx-atf/build/imx8qxp/release/bl31.bin .
> > +$ cp u-boot/u-boot.bin .
> > +
> > +Copy the following firmware to the U-Boot folder:
> > +
> > +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
> > +
> > +Build U-Boot
> > +============
> > +
> > +$ make colibri-imx8qxp_defconfig
> > +$ make u-boot-dtb.imx
> > +
> > +Load the U-Boot Binary Using UUU
> > +================================
> > +
> > +Get the latest version of the universal update utility (uuu) aka
> > mfgtools 3.0:
> > +
> > +
> > https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
> > +
> > +Put the module into USB recovery aka serial downloader mode,
> > connect USB device
> > +to your host and execute uuu:
> > +
> > +sudo ./uuu u-boot/u-boot-dtb.imx
> > +
> > +Flash the U-Boot Binary into the eMMC
> > +=====================================
> > +
> > +Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot
> > area partition:
> > +
> > +load mmc 1:1 $loadaddr u-boot-dtb.imx
> > +setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} /
> > 0x200
> > +mmc dev 0 1
> > +mmc write ${loadaddr} 0x0 ${blkcnt}
> > +
> > +Boot
> > diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> > b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> > new file mode 100644
> > index 0000000000..9aa0f096d2
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
> > @@ -0,0 +1,212 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 Toradex
> > + */
> > +
> > +#include <common.h>
> > +
> > +#include <asm/arch/clock.h>
> > +#include <asm/arch/imx8-pins.h>
> > +#include <asm/arch/iomux.h>
> > +#include <asm/arch/sci/sci.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <asm/gpio.h>
> > +#include <asm/io.h>
> > +#include <asm/mach-imx/video.h>
> > +#include <dm.h>
> > +#include <environment.h>
> > +#include <errno.h>
> > +#include <fdt_support.h>
> > +#include <fsl_esdhc.h>
> > +#include <fsl_ifc.h>
> > +#include <i2c.h>
> > +#include <linux/libfdt.h>
> > +#include <malloc.h>
> > +#include <netdev.h>
> > +#include <power-domain.h>
> > +#include <usb.h>
> > +
> > +#include "../common/tdx-cfg-block.h"
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define GPIO_PAD_CTRL  ((SC_PAD_CONFIG_NORMAL <<
> > PADRING_CONFIG_SHIFT) | \
> > +                        (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT)
> > | \
> > +                        (SC_PAD_28FDSOI_DSE_DV_HIGH <<
> > PADRING_DSE_SHIFT) | \
> > +                        (SC_PAD_28FDSOI_PS_PU <<
> > PADRING_PULL_SHIFT))
> > +
> > +#define UART_PAD_CTRL  ((SC_PAD_CONFIG_OUT_IN <<
> > PADRING_CONFIG_SHIFT) | \
> > +                        (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT)
> > | \
> > +                        (SC_PAD_28FDSOI_DSE_DV_HIGH <<
> > PADRING_DSE_SHIFT) | \
> > +                        (SC_PAD_28FDSOI_PS_PU <<
> > PADRING_PULL_SHIFT))
> > +
> > +static iomux_cfg_t uart3_pads[] = {
> > +       SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) |
> > MUX_PAD_CTRL(UART_PAD_CTRL),
> > +       SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) |
> > MUX_PAD_CTRL(UART_PAD_CTRL),
> > +       /* Transceiver FORCEOFF# signal, mux to use pullup */
> > +       SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) |
> > MUX_PAD_CTRL(UART_PAD_CTRL),
> > +};
> > +
> > +static void setup_iomux_uart(void)
> > +{
> > +       imx8_iomux_setup_multiple_pads(uart3_pads,
> > ARRAY_SIZE(uart3_pads));
> > +}
> > +
> > +int board_early_init_f(void)
> > +{
> > +       sc_pm_clock_rate_t rate;
> > +       sc_err_t err = 0;
> > +
> > +       /*
> > +        * This works around that having only UART3 up the baudrate
> > is 1.2M
> > +        * instead of 115.2k. Set UART0 clock root to 80 MHz
> > +        */
> > +       rate = 80000000;
> > +       err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER,
> > &rate);
> > +       if (err != SC_ERR_NONE)
> > +               return 0;
> > +
> > +       /* Power up UART3 */
> > +       err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3,
> > SC_PM_PW_MODE_ON);
> > +       if (err != SC_ERR_NONE)
> > +               return 0;
> > +
> > +       /* Set UART3 clock root to 80 MHz */
> > +       rate = 80000000;
> > +       err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER,
> > &rate);
> > +       if (err != SC_ERR_NONE)
> > +               return 0;
> > +
> > +       /* Enable UART3 clock root */
> > +       err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER,
> > true, false);
> > +       if (err != SC_ERR_NONE)
> > +               return 0;
> > +
> > +       setup_iomux_uart();
> > +
> > +       return 0;
> > +}
> > +
> > +#undef CONFIG_MXC_GPIO /* TODO */
> > +#ifdef CONFIG_MXC_GPIO
> > +#define IOEXP_RESET IMX_GPIO_NR(1, 1)
> > +
> > +static iomux_cfg_t board_gpios[] = {
> > +       SC_P_SPI2_SDO | MUX_MODE_ALT(4) |
> > MUX_PAD_CTRL(GPIO_PAD_CTRL),
> > +       SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | \
> > +               MUX_PAD_CTRL(GPIO_PAD_CTRL),
> > +};
> > +
> > +static void board_gpio_init(void)
> > +{
> > +       struct gpio_desc desc;
> > +       int ret;
> > +
> > +       ret = dm_gpio_lookup_name("gpio at 1a_3", &desc);
> > +       if (ret)
> > +               return;
> > +
> > +       ret = dm_gpio_request(&desc, "bb_per_rst_b");
> > +       if (ret)
> > +               return;
> > +
> > +       dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
> > +       dm_gpio_set_value(&desc, 0);
> > +       udelay(50);
> > +       dm_gpio_set_value(&desc, 1);
> > +
> > +       imx8_iomux_setup_multiple_pads(board_gpios,
> > ARRAY_SIZE(board_gpios));
> > +
> > +       /* enable i2c port expander assert reset line */
> > +       gpio_request(IOEXP_RESET, "ioexp_rst");
> > +       gpio_direction_output(IOEXP_RESET, 1);
> > +}
> > +#else
> > +static inline void board_gpio_init(void) {}
> > +#endif
> > +
> > +#if IS_ENABLED(CONFIG_FEC_MXC)
> > +#include <miiphy.h>
> > +
> > +int board_phy_config(struct phy_device *phydev)
> > +{
> > +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> > +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> > +
> > +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> > +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> > +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> > +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> > +
> > +       if (phydev->drv->config)
> > +               phydev->drv->config(phydev);
> > +
> > +       return 0;
> > +}
> > +#endif
> > +
> > +void build_info(void)
> > +{
> > +       u32 sc_build = 0, sc_commit = 0;
> > +
> > +       /* Get SCFW build and commit id */
> > +       sc_misc_build_info(-1, &sc_build, &sc_commit);
> > +       if (!sc_build) {
> > +               printf("SCFW does not support build info\n");
> > +               sc_commit = 0; /* Display 0 if build info not
> > supported */
> > +       }
> > +       printf("Build: SCFW %x\n", sc_commit);
> > +}
> > +
> > +int checkboard(void)
> > +{
> > +       puts("Model: Toradex Colibri iMX8X\n");
> > +
> > +       build_info();
> > +       print_bootinfo();
> > +
> > +       return 0;
> > +}
> > +
> > +int board_init(void)
> > +{
> > +       board_gpio_init();
> > +
> > +       return 0;
> > +}
> > +
> > +void detail_board_ddr_info(void)
> > +{
> > +       puts("\nDDR    ");
> > +}
> > +
> > +/*
> > + * Board specific reset that is system reset.
> > + */
> > +void reset_cpu(ulong addr)
> > +{
> > +       /* TODO */
> > +}
> > +
> > +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
> > +int ft_board_setup(void *blob, bd_t *bd)
> > +{
> > +       return ft_common_board_setup(blob, bd);
> > +}
> > +#endif
> > +
> > +int board_mmc_get_env_dev(int devno)
> > +{
> > +       return devno;
> > +}
> > +
> > +int board_late_init(void)
> > +{
> > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > +/* TODO move to common */
> > +       env_set("board_name", "Colibri iMX8QXP");
> > +       env_set("board_rev", "v1.0");
> > +#endif
> > +
> > +       return 0;
> > +}
> > diff --git a/board/toradex/colibri-imx8qxp/imximage.cfg
> > b/board/toradex/colibri-imx8qxp/imximage.cfg
> > new file mode 100644
> > index 0000000000..ce9e66c64d
> > --- /dev/null
> > +++ b/board/toradex/colibri-imx8qxp/imximage.cfg
> > @@ -0,0 +1,24 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2019 Toradex
> > + *
> > + * Refer doc/README.imx8image for more details about how-to
> > configure
> > + * and create imx8image boot image
> > + */
> > +
> > +#define __ASSEMBLY__
> > +
> > +/* Boot from SD, sector size 0x400 */
> > +BOOT_FROM EMMC_FASTBOOT 0x400
> > +/* SoC type IMX8QX */
> > +SOC_TYPE IMX8QX
> > +/* Append seco container image */
> > +APPEND ahab-container.img
> > +/* Create the 2nd container */
> > +CONTAINER
> > +/* Add scfw image with exec attribute */
> > +IMAGE SCU mx8qx-colibri-scfw-tcm.bin
> > +/* Add ATF image with exec attribute */
> > +IMAGE A35 bl31.bin 0x80000000
> > +/* Add U-Boot image with load attribute */
> > +DATA A35 u-boot-dtb.bin 0x80020000
> > diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-
> > imx8qxp_defconfig
> > new file mode 100644
> > index 0000000000..d697546ed7
> > --- /dev/null
> > +++ b/configs/colibri-imx8qxp_defconfig
> > @@ -0,0 +1,53 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_IMX8=y
> > +CONFIG_SYS_TEXT_BASE=0x80020000
> > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > +CONFIG_TARGET_COLIBRI_IMX8QXP=y
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_NR_DRAM_BANKS=3
> > +CONFIG_FIT=y
> > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-
> > imx8qxp/imximage.cfg"
> > +CONFIG_LOG=y
> > +CONFIG_VERSION_VARIABLE=y
> > +# CONFIG_DISPLAY_BOARDINFO is not set
> > +CONFIG_BOARD_EARLY_INIT_F=y
> > +CONFIG_CMD_CPU=y
> > +# CONFIG_CMD_IMPORTENV is not set
> > +CONFIG_CMD_MEMTEST=y
> > +CONFIG_CMD_CLK=y
> > +CONFIG_CMD_DM=y
> > +CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_CMD_UUID=y
> > +CONFIG_CMD_EXT4_WRITE=y
> > +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
> > +CONFIG_ENV_IS_IN_MMC=y
> > +CONFIG_CLK_IMX8=y
> > +CONFIG_CPU=y
> > +CONFIG_DM_GPIO=y
> > +CONFIG_MXC_GPIO=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SYS_I2C_IMX_LPI2C=y
> > +CONFIG_MISC=y
> > +CONFIG_DM_MMC=y
> > +CONFIG_PHYLIB=y
> > +CONFIG_PHY_ADDR_ENABLE=y
> > +CONFIG_PHY_MICREL=y
> > +CONFIG_DM_ETH=y
> > +CONFIG_FEC_MXC_SHARE_MDIO=y
> > +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
> > +CONFIG_FEC_MXC=y
> > +CONFIG_MII=y
> > +CONFIG_PINCTRL=y
> > +CONFIG_PINCTRL_IMX8=y
> > +CONFIG_POWER_DOMAIN=y
> > +CONFIG_IMX8_POWER_DOMAIN=y
> > +CONFIG_DM_REGULATOR=y
> > +CONFIG_DM_REGULATOR_FIXED=y
> > +CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_DM_SERIAL=y
> > +CONFIG_FSL_LPUART=y
> > +CONFIG_DM_THERMAL=y
> > +# CONFIG_EFI_LOADER is not set
> > diff --git a/include/configs/colibri-imx8qxp.h
> > b/include/configs/colibri-imx8qxp.h
> > new file mode 100644
> > index 0000000000..33cbcb44a9
> > --- /dev/null
> > +++ b/include/configs/colibri-imx8qxp.h
> > @@ -0,0 +1,214 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2019 Toradex
> > + */
> > +
> > +#ifndef __COLIBRI_IMX8QXP_H
> > +#define __COLIBRI_IMX8QXP_H
> > +
> > +#include <asm/arch/imx-regs.h>
> > +#include <linux/sizes.h>
> > +
> > +#define CONFIG_REMAKE_ELF
> > +
> > +#define CONFIG_DISPLAY_BOARDINFO_LATE
> > +
> > +#undef CONFIG_CMD_EXPORTENV
> > +#undef CONFIG_CMD_IMPORTENV
> > +#undef CONFIG_CMD_IMLS
> > +
> > +#undef CONFIG_CMD_CRC32
> > +#undef CONFIG_BOOTM_NETBSD
> > +
> > +#define CONFIG_FSL_ESDHC
> > +#define CONFIG_FSL_USDHC
> > +#define CONFIG_SYS_FSL_ESDHC_ADDR      0
> > +#define USDHC1_BASE_ADDR               0x5B010000
> > +#define USDHC2_BASE_ADDR               0x5B020000
> > +#define CONFIG_SUPPORT_EMMC_BOOT       /* eMMC specific */
> > +
> > +#define CONFIG_ENV_OVERWRITE
> > +
> > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > +
> > +#define FEC_QUIRK_ENET_MAC
> > +
> > +#define CONFIG_IP_DEFRAG
> > +#define CONFIG_TFTP_BLOCKSIZE          4096
> 
> 4096 can be replaced with SZ_4K (from include/linux/sizes.h)
> 
> > +#define CONFIG_TFTP_TSIZE
> > +
> > +#define CONFIG_IPADDR                  192.168.10.2
> > +#define CONFIG_NETMASK                 255.255.255.0
> > +#define CONFIG_SERVERIP                        192.168.10.1
> > +
> > +#define MEM_LAYOUT_ENV_SETTINGS \
> > +       "fdt_addr_r=0x84000000\0" \
> > +       "kernel_addr_r=0x82000000\0" \
> > +       "ramdisk_addr_r=0x84100000\0"
> > +
> > +#ifdef CONFIG_AHAB_BOOT
> > +#define AHAB_ENV "sec_boot=yes\0"
> > +#else
> > +#define AHAB_ENV "sec_boot=no\0"
> > +#endif
> > +
> > +/* Boot M4 */
> > +#define M4_BOOT_ENV \
> > +       "m4_0_image=m4_0.bin\0" \
> > +       "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > " \
> > +               "${m4_0_image}\0" \
> > +       "m4boot_0=run loadm4image_0; dcache flush; bootaux
> > ${loadaddr} 0\0" \
> > +
> > +#define MFG_NAND_PARTITION ""
> > +
> > +#define BOOT_TARGET_DEVICES(func) \
> > +       func(MMC, mmc, 0) \
> > +       func(MMC, mmc, 1) \
> > +       func(DHCP, dhcp, na)
> > +#include <config_distro_bootcmd.h>
> > +#undef BOOTENV_RUN_NET_USB_START
> > +#define BOOTENV_RUN_NET_USB_START ""
> > +
> > +#define CONFIG_MFG_ENV_SETTINGS \
> > +       "mfgtool_args=setenv bootargs
> > console=${console},${baudrate} " \
> > +               "rdinit=/linuxrc g_mass_storage.stall=0 " \
> > +               "g_mass_storage.removable=1
> > g_mass_storage.idVendor=0x066F " \
> > +               "g_mass_storage.idProduct=0x37FF " \
> > +               "g_mass_storage.iSerialNumber=\"\" "\
> > +               MFG_NAND_PARTITION \
> > +               "video=imxdpufb5:off video=imxdpufb6:off
> > video=imxdpufb7:off " \
> > +               "clk_ignore_unused "\
> > +               "\0" \
> > +       "initrd_addr=0x83800000\0" \
> > +       "initrd_high=0xffffffff\0" \
> > +       "bootcmd_mfg=run mfgtool_args;booti ${loadaddr}
> > ${initrd_addr} " \
> > +               "${fdt_addr};\0" \
> > +
> > +/* Initial environment variables */
> > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > +       AHAB_ENV \
> > +       BOOTENV \
> > +       CONFIG_MFG_ENV_SETTINGS \
> > +       M4_BOOT_ENV \
> > +       MEM_LAYOUT_ENV_SETTINGS \
> > +       "boot_fdt=try\0" \
> > +       "bootscript=echo Running bootscript from mmc ...; source\0"
> > \
> > +       "console=ttyLP3,115200
> > earlycon=lpuart32,0x5a090000,115200\0" \
> > +       "fdt_addr=0x83000000\0"                 \
> > +       "fdt_file=fsl-imx8qxp-colibri-eval-v3.dtb\0" \
> > +       "fdt_high=0xffffffffffffffff\0"         \
> > +       "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
> > +       "image=Image\0" \
> > +       "initrd_addr=0x83800000\0"              \
> > +       "initrd_high=0xffffffffffffffff\0" \
> > +       "loadbootscript=fatload mmc ${mmcdev}:${mmcpart}
> > ${loadaddr} " \
> > +               "${script};\0" \
> > +       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
> > ${fdt_file}\0" \
> > +       "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > ${image}\0" \
> > +       "mmcargs=setenv bootargs console=${console},${baudrate} " \
> > +               "root=PARTUUID=${uuid} rootwait " \
> > +       "mmcautodetect=yes\0" \
> > +       "mmcboot=echo Booting from mmc ...; " \
> > +               "run finduuid; run mmcargs; " \
> > +               "if test ${boot_fdt} = yes || test ${boot_fdt} =
> > try; then " \
> > +                       "if run loadfdt; then " \
> > +                               "booti ${loadaddr} - ${fdt_addr}; "
> > \
> > +                       "else " \
> > +                               "echo WARN: Cannot load the DT; " \
> > +                       "fi; " \
> > +               "else " \
> > +                       "echo wait for boot; " \
> > +               "fi;\0" \
> > +       "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
> > +       "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> > +       "netargs=setenv bootargs console=${console} root=/dev/nfs
> > ip=dhcp " \
> > +               "nfsroot=${serverip}:${nfsroot},v3,tcp
> > video=imxdpufb5:off " \
> > +               "video=imxdpufb6:off video=imxdpufb7:off\0" \
> > +       "netboot=echo Booting from net ...; " \
> > +               "run netargs; " \
> > +               "if test ${ip_dyn} = yes; then " \
> > +                       "setenv get_cmd dhcp; " \
> > +               "else " \
> > +                       "setenv get_cmd tftp; " \
> > +               "fi; " \
> > +               "${get_cmd} ${loadaddr} ${image}; " \
> > +               "if test ${boot_fdt} = yes || test ${boot_fdt} =
> > try; then " \
> > +                       "if ${get_cmd} ${fdt_addr} ${fdt_file};
> > then " \
> > +                               "booti ${loadaddr} - ${fdt_addr}; "
> > \
> > +                       "else " \
> > +                               "echo WARN: Cannot load the DT; " \
> > +                       "fi; " \
> > +               "else " \
> > +                       "booti; " \
> > +               "fi;\0" \
> > +       "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp
> > ${fdt_addr} " \
> > +               "colibri-imx8qxp/${fdt_file}; booti ${loadaddr} - "
> > \
> > +               "${fdt_addr}\0" \
> > +       "panel=NULL\0" \
> > +       "script=boot.scr\0" \
> > +       "video=imxdpufb5:off video=imxdpufb6:off
> > video=imxdpufb7:off\0"
> > +
> > +#undef CONFIG_BOOTCOMMAND
> > +#define CONFIG_BOOTCOMMAND \
> > +          "mmc dev ${mmcdev}; if mmc rescan; then " \
> > +                  "if run loadbootscript; then " \
> > +                          "run bootscript; " \
> > +                  "else " \
> > +                          "if run loadimage; then " \
> > +                                  "run mmcboot; " \
> > +                          "else run netboot; " \
> > +                          "fi; " \
> > +                  "fi; " \
> > +          "else booti ${loadaddr} - ${fdt_addr}; fi"
> > +
> > +/* Link Definitions */
> > +#define CONFIG_LOADADDR                        0x80280000
> > +
> > +#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
> > +
> > +#define CONFIG_SYS_INIT_SP_ADDR                0x80200000
> > +
> > +#define CONFIG_SYS_MEMTEST_START       0x88000000
> > +#define CONFIG_SYS_MEMTEST_END         0x89000000
> > +
> > +/* Environment in eMMC, before config block at the end of 1st
> > "boot sector" */
> > +#define CONFIG_ENV_SIZE                        (8 * 1024)
> 
>  (8 * 1024) can be replaced with SZ_8K (from include/linux/sizes.h)
> 
> > +#define CONFIG_ENV_OFFSET              (-CONFIG_ENV_SIZE + \
> > +                                        CONFIG_TDX_CFG_BLOCK_OFFSE
> > T)
> > +#define CONFIG_SYS_MMC_ENV_DEV         0
> > +#define CONFIG_SYS_MMC_ENV_PART                1
> > +
> > +#define CONFIG_SYS_MMC_IMG_LOAD_PART   1
> > +
> > +/* On Colibri iMX8 USDHC1 is eMMC, USDHC2 is 4-bit SD */
> > +#define CONFIG_SYS_MMC_ENV_DEV         0                /* USDHC1
> > eMMC */
> > +#define CONFIG_SYS_FSL_USDHC_NUM       2
> > +
> > +/* Size of malloc() pool */
> > +#define CONFIG_SYS_MALLOC_LEN          ((CONFIG_ENV_SIZE + (32 *
> > 1024)) * 1024)
> > +
> > +#define CONFIG_SYS_SDRAM_BASE          0x80000000
> > +#define CONFIG_NR_DRAM_BANKS           3
> > +#define PHYS_SDRAM_1                   0x80000000
> > +#define PHYS_SDRAM_2                   0x880000000
> > +#define PHYS_SDRAM_1_SIZE              0x80000000      /* 2 GB */
> 0x80000000 can be replaced with SZ_2G (from include/linux/sizes.h)
> > +#define PHYS_SDRAM_2_SIZE              0x00000000      /* 0 GB */
> > +
> > +/* Serial */
> > +#define CONFIG_BAUDRATE                        115200
> > +
> > +/* Monitor Command Prompt */
> > +#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
> > +#define CONFIG_SYS_CBSIZE              2048
> 
> Same as above
> 
> > +#define CONFIG_SYS_MAXARGS             64
> > +#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
> > +#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
> > +                                       sizeof(CONFIG_SYS_PROMPT) +
> > 16)
> > +
> > +/* Generic Timer Definitions */
> > +#define COUNTER_FREQUENCY              8000000 /* 8MHz */
> > +
> > +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
> > +#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from
> > second 128MB */
> Same as above
> > +
> > +#endif /* __COLIBRI_IMX8QXP_H */
> > --
> > 2.20.1
> > 
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > https://lists.denx.de/listinfo/u-boot

[U-Boot] [U-Boot, imx-next, v1, 01/14] ARM: Remove HSC|DDC ETH PHY reset code after switching to DM/DTS

[sbabic at denx.de]

> After commit efd0b791069a ("eth: dm: fec: Add gpio phy reset binding")
> the in-board file definition of ETH PHY reset can be removed.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,RESEND,07/10] clk: imx8: add i.MX8QM clk driver

[sbabic at denx.de]

> Add i.MX8QM clk driver, SDHC/FEC/UART/I2C supported.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 08/14] DTS: Enable USB host support (including regulators) on HSC|DDC boards

[sbabic at denx.de]

> This commit enables the support for K&P's HSC|DDC imx53 based boards.
> It was also necessary to provide device tree description for regulators
> to avoid board specific code definition.
> The GPIO pin description responsible for VBUS control has been moved from
> "hog" group to usbh1 dedicated one.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] ARM: imx: Fix typo in select option for ZMX25

[sbabic at denx.de]

> Correct CPU_ARM926EJS1 to CPU_ARM926EJS.
> Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 1/2] ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration

[sbabic at denx.de]

> From: Ludwig Zenz <lzenz@dh-electronics.de>
> The four x16 DDR3 are wired in T-topology. From NXP AN4467:
> 'Although not required, T-Topologies may also benefit from performing
> Write Leveling as there are package delays on both the processor and DDR
> devices that can be de-skewed by performing Write Leveling. Therefore,
> Freescale recommends determining Write Leveling calibration parameters
> for all boards, regardless of topology used.'
> That is why write level calibration is also done.
> Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,RESEND,05/10] imx8: add cpu support

[sbabic at denx.de]

> Add cpu type and Kconfig entry
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 11/14] colibri-imx6ull: migrate fec to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate Ethernet FEC to using driver model.
> Drop PHY_MICREL_KSZ90X1 which slipped in from Apalis iMX6.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] imx: 8qxp_mek: fix fdt_file and console

[sbabic at denx.de]

> Fix fdt_file and console to boot upstream Linux Kernel.
> Upstream linux use imx8qxp-mek.dtb, and pass lpuart32 to earlycon
> will not work for i.MX8QXP, only need to pass earlycon,
> check drivers/tty/serial/earlycon.c,
> " /* Just 'earlycon' is a valid param for devicetree and ACPI SPCR. */ "
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v3, 14/14] ARM: dts: colibri-imx6ull: update device tree

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Fix compatible node to use regular Toradex notation.
> Annotate device tree with standard Colibri pin muxing comments.
> Use open-drain I2C pin muxings.
> Alphabetically re-order iomuxc nodes.
> Rename snvs-ad7879-int-grp touch interrupt node as per Linux device tree.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 01/14] tdx-cfg-block: add support for new colibri iMX6ull skus

[sbabic at denx.de]

> From: Gerard Salvatella <gerard.salvatella@toradex.com>
> Add support for new Colibri iMX6ULL SKUs.
> While at it also checkpatch fix the whole files.
> Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 09/14] colibri-imx6ull: migrate mmc to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate MMC to using driver model.
> Migrate USDHC to using pinctrl.
> While at it also add GPIO1_IO03__OSC32K_32K_OUT pin muxing.
> While at it also update copyright period.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,2/2] mxc_ocotp: Disable fuse sense for imx8mq B1

[sbabic at denx.de]

> From: Ye Li <ye.li@nxp.com>
> On iMX8MQ Rev B1, reading from fuse box is not allowed. The
> OCOTP_READ_FUSE_DATA register is tied to magic number 0xff0055aa
> for chip rev. So u-boot has to disable the fuse sense function for it.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Tested-by: Anson Huang <Anson.Huang@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 12/14] ARM: config: Remove not needed CONFIG_MXC_USB_PORT define

[sbabic at denx.de]

> After i.MX5's EHCI conversion to DM, the CONFIG_MXC_USB_PORT is not needed
> anymore and should be removed.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, 1/2] mxc_ocotp: Update redundancy banks for mx7ulp B0

[sbabic at denx.de]

> From: Ye Li <ye.li@nxp.com>
> On mx7ulp B0, beside bank 0 and 1, the fuse bank 9, 10, 28 are changed to
> Redundancy mode not ECC, so they can support to program different bits of
> a word in multiple times.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v3] ARM: dts: i.MX6Q: fix avoid_unnecessary_addr_size warnings

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Re-synced the device tree with Linux 5.0.
> This fixes the following warnings:
> w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
>  port at 2/endpoint at 0:reg: property has invalid length (4 bytes)
>  (#address-cells == 2, #size-cells == 1)
> w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
>  port at 2/endpoint at 1:reg: property has invalid length (4 bytes)
>  (#address-cells == 2, #size-cells == 1)
> w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
>  port at 2/endpoint at 2:reg: property has invalid length (4 bytes)
>  (#address-cells == 2, #size-cells == 1)
> w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
>  port at 2/endpoint at 3:reg: property has invalid length (4 bytes)
>  (#address-cells == 2, #size-cells == 1)
> w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
>  port at 2/endpoint at 4:reg: property has invalid length (4 bytes)
>  (#address-cells == 2, #size-cells == 1)
> w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
>  port at 3/endpoint at 1:reg: property has invalid length (4 bytes)
>  (#address-cells == 2, #size-cells == 1)
> w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
>  port at 3/endpoint at 2:reg: property has invalid length (4 bytes)
>  (#address-cells == 2, #size-cells == 1)
> w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
>  port at 3/endpoint at 3:reg: property has invalid length (4 bytes)
>  (#address-cells == 2, #size-cells == 1)
> w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu at 2800000/
>  port at 3/endpoint at 4:reg: property has invalid length (4 bytes)
>  (#address-cells == 2, #size-cells == 1)
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 2/endpoint at 0: Relying on default #address-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 2/endpoint at 0: Relying on default #size-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 2/endpoint at 1: Relying on default #address-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 2/endpoint at 1: Relying on default #size-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 2/endpoint at 2: Relying on default #address-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 2/endpoint at 2: Relying on default #size-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 2/endpoint at 3: Relying on default #address-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 2/endpoint at 3: Relying on default #size-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 2/endpoint at 4: Relying on default #address-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 2/endpoint at 4: Relying on default #size-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 3/endpoint at 1: Relying on default #address-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 3/endpoint at 1: Relying on default #size-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 3/endpoint at 2: Relying on default #address-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 3/endpoint at 2: Relying on default #size-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 3/endpoint at 3: Relying on default #address-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 3/endpoint at 3: Relying on default #size-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 3/endpoint at 4: Relying on default #address-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
>  /soc/ipu at 2800000/port at 3/endpoint at 4: Relying on default #size-cells
>  value
> w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
>  Failed prerequisite 'avoid_default_addr_size'
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,3/8] imx8qxp: mek: Enable CMD_FUSE

[sbabic at denx.de]

> Enable CMD_FUSE for i.MX8QXP MEK
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 10/14] USB: DM: Convert i.MX5 ehci code to driver model

[sbabic at denx.de]

> This commit converts i.MX5's EHCI USB host driver to driver model (DM_USB).
> It is a straightforward conversion (to reuse as much code as possible),
> based on ehci-mx6.c code.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 05/14] colibri-imx6ull: fix ethernet phy power on

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Just give the new Ethernet PHY power save mode circuitry time to settle.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 03/14] ARM: Enable CONFIG_DM_MMC and CONFIG_DM_BLK on HSC and DDC boards

[sbabic at denx.de]

> This commit enables DM_MMC and DM_BLK on imx53 based HSC and DDC boards.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, RESEND, 03/10] dt-bindings: clock: dt-bindings: pinctrl: add i.MX8QM clocks definition

[sbabic at denx.de]

> Add i.MX8QM clocks definition
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,v1] colibri_vf: fix tab vs. spaces

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Fix indentation using tab vs. spaces.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,RESEND,10/10] imx: support i.MX8QM MEK board

[sbabic at denx.de]

> Add i.MX8QM MEK board support.
> Included a basic dts, enabled SPL FIT
> Boot log as below:
> U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
> Normal Boot
> Trying to boot from MMC2_2
> U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
> CPU:   NXP i.MX8QM RevB A53 at 142933 MHz
> Model: Freescale i.MX8QM MEK
> Board: iMX8QM MEK
> Build: SCFW 9330215b
> Boot:  SD1
> DRAM:  6 GiB
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1
> Loading Environment from MMC... *** Warning - bad CRC, using default environment
> In:    serial at 5a060000
> Out:   serial at 5a060000
> Err:   serial at 5a060000
> Net:
> Error: ethernet at 5b040000 address not set.
> eth-1: ethernet at 5b040000
> Hit any key to stop autoboot:  0
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 02/14] tdx-cfg-block: simplify i.MX 6 module detection

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Use CONFIG_TARGET_... at compile time to differentiate between
> Apalis iMX6, Colibri iMX6 and Colibri iMX6ULL. Avoid code
> duplication by moving question about Wi-Fi / Bluetooth before
> IT/non-IT decision.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,1/8] imx: sip: add call_imx_sip_ret2

[sbabic at denx.de]

> This function will be used by i.MX8 fuse driver.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 14/14] boot.src: Provide dsa_core.blacklist bootarg when booting via NFS

[sbabic at denx.de]

> This setup is a bit special as Linux kernel (4.19) is not supporting
> in-kernel NFS rootfs mount and Distributed Switch Architecture (DSA)
> operation.
> For that reason it was necessary to provide a bootarg to allow userspace
> enable it afterwards if needed.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 4/5] board: toradex: tdx-cfg-block: add new skus

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Add all the latest new SKUs:
> - Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT
> - Apalis iMX8 QuadMax 4GB IT
> - Apalis iMX8 QuadPlus 2GB Wi-Fi / BT
> - Apalis iMX8 QuadPlus 2GB",
> - Colibri iMX8 QuadXPlus 2GB IT
> - Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth
> - Colibri iMX8 DualX 1GB
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Marcel Ziswiler]

On Fri, 2019-04-26 at 09:03 +0000, Peng Fan wrote:
> > Subject: Re: [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb
> > wb it
> > v1.0b module support
> > 
> > Hi Peng and Stefano
> > 
> > On Fri, 2019-04-26 at 10:38 +0200, Stefano Babic wrote:
> > > Hi Peng,
> > > 
> > > On 26/04/19 04:10, Peng Fan wrote:
> > > > Hi Stefano,
> > > > 
> > > > > Subject: Re: [PATCH v2 5/5] board: toradex: add colibri
> > > > > imx8qxp
> > > > > 2gb wb it v1.0b module support
> > > > > 
> > > > > Hi Marcel,
> > > > > 
> > > > > On 25/04/19 14:35, Marcel Ziswiler wrote:
> > > > > > Hi Stefano
> > > > > > 
> > > > > > On Thu, 2019-04-25 at 12:48 +0200, Stefano Babic wrote:
> > > > > > > Hi Marcel,
> > > > > > > 
> > > > > > > On 09/04/19 17:25, Marcel Ziswiler wrote:
> > > > > > > > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > > > > > > > 
> > > > > > > > This commit adds initial support for the Toradex
> > > > > > > > Colibri
> > > > > > > > iMX8QXP 2GB WB IT V1.0B module. Unlike the V1.0A early
> > > > > > > > access samples exclusively booting from SD card, they
> > > > > > > > are
> > > > > > > > now strapped to boot from eFuses which are factory
> > > > > > > > fused to
> > > > > > > > properly boot from their on-module eMMC. U- Boot
> > > > > > > > supports
> > > > > > > > either booting from the on-module eMMC or
> > > > > may
> > > > > > > > be used for recovery purpose using the universal update
> > > > > > > > utility
> > > > > > > > (uuu) aka mfgtools 3.0.
> > > > > > > > 
> > > > > > > > Functionality wise the following is known to be
> > > > > > > > working:
> > > > > > > > - eMMC and MMC/SD card
> > > > > > > > - Ethernet
> > > > > > > > - GPIOs
> > > > > > > > - I2C
> > > > > > > > 
> > > > > > > > Unfortunately, there is no USB functionality for the
> > > > > > > > i.MX
> > > > > > > > 8QXP as of yet.
> > > > > > > > 
> > > > > > > > Signed-off-by: Marcel Ziswiler <
> > > > > > > > marcel.ziswiler at toradex.com
> > > > > > > > 
> > > > > > > > ---
> > > > > > > > 
> > > > > > > 
> > > > > > > I merged the series and build locally (fine), but Travis
> > > > > > > complains and stops with error:
> > > > > > > 
> > > > > > > +cc1: fatal error: opening output file spl/u-boot-
> > > > > > > spl.cfgout:
> > > > > > > No such
> > > > > > > file or directory
> > > > > > > +compilation terminated.
> > > > > > > 
> > > > > > > Can you take a look at it ?
> > > > > > 
> > > > > > Sure, looks like Peng's commit caceb739ea07 ("imx: build
> > > > > > flash.bin for
> > > > > > i.MX8") takes SPL for granted while my patchset currently
> > > > > > avoids
> > > > > > it.
> > > > > 
> > > > > It looks so, yes.
> > > > > 
> > > > > > BTW: I still don't believe SPL makes much sense on i.MX 8X
> > > > > > given
> > > > > > all the other proprietary parts involved in booting.
> > > > > 
> > > > > SPL makes more sense if it is possible to detect at runtime
> > > > > the HW
> > > > > and change the configuration - for i.MX6, this means RAMS
> > > > > detection, which boot device is booting, and so on.
> > > > > 
> > > > > On i.MX8 there is a lot of proprietary parts - we lose the
> > > > > flexibility of SPL, and most features are lost (or must be
> > > > > provided by proprietary code).
> > > > > I agree that
> > > > > on this platform SPL makes less sense, and i.MX8 should be
> > > > > built
> > > > > independently if CONFIG_SPL is set (this is also for
> > > > > i.MX6 / MX5, there are boards without SPL and using the DCD
> > > > > image
> > > > > to set up the RAM controller).
> > > > 
> > > > The reason we move to use SPL on i.MX8 is that we would like to
> > > > avoid bind ATF/OP-TEE/U-Boot into a flat image with hacked
> > > > offset in
> > > > an image.
> > > > 
> > > 
> > > It seemed I have missed some point. Thanks for clarification.
> > > This
> > > makes sense.
> > 
> > OK, I was also not aware of this.
> > 
> > However, currently I am just happy the current tooling kinda works.
> > Which is we can ship stuff to customers and they may use uuu to
> > recover
> > bricked modules. So far nobody is talking about OP-TEE and such
> > advanced
> > use cases yet.
> > 
> > On the other hand enabling SPL currently does not seem to work at
> > all on our
> > hardware. Neither booting from eMMC nor recovering using uuu.
> > That is really the main reason I decided against it at least for
> > now.
> 
> In vendor tree, we use SPL to load i.MX8 container image.
> To UUU, 1st need to enable usb gadget functions in SPL, then enable
> container
> for the 2nd image. So with uuu, it not work with upstream U-Boot now.

Strange, for me this works just fine with mainline just not with SPL
being enabled e.g. as per board/toradex/colibri-imx8qxp/README:

[user at host uuu]$ sudo ./uuu u-boot/u-boot-dtb.imx
uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.2.66-0-
ga1a8e69

Success 1    Failure 0

1:33   2/ 2   [Done                        ] SDPS: done

U-Boot 2019.04-rc4-00169-g42dd45e2d9-dirty (Apr 26 2019 - 11:30:58
+0200)

CPU:   NXP i.MX8QXP RevB A35 at 1200 MHz

DRAM:  2 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default
environment

In:    serial at 5a090000
Out:   serial at 5a090000
Err:   serial at 5a090000
Model: Toradex Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT V1.0B, Serial#
06410651
Net:   eth0: ethernet at 5b040000
Hit any key to stop autoboot:  0 
=> 

> > > > So the bootflow now is
> > > > SPL->ATF->OPTEE->ATF->U-Boot
> > > > 
> > > > Without SPL, when generating flash.bin, we have to hack ATF to
> > > > copy
> > > > OP-TEE image from flash.bin to the runtime location.
> > > 
> > > Nevertheless, I understand that it is not strictly required to
> > > enable
> > > OPTEE to boot the kernel, and in some applications a secure zone
> > > is
> > > not required. The thing is not that SPL is used here, but to
> > > constrain
> > > all other users like Marcel to do the same. With i.MX6, even if I
> > > strongly suggested to do this to allow run time detection, I let
> > > boards without SPL and with just u-boot.imx (with built-in DCD)
> > > to
> > > flow into mainline - the board maintainer rules as he knows
> > > better
> > > where the device is used.
> > 
> > Thanks!
> > 
> > > So I will prefer that the build assume to have SPL just if SPL is
> > > configured and not in any case, letting boards without SPL (like
> > > this
> > > colibri-mx8
> > 
> > Colibri iMX8X that is while on the Apalis family we have the Apalis
> > iMX8 (e.g. with the i.MX 8QuadMax or i.MX 8QuadPlus) and the new
> > Apalis
> > iMX8X with ECC RAM still in the works. Welcome to the i.MX 8 series
> > with the
> > i.MX 8 and i.MX 8X families and careful with NXP's brilliant naming
> > scheme
> > (;-p).
> > 
> > > ) to build.
> > 
> > Don't worry. I believe I found a fix for the issue at hand and will
> > send a patch
> > shortly.
> 
> ok.
> 
> Regards,
> Peng.
> 
> > > > > > Plus currently SPL
> > > > > > actually breaks the USB serial downloader aka recovery mode
> > > > > > using the universal update utility (uuu) aka mfgtools 3.0.
> > > > 
> > > > The usb related function for i.MX8 is not ready now.
> > > 
> > > That is ok - it s WIP, it will be merged when ready. I agree with
> > > you,
> > > this is *not* a reason to avoid SPL.
> > 
> > Agreed. However, it is kinda painful requiring different U-Boot
> > configuration
> > flavours for regular boot vs. recovery. That said we used to
> > previously do this
> > on Apalis/Colibri iMX6 as well so it is definitely no show stopper.
> > 
> > > > we are almost run out
> > > > of ocram with SPL DM, thinking to use OF_PLATDATA now, then
> > > > move to
> > > > usb functions.
> > > 
> > > Understood.
> > 
> > Yeah, I also played with OF_PLATDATA once before however was not
> > entirely
> > happy with the result as of yet. I guess WIP patches welcome (;-p).
> > 
> > > Best regards,
> > > Stefano
> > 
> > Cheers
> > 
> > Marcel

[U-Boot] [U-Boot, v2, 12/14] ARM: dts: colibri-imx6ull: fix uart-has-rtscts property

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Remove vendor pre-fix fsl, from uart-has-rtscts property.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, RESEND, 01/10] pinctrl: imx8: add i.MX8QM compatible

[sbabic at denx.de]

> Add i.MX8QM compatible
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 07/14] DTS: Provide USB host DTS description for i.MX53 devices

[sbabic at denx.de]

> This code has been ported from Linux kernel - tag v5.1-rc2.
> The difference from the kernel is the removal of:
> fsl,usbmisc = <&usbmisc 1>;
> fsl,usbphy = <&usbphy1>;
> properties, which are not needed for correct u-boot operation (as PHY
> setup is done in ehci-mx5.c file itself).
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 09/14] ARM: Remove EHCI specific code from HSC|DDC board file

[sbabic at denx.de]

> As EHCI on i.MX5 has been converted to driver model, the board specific
> code, necessary for VBUS USB power supply setup is not needed anymore.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 13/14] Convert CONFIG_USB_EHCI_MX5 to Kconfig

[sbabic at denx.de]

> This converts the following to Kconfig:
>    CONFIG_USB_EHCI_MX5
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 3/5] board: toradex: tdx-cfg-block: clean-up sku handling

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Clean-up handling of several SKUs.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 05/14] ARM: Remove non DM/DTS esdhc3 code from HSC|DDC board related files

[sbabic at denx.de]

> After switching to DM/DTS support of esdhc3 - the code in this patch
> can be removed.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 04/14] ARM: defconfig: Move CONFIG_FSL_ESDHC to Kconfig

[sbabic at denx.de]

> The CONFIG_FSL_ESDHC is now enabled and defined in Kconfig, not in
> include/configs/kp_imx53.h
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] imx: i.MX8MQ: clear ocotp error bit

[sbabic at denx.de]

> In case ocotp error bit is set, clear it.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 06/14] board: imx6ull: Add disable PMIC_STBY_REQ

[sbabic at denx.de]

> From: Philippe Schenker <philippe.schenker@toradex.com>
> Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the
> SOC to request for a lower voltage during sleep. This is necessary
> because the voltage is changing too slow for the SOC to wake up
> properly.
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v3, 13/14] ARM: dts: colibri-imx6ull: add osc32k_32k_out pinctrl

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Add GPIO1_IO03__OSC32K_32K_OUT pin muxing.
> While at it also fix indentation of pinfunc header file.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 11/14] ARM: defconfig: kp_imx53: Enable DM_USB support on HSC|DDC boards

[sbabic at denx.de]

> This commit enables the DM_USB on HSC|DDC i.MX53 based boards.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, RESEND, 09/10] misc: imx8: scu: add i.MX8QM support

[sbabic at denx.de]

> According to IMX8QXP/8QM config option, choose the clk/iomuxc
> compatible.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 07/14] colibri-imx6ull: configuration clean-up

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Drop disabling SPL_SYS_THUMB_BUILD as we anyway do not use SPL.
> Enbale CRC32 verify, USB SDP and EFI loader support.
> Drop CMD_GPT and disabling RANDOM_UUID.
> Do savedefconfig which drops USB_FUNCTION_SDP.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 04/14] apalis/colibri_imx6/imx6ull: make sure loadaddr does not collide

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Currently $loadaddr and $fdt_addr_r point to the same address. This
> might be not ideal for some distro boot scripts which make use of
> $loadaddr after loading the device tree.
> Make sure the two variables point to two different addresses. Moving
> $loadaddr is not entirly trivial since it is defined in mx6_common.h.
> Move $fdt_addr_r and $ramdisk_addr_r by 1MiB, which should be enough
> for scripts.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 1/5] misc: imx8: remove duplicates from scfw api

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Remove duplicate function declarations from the SCFW API header file.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, RESEND, 06/10] clk: imx8: split code into common and soc specific part

[sbabic at denx.de]

> To make it easy to add new clk driver for i.MX8, split
> the code into common part and SoC specific part.
> Make the get/set/enable non static and introduce a num_clks for
> soc_clk_dump, because the arrays are moved to clk-imx8qxp.c.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 2/5] arm: dts: imx8dx: add lpuart1, lpuart2, lpuart3

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Add support for lpuart1, lpuart2 and lpuart3.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,2/8] imx8: fuse: add fuse driver

[sbabic at denx.de]

> Add fuse write for i.MX8
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v1] colibri_vf: fix ethernet by adding explicit phy node

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> The implicit fallback mechanism for searching the whole MDIO bus for at
> least one PHY has been gone with the following commit b882005a18de
> ("drivers/net/fec: phy_init: remove redundant logic"). This lead to the
> Ethernet driver erroring out as follows:
> Net:   Could not get PHY for FEC0: addr -19
> eth-1: fec at 400d1000
> Colibri VFxx # dhcp
> Could not get PHY for FEC0: addr -19
> Could not get PHY for FEC0: addr -19
> Could not get PHY for FEC0: addr -19
> Could not get PHY for FEC0: addr -19
> No ethernet found.
> Could not get PHY for FEC0: addr -19
> Colibri VFxx #
> This commit adds an explicit PHY node which makes it work again.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, RESEND, 02/10] dt-bindings: pinctrl: add i.MX8QM pads definition

[sbabic at denx.de]

> Add i.MX8QM pads definition
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 02/14] DTS: Add esdhc3 device tree description tuning for HSC|DDC boards

[sbabic at denx.de]

> In this commit the esdhc3 controller is enabled as well as it is remaped
> to mmc0 to not break legacy code.
> The pinctrl setup (e.g. 0x1e4) is the same as one from in-board file
> definition.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] ddr: imx8m: hide i.MX8M DDR options from device driver entry

[sbabic at denx.de]

> Use one menu to hide the several i.MX8M DDR options from device
> driver entry.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] imx8qxp: mek: enable dm-spl for pm

[sbabic at denx.de]

> with u-boot,dm-spl added for imx8qx-pm node, and SPL_SIMPLE_BUS enabled,
> the bind and probe code in board file could be removed.
> Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 03/14] colibri-imx6ull: set module variant depending on config block

[sbabic at denx.de]

> From: Stefan Agner <stefan.agner@toradex.com>
> Using CPU temperature grading as a discriminator if the Wi-Fi /
> Bluetooth chip is populated is no longer possible due to upcoming
> SKUs. Set variant to -wifi only if a valid config block is present
> and the product id mentions a SKU with Wi-Fi / Bluetooth.
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, RESEND, 04/10] arm: dts: introduce dtsi for i.MX8QM

[sbabic at denx.de]

> Introduce basic dtsi for i.MX8QM, only support SDHC/FEC/LPUART.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 08/14] colibri-imx6ull: migrate pinctrl and regulators to dtb/dm

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate pinctrl and regulators to device tree resp. driver model:
> Ethernet, NAND and UART.
> Drop BOARD_EARLY_INIT_F as it is anyway no longer used.
> Enable CMD_DM, CMD_MTD, CMD_REGULATOR and DM_REGULATOR_FIXED.
> While at it also update copyright period.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,RESEND,08/10] imx8: imx8-pins: add i.MX8QM

[sbabic at denx.de]

> Add i.MX8QM entry
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] imx: add lowlevel init for ARM64

[sbabic at denx.de]

> Sometimes we met SERROR, but only to catch it when Linux boots up.
> Let's enable catching in U-Boot to catch it ealier and ease debug.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Stefano Babic]

On 26/04/19 11:20, Marcel Ziswiler wrote:
> Hi Igor
> 
> Sorry, somehow I missed your comments below (;-p).
> 
> I will send out a v4 (yes there already was a v3 BTW) shortly including
> the SPL resp. without SPL build fix.

Fine - the series (without 5/5) is already applied on u-boot-imx. Please
just send 5/5.

Regards,
Stefano

> 
> On Thu, 2019-04-11 at 12:47 +0200, Igor Opaniuk wrote:
>> Hi Marcel,
>>
>> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
>>
>> Some minor comments below (can be addressed in different patch):
>>
>> On Tue, Apr 9, 2019 at 5:34 PM Marcel Ziswiler <marcel@ziswiler.com>
>> wrote:
>>> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>>>
>>> This commit adds initial support for the Toradex Colibri iMX8QXP
>>> 2GB WB
>>> IT V1.0B module. Unlike the V1.0A early access samples exclusively
>>> booting from SD card, they are now strapped to boot from eFuses
>>> which
>>> are factory fused to properly boot from their on-module eMMC. U-
>>> Boot
>>> supports either booting from the on-module eMMC or may be used for
>>> recovery purpose using the universal update utility (uuu) aka
>>> mfgtools
>>> 3.0.
>>>
>>> Functionality wise the following is known to be working:
>>> - eMMC and MMC/SD card
>>> - Ethernet
>>> - GPIOs
>>> - I2C
>>>
>>> Unfortunately, there is no USB functionality for the i.MX 8QXP as
>>> of
>>> yet.
>>>
>>> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>>>
>>> ---
>>>
>>> Changes in v2:
>>> - Changed imx-atf git clone command to include initial branch
>>>   information as suggested by Igor.
>>> - Sorted board file includes alphabetically as suggested by Igor.
>>> - Got rid of SPL configuration in legacy header file as suggested
>>> by
>>>   Igor and the whole use of SPL on i.MX 8X anyway neither works
>>> well
>>>   nor makes any much sense at all.
>>>
>>>  arch/arm/dts/Makefile                         |   4 +-
>>>  arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi  | 112 ++++++
>>>  arch/arm/dts/fsl-imx8qxp-colibri.dts          | 328
>>> ++++++++++++++++++
>>>  arch/arm/mach-imx/imx8/Kconfig                |   6 +
>>>  board/toradex/colibri-imx8qxp/Kconfig         |  30 ++
>>>  board/toradex/colibri-imx8qxp/MAINTAINERS     |   9 +
>>>  board/toradex/colibri-imx8qxp/Makefile        |   7 +
>>>  board/toradex/colibri-imx8qxp/README          |  66 ++++
>>>  .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 212 +++++++++++
>>>  board/toradex/colibri-imx8qxp/imximage.cfg    |  24 ++
>>>  configs/colibri-imx8qxp_defconfig             |  53 +++
>>>  include/configs/colibri-imx8qxp.h             | 214 ++++++++++++
>>>  12 files changed, 1064 insertions(+), 1 deletion(-)
>>>  create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
>>>  create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts
>>>  create mode 100644 board/toradex/colibri-imx8qxp/Kconfig
>>>  create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS
>>>  create mode 100644 board/toradex/colibri-imx8qxp/Makefile
>>>  create mode 100644 board/toradex/colibri-imx8qxp/README
>>>  create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
>>>  create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg
>>>  create mode 100644 configs/colibri-imx8qxp_defconfig
>>>  create mode 100644 include/configs/colibri-imx8qxp.h
>>>
>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>> index 13d1d67624..2a551d42a4 100644
>>> --- a/arch/arm/dts/Makefile
>>> +++ b/arch/arm/dts/Makefile
>>> @@ -559,7 +559,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
>>>
>>>  dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
>>>
>>> -dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
>>> +dtb-$(CONFIG_ARCH_IMX8) += \
>>> +       fsl-imx8qxp-colibri.dtb \
>>> +       fsl-imx8qxp-mek.dtb
>>>
>>>  dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
>>>
>>> diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
>>> b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
>>> new file mode 100644
>>> index 0000000000..f8686befdf
>>> --- /dev/null
>>> +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
>>> @@ -0,0 +1,112 @@
>>> +// SPDX-License-Identifier: GPL-2.0+ OR X11
>>> +/*
>>> + * Copyright 2019 Toradex AG
>>> + */
>>> +
>>> +&mu {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&clk {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&iomuxc {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_lsio {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_lsio_gpio0 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_lsio_gpio1 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_lsio_gpio2 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_lsio_gpio3 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_lsio_gpio4 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_lsio_gpio5 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_lsio_gpio6 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_lsio_gpio7 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_conn {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_conn_sdch0 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_conn_sdch1 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&pd_conn_sdch2 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&gpio0 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&gpio1 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&gpio2 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&gpio3 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&gpio4 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&gpio5 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&gpio6 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&gpio7 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&lpuart3 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&usdhc1 {
>>> +       u-boot,dm-spl;
>>> +};
>>> +
>>> +&usdhc2 {
>>> +       u-boot,dm-spl;
>>> +};
>>> diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts
>>> b/arch/arm/dts/fsl-imx8qxp-colibri.dts
>>> new file mode 100644
>>> index 0000000000..0c20edf2cf
>>> --- /dev/null
>>> +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts
>>> @@ -0,0 +1,328 @@
>>> +// SPDX-License-Identifier: GPL-2.0+ OR X11
>>> +/*
>>> + * Copyright 2019 Toradex AG
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include "fsl-imx8qxp.dtsi"
>>> +#include "fsl-imx8qxp-colibri-u-boot.dtsi"
>>> +
>>> +/ {
>>> +       model = "Toradex Colibri iMX8QXP";
>>> +       compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";
>>> +
>>> +       chosen {
>>> +               bootargs = "console=ttyLP3,115200
>>> earlycon=lpuart32,0x5a090000,115200";
>>> +               stdout-path = &lpuart3;
>>> +       };
>>> +
>>> +       reg_usbh_vbus: regulator-usbh-vbus {
>>> +               compatible = "regulator-fixed";
>>> +               pinctrl-names = "default";
>>> +               pinctrl-0 = <&pinctrl_usbh1_reg>;
>>> +               regulator-name = "usbh_vbus";
>>> +               regulator-min-microvolt = <5000000>;
>>> +               regulator-max-microvolt = <5000000>;
>>> +               gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
>>> +       };
>>> +};
>>> +
>>> +&iomuxc {
>>> +       pinctrl-names = "default";
>>> +       pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>,
>>> <&pinctrl_hog2>;
>>> +
>>> +       colibri-imx8qxp {
>>> +               pinctrl_lpuart0: lpuart0grp {
>>> +                       fsl,pins = <
>>> +                               SC_P_UART0_RX_ADMA_UART0_RX     0x0
>>> 6000020
>>> +                               SC_P_UART0_TX_ADMA_UART0_TX     0x0
>>> 6000020
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_lpuart3: lpuart3grp {
>>> +                       fsl,pins = <
>>> +                               SC_P_FLEXCAN2_RX_ADMA_UART3_RX  0x0
>>> 6000020
>>> +                               SC_P_FLEXCAN2_TX_ADMA_UART3_TX  0x0
>>> 6000020
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
>>> +                       fsl,pins = <
>>> +                               SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_
>>> IO00 0x00000020 /* DTR */
>>> +                               SC_P_SAI1_RXD_LSIO_GPIO0_IO29      
>>>      0x00000020 /* CTS */
>>> +                               SC_P_SAI1_RXC_LSIO_GPIO0_IO30      
>>>      0x00000020 /* RTS */
>>> +                               SC_P_CSI_RESET_LSIO_GPIO3_IO03     
>>>      0x00000020 /* DSR */
>>> +                               SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22   
>>>      0x00000020 /* DCD */
>>> +                               SC_P_CSI_EN_LSIO_GPIO3_IO02        
>>>      0x00000020 /* RI */
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_fec1: fec1grp {
>>> +                       fsl,pins = <
>>> +                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENE
>>> TB0_PAD      0x000014a0 /* Use pads in 3.3V mode */
>>> +                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENE
>>> TB1_PAD      0x000014a0 /* Use pads in 3.3V mode */
>>> +                               SC_P_ENET0_MDC_CONN_ENET0_MDC      
>>>              0x06000020
>>> +                               SC_P_ENET0_MDIO_CONN_ENET0_MDIO    
>>>              0x06000020
>>> +                               SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_
>>> RGMII_TX_CTL 0x00000061
>>> +                               SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCL
>>> K50M_OUT     0x06000061
>>> +                               SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RG
>>> MII_TXD0     0x00000061
>>> +                               SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RG
>>> MII_TXD1     0x00000061
>>> +                               SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_
>>> RGMII_RX_CTL 0x00000061
>>> +                               SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RG
>>> MII_RXD0     0x00000061
>>> +                               SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RG
>>> MII_RXD1     0x00000061
>>> +                               SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RM
>>> II_RX_ER     0x00000061
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_gpio_bl_on: gpio-bl-on {
>>> +                       fsl,pins = <
>>> +                               SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12  
>>>      0x00000040
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_hog0: hog0grp {
>>> +                       fsl,pins = <
>>> +                               SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_
>>> PAD  0x000514a0 /* Use pads in 3.3V mode */
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_hog1: hog1grp {
>>> +                       fsl,pins = <
>>> +                               SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10  
>>>      0x00000020 /*  45 */
>>> +                               SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO
>>> 02   0x06000020 /*  65 */
>>> +                                       SC_P_CSI_D07_CI_PI_D09     
>>>      0x00000061
>>> +                               SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11  
>>>      0x00000020 /*  69 */
>>> +                               SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13    
>>>      0x00000020 /*  73 */
>>> +                               SC_P_SAI0_TXC_LSIO_GPIO0_IO26      
>>>      0x00000020 /*  79 */
>>> +                                       SC_P_CSI_D02_CI_PI_D04     
>>>      0x00000061
>>> +                               SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO0
>>> 3    0x06000020 /*  85 */
>>> +                                       SC_P_CSI_D06_CI_PI_D08     
>>>      0x00000061
>>> +                               SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17   
>>>      0x00000020 /*  95 */
>>> +                               SC_P_SAI0_RXD_LSIO_GPIO0_IO27      
>>>      0x00000020 /*  97 */
>>> +                                       SC_P_CSI_D03_CI_PI_D05     
>>>      0x00000061
>>> +                               SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18  
>>>      0x00000020 /*  99 */
>>> +                               SC_P_SAI0_TXFS_LSIO_GPIO0_IO28     
>>>      0x00000020 /* 101 */
>>> +                                       SC_P_CSI_D00_CI_PI_D02     
>>>      0x00000061
>>> +                               SC_P_SAI0_TXD_LSIO_GPIO0_IO25      
>>>      0x00000020 /* 103 */
>>> +                                       SC_P_CSI_D01_CI_PI_D03     
>>>      0x00000061
>>
>> I seems that in 20 lines above alignment is broken a bit.
> 
> No, I believe Max intentionally did it that way downstream indicating
> that those SODIMM pins are each multiplexed onto two SoC balls. Toradex
> does this at times to gain greater pin compatibility across our module
> families.
> 
> Further comments down below taken into account. Thanks!
> 
> Cheers
> 
> Marcel
> 
>>> +                               SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19  
>>>      0x00000020 /* 105 */
>>> +                               SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20  
>>>      0x00000020 /* 107 */
>>> +                               SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05   
>>>      0x00000020 /* 127 */
>>> +                               SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06   
>>>      0x00000020 /* 131 */
>>> +                               SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04   
>>>      0x00000020 /* 133 */
>>> +                               SC_P_CSI_PCLK_LSIO_GPIO3_IO00      
>>>      0x00000020 /*  96 */
>>> +                               SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21  
>>>      0x00000020 /*  98 */
>>> +                               SC_P_SAI1_RXFS_LSIO_GPIO0_IO31     
>>>      0x00000020 /* 100 */
>>> +                               SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22    
>>>      0x00000020 /* 102 */
>>> +                               SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23  
>>>      0x00000020 /* 104 */
>>> +                               SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24  
>>>      0x00000020 /* 106 */
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_hog2: hog2grp {
>>> +                       fsl,pins = <
>>> +                               SC_P_CSI_MCLK_LSIO_GPIO3_IO01      
>>>      0x00000020 /*  75 */
>>> +                               SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14  
>>>      0x00000020 /*  77 */
>>> +                               SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15  
>>>      0x00000020 /*  89 */
>>> +                               SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16   
>>>      0x00000020 /*  93 */
>>> +                       >;
>>> +               };
>>> +
>>> +               /* Off Module I2C */
>>> +               pinctrl_i2c1: i2c1grp {
>>> +                       fsl,pins = <
>>> +                               SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_S
>>> CL   0x06000021
>>> +                               SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_S
>>> DA   0x06000021
>>> +                       >;
>>> +               };
>>> +
>>> +               /*INT*/
>>> +               pinctrl_usb3503a: usb3503a-grp {
>>> +                       fsl,pins = <
>>> +                               SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_
>>> IO04 0x00000061
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_usbc_det: usbc-det {
>>> +                       fsl,pins = <
>>> +                               SC_P_ENET0_REFCLK_125M_25M_LSIO_GPI
>>> O5_IO09      0x06000040
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_usbh1_reg: usbh1-reg {
>>> +                       fsl,pins = <
>>> +                               SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03   
>>>      0x06000040
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_usdhc1: usdhc1grp {
>>> +                       fsl,pins = <
>>> +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK      
>>>      0x06000041
>>> +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD      
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7  
>>>      0x00000021
>>> +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE
>>>      0x00000041
>>> +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET
>>> _B   0x00000021
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
>>> +                       fsl,pins = <
>>> +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK      
>>>      0x06000041
>>> +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD      
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7  
>>>      0x00000021
>>> +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE
>>>      0x00000041
>>> +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET
>>> _B   0x00000021
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>>> +                       fsl,pins = <
>>> +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK      
>>>      0x06000041
>>> +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD      
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6  
>>>      0x00000021
>>> +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7  
>>>      0x00000021
>>> +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE
>>>      0x00000041
>>> +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET
>>> _B   0x00000021
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_usdhc2_gpio: usdhc2gpiogrp {
>>> +                       fsl,pins = <
>>> +                               SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09  
>>>      0x06000021
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_usdhc2: usdhc2grp {
>>> +                       fsl,pins = <
>>> +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK    
>>>      0x06000041
>>> +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD    
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3
>>>      0x00000021
>>> +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSE
>>> LECT 0x00000021
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>>> +                       fsl,pins = <
>>> +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK    
>>>      0x06000041
>>> +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD    
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3
>>>      0x00000021
>>> +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSE
>>> LECT 0x00000021
>>> +                       >;
>>> +               };
>>> +
>>> +               pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>>> +                       fsl,pins = <
>>> +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK    
>>>      0x06000041
>>> +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD    
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2
>>>      0x00000021
>>> +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3
>>>      0x00000021
>>> +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSE
>>> LECT 0x00000021
>>> +                       >;
>>> +               };
>>> +       };
>>> +};
>>> +
>>> +&lpuart0 {
>>> +       pinctrl-names = "default";
>>> +       pinctrl-0 = <&pinctrl_lpuart0>;
>>> +       status = "okay";
>>> +};
>>> +
>>> +&lpuart3 {
>>> +       pinctrl-names = "default";
>>> +       pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
>>> +       status = "okay";
>>> +};
>>> +
>>> +&gpio0 {
>>> +       status = "okay";
>>> +};
>>> +
>>> +&gpio1 {
>>> +       status = "okay";
>>> +};
>>> +
>>> +&gpio3 {
>>> +       status = "okay";
>>> +};
>>> +
>>> +&gpio4 {
>>> +       status = "okay";
>>> +};
>>> +
>>> +&fec1 {
>>> +       phy-handle = <&ethphy0>;
>>> +       phy-mode = "rmii";
>>> +       pinctrl-names = "default";
>>> +       pinctrl-0 = <&pinctrl_fec1>;
>>> +       status = "okay";
>>> +
>>> +       mdio {
>>> +               #address-cells = <1>;
>>> +               #size-cells = <0>;
>>> +
>>> +               ethphy0: ethernet-phy at 2 {
>>> +                       compatible = "ethernet-phy-ieee802.3-c22";
>>> +                       max-speed = <100>;
>>> +                       reg = <2>;
>>> +               };
>>> +       };
>>> +};
>>> +
>>> +&i2c1 {
>>> +       #address-cells = <1>;
>>> +       #size-cells = <0>;
>>> +       clock-frequency = <100000>;
>>> +       pinctrl-names = "default";
>>> +       pinctrl-0 = <&pinctrl_i2c1>;
>>> +       status = "okay";
>>> +};
>>> +
>>> +&usdhc1 {
>>> +       bus-width = <8>;
>>> +       non-removable;
>>> +       pinctrl-names = "default", "state_100mhz", "state_200mhz";
>>> +       pinctrl-0 = <&pinctrl_usdhc1>;
>>> +       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>>> +       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>>> +       status = "okay";
>>> +};
>>> +
>>> +&usdhc2 {
>>> +       bus-width = <4>;
>>> +       cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
>>> +       pinctrl-names = "default", "state_100mhz", "state_200mhz";
>>> +       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
>>> +       pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
>>> <&pinctrl_usdhc2_gpio>;
>>> +       pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
>>> <&pinctrl_usdhc2_gpio>;
>>> +       status = "okay";
>>> +};
>>> diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-
>>> imx/imx8/Kconfig
>>> index f76a139684..feea07f135 100644
>>> --- a/arch/arm/mach-imx/imx8/Kconfig
>>> +++ b/arch/arm/mach-imx/imx8/Kconfig
>>> @@ -22,6 +22,11 @@ choice
>>>         prompt "i.MX8 board select"
>>>         optional
>>>
>>> +config TARGET_COLIBRI_IMX8QXP
>>> +       bool "Support Colibri iMX8QXP module"
>>> +       select BOARD_LATE_INIT
>>> +       select IMX8QXP
>>> +
>>>  config TARGET_IMX8QXP_MEK
>>>         bool "Support i.MX8QXP MEK board"
>>>         select BOARD_LATE_INIT
>>> @@ -30,5 +35,6 @@ config TARGET_IMX8QXP_MEK
>>>  endchoice
>>>
>>>  source "board/freescale/imx8qxp_mek/Kconfig"
>>> +source "board/toradex/colibri-imx8qxp/Kconfig"
>>>
>>>  endif
>>> diff --git a/board/toradex/colibri-imx8qxp/Kconfig
>>> b/board/toradex/colibri-imx8qxp/Kconfig
>>> new file mode 100644
>>> index 0000000000..340fe72816
>>> --- /dev/null
>>> +++ b/board/toradex/colibri-imx8qxp/Kconfig
>>> @@ -0,0 +1,30 @@
>>> +if TARGET_COLIBRI_IMX8QXP
>>> +
>>> +config SYS_BOARD
>>> +       default "colibri-imx8qxp"
>>> +
>>> +config SYS_VENDOR
>>> +       default "toradex"
>>> +
>>> +config SYS_CONFIG_NAME
>>> +       default "colibri-imx8qxp"
>>> +
>>> +config TDX_CFG_BLOCK
>>> +       default y
>>> +
>>> +config TDX_HAVE_MMC
>>> +       default y
>>> +
>>> +config TDX_CFG_BLOCK_DEV
>>> +       default "0"
>>> +
>>> +config TDX_CFG_BLOCK_PART
>>> +       default "1"
>>> +
>>> +# Toradex config block in eMMC, at the end of 1st "boot sector"
>>> +config TDX_CFG_BLOCK_OFFSET
>>> +       default "-512"
>>> +
>>> +source "board/toradex/common/Kconfig"
>>> +
>>> +endif
>>> diff --git a/board/toradex/colibri-imx8qxp/MAINTAINERS
>>> b/board/toradex/colibri-imx8qxp/MAINTAINERS
>>> new file mode 100644
>>> index 0000000000..39a9eb79b7
>>> --- /dev/null
>>> +++ b/board/toradex/colibri-imx8qxp/MAINTAINERS
>>> @@ -0,0 +1,9 @@
>>> +Colibri iMX8QXP
>>> +M:     Marcel Ziswiler <marcel.ziswiler@toradex.com>
>>> +W:     http://developer.toradex.com/software/linux/linux-software
>>> +S:     Maintained
>>> +F:     arch/arm/dts/fsl-imx8qxp-colibri.dts
>>> +F:     arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
>>> +F:     board/toradex/colibri-imx8qxp/
>>> +F:     configs/colibri-imx8qxp_defconfig
>>> +F:     include/configs/colibri-imx8qxp.h
>>> diff --git a/board/toradex/colibri-imx8qxp/Makefile
>>> b/board/toradex/colibri-imx8qxp/Makefile
>>> new file mode 100644
>>> index 0000000000..f6342e1dca
>>> --- /dev/null
>>> +++ b/board/toradex/colibri-imx8qxp/Makefile
>>> @@ -0,0 +1,7 @@
>>> +#
>>> +# Copyright 2019 Toradex
>>> +#
>>> +# SPDX-License-Identifier:     GPL-2.0+
>>
>> SPDX line should be in the beginning of the file.
>>
>>> +#
>>> +
>>> +obj-y += colibri-imx8qxp.o
>>> diff --git a/board/toradex/colibri-imx8qxp/README
>>> b/board/toradex/colibri-imx8qxp/README
>>> new file mode 100644
>>> index 0000000000..e68d183fe6
>>> --- /dev/null
>>> +++ b/board/toradex/colibri-imx8qxp/README
>>> @@ -0,0 +1,66 @@
>>> +U-Boot for the Toradex Colibri iMX8QXP V1.0B module
>>> +
>>> +Quick Start
>>> +===========
>>> +
>>> +- Build the ARM trusted firmware binary
>>> +- Get scfw_tcm.bin and ahab-container.img
>>> +- Build U-Boot
>>> +- Load U-Boot binary using uuu
>>> +- Flash U-Boot binary into the eMMC
>>> +- Boot
>>> +
>>> +Get and Build the ARM Trusted Firmware
>>> +======================================
>>> +
>>> +$ git clone -b imx_4.14.78_1.0.0_ga 
>>> https://source.codeaurora.org/external/imx/imx-atf
>>> +$ cd imx-atf/
>>> +$ make PLAT=imx8qxp bl31
>>> +
>>> +Get scfw_tcm.bin and ahab-container.img
>>> +=======================================
>>> +
>>> +$ wget 
>>> https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
>>> +$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-
>>> tcm.bin
>>> +$ wget 
>>> https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin
>>> +$ chmod +x firmware-imx-7.6.bin
>>> +$ ./firmware-imx-7.6.bin
>>> +
>>> +Copy the following binaries to the U-Boot folder:
>>> +
>>> +$ cp imx-atf/build/imx8qxp/release/bl31.bin .
>>> +$ cp u-boot/u-boot.bin .
>>> +
>>> +Copy the following firmware to the U-Boot folder:
>>> +
>>> +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
>>> +
>>> +Build U-Boot
>>> +============
>>> +
>>> +$ make colibri-imx8qxp_defconfig
>>> +$ make u-boot-dtb.imx
>>> +
>>> +Load the U-Boot Binary Using UUU
>>> +================================
>>> +
>>> +Get the latest version of the universal update utility (uuu) aka
>>> mfgtools 3.0:
>>> +
>>> +
>>> https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
>>> +
>>> +Put the module into USB recovery aka serial downloader mode,
>>> connect USB device
>>> +to your host and execute uuu:
>>> +
>>> +sudo ./uuu u-boot/u-boot-dtb.imx
>>> +
>>> +Flash the U-Boot Binary into the eMMC
>>> +=====================================
>>> +
>>> +Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot
>>> area partition:
>>> +
>>> +load mmc 1:1 $loadaddr u-boot-dtb.imx
>>> +setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} /
>>> 0x200
>>> +mmc dev 0 1
>>> +mmc write ${loadaddr} 0x0 ${blkcnt}
>>> +
>>> +Boot
>>> diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
>>> b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
>>> new file mode 100644
>>> index 0000000000..9aa0f096d2
>>> --- /dev/null
>>> +++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
>>> @@ -0,0 +1,212 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright 2019 Toradex
>>> + */
>>> +
>>> +#include <common.h>
>>> +
>>> +#include <asm/arch/clock.h>
>>> +#include <asm/arch/imx8-pins.h>
>>> +#include <asm/arch/iomux.h>
>>> +#include <asm/arch/sci/sci.h>
>>> +#include <asm/arch/sys_proto.h>
>>> +#include <asm/gpio.h>
>>> +#include <asm/io.h>
>>> +#include <asm/mach-imx/video.h>
>>> +#include <dm.h>
>>> +#include <environment.h>
>>> +#include <errno.h>
>>> +#include <fdt_support.h>
>>> +#include <fsl_esdhc.h>
>>> +#include <fsl_ifc.h>
>>> +#include <i2c.h>
>>> +#include <linux/libfdt.h>
>>> +#include <malloc.h>
>>> +#include <netdev.h>
>>> +#include <power-domain.h>
>>> +#include <usb.h>
>>> +
>>> +#include "../common/tdx-cfg-block.h"
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +#define GPIO_PAD_CTRL  ((SC_PAD_CONFIG_NORMAL <<
>>> PADRING_CONFIG_SHIFT) | \
>>> +                        (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT)
>>> | \
>>> +                        (SC_PAD_28FDSOI_DSE_DV_HIGH <<
>>> PADRING_DSE_SHIFT) | \
>>> +                        (SC_PAD_28FDSOI_PS_PU <<
>>> PADRING_PULL_SHIFT))
>>> +
>>> +#define UART_PAD_CTRL  ((SC_PAD_CONFIG_OUT_IN <<
>>> PADRING_CONFIG_SHIFT) | \
>>> +                        (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT)
>>> | \
>>> +                        (SC_PAD_28FDSOI_DSE_DV_HIGH <<
>>> PADRING_DSE_SHIFT) | \
>>> +                        (SC_PAD_28FDSOI_PS_PU <<
>>> PADRING_PULL_SHIFT))
>>> +
>>> +static iomux_cfg_t uart3_pads[] = {
>>> +       SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) |
>>> MUX_PAD_CTRL(UART_PAD_CTRL),
>>> +       SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) |
>>> MUX_PAD_CTRL(UART_PAD_CTRL),
>>> +       /* Transceiver FORCEOFF# signal, mux to use pullup */
>>> +       SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) |
>>> MUX_PAD_CTRL(UART_PAD_CTRL),
>>> +};
>>> +
>>> +static void setup_iomux_uart(void)
>>> +{
>>> +       imx8_iomux_setup_multiple_pads(uart3_pads,
>>> ARRAY_SIZE(uart3_pads));
>>> +}
>>> +
>>> +int board_early_init_f(void)
>>> +{
>>> +       sc_pm_clock_rate_t rate;
>>> +       sc_err_t err = 0;
>>> +
>>> +       /*
>>> +        * This works around that having only UART3 up the baudrate
>>> is 1.2M
>>> +        * instead of 115.2k. Set UART0 clock root to 80 MHz
>>> +        */
>>> +       rate = 80000000;
>>> +       err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER,
>>> &rate);
>>> +       if (err != SC_ERR_NONE)
>>> +               return 0;
>>> +
>>> +       /* Power up UART3 */
>>> +       err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3,
>>> SC_PM_PW_MODE_ON);
>>> +       if (err != SC_ERR_NONE)
>>> +               return 0;
>>> +
>>> +       /* Set UART3 clock root to 80 MHz */
>>> +       rate = 80000000;
>>> +       err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER,
>>> &rate);
>>> +       if (err != SC_ERR_NONE)
>>> +               return 0;
>>> +
>>> +       /* Enable UART3 clock root */
>>> +       err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER,
>>> true, false);
>>> +       if (err != SC_ERR_NONE)
>>> +               return 0;
>>> +
>>> +       setup_iomux_uart();
>>> +
>>> +       return 0;
>>> +}
>>> +
>>> +#undef CONFIG_MXC_GPIO /* TODO */
>>> +#ifdef CONFIG_MXC_GPIO
>>> +#define IOEXP_RESET IMX_GPIO_NR(1, 1)
>>> +
>>> +static iomux_cfg_t board_gpios[] = {
>>> +       SC_P_SPI2_SDO | MUX_MODE_ALT(4) |
>>> MUX_PAD_CTRL(GPIO_PAD_CTRL),
>>> +       SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | \
>>> +               MUX_PAD_CTRL(GPIO_PAD_CTRL),
>>> +};
>>> +
>>> +static void board_gpio_init(void)
>>> +{
>>> +       struct gpio_desc desc;
>>> +       int ret;
>>> +
>>> +       ret = dm_gpio_lookup_name("gpio at 1a_3", &desc);
>>> +       if (ret)
>>> +               return;
>>> +
>>> +       ret = dm_gpio_request(&desc, "bb_per_rst_b");
>>> +       if (ret)
>>> +               return;
>>> +
>>> +       dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
>>> +       dm_gpio_set_value(&desc, 0);
>>> +       udelay(50);
>>> +       dm_gpio_set_value(&desc, 1);
>>> +
>>> +       imx8_iomux_setup_multiple_pads(board_gpios,
>>> ARRAY_SIZE(board_gpios));
>>> +
>>> +       /* enable i2c port expander assert reset line */
>>> +       gpio_request(IOEXP_RESET, "ioexp_rst");
>>> +       gpio_direction_output(IOEXP_RESET, 1);
>>> +}
>>> +#else
>>> +static inline void board_gpio_init(void) {}
>>> +#endif
>>> +
>>> +#if IS_ENABLED(CONFIG_FEC_MXC)
>>> +#include <miiphy.h>
>>> +
>>> +int board_phy_config(struct phy_device *phydev)
>>> +{
>>> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
>>> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
>>> +
>>> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
>>> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
>>> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
>>> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
>>> +
>>> +       if (phydev->drv->config)
>>> +               phydev->drv->config(phydev);
>>> +
>>> +       return 0;
>>> +}
>>> +#endif
>>> +
>>> +void build_info(void)
>>> +{
>>> +       u32 sc_build = 0, sc_commit = 0;
>>> +
>>> +       /* Get SCFW build and commit id */
>>> +       sc_misc_build_info(-1, &sc_build, &sc_commit);
>>> +       if (!sc_build) {
>>> +               printf("SCFW does not support build info\n");
>>> +               sc_commit = 0; /* Display 0 if build info not
>>> supported */
>>> +       }
>>> +       printf("Build: SCFW %x\n", sc_commit);
>>> +}
>>> +
>>> +int checkboard(void)
>>> +{
>>> +       puts("Model: Toradex Colibri iMX8X\n");
>>> +
>>> +       build_info();
>>> +       print_bootinfo();
>>> +
>>> +       return 0;
>>> +}
>>> +
>>> +int board_init(void)
>>> +{
>>> +       board_gpio_init();
>>> +
>>> +       return 0;
>>> +}
>>> +
>>> +void detail_board_ddr_info(void)
>>> +{
>>> +       puts("\nDDR    ");
>>> +}
>>> +
>>> +/*
>>> + * Board specific reset that is system reset.
>>> + */
>>> +void reset_cpu(ulong addr)
>>> +{
>>> +       /* TODO */
>>> +}
>>> +
>>> +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
>>> +int ft_board_setup(void *blob, bd_t *bd)
>>> +{
>>> +       return ft_common_board_setup(blob, bd);
>>> +}
>>> +#endif
>>> +
>>> +int board_mmc_get_env_dev(int devno)
>>> +{
>>> +       return devno;
>>> +}
>>> +
>>> +int board_late_init(void)
>>> +{
>>> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
>>> +/* TODO move to common */
>>> +       env_set("board_name", "Colibri iMX8QXP");
>>> +       env_set("board_rev", "v1.0");
>>> +#endif
>>> +
>>> +       return 0;
>>> +}
>>> diff --git a/board/toradex/colibri-imx8qxp/imximage.cfg
>>> b/board/toradex/colibri-imx8qxp/imximage.cfg
>>> new file mode 100644
>>> index 0000000000..ce9e66c64d
>>> --- /dev/null
>>> +++ b/board/toradex/colibri-imx8qxp/imximage.cfg
>>> @@ -0,0 +1,24 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/*
>>> + * Copyright 2019 Toradex
>>> + *
>>> + * Refer doc/README.imx8image for more details about how-to
>>> configure
>>> + * and create imx8image boot image
>>> + */
>>> +
>>> +#define __ASSEMBLY__
>>> +
>>> +/* Boot from SD, sector size 0x400 */
>>> +BOOT_FROM EMMC_FASTBOOT 0x400
>>> +/* SoC type IMX8QX */
>>> +SOC_TYPE IMX8QX
>>> +/* Append seco container image */
>>> +APPEND ahab-container.img
>>> +/* Create the 2nd container */
>>> +CONTAINER
>>> +/* Add scfw image with exec attribute */
>>> +IMAGE SCU mx8qx-colibri-scfw-tcm.bin
>>> +/* Add ATF image with exec attribute */
>>> +IMAGE A35 bl31.bin 0x80000000
>>> +/* Add U-Boot image with load attribute */
>>> +DATA A35 u-boot-dtb.bin 0x80020000
>>> diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-
>>> imx8qxp_defconfig
>>> new file mode 100644
>>> index 0000000000..d697546ed7
>>> --- /dev/null
>>> +++ b/configs/colibri-imx8qxp_defconfig
>>> @@ -0,0 +1,53 @@
>>> +CONFIG_ARM=y
>>> +CONFIG_ARCH_IMX8=y
>>> +CONFIG_SYS_TEXT_BASE=0x80020000
>>> +CONFIG_SYS_MALLOC_F_LEN=0x2000
>>> +CONFIG_TARGET_COLIBRI_IMX8QXP=y
>>> +CONFIG_DISTRO_DEFAULTS=y
>>> +CONFIG_NR_DRAM_BANKS=3
>>> +CONFIG_FIT=y
>>> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-
>>> imx8qxp/imximage.cfg"
>>> +CONFIG_LOG=y
>>> +CONFIG_VERSION_VARIABLE=y
>>> +# CONFIG_DISPLAY_BOARDINFO is not set
>>> +CONFIG_BOARD_EARLY_INIT_F=y
>>> +CONFIG_CMD_CPU=y
>>> +# CONFIG_CMD_IMPORTENV is not set
>>> +CONFIG_CMD_MEMTEST=y
>>> +CONFIG_CMD_CLK=y
>>> +CONFIG_CMD_DM=y
>>> +CONFIG_CMD_GPIO=y
>>> +CONFIG_CMD_I2C=y
>>> +CONFIG_CMD_MMC=y
>>> +CONFIG_CMD_CACHE=y
>>> +CONFIG_CMD_UUID=y
>>> +CONFIG_CMD_EXT4_WRITE=y
>>> +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
>>> +CONFIG_ENV_IS_IN_MMC=y
>>> +CONFIG_CLK_IMX8=y
>>> +CONFIG_CPU=y
>>> +CONFIG_DM_GPIO=y
>>> +CONFIG_MXC_GPIO=y
>>> +CONFIG_DM_I2C=y
>>> +CONFIG_SYS_I2C_IMX_LPI2C=y
>>> +CONFIG_MISC=y
>>> +CONFIG_DM_MMC=y
>>> +CONFIG_PHYLIB=y
>>> +CONFIG_PHY_ADDR_ENABLE=y
>>> +CONFIG_PHY_MICREL=y
>>> +CONFIG_DM_ETH=y
>>> +CONFIG_FEC_MXC_SHARE_MDIO=y
>>> +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
>>> +CONFIG_FEC_MXC=y
>>> +CONFIG_MII=y
>>> +CONFIG_PINCTRL=y
>>> +CONFIG_PINCTRL_IMX8=y
>>> +CONFIG_POWER_DOMAIN=y
>>> +CONFIG_IMX8_POWER_DOMAIN=y
>>> +CONFIG_DM_REGULATOR=y
>>> +CONFIG_DM_REGULATOR_FIXED=y
>>> +CONFIG_DM_REGULATOR_GPIO=y
>>> +CONFIG_DM_SERIAL=y
>>> +CONFIG_FSL_LPUART=y
>>> +CONFIG_DM_THERMAL=y
>>> +# CONFIG_EFI_LOADER is not set
>>> diff --git a/include/configs/colibri-imx8qxp.h
>>> b/include/configs/colibri-imx8qxp.h
>>> new file mode 100644
>>> index 0000000000..33cbcb44a9
>>> --- /dev/null
>>> +++ b/include/configs/colibri-imx8qxp.h
>>> @@ -0,0 +1,214 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/*
>>> + * Copyright 2019 Toradex
>>> + */
>>> +
>>> +#ifndef __COLIBRI_IMX8QXP_H
>>> +#define __COLIBRI_IMX8QXP_H
>>> +
>>> +#include <asm/arch/imx-regs.h>
>>> +#include <linux/sizes.h>
>>> +
>>> +#define CONFIG_REMAKE_ELF
>>> +
>>> +#define CONFIG_DISPLAY_BOARDINFO_LATE
>>> +
>>> +#undef CONFIG_CMD_EXPORTENV
>>> +#undef CONFIG_CMD_IMPORTENV
>>> +#undef CONFIG_CMD_IMLS
>>> +
>>> +#undef CONFIG_CMD_CRC32
>>> +#undef CONFIG_BOOTM_NETBSD
>>> +
>>> +#define CONFIG_FSL_ESDHC
>>> +#define CONFIG_FSL_USDHC
>>> +#define CONFIG_SYS_FSL_ESDHC_ADDR      0
>>> +#define USDHC1_BASE_ADDR               0x5B010000
>>> +#define USDHC2_BASE_ADDR               0x5B020000
>>> +#define CONFIG_SUPPORT_EMMC_BOOT       /* eMMC specific */
>>> +
>>> +#define CONFIG_ENV_OVERWRITE
>>> +
>>> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
>>> +
>>> +#define FEC_QUIRK_ENET_MAC
>>> +
>>> +#define CONFIG_IP_DEFRAG
>>> +#define CONFIG_TFTP_BLOCKSIZE          4096
>>
>> 4096 can be replaced with SZ_4K (from include/linux/sizes.h)
>>
>>> +#define CONFIG_TFTP_TSIZE
>>> +
>>> +#define CONFIG_IPADDR                  192.168.10.2
>>> +#define CONFIG_NETMASK                 255.255.255.0
>>> +#define CONFIG_SERVERIP                        192.168.10.1
>>> +
>>> +#define MEM_LAYOUT_ENV_SETTINGS \
>>> +       "fdt_addr_r=0x84000000\0" \
>>> +       "kernel_addr_r=0x82000000\0" \
>>> +       "ramdisk_addr_r=0x84100000\0"
>>> +
>>> +#ifdef CONFIG_AHAB_BOOT
>>> +#define AHAB_ENV "sec_boot=yes\0"
>>> +#else
>>> +#define AHAB_ENV "sec_boot=no\0"
>>> +#endif
>>> +
>>> +/* Boot M4 */
>>> +#define M4_BOOT_ENV \
>>> +       "m4_0_image=m4_0.bin\0" \
>>> +       "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
>>> " \
>>> +               "${m4_0_image}\0" \
>>> +       "m4boot_0=run loadm4image_0; dcache flush; bootaux
>>> ${loadaddr} 0\0" \
>>> +
>>> +#define MFG_NAND_PARTITION ""
>>> +
>>> +#define BOOT_TARGET_DEVICES(func) \
>>> +       func(MMC, mmc, 0) \
>>> +       func(MMC, mmc, 1) \
>>> +       func(DHCP, dhcp, na)
>>> +#include <config_distro_bootcmd.h>
>>> +#undef BOOTENV_RUN_NET_USB_START
>>> +#define BOOTENV_RUN_NET_USB_START ""
>>> +
>>> +#define CONFIG_MFG_ENV_SETTINGS \
>>> +       "mfgtool_args=setenv bootargs
>>> console=${console},${baudrate} " \
>>> +               "rdinit=/linuxrc g_mass_storage.stall=0 " \
>>> +               "g_mass_storage.removable=1
>>> g_mass_storage.idVendor=0x066F " \
>>> +               "g_mass_storage.idProduct=0x37FF " \
>>> +               "g_mass_storage.iSerialNumber=\"\" "\
>>> +               MFG_NAND_PARTITION \
>>> +               "video=imxdpufb5:off video=imxdpufb6:off
>>> video=imxdpufb7:off " \
>>> +               "clk_ignore_unused "\
>>> +               "\0" \
>>> +       "initrd_addr=0x83800000\0" \
>>> +       "initrd_high=0xffffffff\0" \
>>> +       "bootcmd_mfg=run mfgtool_args;booti ${loadaddr}
>>> ${initrd_addr} " \
>>> +               "${fdt_addr};\0" \
>>> +
>>> +/* Initial environment variables */
>>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>>> +       AHAB_ENV \
>>> +       BOOTENV \
>>> +       CONFIG_MFG_ENV_SETTINGS \
>>> +       M4_BOOT_ENV \
>>> +       MEM_LAYOUT_ENV_SETTINGS \
>>> +       "boot_fdt=try\0" \
>>> +       "bootscript=echo Running bootscript from mmc ...; source\0"
>>> \
>>> +       "console=ttyLP3,115200
>>> earlycon=lpuart32,0x5a090000,115200\0" \
>>> +       "fdt_addr=0x83000000\0"                 \
>>> +       "fdt_file=fsl-imx8qxp-colibri-eval-v3.dtb\0" \
>>> +       "fdt_high=0xffffffffffffffff\0"         \
>>> +       "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
>>> +       "image=Image\0" \
>>> +       "initrd_addr=0x83800000\0"              \
>>> +       "initrd_high=0xffffffffffffffff\0" \
>>> +       "loadbootscript=fatload mmc ${mmcdev}:${mmcpart}
>>> ${loadaddr} " \
>>> +               "${script};\0" \
>>> +       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
>>> ${fdt_file}\0" \
>>> +       "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
>>> ${image}\0" \
>>> +       "mmcargs=setenv bootargs console=${console},${baudrate} " \
>>> +               "root=PARTUUID=${uuid} rootwait " \
>>> +       "mmcautodetect=yes\0" \
>>> +       "mmcboot=echo Booting from mmc ...; " \
>>> +               "run finduuid; run mmcargs; " \
>>> +               "if test ${boot_fdt} = yes || test ${boot_fdt} =
>>> try; then " \
>>> +                       "if run loadfdt; then " \
>>> +                               "booti ${loadaddr} - ${fdt_addr}; "
>>> \
>>> +                       "else " \
>>> +                               "echo WARN: Cannot load the DT; " \
>>> +                       "fi; " \
>>> +               "else " \
>>> +                       "echo wait for boot; " \
>>> +               "fi;\0" \
>>> +       "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
>>> +       "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
>>> +       "netargs=setenv bootargs console=${console} root=/dev/nfs
>>> ip=dhcp " \
>>> +               "nfsroot=${serverip}:${nfsroot},v3,tcp
>>> video=imxdpufb5:off " \
>>> +               "video=imxdpufb6:off video=imxdpufb7:off\0" \
>>> +       "netboot=echo Booting from net ...; " \
>>> +               "run netargs; " \
>>> +               "if test ${ip_dyn} = yes; then " \
>>> +                       "setenv get_cmd dhcp; " \
>>> +               "else " \
>>> +                       "setenv get_cmd tftp; " \
>>> +               "fi; " \
>>> +               "${get_cmd} ${loadaddr} ${image}; " \
>>> +               "if test ${boot_fdt} = yes || test ${boot_fdt} =
>>> try; then " \
>>> +                       "if ${get_cmd} ${fdt_addr} ${fdt_file};
>>> then " \
>>> +                               "booti ${loadaddr} - ${fdt_addr}; "
>>> \
>>> +                       "else " \
>>> +                               "echo WARN: Cannot load the DT; " \
>>> +                       "fi; " \
>>> +               "else " \
>>> +                       "booti; " \
>>> +               "fi;\0" \
>>> +       "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp
>>> ${fdt_addr} " \
>>> +               "colibri-imx8qxp/${fdt_file}; booti ${loadaddr} - "
>>> \
>>> +               "${fdt_addr}\0" \
>>> +       "panel=NULL\0" \
>>> +       "script=boot.scr\0" \
>>> +       "video=imxdpufb5:off video=imxdpufb6:off
>>> video=imxdpufb7:off\0"
>>> +
>>> +#undef CONFIG_BOOTCOMMAND
>>> +#define CONFIG_BOOTCOMMAND \
>>> +          "mmc dev ${mmcdev}; if mmc rescan; then " \
>>> +                  "if run loadbootscript; then " \
>>> +                          "run bootscript; " \
>>> +                  "else " \
>>> +                          "if run loadimage; then " \
>>> +                                  "run mmcboot; " \
>>> +                          "else run netboot; " \
>>> +                          "fi; " \
>>> +                  "fi; " \
>>> +          "else booti ${loadaddr} - ${fdt_addr}; fi"
>>> +
>>> +/* Link Definitions */
>>> +#define CONFIG_LOADADDR                        0x80280000
>>> +
>>> +#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
>>> +
>>> +#define CONFIG_SYS_INIT_SP_ADDR                0x80200000
>>> +
>>> +#define CONFIG_SYS_MEMTEST_START       0x88000000
>>> +#define CONFIG_SYS_MEMTEST_END         0x89000000
>>> +
>>> +/* Environment in eMMC, before config block at the end of 1st
>>> "boot sector" */
>>> +#define CONFIG_ENV_SIZE                        (8 * 1024)
>>
>>  (8 * 1024) can be replaced with SZ_8K (from include/linux/sizes.h)
>>
>>> +#define CONFIG_ENV_OFFSET              (-CONFIG_ENV_SIZE + \
>>> +                                        CONFIG_TDX_CFG_BLOCK_OFFSE
>>> T)
>>> +#define CONFIG_SYS_MMC_ENV_DEV         0
>>> +#define CONFIG_SYS_MMC_ENV_PART                1
>>> +
>>> +#define CONFIG_SYS_MMC_IMG_LOAD_PART   1
>>> +
>>> +/* On Colibri iMX8 USDHC1 is eMMC, USDHC2 is 4-bit SD */
>>> +#define CONFIG_SYS_MMC_ENV_DEV         0                /* USDHC1
>>> eMMC */
>>> +#define CONFIG_SYS_FSL_USDHC_NUM       2
>>> +
>>> +/* Size of malloc() pool */
>>> +#define CONFIG_SYS_MALLOC_LEN          ((CONFIG_ENV_SIZE + (32 *
>>> 1024)) * 1024)
>>> +
>>> +#define CONFIG_SYS_SDRAM_BASE          0x80000000
>>> +#define CONFIG_NR_DRAM_BANKS           3
>>> +#define PHYS_SDRAM_1                   0x80000000
>>> +#define PHYS_SDRAM_2                   0x880000000
>>> +#define PHYS_SDRAM_1_SIZE              0x80000000      /* 2 GB */
>> 0x80000000 can be replaced with SZ_2G (from include/linux/sizes.h)
>>> +#define PHYS_SDRAM_2_SIZE              0x00000000      /* 0 GB */
>>> +
>>> +/* Serial */
>>> +#define CONFIG_BAUDRATE                        115200
>>> +
>>> +/* Monitor Command Prompt */
>>> +#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
>>> +#define CONFIG_SYS_CBSIZE              2048
>>
>> Same as above
>>
>>> +#define CONFIG_SYS_MAXARGS             64
>>> +#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
>>> +#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
>>> +                                       sizeof(CONFIG_SYS_PROMPT) +
>>> 16)
>>> +
>>> +/* Generic Timer Definitions */
>>> +#define COUNTER_FREQUENCY              8000000 /* 8MHz */
>>> +
>>> +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
>>> +#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from
>>> second 128MB */
>> Same as above
>>> +
>>> +#endif /* __COLIBRI_IMX8QXP_H */
>>> --
>>> 2.20.1
>>>
>>> _______________________________________________
>>> U-Boot mailing list
>>> U-Boot at lists.denx.de
>>> https://lists.denx.de/listinfo/u-boot


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,8/8] imx8: mek: move HUSH_PARSER to defconfig

[sbabic at denx.de]

> Move HUSH_PARSER to defconfig, otherwise meet
> "
> => run netboot
> Booting from net ...
> Unknown command 'if' - try 'help'
> Unknown command 'then' - try 'help'
> Unknown command 'else' - try 'help'
> Unknown command 'fi' - try 'help'
> Unknown command '0x80280000' - try 'help'
> Unknown command 'if' - try 'help'
> Unknown command 'then' - try 'help'
> Unknown command 'then' - try 'help'
> Unknown command 'else' - try 'help'
> Unknown command 'fi' - try 'help'
> Unknown command 'else' - try 'help'
> Unknown command 'fi' - try 'help'
> "
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, imx-next, v1, 06/14] ARM: kp_imx53: config: Do not use ${boardtype} to setup update wic file

[sbabic at denx.de]

> After unification of the rootfs for both HSC and DDC devices, only one,
> common wic file is necessary - without the distinction of specific board.
> Signed-off-by: Lukasz Majewski <lukma@denx.de>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot, v2, 10/14] colibri-imx6ull: migrate usb to using driver model

[sbabic at denx.de]

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Migrate USB to using driver model.
> Add USBH_PEN GPIO regulator.
> While at it also add alias e.g. as required for UMS.
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Marcel Ziswiler]

Hi Stefano

On Fri, 2019-04-26 at 11:46 +0200, Stefano Babic wrote:
> On 26/04/19 11:20, Marcel Ziswiler wrote:
> > Hi Igor
> > 
> > Sorry, somehow I missed your comments below (;-p).
> > 
> > I will send out a v4 (yes there already was a v3 BTW) shortly
> > including
> > the SPL resp. without SPL build fix.
> 
> Fine - the series (without 5/5) is already applied on u-boot-imx.
> Please
> just send 5/5.

OK, strange. While I thought I just checked on git.denx.de I somehow
missed that. Will just send 5/5 plus the SPL fix. Thanks!

> Regards,
> Stefano

Cheers

Marcel

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Peng Fan]

> -----Original Message-----
> From: Marcel Ziswiler [mailto:marcel.ziswiler at toradex.com]
> Sent: 2019年4月26日 17:38
> To: Peng Fan <peng.fan@nxp.com>; u-boot at lists.denx.de; sbabic at denx.de
> Cc: siva.durga.paladugu at xilinx.com; marek.vasut+renesas at gmail.com;
> maxime.ripard at bootlin.com; festevam at gmail.com;
> michal.simek at xilinx.com; wens at csie.org; dl-uboot-imx
> <uboot-imx@nxp.com>; yamada.masahiro at socionext.com; sr at denx.de;
> jagan at amarulasolutions.com; agust at denx.de; albert.u.boot at aribaud.net
> Subject: Re: [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it
> v1.0b module support
> 
> On Fri, 2019-04-26 at 09:03 +0000, Peng Fan wrote:
> > > Subject: Re: [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb
> > > wb it v1.0b module support
> > >
> > > Hi Peng and Stefano
> > >
> > > On Fri, 2019-04-26 at 10:38 +0200, Stefano Babic wrote:
> > > > Hi Peng,
> > > >
> > > > On 26/04/19 04:10, Peng Fan wrote:
> > > > > Hi Stefano,
> > > > >
> > > > > > Subject: Re: [PATCH v2 5/5] board: toradex: add colibri
> > > > > > imx8qxp 2gb wb it v1.0b module support
> > > > > >
> > > > > > Hi Marcel,
> > > > > >
> > > > > > On 25/04/19 14:35, Marcel Ziswiler wrote:
> > > > > > > Hi Stefano
> > > > > > >
> > > > > > > On Thu, 2019-04-25 at 12:48 +0200, Stefano Babic wrote:
> > > > > > > > Hi Marcel,
> > > > > > > >
> > > > > > > > On 09/04/19 17:25, Marcel Ziswiler wrote:
> > > > > > > > > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > > > > > > > >
> > > > > > > > > This commit adds initial support for the Toradex Colibri
> > > > > > > > > iMX8QXP 2GB WB IT V1.0B module. Unlike the V1.0A early
> > > > > > > > > access samples exclusively booting from SD card, they
> > > > > > > > > are now strapped to boot from eFuses which are factory
> > > > > > > > > fused to properly boot from their on-module eMMC. U-
> > > > > > > > > Boot supports either booting from the on-module eMMC or
> > > > > > may
> > > > > > > > > be used for recovery purpose using the universal update
> > > > > > > > > utility
> > > > > > > > > (uuu) aka mfgtools 3.0.
> > > > > > > > >
> > > > > > > > > Functionality wise the following is known to be
> > > > > > > > > working:
> > > > > > > > > - eMMC and MMC/SD card
> > > > > > > > > - Ethernet
> > > > > > > > > - GPIOs
> > > > > > > > > - I2C
> > > > > > > > >
> > > > > > > > > Unfortunately, there is no USB functionality for the
> > > > > > > > > i.MX 8QXP as of yet.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Marcel Ziswiler <
> > > > > > > > > marcel.ziswiler at toradex.com
> > > > > > > > >
> > > > > > > > > ---
> > > > > > > > >
> > > > > > > >
> > > > > > > > I merged the series and build locally (fine), but Travis
> > > > > > > > complains and stops with error:
> > > > > > > >
> > > > > > > > +cc1: fatal error: opening output file spl/u-boot-
> > > > > > > > spl.cfgout:
> > > > > > > > No such
> > > > > > > > file or directory
> > > > > > > > +compilation terminated.
> > > > > > > >
> > > > > > > > Can you take a look at it ?
> > > > > > >
> > > > > > > Sure, looks like Peng's commit caceb739ea07 ("imx: build
> > > > > > > flash.bin for
> > > > > > > i.MX8") takes SPL for granted while my patchset currently
> > > > > > > avoids it.
> > > > > >
> > > > > > It looks so, yes.
> > > > > >
> > > > > > > BTW: I still don't believe SPL makes much sense on i.MX 8X
> > > > > > > given all the other proprietary parts involved in booting.
> > > > > >
> > > > > > SPL makes more sense if it is possible to detect at runtime
> > > > > > the HW and change the configuration - for i.MX6, this means
> > > > > > RAMS detection, which boot device is booting, and so on.
> > > > > >
> > > > > > On i.MX8 there is a lot of proprietary parts - we lose the
> > > > > > flexibility of SPL, and most features are lost (or must be
> > > > > > provided by proprietary code).
> > > > > > I agree that
> > > > > > on this platform SPL makes less sense, and i.MX8 should be
> > > > > > built independently if CONFIG_SPL is set (this is also for
> > > > > > i.MX6 / MX5, there are boards without SPL and using the DCD
> > > > > > image to set up the RAM controller).
> > > > >
> > > > > The reason we move to use SPL on i.MX8 is that we would like to
> > > > > avoid bind ATF/OP-TEE/U-Boot into a flat image with hacked
> > > > > offset in an image.
> > > > >
> > > >
> > > > It seemed I have missed some point. Thanks for clarification.
> > > > This
> > > > makes sense.
> > >
> > > OK, I was also not aware of this.
> > >
> > > However, currently I am just happy the current tooling kinda works.
> > > Which is we can ship stuff to customers and they may use uuu to
> > > recover bricked modules. So far nobody is talking about OP-TEE and
> > > such advanced use cases yet.
> > >
> > > On the other hand enabling SPL currently does not seem to work at
> > > all on our hardware. Neither booting from eMMC nor recovering using
> > > uuu.
> > > That is really the main reason I decided against it at least for
> > > now.
> >
> > In vendor tree, we use SPL to load i.MX8 container image.
> > To UUU, 1st need to enable usb gadget functions in SPL, then enable
> > container for the 2nd image. So with uuu, it not work with upstream
> > U-Boot now.
> 
> Strange, for me this works just fine with mainline just not with SPL being

For flash.bin with SPL, UUU will not work for upstream uboot to load 2nd images.
For flash.bin without SPL, UUU will able to work. So it works for you.

Regards,
Peng.

> enabled e.g. as per board/toradex/colibri-imx8qxp/README:
> 
> [user at host uuu]$ sudo ./uuu u-boot/u-boot-dtb.imx uuu (Universal Update
> Utility) for nxp imx chips -- libuuu_1.2.66-0-
> ga1a8e69
> 
> Success 1    Failure 0
> 
> 1:33   2/ 2   [Done                        ] SDPS: done
> 
> U-Boot 2019.04-rc4-00169-g42dd45e2d9-dirty (Apr 26 2019 - 11:30:58
> +0200)
> 
> CPU:   NXP i.MX8QXP RevB A35 at 1200 MHz
> 
> DRAM:  2 GiB
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1
> Loading Environment from MMC... *** Warning - bad CRC, using default
> environment
> 
> In:    serial at 5a090000
> Out:   serial at 5a090000
> Err:   serial at 5a090000
> Model: Toradex Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT V1.0B, Serial#
> 06410651
> Net:   eth0: ethernet at 5b040000
> Hit any key to stop autoboot:  0
> =>
> 
> > > > > So the bootflow now is
> > > > > SPL->ATF->OPTEE->ATF->U-Boot
> > > > >
> > > > > Without SPL, when generating flash.bin, we have to hack ATF to
> > > > > copy OP-TEE image from flash.bin to the runtime location.
> > > >
> > > > Nevertheless, I understand that it is not strictly required to
> > > > enable OPTEE to boot the kernel, and in some applications a secure
> > > > zone is not required. The thing is not that SPL is used here, but
> > > > to constrain all other users like Marcel to do the same. With
> > > > i.MX6, even if I strongly suggested to do this to allow run time
> > > > detection, I let boards without SPL and with just u-boot.imx (with
> > > > built-in DCD) to flow into mainline - the board maintainer rules
> > > > as he knows better where the device is used.
> > >
> > > Thanks!
> > >
> > > > So I will prefer that the build assume to have SPL just if SPL is
> > > > configured and not in any case, letting boards without SPL (like
> > > > this
> > > > colibri-mx8
> > >
> > > Colibri iMX8X that is while on the Apalis family we have the Apalis
> > > iMX8 (e.g. with the i.MX 8QuadMax or i.MX 8QuadPlus) and the new
> > > Apalis iMX8X with ECC RAM still in the works. Welcome to the i.MX 8
> > > series with the i.MX 8 and i.MX 8X families and careful with NXP's
> > > brilliant naming scheme (;-p).
> > >
> > > > ) to build.
> > >
> > > Don't worry. I believe I found a fix for the issue at hand and will
> > > send a patch shortly.
> >
> > ok.
> >
> > Regards,
> > Peng.
> >
> > > > > > > Plus currently SPL
> > > > > > > actually breaks the USB serial downloader aka recovery mode
> > > > > > > using the universal update utility (uuu) aka mfgtools 3.0.
> > > > >
> > > > > The usb related function for i.MX8 is not ready now.
> > > >
> > > > That is ok - it s WIP, it will be merged when ready. I agree with
> > > > you, this is *not* a reason to avoid SPL.
> > >
> > > Agreed. However, it is kinda painful requiring different U-Boot
> > > configuration flavours for regular boot vs. recovery. That said we
> > > used to previously do this on Apalis/Colibri iMX6 as well so it is
> > > definitely no show stopper.
> > >
> > > > > we are almost run out
> > > > > of ocram with SPL DM, thinking to use OF_PLATDATA now, then move
> > > > > to usb functions.
> > > >
> > > > Understood.
> > >
> > > Yeah, I also played with OF_PLATDATA once before however was not
> > > entirely happy with the result as of yet. I guess WIP patches
> > > welcome (;-p).
> > >
> > > > Best regards,
> > > > Stefano
> > >
> > > Cheers
> > >
> > > Marcel

[U-Boot] [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support

[Stefano Babic]

Hi Marcel,

On 26/04/19 11:58, Marcel Ziswiler wrote:
> Hi Stefano
> 
> On Fri, 2019-04-26 at 11:46 +0200, Stefano Babic wrote:
>> On 26/04/19 11:20, Marcel Ziswiler wrote:
>>> Hi Igor
>>>
>>> Sorry, somehow I missed your comments below (;-p).
>>>
>>> I will send out a v4 (yes there already was a v3 BTW) shortly
>>> including
>>> the SPL resp. without SPL build fix.
>>
>> Fine - the series (without 5/5) is already applied on u-boot-imx.
>> Please
>> just send 5/5.
> 
> OK, strange. While I thought I just checked on git.denx.de I somehow
> missed that.

It does not depend on you, but on my changed work-flow. Because Tom does
not accept PR that does not pass Travis' build, I push currently first
to my github account (where I rebase often and I fix myself small
issues), and I push later to git.denx.de just after build passed. This
avoids that my rebasess make people unhappy because history is broken,
and tree on git.denx.de is always in a good state.

> Will just send 5/5 plus the SPL fix. Thanks!
> 

Regards,
Stefano


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [U-Boot,RESEND,10/10] imx: support i.MX8QM MEK board

[Marcel Ziswiler]

Hi Stefano

On Fri, 2019-04-26 at 09:37 +0000, sbabic at denx.de wrote:
> > Add i.MX8QM MEK board support.
> > Included a basic dts, enabled SPL FIT
> > Boot log as below:
> > U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30
> > +0800)
> > Normal Boot
> > Trying to boot from MMC2_2
> > U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
> > CPU:   NXP i.MX8QM RevB A53 at 142933 MHz
> > Model: Freescale i.MX8QM MEK
> > Board: iMX8QM MEK
> > Build: SCFW 9330215b
> > Boot:  SD1
> > DRAM:  6 GiB
> > MMC:   FSL_SDHC: 0, FSL_SDHC: 1
> > Loading Environment from MMC... *** Warning - bad CRC, using
> > default environment
> > In:    serial at 5a060000
> > Out:   serial at 5a060000
> > Err:   serial at 5a060000
> > Net:
> > Error: ethernet at 5b040000 address not set.
> > eth-1: ethernet at 5b040000
> > Hit any key to stop autoboot:  0
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> 
> Applied to u-boot-imx, master, thanks !

This one introduced a superfluous trailing line continuation in the
Makefile:

https://git.denx.de/?p=u-boot/u-boot-imx.git;a=commitdiff;h=0d331c035a091c1c1af4180b40bd234e3b87e80a#patch1

I will fix this and also make sure stuff is alphabetically sorted again
in my updated Colibri iMX8X introduction patch. OK?

> Best regards,
> Stefano Babic

Cheers

Marcel

[U-Boot] [U-Boot,RESEND,10/10] imx: support i.MX8QM MEK board

[Stefano Babic]

On 26/04/19 12:50, Marcel Ziswiler wrote:
> Hi Stefano
> 
> On Fri, 2019-04-26 at 09:37 +0000, sbabic at denx.de wrote:
>>> Add i.MX8QM MEK board support.
>>> Included a basic dts, enabled SPL FIT
>>> Boot log as below:
>>> U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30
>>> +0800)
>>> Normal Boot
>>> Trying to boot from MMC2_2
>>> U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
>>> CPU:   NXP i.MX8QM RevB A53 at 142933 MHz
>>> Model: Freescale i.MX8QM MEK
>>> Board: iMX8QM MEK
>>> Build: SCFW 9330215b
>>> Boot:  SD1
>>> DRAM:  6 GiB
>>> MMC:   FSL_SDHC: 0, FSL_SDHC: 1
>>> Loading Environment from MMC... *** Warning - bad CRC, using
>>> default environment
>>> In:    serial at 5a060000
>>> Out:   serial at 5a060000
>>> Err:   serial at 5a060000
>>> Net:
>>> Error: ethernet at 5b040000 address not set.
>>> eth-1: ethernet at 5b040000
>>> Hit any key to stop autoboot:  0
>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>
>> Applied to u-boot-imx, master, thanks !
> 
> This one introduced a superfluous trailing line continuation in the
> Makefile:
> 
> https://git.denx.de/?p=u-boot/u-boot-imx.git;a=commitdiff;h=0d331c035a091c1c1af4180b40bd234e3b87e80a#patch1
> 
> I will fix this and also make sure stuff is alphabetically sorted again
> in my updated Colibri iMX8X introduction patch. OK?

That's fine, thanks !


Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [REGRESSION] [PATCH] imx: add lowlevel init for ARM64

[Marcel Ziswiler]

Hi Peng and Stefano

Unfortunately, this seems to break Ethernet on Colibri iMX8X:

=> dhcp
"Error" handler, esr 0xbf000002
elr: 0000000080049664 lr : 000000008004964c (reloc)
elr: 00000000ffef6664 lr : 00000000ffef664c
x0 : 000000005b040288 x1 : 0000000000000001
x2 : 00000000fd6c5ff4 x3 : 0000000000000020
x4 : 00000000fd6c5ff0 x5 : 0000000000000020
x6 : 00000000ffef079c x7 : 00000000fd6f1600
x8 : 0000000000000044 x9 : 0000000000000008
x10: 00000000fd6d1620 x11: 00000000fd6d3a10
x12: 0000000000000000 x13: 0000000000000200
x14: 00000000fd6c62cc x15: 0000000000000002
x16: 0000000000002080 x17: 0000000000000000
x18: 00000000fd6cada8 x19: 00000000fd6d1160
x20: 0000000000000200 x21: 000000005b040300
x22: 00000000fd6f1000 x23: 00000000fd6cfdf0
x24: 00000000ffff8000 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 00000000fd6d15c0 x29: 00000000fd6c6030

Resetting CPU ...

resetting ...

Reverting commit 5955c6eeb453 ("imx: add lowlevel init for ARM64")
makes it work again.

Unfortunately, I don't have a MEK in my home office but will check
Ethernet operation there on Monday as well.

Anyway, does anybody know what exactly is going on?

Cheers

Marcel

On Mon, 2019-04-15 at 05:20 +0000, Peng Fan wrote:
> Sometimes we met SERROR, but only to catch it when Linux boots up.
> Let's enable catching in U-Boot to catch it ealier and ease debug.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/mach-imx/Makefile   |  2 +-
>  arch/arm/mach-imx/lowlevel.S | 22 ++++++++++++++++++++++
>  2 files changed, 23 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/mach-imx/lowlevel.S
> 
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index c3ed62aed6..37675d0558 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -204,7 +204,7 @@ endif
>  
>  targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-
> dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
>  
> -obj-$(CONFIG_ARM64) += sip.o
> +obj-$(CONFIG_ARM64) += lowlevel.o sip.o
>  
>  obj-$(CONFIG_MX5) += mx5/
>  obj-$(CONFIG_MX6) += mx6/
> diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-
> imx/lowlevel.S
> new file mode 100644
> index 0000000000..158fdb7d87
> --- /dev/null
> +++ b/arch/arm/mach-imx/lowlevel.S
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +#include <linux/linkage.h>
> +
> +ENTRY(lowlevel_init)
> +	mrs	x0, CurrentEL
> +	cmp	x0, #8
> +	b.eq	1f
> +	ret
> +1:
> +	msr daifclr, #4
> +
> +	/* set HCR_EL2.AMO to catch SERROR */
> +	mrs	x0, hcr_el2
> +	orr	x0, x0, #0x20
> +	msr	hcr_el2, x0
> +	isb
> +	ret
> +ENDPROC(lowlevel_init)
> -- 
> 2.16.4
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [REGRESSION] [PATCH] imx: 8qxp_mek: fix fdt_file and console

[Marcel Ziswiler]

Hi Peng and Stefano

On Mon, 2019-04-15 at 12:00 +0000, Peng Fan wrote:
> Fix fdt_file and console to boot upstream Linux Kernel.
> 
> Upstream linux use imx8qxp-mek.dtb, and pass lpuart32 to earlycon
> will not work for i.MX8QXP, only need to pass earlycon,
> check drivers/tty/serial/earlycon.c,
> " /* Just 'earlycon' is a valid param for devicetree and ACPI SPCR.
> */ "
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  include/configs/imx8qxp_mek.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/include/configs/imx8qxp_mek.h
> b/include/configs/imx8qxp_mek.h
> index 1cff18e05e..5c83505ff0 100644
> --- a/include/configs/imx8qxp_mek.h
> +++ b/include/configs/imx8qxp_mek.h
> @@ -65,11 +65,11 @@
>  	"script=boot.scr\0" \
>  	"image=Image\0" \
>  	"panel=NULL\0" \
> -	"console=ttyLP0,${baudrate}
> earlycon=lpuart32,0x5a060000,${baudrate}\0" \
> +	"console=ttyLP0,${baudrate} earlycon\0" \

I don't think using ${baudrate} in console= like that actually works.
At least for me this lead to the following:

root at colibri-imx8qxp:~# cat /proc/cmdline 
console=ttyLP3,${baudrate} earlycon,115200 root=PARTUUID=5e6e3605-02
rootwait mmcautodetect=yes

E.g. ${baudrate} is never actually evaluated unless one does an
explicit assignment aka setenv something something.

>  	"fdt_addr=0x83000000\0"			\
>  	"fdt_high=0xffffffffffffffff\0"		\
>  	"boot_fdt=try\0" \
> -	"fdt_file=fsl-imx8qxp-mek.dtb\0" \
> +	"fdt_file=imx8qxp-mek.dtb\0" \
>  	"initrd_addr=0x83800000\0"		\
>  	"initrd_high=0xffffffffffffffff\0" \
>  	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> -- 
> 2.16.4
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

Cheers

Marcel

[U-Boot] [REGRESSION] [PATCH] imx: add lowlevel init for ARM64

[Peng Fan]

Hi Marcel,

Please apply this patch, Joe has not pick it up.
https://patchwork.ozlabs.org/patch/1085432/

Stefano,

Would you pick it up?


> Subject: [REGRESSION] [PATCH] imx: add lowlevel init for ARM64
> 
> Hi Peng and Stefano
> 
> Unfortunately, this seems to break Ethernet on Colibri iMX8X:
> 
> => dhcp
> "Error" handler, esr 0xbf000002
> elr: 0000000080049664 lr : 000000008004964c (reloc)
> elr: 00000000ffef6664 lr : 00000000ffef664c
> x0 : 000000005b040288 x1 : 0000000000000001
> x2 : 00000000fd6c5ff4 x3 : 0000000000000020
> x4 : 00000000fd6c5ff0 x5 : 0000000000000020
> x6 : 00000000ffef079c x7 : 00000000fd6f1600
> x8 : 0000000000000044 x9 : 0000000000000008
> x10: 00000000fd6d1620 x11: 00000000fd6d3a10
> x12: 0000000000000000 x13: 0000000000000200
> x14: 00000000fd6c62cc x15: 0000000000000002
> x16: 0000000000002080 x17: 0000000000000000
> x18: 00000000fd6cada8 x19: 00000000fd6d1160
> x20: 0000000000000200 x21: 000000005b040300
> x22: 00000000fd6f1000 x23: 00000000fd6cfdf0
> x24: 00000000ffff8000 x25: 0000000000000000
> x26: 0000000000000000 x27: 0000000000000000
> x28: 00000000fd6d15c0 x29: 00000000fd6c6030
> 
> Resetting CPU ...
> 
> resetting ...
> 
> Reverting commit 5955c6eeb453 ("imx: add lowlevel init for ARM64") makes
> it work again.
> 
> Unfortunately, I don't have a MEK in my home office but will check Ethernet
> operation there on Monday as well.
> 
> Anyway, does anybody know what exactly is going on?

Regards,
Peng.

> 
> Cheers
> 
> Marcel
> 
> On Mon, 2019-04-15 at 05:20 +0000, Peng Fan wrote:
> > Sometimes we met SERROR, but only to catch it when Linux boots up.
> > Let's enable catching in U-Boot to catch it ealier and ease debug.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  arch/arm/mach-imx/Makefile   |  2 +-
> >  arch/arm/mach-imx/lowlevel.S | 22 ++++++++++++++++++++++
> >  2 files changed, 23 insertions(+), 1 deletion(-)  create mode 100644
> > arch/arm/mach-imx/lowlevel.S
> >
> > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> > index c3ed62aed6..37675d0558 100644
> > --- a/arch/arm/mach-imx/Makefile
> > +++ b/arch/arm/mach-imx/Makefile
> > @@ -204,7 +204,7 @@ endif
> >
> >  targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-
> > dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
> >
> > -obj-$(CONFIG_ARM64) += sip.o
> > +obj-$(CONFIG_ARM64) += lowlevel.o sip.o
> >
> >  obj-$(CONFIG_MX5) += mx5/
> >  obj-$(CONFIG_MX6) += mx6/
> > diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-
> > imx/lowlevel.S new file mode 100644 index 0000000000..158fdb7d87
> > --- /dev/null
> > +++ b/arch/arm/mach-imx/lowlevel.S
> > @@ -0,0 +1,22 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2019 NXP
> > + */
> > +
> > +#include <linux/linkage.h>
> > +
> > +ENTRY(lowlevel_init)
> > +	mrs	x0, CurrentEL
> > +	cmp	x0, #8
> > +	b.eq	1f
> > +	ret
> > +1:
> > +	msr daifclr, #4
> > +
> > +	/* set HCR_EL2.AMO to catch SERROR */
> > +	mrs	x0, hcr_el2
> > +	orr	x0, x0, #0x20
> > +	msr	hcr_el2, x0
> > +	isb
> > +	ret
> > +ENDPROC(lowlevel_init)
> > --
> > 2.16.4
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> >
> s.denx.de%2Flistinfo%2Fu-boot&amp;data=02%7C01%7Cpeng.fan%40nxp.co
> m%7C
> >
> d671eca9f1cc4d06a7d008d6ca7661b1%7C686ea1d3bc2b4c6fa92cd99c5c30
> 1635%7C
> >
> 0%7C0%7C636919007134459412&amp;sdata=R6xBpoVJHL7meQkRkBi1I8vg
> MgOTXlFEA
> > QfMePrDdSc%3D&amp;reserved=0

[U-Boot] [REGRESSION] [PATCH] imx: 8qxp_mek: fix fdt_file and console

[Peng Fan]

> Subject: [REGRESSION] [PATCH] imx: 8qxp_mek: fix fdt_file and console
> 
> Hi Peng and Stefano
> 
> On Mon, 2019-04-15 at 12:00 +0000, Peng Fan wrote:
> > Fix fdt_file and console to boot upstream Linux Kernel.
> >
> > Upstream linux use imx8qxp-mek.dtb, and pass lpuart32 to earlycon will
> > not work for i.MX8QXP, only need to pass earlycon, check
> > drivers/tty/serial/earlycon.c, " /* Just 'earlycon' is a valid param
> > for devicetree and ACPI SPCR.
> > */ "
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  include/configs/imx8qxp_mek.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/include/configs/imx8qxp_mek.h
> > b/include/configs/imx8qxp_mek.h index 1cff18e05e..5c83505ff0 100644
> > --- a/include/configs/imx8qxp_mek.h
> > +++ b/include/configs/imx8qxp_mek.h
> > @@ -65,11 +65,11 @@
> >  	"script=boot.scr\0" \
> >  	"image=Image\0" \
> >  	"panel=NULL\0" \
> > -	"console=ttyLP0,${baudrate}
> > earlycon=lpuart32,0x5a060000,${baudrate}\0" \
> > +	"console=ttyLP0,${baudrate} earlycon\0" \
> 
> I don't think using ${baudrate} in console= like that actually works.
> At least for me this lead to the following:

You mean include/env_default.h this not work?

Regards,
Peng.

> 
> root at colibri-imx8qxp:~# cat /proc/cmdline console=ttyLP3,${baudrate}
> earlycon,115200 root=PARTUUID=5e6e3605-02 rootwait
> mmcautodetect=yes
> 
> E.g. ${baudrate} is never actually evaluated unless one does an explicit
> assignment aka setenv something something.
> 
> >  	"fdt_addr=0x83000000\0"			\
> >  	"fdt_high=0xffffffffffffffff\0"		\
> >  	"boot_fdt=try\0" \
> > -	"fdt_file=fsl-imx8qxp-mek.dtb\0" \
> > +	"fdt_file=imx8qxp-mek.dtb\0" \
> >  	"initrd_addr=0x83800000\0"		\
> >  	"initrd_high=0xffffffffffffffff\0" \
> >  	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> > --
> > 2.16.4
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> >
> s.denx.de%2Flistinfo%2Fu-boot&amp;data=02%7C01%7Cpeng.fan%40nxp.co
> m%7C
> >
> 0e6a5db6025549efd94708d6ca76ec09%7C686ea1d3bc2b4c6fa92cd99c5c30
> 1635%7C
> >
> 0%7C0%7C636919009450074747&amp;sdata=g8pl8UzcwoFAlfZAHDOeBb1s4
> zcH%2BzJ
> > qFkGukoHAfnQ%3D&amp;reserved=0
> 
> Cheers
> 
> Marcel

[U-Boot] [REGRESSION] [PATCH] imx: add lowlevel init for ARM64

[Stefano Babic]

On 27/04/19 01:58, Peng Fan wrote:
> Hi Marcel,
> 
> Please apply this patch, Joe has not pick it up.
> https://patchwork.ozlabs.org/patch/1085432/
> 
> Stefano,
> 
> Would you pick it up?

It is acked by Joe, i assign the patch to me in patchwork and I pick it up.

Regards,
Stefano

> 
> 
>> Subject: [REGRESSION] [PATCH] imx: add lowlevel init for ARM64
>>
>> Hi Peng and Stefano
>>
>> Unfortunately, this seems to break Ethernet on Colibri iMX8X:
>>
>> => dhcp
>> "Error" handler, esr 0xbf000002
>> elr: 0000000080049664 lr : 000000008004964c (reloc)
>> elr: 00000000ffef6664 lr : 00000000ffef664c
>> x0 : 000000005b040288 x1 : 0000000000000001
>> x2 : 00000000fd6c5ff4 x3 : 0000000000000020
>> x4 : 00000000fd6c5ff0 x5 : 0000000000000020
>> x6 : 00000000ffef079c x7 : 00000000fd6f1600
>> x8 : 0000000000000044 x9 : 0000000000000008
>> x10: 00000000fd6d1620 x11: 00000000fd6d3a10
>> x12: 0000000000000000 x13: 0000000000000200
>> x14: 00000000fd6c62cc x15: 0000000000000002
>> x16: 0000000000002080 x17: 0000000000000000
>> x18: 00000000fd6cada8 x19: 00000000fd6d1160
>> x20: 0000000000000200 x21: 000000005b040300
>> x22: 00000000fd6f1000 x23: 00000000fd6cfdf0
>> x24: 00000000ffff8000 x25: 0000000000000000
>> x26: 0000000000000000 x27: 0000000000000000
>> x28: 00000000fd6d15c0 x29: 00000000fd6c6030
>>
>> Resetting CPU ...
>>
>> resetting ...
>>
>> Reverting commit 5955c6eeb453 ("imx: add lowlevel init for ARM64") makes
>> it work again.
>>
>> Unfortunately, I don't have a MEK in my home office but will check Ethernet
>> operation there on Monday as well.
>>
>> Anyway, does anybody know what exactly is going on?
> 
> Regards,
> Peng.
> 
>>
>> Cheers
>>
>> Marcel
>>
>> On Mon, 2019-04-15 at 05:20 +0000, Peng Fan wrote:
>>> Sometimes we met SERROR, but only to catch it when Linux boots up.
>>> Let's enable catching in U-Boot to catch it ealier and ease debug.
>>>
>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>> ---
>>>  arch/arm/mach-imx/Makefile   |  2 +-
>>>  arch/arm/mach-imx/lowlevel.S | 22 ++++++++++++++++++++++
>>>  2 files changed, 23 insertions(+), 1 deletion(-)  create mode 100644
>>> arch/arm/mach-imx/lowlevel.S
>>>
>>> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
>>> index c3ed62aed6..37675d0558 100644
>>> --- a/arch/arm/mach-imx/Makefile
>>> +++ b/arch/arm/mach-imx/Makefile
>>> @@ -204,7 +204,7 @@ endif
>>>
>>>  targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-
>>> dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
>>>
>>> -obj-$(CONFIG_ARM64) += sip.o
>>> +obj-$(CONFIG_ARM64) += lowlevel.o sip.o
>>>
>>>  obj-$(CONFIG_MX5) += mx5/
>>>  obj-$(CONFIG_MX6) += mx6/
>>> diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-
>>> imx/lowlevel.S new file mode 100644 index 0000000000..158fdb7d87
>>> --- /dev/null
>>> +++ b/arch/arm/mach-imx/lowlevel.S
>>> @@ -0,0 +1,22 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/*
>>> + * Copyright 2019 NXP
>>> + */
>>> +
>>> +#include <linux/linkage.h>
>>> +
>>> +ENTRY(lowlevel_init)
>>> +	mrs	x0, CurrentEL
>>> +	cmp	x0, #8
>>> +	b.eq	1f
>>> +	ret
>>> +1:
>>> +	msr daifclr, #4
>>> +
>>> +	/* set HCR_EL2.AMO to catch SERROR */
>>> +	mrs	x0, hcr_el2
>>> +	orr	x0, x0, #0x20
>>> +	msr	hcr_el2, x0
>>> +	isb
>>> +	ret
>>> +ENDPROC(lowlevel_init)
>>> --
>>> 2.16.4
>>>
>>> _______________________________________________
>>> U-Boot mailing list
>>> U-Boot at lists.denx.de
>>> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
>>>
>> s.denx.de%2Flistinfo%2Fu-boot&amp;data=02%7C01%7Cpeng.fan%40nxp.co
>> m%7C
>>>
>> d671eca9f1cc4d06a7d008d6ca7661b1%7C686ea1d3bc2b4c6fa92cd99c5c30
>> 1635%7C
>>>
>> 0%7C0%7C636919007134459412&amp;sdata=R6xBpoVJHL7meQkRkBi1I8vg
>> MgOTXlFEA
>>> QfMePrDdSc%3D&amp;reserved=0

[U-Boot] [REGRESSION] [PATCH] imx: add lowlevel init for ARM64

[Joe Hershberger]

> On Apr 28, 2019, at 12:52 PM, Stefano Babic <sbabic@denx.de> wrote:
> 
> 
> 
>> On 27/04/19 01:58, Peng Fan wrote:
>> Hi Marcel,
>> 
>> Please apply this patch, Joe has not pick it up.
>> https://patchwork.ozlabs.org/patch/1085432/
>> 
>> Stefano,
>> 
>> Would you pick it up?
> 
> It is acked by Joe, i assign the patch to me in patchwork and I pick it up.
> 
> Regards,
> Stefano
> 
>> 
>> 
>>> Subject: [REGRESSION] [PATCH] imx: add lowlevel init for ARM64
>>> 
>>> Hi Peng and Stefano
>>> 
>>> Unfortunately, this seems to break Ethernet on Colibri iMX8X:

Has this been addressed?

>>> 
>>> => dhcp
>>> "Error" handler, esr 0xbf000002
>>> elr: 0000000080049664 lr : 000000008004964c (reloc)
>>> elr: 00000000ffef6664 lr : 00000000ffef664c
>>> x0 : 000000005b040288 x1 : 0000000000000001
>>> x2 : 00000000fd6c5ff4 x3 : 0000000000000020
>>> x4 : 00000000fd6c5ff0 x5 : 0000000000000020
>>> x6 : 00000000ffef079c x7 : 00000000fd6f1600
>>> x8 : 0000000000000044 x9 : 0000000000000008
>>> x10: 00000000fd6d1620 x11: 00000000fd6d3a10
>>> x12: 0000000000000000 x13: 0000000000000200
>>> x14: 00000000fd6c62cc x15: 0000000000000002
>>> x16: 0000000000002080 x17: 0000000000000000
>>> x18: 00000000fd6cada8 x19: 00000000fd6d1160
>>> x20: 0000000000000200 x21: 000000005b040300
>>> x22: 00000000fd6f1000 x23: 00000000fd6cfdf0
>>> x24: 00000000ffff8000 x25: 0000000000000000
>>> x26: 0000000000000000 x27: 0000000000000000
>>> x28: 00000000fd6d15c0 x29: 00000000fd6c6030
>>> 
>>> Resetting CPU ...
>>> 
>>> resetting ...
>>> 
>>> Reverting commit 5955c6eeb453 ("imx: add lowlevel init for ARM64") makes
>>> it work again.
>>> 
>>> Unfortunately, I don't have a MEK in my home office but will check Ethernet
>>> operation there on Monday as well.
>>> 
>>> Anyway, does anybody know what exactly is going on?
>> 
>> Regards,
>> Peng.
>> 
>>> 
>>> Cheers
>>> 
>>> Marcel
>>> 
>>>> On Mon, 2019-04-15 at 05:20 +0000, Peng Fan wrote:
>>>> Sometimes we met SERROR, but only to catch it when Linux boots up.
>>>> Let's enable catching in U-Boot to catch it ealier and ease debug.
>>>> 
>>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>>> ---
>>>> arch/arm/mach-imx/Makefile   |  2 +-
>>>> arch/arm/mach-imx/lowlevel.S | 22 ++++++++++++++++++++++
>>>> 2 files changed, 23 insertions(+), 1 deletion(-)  create mode 100644
>>>> arch/arm/mach-imx/lowlevel.S
>>>> 
>>>> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
>>>> index c3ed62aed6..37675d0558 100644
>>>> --- a/arch/arm/mach-imx/Makefile
>>>> +++ b/arch/arm/mach-imx/Makefile
>>>> @@ -204,7 +204,7 @@ endif
>>>> 
>>>> targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-
>>>> dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
>>>> 
>>>> -obj-$(CONFIG_ARM64) += sip.o
>>>> +obj-$(CONFIG_ARM64) += lowlevel.o sip.o
>>>> 
>>>> obj-$(CONFIG_MX5) += mx5/
>>>> obj-$(CONFIG_MX6) += mx6/
>>>> diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-
>>>> imx/lowlevel.S new file mode 100644 index 0000000000..158fdb7d87
>>>> --- /dev/null
>>>> +++ b/arch/arm/mach-imx/lowlevel.S
>>>> @@ -0,0 +1,22 @@
>>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>>> +/*
>>>> + * Copyright 2019 NXP
>>>> + */
>>>> +
>>>> +#include <linux/linkage.h>
>>>> +
>>>> +ENTRY(lowlevel_init)
>>>> +    mrs    x0, CurrentEL
>>>> +    cmp    x0, #8
>>>> +    b.eq    1f
>>>> +    ret
>>>> +1:
>>>> +    msr daifclr, #4
>>>> +
>>>> +    /* set HCR_EL2.AMO to catch SERROR */
>>>> +    mrs    x0, hcr_el2
>>>> +    orr    x0, x0, #0x20
>>>> +    msr    hcr_el2, x0
>>>> +    isb
>>>> +    ret
>>>> +ENDPROC(lowlevel_init)
>>>> --
>>>> 2.16.4
>>>> 
>>>> _______________________________________________
>>>> U-Boot mailing list
>>>> U-Boot at lists.denx.de
>>>> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
>>>> 
>>> s.denx.de%2Flistinfo%2Fu-boot&amp;data=02%7C01%7Cpeng.fan%40nxp.co
>>> m%7C
>>>> 
>>> d671eca9f1cc4d06a7d008d6ca7661b1%7C686ea1d3bc2b4c6fa92cd99c5c30
>>> 1635%7C
>>>> 
>>> 0%7C0%7C636919007134459412&amp;sdata=R6xBpoVJHL7meQkRkBi1I8vg
>>> MgOTXlFEA
>>>> QfMePrDdSc%3D&amp;reserved=0
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [REGRESSION] [PATCH] imx: add lowlevel init for ARM64

[Marcel Ziswiler]

On Sun, 2019-04-28 at 14:24 -0400, Joe Hershberger wrote:
> > On Apr 28, 2019, at 12:52 PM, Stefano Babic <sbabic@denx.de> wrote:
> > 
> > 
> > 
> > > On 27/04/19 01:58, Peng Fan wrote:
> > > Hi Marcel,
> > > 
> > > Please apply this patch, Joe has not pick it up.
> > > https://patchwork.ozlabs.org/patch/1085432/
> > > 
> > > Stefano,
> > > 
> > > Would you pick it up?
> > 
> > It is acked by Joe, i assign the patch to me in patchwork and I
> > pick it up.
> > 
> > Regards,
> > Stefano
> > 
> > > 
> > > > Subject: [REGRESSION] [PATCH] imx: add lowlevel init for ARM64
> > > > 
> > > > Hi Peng and Stefano
> > > > 
> > > > Unfortunately, this seems to break Ethernet on Colibri iMX8X:
> 
> Has this been addressed?

Yes, sorry. The following patch as suggested by Peng does fix it:

https://patchwork.ozlabs.org/patch/1085432/

Thanks!

> > > > => dhcp
> > > > "Error" handler, esr 0xbf000002
> > > > elr: 0000000080049664 lr : 000000008004964c (reloc)
> > > > elr: 00000000ffef6664 lr : 00000000ffef664c
> > > > x0 : 000000005b040288 x1 : 0000000000000001
> > > > x2 : 00000000fd6c5ff4 x3 : 0000000000000020
> > > > x4 : 00000000fd6c5ff0 x5 : 0000000000000020
> > > > x6 : 00000000ffef079c x7 : 00000000fd6f1600
> > > > x8 : 0000000000000044 x9 : 0000000000000008
> > > > x10: 00000000fd6d1620 x11: 00000000fd6d3a10
> > > > x12: 0000000000000000 x13: 0000000000000200
> > > > x14: 00000000fd6c62cc x15: 0000000000000002
> > > > x16: 0000000000002080 x17: 0000000000000000
> > > > x18: 00000000fd6cada8 x19: 00000000fd6d1160
> > > > x20: 0000000000000200 x21: 000000005b040300
> > > > x22: 00000000fd6f1000 x23: 00000000fd6cfdf0
> > > > x24: 00000000ffff8000 x25: 0000000000000000
> > > > x26: 0000000000000000 x27: 0000000000000000
> > > > x28: 00000000fd6d15c0 x29: 00000000fd6c6030
> > > > 
> > > > Resetting CPU ...
> > > > 
> > > > resetting ...
> > > > 
> > > > Reverting commit 5955c6eeb453 ("imx: add lowlevel init for
> > > > ARM64") makes
> > > > it work again.
> > > > 
> > > > Unfortunately, I don't have a MEK in my home office but will
> > > > check Ethernet
> > > > operation there on Monday as well.
> > > > 
> > > > Anyway, does anybody know what exactly is going on?
> > > 
> > > Regards,
> > > Peng.
> > > 
> > > > Cheers
> > > > 
> > > > Marcel
> > > > 
> > > > > On Mon, 2019-04-15 at 05:20 +0000, Peng Fan wrote:
> > > > > Sometimes we met SERROR, but only to catch it when Linux
> > > > > boots up.
> > > > > Let's enable catching in U-Boot to catch it ealier and ease
> > > > > debug.
> > > > > 
> > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > ---
> > > > > arch/arm/mach-imx/Makefile   |  2 +-
> > > > > arch/arm/mach-imx/lowlevel.S | 22 ++++++++++++++++++++++
> > > > > 2 files changed, 23 insertions(+), 1 deletion(-)  create mode
> > > > > 100644
> > > > > arch/arm/mach-imx/lowlevel.S
> > > > > 
> > > > > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-
> > > > > imx/Makefile
> > > > > index c3ed62aed6..37675d0558 100644
> > > > > --- a/arch/arm/mach-imx/Makefile
> > > > > +++ b/arch/arm/mach-imx/Makefile
> > > > > @@ -204,7 +204,7 @@ endif
> > > > > 
> > > > > targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-
> > > > > boot-
> > > > > dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
> > > > > 
> > > > > -obj-$(CONFIG_ARM64) += sip.o
> > > > > +obj-$(CONFIG_ARM64) += lowlevel.o sip.o
> > > > > 
> > > > > obj-$(CONFIG_MX5) += mx5/
> > > > > obj-$(CONFIG_MX6) += mx6/
> > > > > diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-
> > > > > imx/lowlevel.S new file mode 100644 index
> > > > > 0000000000..158fdb7d87
> > > > > --- /dev/null
> > > > > +++ b/arch/arm/mach-imx/lowlevel.S
> > > > > @@ -0,0 +1,22 @@
> > > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > > +/*
> > > > > + * Copyright 2019 NXP
> > > > > + */
> > > > > +
> > > > > +#include <linux/linkage.h>
> > > > > +
> > > > > +ENTRY(lowlevel_init)
> > > > > +    mrs    x0, CurrentEL
> > > > > +    cmp    x0, #8
> > > > > +    b.eq    1f
> > > > > +    ret
> > > > > +1:
> > > > > +    msr daifclr, #4
> > > > > +
> > > > > +    /* set HCR_EL2.AMO to catch SERROR */
> > > > > +    mrs    x0, hcr_el2
> > > > > +    orr    x0, x0, #0x20
> > > > > +    msr    hcr_el2, x0
> > > > > +    isb
> > > > > +    ret
> > > > > +ENDPROC(lowlevel_init)
> > > > > --
> > > > > 2.16.4
> > > > > 
> > > > > _______________________________________________
> > > > > U-Boot mailing list
> > > > > U-Boot at lists.denx.de
> > > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > > > > 
> > > > s.denx.de%2Flistinfo%2Fu-
> > > > boot&amp;data=02%7C01%7Cpeng.fan%40nxp.co
> > > > m%7C
> > > > d671eca9f1cc4d06a7d008d6ca7661b1%7C686ea1d3bc2b4c6fa92cd99c5c30
> > > > 1635%7C
> > > > 0%7C0%7C636919007134459412&amp;sdata=R6xBpoVJHL7meQkRkBi1I8vg
> > > > MgOTXlFEA
> > > > > QfMePrDdSc%3D&amp;reserved=0
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] ARM: imx: apalis_imx6: Drop ad-hoc SATA binding

[Marek Vasut]

Drop the ad-hoc AHCI binding code, this is superseded by
CONFIG_DWC_AHSATA_AHCI=y resp. drivers/ata/dwc_ahsata.c

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Stefan Agner <stefan.agner@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 board/toradex/apalis_imx6/apalis_imx6.c | 49 -------------------------
 1 file changed, 49 deletions(-)

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 3e59185438..b502d4ef13 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -1131,52 +1131,3 @@ U_BOOT_DEVICE(mxc_serial) = {
 	.name = "serial_mxc",
 	.platdata = &mxc_serial_plat,
 };
-
-#if CONFIG_IS_ENABLED(AHCI)
-static int sata_imx_probe(struct udevice *dev)
-{
-	int i, err;
-
-	for (i = 0; i < APALIS_IMX6_SATA_INIT_RETRIES; i++) {
-		err = setup_sata();
-		if (err) {
-			printf("SATA setup failed: %d\n", err);
-			return err;
-		}
-
-		udelay(100);
-
-		err = dwc_ahsata_probe(dev);
-		if (!err)
-			break;
-
-		/* There is no device on the SATA port */
-		if (sata_dm_port_status(0, 0) == 0)
-			break;
-
-		/* There's a device, but link not established. Retry */
-		device_remove(dev, DM_REMOVE_NORMAL);
-	}
-
-	return 0;
-}
-
-struct ahci_ops sata_imx_ops = {
-	.port_status = dwc_ahsata_port_status,
-	.reset	= dwc_ahsata_bus_reset,
-	.scan	= dwc_ahsata_scan,
-};
-
-static const struct udevice_id sata_imx_ids[] = {
-	{ .compatible = "fsl,imx6q-ahci" },
-	{ }
-};
-
-U_BOOT_DRIVER(sata_imx) = {
-	.name		= "dwc_ahci",
-	.id		= UCLASS_AHCI,
-	.of_match	= sata_imx_ids,
-	.ops		= &sata_imx_ops,
-	.probe		= sata_imx_probe,
-};
-#endif /* AHCI */
-- 
2.20.1

[U-Boot] [PATCH] ARM: imx: apalis_imx6: Drop ad-hoc SATA binding

[Marcel Ziswiler]

On Sun, 2019-05-12 at 22:43 +0200, Marek Vasut wrote:
> Drop the ad-hoc AHCI binding code, this is superseded by
> CONFIG_DWC_AHSATA_AHCI=y resp. drivers/ata/dwc_ahsata.c
> 
> Signed-off-by: Marek Vasut <marex@denx.de>

Works fine, thanks!

Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Cc: Max Krummenacher <max.krummenacher@toradex.com>
> Cc: Stefan Agner <stefan.agner@toradex.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
>  board/toradex/apalis_imx6/apalis_imx6.c | 49 ---------------------
> ----
>  1 file changed, 49 deletions(-)
> 
> diff --git a/board/toradex/apalis_imx6/apalis_imx6.c
> b/board/toradex/apalis_imx6/apalis_imx6.c
> index 3e59185438..b502d4ef13 100644
> --- a/board/toradex/apalis_imx6/apalis_imx6.c
> +++ b/board/toradex/apalis_imx6/apalis_imx6.c
> @@ -1131,52 +1131,3 @@ U_BOOT_DEVICE(mxc_serial) = {
>  	.name = "serial_mxc",
>  	.platdata = &mxc_serial_plat,
>  };
> -
> -#if CONFIG_IS_ENABLED(AHCI)
> -static int sata_imx_probe(struct udevice *dev)
> -{
> -	int i, err;
> -
> -	for (i = 0; i < APALIS_IMX6_SATA_INIT_RETRIES; i++) {
> -		err = setup_sata();
> -		if (err) {
> -			printf("SATA setup failed: %d\n", err);
> -			return err;
> -		}
> -
> -		udelay(100);
> -
> -		err = dwc_ahsata_probe(dev);
> -		if (!err)
> -			break;
> -
> -		/* There is no device on the SATA port */
> -		if (sata_dm_port_status(0, 0) == 0)
> -			break;
> -
> -		/* There's a device, but link not established. Retry */
> -		device_remove(dev, DM_REMOVE_NORMAL);
> -	}
> -
> -	return 0;
> -}
> -
> -struct ahci_ops sata_imx_ops = {
> -	.port_status = dwc_ahsata_port_status,
> -	.reset	= dwc_ahsata_bus_reset,
> -	.scan	= dwc_ahsata_scan,
> -};
> -
> -static const struct udevice_id sata_imx_ids[] = {
> -	{ .compatible = "fsl,imx6q-ahci" },
> -	{ }
> -};
> -
> -U_BOOT_DRIVER(sata_imx) = {
> -	.name		= "dwc_ahci",
> -	.id		= UCLASS_AHCI,
> -	.of_match	= sata_imx_ids,
> -	.ops		= &sata_imx_ops,
> -	.probe		= sata_imx_probe,
> -};
> -#endif /* AHCI */

[U-Boot] [PATCH] ARM: imx: apalis_imx6: Drop ad-hoc SATA binding <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> <mailto:u-boot-request@lists.denx.de?subject=subscribe>

[sbabic at denx.de]

> Drop the ad-hoc AHCI binding code, this is superseded by
> CONFIG_DWC_AHSATA_AHCI=y resp. drivers/ata/dwc_ahsata.c
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Cc: Max Krummenacher <max.krummenacher@toradex.com>
> Cc: Stefan Agner <stefan.agner@toradex.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 09/17] mx6sabresd: convert to DM_VIDEO

[Fabio Estevam]

Hi Anatolij,

On Mon, Mar 18, 2019 at 7:36 PM Anatolij Gustschin <agust@denx.de> wrote:
>
> Enable DM_VIDEO in defconfig.
>
> Signed-off-by: Anatolij Gustschin <agust@denx.de>
> ---
>  configs/mx6sabresd_defconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
> index ea34217e1c..825218c0d6 100644
> --- a/configs/mx6sabresd_defconfig
> +++ b/configs/mx6sabresd_defconfig
> @@ -93,6 +93,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
>  CONFIG_CI_UDC=y
>  CONFIG_USB_HOST_ETHER=y
>  CONFIG_USB_ETHER_ASIX=y
> -CONFIG_VIDEO=y
> +CONFIG_DM_VIDEO=y

I am running the latest tree from Stefano and I do not have LVDS
output after this patch.

If I revert it, then LVDS output is normal again.

Any ideas?

Thanks

[U-Boot] [PATCH 09/17] mx6sabresd: convert to DM_VIDEO

[Anatolij Gustschin]

Hi Fabio,

On Mon, 16 Sep 2019 15:18:34 -0300
Fabio Estevam festevam at gmail.com wrote:
...
> > -CONFIG_VIDEO=y
> > +CONFIG_DM_VIDEO=y  
> 
> I am running the latest tree from Stefano and I do not have LVDS
> output after this patch.
> 
> If I revert it, then LVDS output is normal again.
> 
> Any ideas?

Most probably this is because there was no user of the video
device when booting and therefore the video driver was not
probed/bound. Please try do display some bitmap with bmp
command or try to switch to the video console by command
"setenv stdout vidconsole0". Then, the video device will be
probed and you should see the LVDS output.

--
Anatolij

[U-Boot] [PATCH 09/17] mx6sabresd: convert to DM_VIDEO

[Anatolij Gustschin]

Hi Fabio,

On Mon, 16 Sep 2019 21:21:38 +0200
Anatolij Gustschin agust at denx.de wrote:

>Hi Fabio,
>
>On Mon, 16 Sep 2019 15:18:34 -0300
>Fabio Estevam festevam at gmail.com wrote:
>...
>> > -CONFIG_VIDEO=y
>> > +CONFIG_DM_VIDEO=y    
>> 
>> I am running the latest tree from Stefano and I do not have LVDS
>> output after this patch.
>> 
>> If I revert it, then LVDS output is normal again.
>> 
>> Any ideas?  
>
>Most probably this is because there was no user of the video
>device when booting and therefore the video driver was not
>probed/bound. Please try do display some bitmap with bmp
>command or try to switch to the video console by command
>"setenv stdout vidconsole0". Then, the video device will be
>probed and you should see the LVDS output.

There is an example how boards can enforce using video device
when booting, e.g. for displaying splash image. Please see commit
f0be8ff45fb8 (ARM: imx: m53menlo: Convert to DM VIDEO).

I'm not happy that it requires to extend the board code for this
and would prefer if it could be in common code. But this is what
we have now.

--
Anatolij

[U-Boot] [PATCH 09/17] mx6sabresd: convert to DM_VIDEO

[Fabio Estevam]

Hi Anatolij,

On Mon, Sep 16, 2019 at 4:21 PM Anatolij Gustschin <agust@denx.de> wrote:

> Most probably this is because there was no user of the video
> device when booting and therefore the video driver was not
> probed/bound. Please try do display some bitmap with bmp
> command or try to switch to the video console by command
> "setenv stdout vidconsole0". Then, the video device will be
> probed and you should see the LVDS output.

Here is what I tried:

=> setenv stdout vidconsole0
## Error inserting "stdout" variable, errno=22

Then I see garbage on the LVDS panel.

Any ideas as to why setting "stdout" failed?

Thanks

[U-Boot] [PATCH 09/17] mx6sabresd: convert to DM_VIDEO

[Anatolij Gustschin]

Hi Fabio,

On Tue, 17 Sep 2019 09:32:37 -0300
Fabio Estevam festevam at gmail.com wrote:

> Hi Anatolij,
> 
> On Mon, Sep 16, 2019 at 4:21 PM Anatolij Gustschin <agust@denx.de> wrote:
> 
> > Most probably this is because there was no user of the video
> > device when booting and therefore the video driver was not
> > probed/bound. Please try do display some bitmap with bmp
> > command or try to switch to the video console by command
> > "setenv stdout vidconsole0". Then, the video device will be
> > probed and you should see the LVDS output.  
> 
> Here is what I tried:
> 
> => setenv stdout vidconsole0  
> ## Error inserting "stdout" variable, errno=22
> 
> Then I see garbage on the LVDS panel.
> 
> Any ideas as to why setting "stdout" failed?

Does "setenv stdout vidconsole" work? I think I've suggested
wrong command, sorry. "vidconsole0" is the driver instance name
for the first video console, "vidconsole" is the correct name
for console device on framebuffer.

--
Anatolij