From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E59FC43381 for ; Mon, 18 Feb 2019 15:56:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D53E52184A for ; Mon, 18 Feb 2019 15:56:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388043AbfBRP4Q (ORCPT ); Mon, 18 Feb 2019 10:56:16 -0500 Received: from foss.arm.com ([217.140.101.70]:33598 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387848AbfBRP4O (ORCPT ); Mon, 18 Feb 2019 10:56:14 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0FD2180D; Mon, 18 Feb 2019 07:56:14 -0800 (PST) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 80AE93F675; Mon, 18 Feb 2019 07:56:12 -0800 (PST) Date: Mon, 18 Feb 2019 15:56:07 +0000 From: Will Deacon To: Palmer Dabbelt Cc: Arnd Bergmann , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, andrew.murray@arm.com, catalin.marinas@arm.com, linux-riscv@lists.infradead.org, aou@eecs.berkeley.edu Subject: Re: [PATCH 1/2] asm-generic/io: Pass result on inX() accessor to __io_par() Message-ID: <20190218155607.GA16713@fuggles.cambridge.arm.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Feb 13, 2019 at 01:57:50PM -0800, Palmer Dabbelt wrote: > On Wed, 13 Feb 2019 12:59:28 PST (-0800), Arnd Bergmann wrote: > > On Wed, Feb 13, 2019 at 6:46 PM Will Deacon wrote: > > > > > On Tue, Feb 12, 2019 at 12:55:17PM +0100, Arnd Bergmann wrote: > > > > > > > For all I can see, this should not conflict with the usage of the > > > > same macros on RISC-V, though it does make add a significant > > > > difference, so I'd like to see an Ack from the RISC-V folks as > > > > well (added to Cc), or possibly a change to arch/riscv/include/asm/io.h > > > > to do a corresponding change. > > Thanks, the original patches didn't make it through my filters. > > > > There's already a comment in that header which says that the accesses are > > > ordered wrt timer reads, so I don't think anything needs to change there. > > > For consistency with the macro arguments, I could augment their __io_par to > > > take the read value as an unused argument, if that's what you mean? > > FWIW, we don't really have a way to mandate this in the ISA yet as there's > no formal model for either CSR orderings or the IO memory space. Ah, so you may end up needing the dependency trick too, depending on where you land with the ISA. > > Yes, that's what I meant, I should have been clearer there. > > That sounds reasonable to me. It looks like we can also go ahead and delete > a bunch of arch/riscv/include/asm/io.h now that this stuff is in > asm-generic, which would cause us to actually start using these things. I > didn't know this had all been moved to asm-generic otherwise I would have > cleaned this up earlier. > > I think this should do it, but this does bring up a bit of an issue: the > RISC-V versions of reads and friends put barriers outside the loop, while > the asm-generic version don't. What are these actually supposed to do? You're referring to the string accessors (e.g. insb() and readsw()), right? arm and arm64 don't provide barriers here either, and I don't think they should have to given that these routines are usually used to poll data register-based FIFOs and therefore don't need to provide ordering guarantees against DMA operations. However, this is woefully undocumented and I shall try to address this in the next version of my memory-barriers.txt patch relating to this area [1]. > Either way that resolves, feel free to consider something like > > diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h > index b269451e7e85..378975f180a7 100644 > --- a/arch/riscv/include/asm/io.h > +++ b/arch/riscv/include/asm/io.h > @@ -198,20 +198,20 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) > * writes. > */ > #define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory"); > -#define __io_par() __asm__ __volatile__ ("fence i,ior" : : : "memory"); > +#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory"); > #define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); > #define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); > > -#define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) > -#define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) > -#define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) > +#define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) > +#define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) > +#define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) > > #define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) > #define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) > #define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) > > #ifdef CONFIG_64BIT > -#define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(); __v; }) > +#define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; }) > #define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); }) > #endif > > @@ -261,9 +261,9 @@ __io_reads_ins(reads, u32, l, __io_br(), __io_ar()) > #define readsw(addr, buffer, count) __readsw(addr, buffer, count) > #define readsl(addr, buffer, count) __readsl(addr, buffer, count) > > -__io_reads_ins(ins, u8, b, __io_pbr(), __io_par()) > -__io_reads_ins(ins, u16, w, __io_pbr(), __io_par()) > -__io_reads_ins(ins, u32, l, __io_pbr(), __io_par()) > +__io_reads_ins(ins, u8, b, __io_pbr(), __io_par(addr)) > +__io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr)) > +__io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr)) > #define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count) > #define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count) > #define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count) > > as > > Revewied-by: Palmer Dabbelt > > when included along with the other diff. That way we can at least keep the > macro signatures matching, the cleanup can come later... Thanks, Palmer! I'll send a v2 of this patch, updated to fix up insq() as well as the readX() macros too, since they're likely to suffer the exact same issues as inX() in this regard. Will [1] https://lkml.org/lkml/2019/2/11/1803 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21C6EC4360F for ; Mon, 18 Feb 2019 15:56:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C263F2084D for ; Mon, 18 Feb 2019 15:56:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="VGdzCz4z" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C263F2084D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cdWrjxKMkRxoqJUX+W76zKkDnUlNY2YP9FkPmjb2jH4=; b=VGdzCz4zuDrekX HDidSrGj8/MiH15EPOfvhCQ5dHGTXdDbPmFj1YD3jc80Y1x7BMlGVTl6+EioGDfIH/j5SW9GnqYrx jFdvIUgUgVrVXkgXkIkanXXevBlW0T4jWcfeIigi5p3Z6aIevIfonI+cY0D6faFFcrFCxQmfsg0cR cFO1zNTYmQlQ6opPY5QbaQnQhw6YbPr6SMYrwlUD/KNsI6mM/O4g4NrFmT2wdeQhGQMIDZlvIQRU6 o6VU77jXKOBD8tXLUEtjrOX3bNTuad8O0B1rvzq8wwYjN2X94RC134dI75U9JH/XtVP95RWGxeGkt gpMZxbLsYJae8iRnmPzQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gvlHF-0000f6-Uz; Mon, 18 Feb 2019 15:56:17 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gvlHC-0000ee-Tu for linux-riscv@lists.infradead.org; Mon, 18 Feb 2019 15:56:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0FD2180D; Mon, 18 Feb 2019 07:56:14 -0800 (PST) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 80AE93F675; Mon, 18 Feb 2019 07:56:12 -0800 (PST) Date: Mon, 18 Feb 2019 15:56:07 +0000 From: Will Deacon To: Palmer Dabbelt Subject: Re: [PATCH 1/2] asm-generic/io: Pass result on inX() accessor to __io_par() Message-ID: <20190218155607.GA16713@fuggles.cambridge.arm.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190218_075614_971971_781739E2 X-CRM114-Status: GOOD ( 28.37 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, aou@eecs.berkeley.edu, Arnd Bergmann , catalin.marinas@arm.com, linux-kernel@vger.kernel.org, andrew.murray@arm.com, linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Feb 13, 2019 at 01:57:50PM -0800, Palmer Dabbelt wrote: > On Wed, 13 Feb 2019 12:59:28 PST (-0800), Arnd Bergmann wrote: > > On Wed, Feb 13, 2019 at 6:46 PM Will Deacon wrote: > > > > > On Tue, Feb 12, 2019 at 12:55:17PM +0100, Arnd Bergmann wrote: > > > > > > > For all I can see, this should not conflict with the usage of the > > > > same macros on RISC-V, though it does make add a significant > > > > difference, so I'd like to see an Ack from the RISC-V folks as > > > > well (added to Cc), or possibly a change to arch/riscv/include/asm/io.h > > > > to do a corresponding change. > > Thanks, the original patches didn't make it through my filters. > > > > There's already a comment in that header which says that the accesses are > > > ordered wrt timer reads, so I don't think anything needs to change there. > > > For consistency with the macro arguments, I could augment their __io_par to > > > take the read value as an unused argument, if that's what you mean? > > FWIW, we don't really have a way to mandate this in the ISA yet as there's > no formal model for either CSR orderings or the IO memory space. Ah, so you may end up needing the dependency trick too, depending on where you land with the ISA. > > Yes, that's what I meant, I should have been clearer there. > > That sounds reasonable to me. It looks like we can also go ahead and delete > a bunch of arch/riscv/include/asm/io.h now that this stuff is in > asm-generic, which would cause us to actually start using these things. I > didn't know this had all been moved to asm-generic otherwise I would have > cleaned this up earlier. > > I think this should do it, but this does bring up a bit of an issue: the > RISC-V versions of reads and friends put barriers outside the loop, while > the asm-generic version don't. What are these actually supposed to do? You're referring to the string accessors (e.g. insb() and readsw()), right? arm and arm64 don't provide barriers here either, and I don't think they should have to given that these routines are usually used to poll data register-based FIFOs and therefore don't need to provide ordering guarantees against DMA operations. However, this is woefully undocumented and I shall try to address this in the next version of my memory-barriers.txt patch relating to this area [1]. > Either way that resolves, feel free to consider something like > > diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h > index b269451e7e85..378975f180a7 100644 > --- a/arch/riscv/include/asm/io.h > +++ b/arch/riscv/include/asm/io.h > @@ -198,20 +198,20 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) > * writes. > */ > #define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory"); > -#define __io_par() __asm__ __volatile__ ("fence i,ior" : : : "memory"); > +#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory"); > #define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); > #define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); > > -#define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) > -#define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) > -#define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) > +#define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) > +#define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) > +#define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) > > #define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) > #define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) > #define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) > > #ifdef CONFIG_64BIT > -#define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(); __v; }) > +#define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; }) > #define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); }) > #endif > > @@ -261,9 +261,9 @@ __io_reads_ins(reads, u32, l, __io_br(), __io_ar()) > #define readsw(addr, buffer, count) __readsw(addr, buffer, count) > #define readsl(addr, buffer, count) __readsl(addr, buffer, count) > > -__io_reads_ins(ins, u8, b, __io_pbr(), __io_par()) > -__io_reads_ins(ins, u16, w, __io_pbr(), __io_par()) > -__io_reads_ins(ins, u32, l, __io_pbr(), __io_par()) > +__io_reads_ins(ins, u8, b, __io_pbr(), __io_par(addr)) > +__io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr)) > +__io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr)) > #define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count) > #define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count) > #define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count) > > as > > Revewied-by: Palmer Dabbelt > > when included along with the other diff. That way we can at least keep the > macro signatures matching, the cleanup can come later... Thanks, Palmer! I'll send a v2 of this patch, updated to fix up insq() as well as the readX() macros too, since they're likely to suffer the exact same issues as inX() in this regard. Will [1] https://lkml.org/lkml/2019/2/11/1803 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv