From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67988C43381 for ; Wed, 20 Feb 2019 01:01:16 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C5AE42086C for ; Wed, 20 Feb 2019 01:01:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=ozlabs.org header.i=@ozlabs.org header.b="h+2qtoNj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C5AE42086C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ozlabs.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 443znP58kkzDqL2 for ; Wed, 20 Feb 2019 12:01:13 +1100 (AEDT) Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 443zlK6WM5zDq5v for ; Wed, 20 Feb 2019 11:59:25 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=ozlabs.org Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.b="h+2qtoNj"; dkim-atps=neutral Received: by ozlabs.org (Postfix, from userid 1003) id 443zlK4CY4z9sDr; Wed, 20 Feb 2019 11:59:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1550624365; bh=ZIMGo/ib2gf/8xFm6867M2UBD+22z3Ri/up2QbZ9Yi0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=h+2qtoNjhH1XBu460a9b2at7aJDDa2hS+80yA5YFEniLIA9CPbnIKh2NBqsgcR9Jy tJBVlY2Lj1PNsN4OjSyiyb1uB8d5ZwfljFOrcy/ncKfupTYaqi4DdiVEBmu5l/KmHL PBT+B0s6SkmYJF9PHPfKAEdqSCXuJfjjU5Sy9f6Ldwliml6Ni3QPb3YZ30NxcE9RRF xxQNFz+yq2tR1mkL7KGk2wwf5IaZvv3NRHXZtmt8ABnJvj4FWghv/lvy8cjsdU3NXf 77MnVaAHsn+Qmz0fxv4Y+2nHZMt9xPjqor3DnA2mRKWVQ1etmS2lS9MEHFfNLzg8rn xGVKmneQqVl7A== Date: Wed, 20 Feb 2019 11:59:22 +1100 From: Paul Mackerras To: Nicholas Piggin Subject: Re: [PATCH v6] powerpc/64s: reimplement book3s idle code in C Message-ID: <20190220005922.GC5353@blackberry> References: <20181013120409.1993-1-npiggin@gmail.com> <20190217230640.GA922@blackberry> <1550549470.22tqiqz5em.astroid@bobo.none> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1550549470.22tqiqz5em.astroid@bobo.none> User-Agent: Mutt/1.5.24 (2015-08-30) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Gautham R . Shenoy" , Mahesh Jagannath Salgaonkar , kvm-ppc@vger.kernel.org, "Aneesh Kumar K.V" , linuxppc-dev@lists.ozlabs.org, Akshay Adiga Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue, Feb 19, 2019 at 02:13:51PM +1000, Nicholas Piggin wrote: > Paul Mackerras's on February 18, 2019 9:06 am: > > On Sat, Oct 13, 2018 at 10:04:09PM +1000, Nicholas Piggin wrote: > >> Reimplement Book3S idle code in C, moving POWER7/8/9 implementation > >> speific HV idle code to the powernv platform code. > >> > > > > [...] > > > >> @@ -2760,21 +2744,47 @@ BEGIN_FTR_SECTION > >> li r4, LPCR_PECE_HVEE@higher > >> sldi r4, r4, 32 > >> or r5, r5, r4 > >> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) > >> +FTR_SECTION_ELSE > >> + li r3, PNV_THREAD_NAP > >> +ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) > >> mtspr SPRN_LPCR,r5 > >> isync > >> - li r0, 0 > >> - std r0, HSTATE_SCRATCH0(r13) > >> - ptesync > >> - ld r0, HSTATE_SCRATCH0(r13) > >> -1: cmpd r0, r0 > >> - bne 1b > >> + > >> + mr r0, r1 > >> + ld r1, PACAEMERGSP(r13) > >> + subi r1, r1, STACK_FRAME_OVERHEAD > >> + std r0, 0(r1) > >> + ld r0, PACAR1(r13) > >> + std r0, 8(r1) > > > > This bit seems wrong to me. If this is a secondary thread on POWER8, > > we were already on the emergency stack, and now we've reset r1 back to > > the top of the emergency stack and we're overwriting it. > > I'll have to find some time to take another look at this stuff. The KVM > stuff was a bit hasty. > > > I wonder why you didn't see secondary threads going off into lala land > > in your tests? > > It must have been because I wasn't testing the guest SMT properly > because I did get it to break trivially sometime after posting this > patch out. So we were on the emergency stack here, that should make > things easier, that may be what's wrong. In fact I don't see why you need to load up a new stack here at all; you could just use whatever stack we're currently on AFAICS. Paul. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Mackerras Date: Wed, 20 Feb 2019 00:59:22 +0000 Subject: Re: [PATCH v6] powerpc/64s: reimplement book3s idle code in C Message-Id: <20190220005922.GC5353@blackberry> List-Id: References: <20181013120409.1993-1-npiggin@gmail.com> <20190217230640.GA922@blackberry> <1550549470.22tqiqz5em.astroid@bobo.none> In-Reply-To: <1550549470.22tqiqz5em.astroid@bobo.none> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Nicholas Piggin Cc: "Gautham R . Shenoy" , Mahesh Jagannath Salgaonkar , kvm-ppc@vger.kernel.org, "Aneesh Kumar K.V" , linuxppc-dev@lists.ozlabs.org, Akshay Adiga On Tue, Feb 19, 2019 at 02:13:51PM +1000, Nicholas Piggin wrote: > Paul Mackerras's on February 18, 2019 9:06 am: > > On Sat, Oct 13, 2018 at 10:04:09PM +1000, Nicholas Piggin wrote: > >> Reimplement Book3S idle code in C, moving POWER7/8/9 implementation > >> speific HV idle code to the powernv platform code. > >> > > > > [...] > > > >> @@ -2760,21 +2744,47 @@ BEGIN_FTR_SECTION > >> li r4, LPCR_PECE_HVEE@higher > >> sldi r4, r4, 32 > >> or r5, r5, r4 > >> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) > >> +FTR_SECTION_ELSE > >> + li r3, PNV_THREAD_NAP > >> +ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) > >> mtspr SPRN_LPCR,r5 > >> isync > >> - li r0, 0 > >> - std r0, HSTATE_SCRATCH0(r13) > >> - ptesync > >> - ld r0, HSTATE_SCRATCH0(r13) > >> -1: cmpd r0, r0 > >> - bne 1b > >> + > >> + mr r0, r1 > >> + ld r1, PACAEMERGSP(r13) > >> + subi r1, r1, STACK_FRAME_OVERHEAD > >> + std r0, 0(r1) > >> + ld r0, PACAR1(r13) > >> + std r0, 8(r1) > > > > This bit seems wrong to me. If this is a secondary thread on POWER8, > > we were already on the emergency stack, and now we've reset r1 back to > > the top of the emergency stack and we're overwriting it. > > I'll have to find some time to take another look at this stuff. The KVM > stuff was a bit hasty. > > > I wonder why you didn't see secondary threads going off into lala land > > in your tests? > > It must have been because I wasn't testing the guest SMT properly > because I did get it to break trivially sometime after posting this > patch out. So we were on the emergency stack here, that should make > things easier, that may be what's wrong. In fact I don't see why you need to load up a new stack here at all; you could just use whatever stack we're currently on AFAICS. Paul.