From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_PASS,USER_AGENT_NEOMUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C060C43381 for ; Fri, 22 Feb 2019 14:58:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DE43720665 for ; Fri, 22 Feb 2019 14:58:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="uVJvFgfU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727150AbfBVO66 (ORCPT ); Fri, 22 Feb 2019 09:58:58 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:39812 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726419AbfBVO65 (ORCPT ); Fri, 22 Feb 2019 09:58:57 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1MEwf9O110754; Fri, 22 Feb 2019 08:58:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1550847521; bh=mJOEhjQGcBwfv5TfW4E0PHKOuaVVDjPsRlfzyxkxLkc=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=uVJvFgfUynTHfrVt4j6GZqhf8zCHvOYIfMnyG6RgDzPCp3i7bAZR5ZjSbyrkSvcQc 08VgWf1Bx7C3294tXrpIE2qXy8GSDxpwzMYbb7ibd2vpMiPf/qUB6NPbTG0GF08CXF 0G8tJZTXy4EKOgzCcyySOugTXb02MixwdVlNqfqA= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1MEwfJR069703 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 22 Feb 2019 08:58:41 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Fri, 22 Feb 2019 08:58:40 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Fri, 22 Feb 2019 08:58:40 -0600 Received: from ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with SMTP id x1MEweFZ003204; Fri, 22 Feb 2019 08:58:40 -0600 Date: Fri, 22 Feb 2019 08:54:56 -0600 From: Benoit Parrot To: Maxime Ripard CC: Mauro Carvalho Chehab , Laurent Pinchart , "linux-media@vger.kernel.org" , Thomas Petazzoni , Mylene Josserand , Hans Verkuil , Sakari Ailus , Hugues Fruchet , Loic Poulain , Samuel Bobrowicz , Steve Longerbeam , Daniel Mack , Jacopo Mondi Subject: Re: [PATCH v4 05/12] media: ov5640: Compute the clock rate at runtime Message-ID: <20190222145456.3v6lsslj7slb2kob@ti.com> References: <20181011092107.30715-1-maxime.ripard@bootlin.com> <20181011092107.30715-6-maxime.ripard@bootlin.com> <20190221162020.keonztyi7yq2a4hg@ti.com> <20190222143959.gothnp6namn2gt2w@flea> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20190222143959.gothnp6namn2gt2w@flea> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Maxime Ripard wrote on Fri [2019-Feb-22 15:39:59 +0100]: > On Thu, Feb 21, 2019 at 10:20:20AM -0600, Benoit Parrot wrote: > > Hi Maxime, > > > > A couple of questions, > > > > Maxime Ripard wrote on Thu [2018-Oct-11 04:21:00 -0500]: > > > The clock rate, while hardcoded until now, is actually a function of the > > > resolution, framerate and bytes per pixel. Now that we have an algorithm to > > > adjust our clock rate, we can select it dynamically when we change the > > > mode. > > > > > > This changes a bit the clock rate being used, with the following effect: > > > > > > +------+------+------+------+-----+-----------------+----------------+-----------+ > > > | Hact | Vact | Htot | Vtot | FPS | Hardcoded clock | Computed clock | Deviation | > > > +------+------+------+------+-----+-----------------+----------------+-----------+ > > > | 640 | 480 | 1896 | 1080 | 15 | 56000000 | 61430400 | 8.84 % | > > > | 640 | 480 | 1896 | 1080 | 30 | 112000000 | 122860800 | 8.84 % | > > > | 1024 | 768 | 1896 | 1080 | 15 | 56000000 | 61430400 | 8.84 % | > > > | 1024 | 768 | 1896 | 1080 | 30 | 112000000 | 122860800 | 8.84 % | > > > | 320 | 240 | 1896 | 984 | 15 | 56000000 | 55969920 | 0.05 % | > > > | 320 | 240 | 1896 | 984 | 30 | 112000000 | 111939840 | 0.05 % | > > > | 176 | 144 | 1896 | 984 | 15 | 56000000 | 55969920 | 0.05 % | > > > | 176 | 144 | 1896 | 984 | 30 | 112000000 | 111939840 | 0.05 % | > > > | 720 | 480 | 1896 | 984 | 15 | 56000000 | 55969920 | 0.05 % | > > > | 720 | 480 | 1896 | 984 | 30 | 112000000 | 111939840 | 0.05 % | > > > | 720 | 576 | 1896 | 984 | 15 | 56000000 | 55969920 | 0.05 % | > > > | 720 | 576 | 1896 | 984 | 30 | 112000000 | 111939840 | 0.05 % | > > > | 1280 | 720 | 1892 | 740 | 15 | 42000000 | 42002400 | 0.01 % | > > > | 1280 | 720 | 1892 | 740 | 30 | 84000000 | 84004800 | 0.01 % | > > > | 1920 | 1080 | 2500 | 1120 | 15 | 84000000 | 84000000 | 0.00 % | > > > | 1920 | 1080 | 2500 | 1120 | 30 | 168000000 | 168000000 | 0.00 % | > > > | 2592 | 1944 | 2844 | 1944 | 15 | 84000000 | 165862080 | 49.36 % | > > > +------+------+------+------+-----+-----------------+----------------+-----------+ > > > > Is the computed clock above the same for both parallel and CSI2? > > > > I want to add controls for PIXEL_RATE and LINK_FREQ, would you have any > > quick pointer on taking the computed clock and translating that into the > > PIXEL_RATE and LINK_FREQ values? > > > > I am trying to use this sensor with TI CAL driver which at the moment uses > > the PIXEL_RATE values in order to compute ths_settle and ths_term values > > needed to program the DPHY properly. This is similar in behavior as the way > > omap3isp relies on this info as well. > > I haven't looked that much into the csi-2 case, but the pixel rate > should be the same at least. I'll have to study the way the computed clock is actually calculated for either case, but if they yield the same number then I would be surprised that the pixel rate would be the same as in parallel mode you get 8 data bits per clock whereas in CSI2 using 2 data lanes you get 4 data bits per clock. So just to be certain here the "Computed clock" column above would be the pixel clock frequency? Benoit > > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com