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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: gkurz@kaod.org, clg@kaod.org, lvivier@redhat.com,
	qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 09/50] target/ppc: Add POWER9 external interrupt model
Date: Tue, 26 Feb 2019 15:52:23 +1100	[thread overview]
Message-ID: <20190226045304.25618-10-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20190226045304.25618-1-david@gibson.dropbear.id.au>

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Adds support for the Hypervisor directed interrupts in addition to the
OS ones.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: - modified the icp_realize() and xive_tctx_realize() to take
        into account explicitely the POWER9 interrupt model
      - introduced a specific power9_set_irq for POWER9 ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190215161648.9600-10-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/intc/xics.c                  |  3 +++
 hw/intc/xive.c                  |  3 +++
 hw/ppc/ppc.c                    | 42 +++++++++++++++++++++++++++++++++
 include/hw/ppc/ppc.h            |  2 ++
 target/ppc/cpu-qom.h            |  2 ++
 target/ppc/cpu.h                |  7 ++++++
 target/ppc/translate_init.inc.c |  4 ++--
 7 files changed, 61 insertions(+), 2 deletions(-)

diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 3009fa7472..767fdeb829 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -338,6 +338,9 @@ static void icp_realize(DeviceState *dev, Error **errp)
     case PPC_FLAGS_INPUT_POWER7:
         icp->output = env->irq_inputs[POWER7_INPUT_INT];
         break;
+    case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
+        icp->output = env->irq_inputs[POWER9_INPUT_INT];
+        break;
 
     case PPC_FLAGS_INPUT_970:
         icp->output = env->irq_inputs[PPC970_INPUT_INT];
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 2e9b8efd43..425aa97ef9 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -484,6 +484,9 @@ static void xive_tctx_realize(DeviceState *dev, Error **errp)
     case PPC_FLAGS_INPUT_POWER7:
         tctx->output = env->irq_inputs[POWER7_INPUT_INT];
         break;
+    case PPC_FLAGS_INPUT_POWER9:
+        tctx->output = env->irq_inputs[POWER9_INPUT_INT];
+        break;
 
     default:
         error_setg(errp, "XIVE interrupt controller does not support "
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 12439dbe5d..d1e3d4cd20 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -306,6 +306,48 @@ void ppcPOWER7_irq_init(PowerPCCPU *cpu)
     env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
                                                   POWER7_INPUT_NB);
 }
+
+/* POWER9 internal IRQ controller */
+static void power9_set_irq(void *opaque, int pin, int level)
+{
+    PowerPCCPU *cpu = opaque;
+    CPUPPCState *env = &cpu->env;
+
+    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
+                env, pin, level);
+
+    switch (pin) {
+    case POWER9_INPUT_INT:
+        /* Level sensitive - active high */
+        LOG_IRQ("%s: set the external IRQ state to %d\n",
+                __func__, level);
+        ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
+        break;
+    case POWER9_INPUT_HINT:
+        /* Level sensitive - active high */
+        LOG_IRQ("%s: set the external IRQ state to %d\n",
+                __func__, level);
+        ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level);
+        break;
+    default:
+        /* Unknown pin - do nothing */
+        LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
+        return;
+    }
+    if (level) {
+        env->irq_input_state |= 1 << pin;
+    } else {
+        env->irq_input_state &= ~(1 << pin);
+    }
+}
+
+void ppcPOWER9_irq_init(PowerPCCPU *cpu)
+{
+    CPUPPCState *env = &cpu->env;
+
+    env->irq_inputs = (void **)qemu_allocate_irqs(&power9_set_irq, cpu,
+                                                  POWER9_INPUT_NB);
+}
 #endif /* defined(TARGET_PPC64) */
 
 void ppc40x_core_reset(PowerPCCPU *cpu)
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 298ec354a8..746170f635 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -73,6 +73,7 @@ static inline void ppc40x_irq_init(PowerPCCPU *cpu) {}
 static inline void ppc6xx_irq_init(PowerPCCPU *cpu) {}
 static inline void ppc970_irq_init(PowerPCCPU *cpu) {}
 static inline void ppcPOWER7_irq_init(PowerPCCPU *cpu) {}
+static inline void ppcPOWER9_irq_init(PowerPCCPU *cpu) {}
 static inline void ppce500_irq_init(PowerPCCPU *cpu) {}
 #else
 void ppc40x_irq_init(PowerPCCPU *cpu);
@@ -80,6 +81,7 @@ void ppce500_irq_init(PowerPCCPU *cpu);
 void ppc6xx_irq_init(PowerPCCPU *cpu);
 void ppc970_irq_init(PowerPCCPU *cpu);
 void ppcPOWER7_irq_init(PowerPCCPU *cpu);
+void ppcPOWER9_irq_init(PowerPCCPU *cpu);
 #endif
 
 /* PPC machines for OpenBIOS */
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 904ee694ac..ae51fe754e 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -142,6 +142,8 @@ enum powerpc_input_t {
     PPC_FLAGS_INPUT_970,
     /* PowerPC POWER7 bus               */
     PPC_FLAGS_INPUT_POWER7,
+    /* PowerPC POWER9 bus               */
+    PPC_FLAGS_INPUT_POWER9,
     /* PowerPC 401 bus                  */
     PPC_FLAGS_INPUT_401,
     /* Freescale RCPU bus               */
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 7d37d85ac5..ececad9f1f 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2327,6 +2327,13 @@ enum {
      * them */
     POWER7_INPUT_NB,
 };
+
+enum {
+    /* POWER9 input pins */
+    POWER9_INPUT_INT        = 0,
+    POWER9_INPUT_HINT       = 1,
+    POWER9_INPUT_NB,
+};
 #endif
 
 /* Hardware exceptions definitions */
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 6062163d85..9d84164915 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8793,7 +8793,7 @@ static void init_proc_POWER9(CPUPPCState *env)
 
     /* Allocate hardware IRQ controller */
     init_excp_POWER9(env);
-    ppcPOWER7_irq_init(ppc_env_get_cpu(env));
+    ppcPOWER9_irq_init(ppc_env_get_cpu(env));
 }
 
 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
@@ -8920,7 +8920,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
     pcc->radix_page_info = &POWER9_radix_page_info;
 #endif
     pcc->excp_model = POWERPC_EXCP_POWER9;
-    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
+    pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
     pcc->bfd_mach = bfd_mach_ppc64;
     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
-- 
2.20.1

  parent reply	other threads:[~2019-02-26  4:54 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-26  4:52 [Qemu-devel] [PULL 00/50] ppc-for-4.0 queue 20190226 David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 01/50] target/ppc: Fix nip on power management instructions David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 02/50] target/ppc: Don't clobber MSR:EE on PM instructions David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 03/50] target/ppc: Fix support for "STOP light" states on POWER9 David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 04/50] target/ppc: Move "wakeup reset" code to a separate function David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 05/50] target/ppc: Rename "in_pm_state" to "resume_as_sreset" David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 06/50] target/ppc: Add POWER9 exception model David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 07/50] target/ppc: Detect erroneous condition in interrupt delivery David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 08/50] target/ppc: Add Hypervisor Virtualization Interrupt on POWER9 David Gibson
2019-02-26  4:52 ` David Gibson [this message]
2019-02-26  4:52 ` [Qemu-devel] [PULL 10/50] target/ppc: Add support for LPCR:HEIC " David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 11/50] ppc: add host-serial and host-model machine attributes (CVE-2019-8934) David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 12/50] cpus: Properly release the iothread lock when killing a dummy VCPU David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 13/50] spapr: support memory unplug for qtest David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 14/50] tests/device-plug: Add a simple PCI unplug request test David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 15/50] tests/device-plug: Add CCW unplug test for s390x David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 16/50] tests/device-plug: Add CPU core unplug request test for spapr David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 17/50] tests/device-plug: Add memory " David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 18/50] target/ppc/spapr: Set LPCR:HR when using Radix mode David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 19/50] target/ppc/mmu: Use LPCR:HR to chose radix vs. hash translation David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 20/50] target/ppc: Re-enable RMLS on POWER9 for virtual hypervisors David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 21/50] target/ppc: Fix #include guard in mmu-book3s-v3.h David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 22/50] target/ppc: Fix ordering of hash MMU accesses David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 23/50] target/ppc: Add basic support for "new format" HPTE as found on POWER9 David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 24/50] target/ppc: Fix synchronization of mttcg with broadcast TLB flushes David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 25/50] target/ppc: Flush the TLB locally when the LPIDR is written David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 26/50] target/ppc: Rename PATB/PATBE -> PATE David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 27/50] target/ppc: Support for POWER9 native hash David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 28/50] target/ppc: Basic POWER9 bare-metal radix MMU support David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 29/50] spapr_drc: Allow FDT fragment to be added later David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 30/50] spapr: Generate FDT fragment for LMBs at configure connector time David Gibson
2019-03-05 16:10   ` Peter Maydell
2019-03-06  3:16     ` David Gibson
2019-03-11  9:40       ` Greg Kurz
2019-02-26  4:52 ` [Qemu-devel] [PULL 31/50] spapr: Generate FDT fragment for CPUs " David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 32/50] spapr/pci: Generate FDT fragment " David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 33/50] spapr/drc: Drop spapr_drc_attach() fdt argument David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 34/50] xics: Write source state to KVM at claim time David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 35/50] spapr: Expose the name of the interrupt controller node David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 36/50] spapr_irq: Expose the phandle of the interrupt controller David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 37/50] spapr_pci: add PHB unrealize David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 38/50] spapr: create DR connectors for PHBs David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 39/50] spapr: populate PHB DRC entries for root DT node David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 40/50] spapr_events: add support for phb hotplug events David Gibson
2019-02-28 18:40   ` Thomas Huth
2019-03-01  1:31     ` Michael Roth
2019-03-01 10:30       ` David Hildenbrand
2019-03-01 10:48         ` Greg Kurz
2019-03-01 10:49           ` Thomas Huth
2019-03-01 12:22             ` Greg Kurz
2019-02-26  4:52 ` [Qemu-devel] [PULL 41/50] spapr_pci: provide node start offset via spapr_populate_pci_dt() David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 42/50] spapr_pci: add ibm, my-drc-index property for PHB hotplug David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 43/50] spapr: add hotplug hooks " David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 44/50] spapr: enable PHB hotplug for default pseries machine type David Gibson
2019-02-26  4:52 ` [Qemu-devel] [PULL 45/50] tests/device-plug: Add PHB unplug request test for spapr David Gibson
2019-02-26  4:53 ` [Qemu-devel] [PULL 46/50] ppc/xive: xive does not have a POWER7 interrupt model David Gibson
2019-02-26  4:53 ` [Qemu-devel] [PULL 47/50] hw/ppc: Use object_initialize_child for correct reference counting David Gibson
2019-02-26  4:53 ` [Qemu-devel] [PULL 48/50] ppc/pnv: increase kernel size limit to 256MiB David Gibson
2019-02-26  4:53 ` [Qemu-devel] [PULL 49/50] ppc/pnv: add INITRD_MAX_SIZE constant David Gibson
2019-02-26  4:53 ` [Qemu-devel] [PULL 50/50] ppc/pnv: use IEC binary prefixes to represent sizes David Gibson
2019-02-28 11:13 ` [Qemu-devel] [PULL 00/50] ppc-for-4.0 queue 20190226 Peter Maydell

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