From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F2DCC43381 for ; Sat, 2 Mar 2019 09:06:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2A08320836 for ; Sat, 2 Mar 2019 09:06:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728205AbfCBJGi (ORCPT ); Sat, 2 Mar 2019 04:06:38 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:4195 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727470AbfCBJFi (ORCPT ); Sat, 2 Mar 2019 04:05:38 -0500 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C1EC2BD2D18A4F4D796C; Sat, 2 Mar 2019 17:05:35 +0800 (CST) Received: from vm100-107-113-134.huawei.com (100.107.113.134) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.408.0; Sat, 2 Mar 2019 17:05:25 +0800 From: Yu Chen To: , , CC: , , , , , , , , , , , , , , Yu Chen , Andy Shevchenko , Felipe Balbi , "Greg Kroah-Hartman" , Binghui Wang Subject: [PATCH v3 05/12] usb: dwc3: Execute GCTL Core Soft Reset while switch mdoe for Hisilicon Kirin Soc Date: Sat, 2 Mar 2019 17:04:58 +0800 Message-ID: <20190302090505.65542-6-chenyu56@huawei.com> X-Mailer: git-send-email 2.15.0-rc2 In-Reply-To: <20190302090505.65542-1-chenyu56@huawei.com> References: <20190302090505.65542-1-chenyu56@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [100.107.113.134] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A GCTL soft reset should be executed when switch mode for dwc3 core of Hisilicon Kirin Soc. Cc: Andy Shevchenko Cc: Felipe Balbi Cc: Greg Kroah-Hartman Cc: John Stultz Cc: Binghui Wang Signed-off-by: Yu Chen --- drivers/usb/dwc3/core.c | 19 +++++++++++++++++++ drivers/usb/dwc3/core.h | 1 + 2 files changed, 20 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index f7d561fe1f04..f260977f0206 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -112,6 +112,19 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) dwc->current_dr_role = mode; } +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc) +{ + u32 reg; + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); @@ -157,6 +170,10 @@ static void __dwc3_set_mode(struct work_struct *work) dwc3_set_prtcap(dwc, dwc->desired_dr_role); + /* Execute a GCTL Core Soft Reset when switch mode */ + if (dwc->gctl_reset_quirk) + dwc3_gctl_core_soft_reset(dwc); + spin_unlock_irqrestore(&dwc->lock, flags); switch (dwc->desired_dr_role) { @@ -1314,6 +1331,8 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->dis_split_quirk = device_property_read_bool(dev, "snps,dis-split-quirk"); + dwc->gctl_reset_quirk = device_property_read_bool(dev, + "snps,gctl-reset-quirk"); dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index bc2a1ebc0076..402b3c29eb26 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1215,6 +1215,7 @@ struct dwc3 { unsigned dis_metastability_quirk:1; unsigned dis_split_quirk:1; + unsigned gctl_reset_quirk:1; u16 imod_interval; }; -- 2.15.0-rc2 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu Chen Subject: [PATCH v3 05/12] usb: dwc3: Execute GCTL Core Soft Reset while switch mdoe for Hisilicon Kirin Soc Date: Sat, 2 Mar 2019 17:04:58 +0800 Message-ID: <20190302090505.65542-6-chenyu56@huawei.com> References: <20190302090505.65542-1-chenyu56@huawei.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20190302090505.65542-1-chenyu56@huawei.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: john.stultz@linaro.org, suzhuangluan@hisilicon.com, kongfei@hisilicon.com, liuyu712@hisilicon.com, wanghu17@hisilicon.com, butao@hisilicon.com, chenyao11@huawei.com, fangshengzhou@hisilicon.com, lipengcheng8@huawei.com, songxiaowei@hisilicon.com, xuyiping@hisilicon.com, xuyoujun4@huawei.com, yudongbin@hisilicon.com, zangleigang@hisilicon.com, Yu Chen , Andy Shevchenko , Felipe Balbi , Greg Kroah-Hartman , Binghui Wang List-Id: devicetree@vger.kernel.org A GCTL soft reset should be executed when switch mode for dwc3 core of Hisilicon Kirin Soc. Cc: Andy Shevchenko Cc: Felipe Balbi Cc: Greg Kroah-Hartman Cc: John Stultz Cc: Binghui Wang Signed-off-by: Yu Chen --- drivers/usb/dwc3/core.c | 19 +++++++++++++++++++ drivers/usb/dwc3/core.h | 1 + 2 files changed, 20 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index f7d561fe1f04..f260977f0206 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -112,6 +112,19 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) dwc->current_dr_role = mode; } +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc) +{ + u32 reg; + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); @@ -157,6 +170,10 @@ static void __dwc3_set_mode(struct work_struct *work) dwc3_set_prtcap(dwc, dwc->desired_dr_role); + /* Execute a GCTL Core Soft Reset when switch mode */ + if (dwc->gctl_reset_quirk) + dwc3_gctl_core_soft_reset(dwc); + spin_unlock_irqrestore(&dwc->lock, flags); switch (dwc->desired_dr_role) { @@ -1314,6 +1331,8 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->dis_split_quirk = device_property_read_bool(dev, "snps,dis-split-quirk"); + dwc->gctl_reset_quirk = device_property_read_bool(dev, + "snps,gctl-reset-quirk"); dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index bc2a1ebc0076..402b3c29eb26 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1215,6 +1215,7 @@ struct dwc3 { unsigned dis_metastability_quirk:1; unsigned dis_split_quirk:1; + unsigned gctl_reset_quirk:1; u16 imod_interval; }; -- 2.15.0-rc2 From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v3,05/12] usb: dwc3: Execute GCTL Core Soft Reset while switch mdoe for Hisilicon Kirin Soc From: Yu Chen Message-Id: <20190302090505.65542-6-chenyu56@huawei.com> Date: Sat, 2 Mar 2019 17:04:58 +0800 To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: john.stultz@linaro.org, suzhuangluan@hisilicon.com, kongfei@hisilicon.com, liuyu712@hisilicon.com, wanghu17@hisilicon.com, butao@hisilicon.com, chenyao11@huawei.com, fangshengzhou@hisilicon.com, lipengcheng8@huawei.com, songxiaowei@hisilicon.com, xuyiping@hisilicon.com, xuyoujun4@huawei.com, yudongbin@hisilicon.com, zangleigang@hisilicon.com, Yu Chen , Andy Shevchenko , Felipe Balbi , Greg Kroah-Hartman , Binghui Wang List-ID: QSBHQ1RMIHNvZnQgcmVzZXQgc2hvdWxkIGJlIGV4ZWN1dGVkIHdoZW4gc3dpdGNoIG1vZGUgZm9y IGR3YzMgY29yZQpvZiBIaXNpbGljb24gS2lyaW4gU29jLgoKQ2M6IEFuZHkgU2hldmNoZW5rbyA8 YW5keS5zaGV2Y2hlbmtvQGdtYWlsLmNvbT4KQ2M6IEZlbGlwZSBCYWxiaSA8YmFsYmlAa2VybmVs Lm9yZz4KQ2M6IEdyZWcgS3JvYWgtSGFydG1hbiA8Z3JlZ2toQGxpbnV4Zm91bmRhdGlvbi5vcmc+ CkNjOiBKb2huIFN0dWx0eiA8am9obi5zdHVsdHpAbGluYXJvLm9yZz4KQ2M6IEJpbmdodWkgV2Fu ZyA8d2FuZ2JpbmdodWlAaGlzaWxpY29uLmNvbT4KU2lnbmVkLW9mZi1ieTogWXUgQ2hlbiA8Y2hl bnl1NTZAaHVhd2VpLmNvbT4KLS0tCiBkcml2ZXJzL3VzYi9kd2MzL2NvcmUuYyB8IDE5ICsrKysr KysrKysrKysrKysrKysKIGRyaXZlcnMvdXNiL2R3YzMvY29yZS5oIHwgIDEgKwogMiBmaWxlcyBj aGFuZ2VkLCAyMCBpbnNlcnRpb25zKCspCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy91c2IvZHdjMy9j b3JlLmMgYi9kcml2ZXJzL3VzYi9kd2MzL2NvcmUuYwppbmRleCBmN2Q1NjFmZTFmMDQuLmYyNjA5 NzdmMDIwNiAxMDA2NDQKLS0tIGEvZHJpdmVycy91c2IvZHdjMy9jb3JlLmMKKysrIGIvZHJpdmVy cy91c2IvZHdjMy9jb3JlLmMKQEAgLTExMiw2ICsxMTIsMTkgQEAgdm9pZCBkd2MzX3NldF9wcnRj YXAoc3RydWN0IGR3YzMgKmR3YywgdTMyIG1vZGUpCiAJZHdjLT5jdXJyZW50X2RyX3JvbGUgPSBt b2RlOwogfQogCitzdGF0aWMgdm9pZCBkd2MzX2djdGxfY29yZV9zb2Z0X3Jlc2V0KHN0cnVjdCBk d2MzICpkd2MpCit7CisJdTMyIHJlZzsKKworCXJlZyA9IGR3YzNfcmVhZGwoZHdjLT5yZWdzLCBE V0MzX0dDVEwpOworCXJlZyB8PSBEV0MzX0dDVExfQ09SRVNPRlRSRVNFVDsKKwlkd2MzX3dyaXRl bChkd2MtPnJlZ3MsIERXQzNfR0NUTCwgcmVnKTsKKworCXJlZyA9IGR3YzNfcmVhZGwoZHdjLT5y ZWdzLCBEV0MzX0dDVEwpOworCXJlZyAmPSB+RFdDM19HQ1RMX0NPUkVTT0ZUUkVTRVQ7CisJZHdj M193cml0ZWwoZHdjLT5yZWdzLCBEV0MzX0dDVEwsIHJlZyk7Cit9CisKIHN0YXRpYyB2b2lkIF9f ZHdjM19zZXRfbW9kZShzdHJ1Y3Qgd29ya19zdHJ1Y3QgKndvcmspCiB7CiAJc3RydWN0IGR3YzMg KmR3YyA9IHdvcmtfdG9fZHdjKHdvcmspOwpAQCAtMTU3LDYgKzE3MCwxMCBAQCBzdGF0aWMgdm9p ZCBfX2R3YzNfc2V0X21vZGUoc3RydWN0IHdvcmtfc3RydWN0ICp3b3JrKQogCiAJZHdjM19zZXRf cHJ0Y2FwKGR3YywgZHdjLT5kZXNpcmVkX2RyX3JvbGUpOwogCisJLyogRXhlY3V0ZSBhIEdDVEwg Q29yZSBTb2Z0IFJlc2V0IHdoZW4gc3dpdGNoIG1vZGUgKi8KKwlpZiAoZHdjLT5nY3RsX3Jlc2V0 X3F1aXJrKQorCQlkd2MzX2djdGxfY29yZV9zb2Z0X3Jlc2V0KGR3Yyk7CisKIAlzcGluX3VubG9j a19pcnFyZXN0b3JlKCZkd2MtPmxvY2ssIGZsYWdzKTsKIAogCXN3aXRjaCAoZHdjLT5kZXNpcmVk X2RyX3JvbGUpIHsKQEAgLTEzMTQsNiArMTMzMSw4IEBAIHN0YXRpYyB2b2lkIGR3YzNfZ2V0X3By b3BlcnRpZXMoc3RydWN0IGR3YzMgKmR3YykKIAogCWR3Yy0+ZGlzX3NwbGl0X3F1aXJrID0gZGV2 aWNlX3Byb3BlcnR5X3JlYWRfYm9vbChkZXYsCiAJCQkJInNucHMsZGlzLXNwbGl0LXF1aXJrIik7 CisJZHdjLT5nY3RsX3Jlc2V0X3F1aXJrID0gZGV2aWNlX3Byb3BlcnR5X3JlYWRfYm9vbChkZXYs CisJCQkJInNucHMsZ2N0bC1yZXNldC1xdWlyayIpOwogCiAJZHdjLT5scG1fbnlldF90aHJlc2hv bGQgPSBscG1fbnlldF90aHJlc2hvbGQ7CiAJZHdjLT50eF9kZV9lbXBoYXNpcyA9IHR4X2RlX2Vt cGhhc2lzOwpkaWZmIC0tZ2l0IGEvZHJpdmVycy91c2IvZHdjMy9jb3JlLmggYi9kcml2ZXJzL3Vz Yi9kd2MzL2NvcmUuaAppbmRleCBiYzJhMWViYzAwNzYuLjQwMmIzYzI5ZWIyNiAxMDA2NDQKLS0t IGEvZHJpdmVycy91c2IvZHdjMy9jb3JlLmgKKysrIGIvZHJpdmVycy91c2IvZHdjMy9jb3JlLmgK QEAgLTEyMTUsNiArMTIxNSw3IEBAIHN0cnVjdCBkd2MzIHsKIAl1bnNpZ25lZAkJZGlzX21ldGFz dGFiaWxpdHlfcXVpcms6MTsKIAogCXVuc2lnbmVkCQlkaXNfc3BsaXRfcXVpcms6MTsKKwl1bnNp Z25lZAkJZ2N0bF9yZXNldF9xdWlyazoxOwogCiAJdTE2CQkJaW1vZF9pbnRlcnZhbDsKIH07Cg==