From mboxrd@z Thu Jan 1 00:00:00 1970 From: tien.fong.chee at intel.com Date: Tue, 5 Mar 2019 23:19:30 +0800 Subject: [U-Boot] [PATCH v10 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK In-Reply-To: <20190305151937.31054-1-tien.fong.chee@intel.com> References: <20190305151937.31054-1-tien.fong.chee@intel.com> Message-ID: <20190305151937.31054-3-tien.fong.chee@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Tien Fong Chee Add default fitImage file bundling FPGA bitstreams for Arria10. Signed-off-by: Tien Fong Chee --- changes for v10 - Replaced both image nodes "@1" and "@2" with "-1" and "-2" respectively. changes for v9 - Reordered the images and fpga configurations. - Removed the load property at core image. changes for v8 - Changed the FPGA node name to fpga-core and fpga-periph for both core and periph bitstreams respectively. --- board/altera/arria10-socdk/fit_spl_fpga.its | 38 +++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its new file mode 100644 index 0000000000..368de88085 --- /dev/null +++ b/board/altera/arria10-socdk/fit_spl_fpga.its @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 + /* + * Copyright (C) 2019 Intel Corporation + * + */ + +/dts-v1/; + +/ { + description = "FIT image with FPGA bistream"; + #address-cells = <1>; + + images { + fpga-periph-1 { + description = "FPGA peripheral bitstream"; + data = /incbin/("../../../ghrd_10as066n2.periph.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + + fpga-core-2 { + description = "FPGA core bitstream"; + data = /incbin/("../../../ghrd_10as066n2.core.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "Boot with FPGA early IO release config"; + fpga = "fpga-periph-1", "fpga-core-2"; + }; + }; +}; -- 2.13.0