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From: tien.fong.chee at intel.com <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v10 4/9] ARM: socfpga: Move the watchdog reset to the looping location
Date: Tue,  5 Mar 2019 23:19:32 +0800	[thread overview]
Message-ID: <20190305151937.31054-5-tien.fong.chee@intel.com> (raw)
In-Reply-To: <20190305151937.31054-1-tien.fong.chee@intel.com>

From: Tien Fong Chee <tien.fong.chee@intel.com>

Ensure the watchdog is reset timely if the looping is long.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 drivers/fpga/socfpga_arria10.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index b0abe1955c..9499d1a014 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -360,6 +360,7 @@ static int fpgamgr_program_poll_cd(void)
 			printf("nstatus == 0 while waiting for condone\n");
 			return -EPERM;
 		}
+		WATCHDOG_RESET();
 	}
 
 	if (i == FPGA_TIMEOUT_CNT)
@@ -433,7 +434,6 @@ int fpgamgr_program_finish(void)
 		printf("FPGA: Poll CD failed with error code %d\n", status);
 		return -EPERM;
 	}
-	WATCHDOG_RESET();
 
 	/* Ensure the FPGA entering user mode */
 	status = fpgamgr_program_poll_usermode();
-- 
2.13.0

  parent reply	other threads:[~2019-03-05 15:19 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-05 15:19 [U-Boot] [PATCH v10 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2019-03-05 15:19 ` [U-Boot] [PATCH v10 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2019-03-05 15:19 ` [U-Boot] [PATCH v10 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK tien.fong.chee at intel.com
2019-03-05 15:19 ` [U-Boot] [PATCH v10 3/9] ARM: socfpga: Cleaning up the messages tien.fong.chee at intel.com
2019-03-05 15:19 ` tien.fong.chee at intel.com [this message]
2019-03-05 15:19 ` [U-Boot] [PATCH v10 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2019-03-05 15:19 ` [U-Boot] [PATCH v10 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2019-03-05 15:19 ` [U-Boot] [PATCH v10 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2019-03-05 15:19 ` [U-Boot] [PATCH v10 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2019-03-05 15:19 ` [U-Boot] [PATCH v10 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
2019-03-05 15:42 ` [U-Boot] [PATCH v10 0/9] Add support for loading FPGA bitstream Chee, Tien Fong
2019-03-05 15:53 tien.fong.chee at intel.com
2019-03-05 15:53 ` [U-Boot] [PATCH v10 4/9] ARM: socfpga: Move the watchdog reset to the looping location tien.fong.chee at intel.com

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