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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: Mika Kuoppala <mika.kuoppala@intel.com>,
	Matthew Auld <matthew.auld@intel.com>
Subject: [PATCH] drm/i915/selftests: Fix MI_STORE_DWORD_IMM alignment
Date: Wed,  6 Mar 2019 08:24:47 +0000	[thread overview]
Message-ID: <20190306082447.21563-1-chris@chris-wilson.co.uk> (raw)

MI_STORE_DWORD_IMM wants to write into a dword-aligned (4B) address, we
mistakenly cleared bit2 and not bits 0 and 1.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/selftests/i915_gem_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 30111c004eb6..0346ff224d5d 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -1433,7 +1433,7 @@ static int igt_vm_isolation(void *arg)
 
 			div64_u64_rem(i915_prandom_u64_state(&prng),
 				      vm_total, &offset);
-			offset &= ~sizeof(u32);
+			offset &= -sizeof(u32);
 			offset += I915_GTT_PAGE_SIZE;
 
 			err = write_to_scratch(ctx_a, engine,
-- 
2.20.1

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             reply	other threads:[~2019-03-06  8:25 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-06  8:24 Chris Wilson [this message]
2019-03-06  9:33 ` ✓ Fi.CI.BAT: success for drm/i915/selftests: Fix MI_STORE_DWORD_IMM alignment Patchwork
2019-03-06 11:04 ` [PATCH] " Matthew Auld
2019-03-06 12:32 ` ✓ Fi.CI.IGT: success for " Patchwork

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