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Violators will be prosecuted for from ; Wed, 6 Mar 2019 08:50:59 -0000 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 6 Mar 2019 09:50:28 +0100 In-Reply-To: <20190306085032.15744-1-clg@kaod.org> References: <20190306085032.15744-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Message-Id: <20190306085032.15744-24-clg@kaod.org> Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 23/27] ppc/pnv: POWER9 XSCOM quad support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= The POWER9 processor does not support per-core frequency control. The cores are arranged in groups of four, along with their respective L2 and L3 caches, into a structure known as a Quad. The frequency must be managed at the Quad level. Provide a basic Quad model to fake the settings done by the firmware on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special BAR setting for the TIMA area of XIVE because it resides on the same address on all chips. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 4 ++ include/hw/ppc/pnv_core.h | 10 +++++ include/hw/ppc/pnv_xscom.h | 12 ++++-- hw/ppc/pnv.c | 38 ++++++++++++++++- hw/ppc/pnv_core.c | 87 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 146 insertions(+), 5 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index ad3bf0690ecf..04c7125a876d 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -26,6 +26,7 @@ #include "hw/ppc/pnv_psi.h" #include "hw/ppc/pnv_occ.h" #include "hw/ppc/pnv_xive.h" +#include "hw/ppc/pnv_core.h" =20 #define TYPE_PNV_CHIP "pnv-chip" #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) @@ -87,6 +88,9 @@ typedef struct Pnv9Chip { PnvPsi psi; PnvLpcController lpc; PnvOCC occ; + + uint32_t nr_quads; + PnvQuad *quads; } Pnv9Chip; =20 typedef struct PnvChipClass { diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 6874bb847a01..4dcd63660bd1 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -56,4 +56,14 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *c= pu) return (PnvCPUState *)cpu->machine_data; } =20 +#define TYPE_PNV_QUAD "powernv-cpu-quad" +#define PNV_QUAD(obj) \ + OBJECT_CHECK(PnvQuad, (obj), TYPE_PNV_QUAD) + +typedef struct PnvQuad { + DeviceState parent_obj; + + uint32_t id; + MemoryRegion xscom_regs; +} PnvQuad; #endif /* _PPC_PNV_CORE_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 3292459fbb78..68dfae0dfe41 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -60,10 +60,6 @@ typedef struct PnvXScomInterfaceClass { (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24)) #define PNV_XSCOM_EX_SIZE 0x100000 =20 -#define PNV_XSCOM_P9_EC_BASE(core) \ - ((uint64_t)(((core) & 0x1F) + 0x20) << 24) -#define PNV_XSCOM_P9_EC_SIZE 0x100000 - #define PNV_XSCOM_LPC_BASE 0xb0020 #define PNV_XSCOM_LPC_SIZE 0x4 =20 @@ -73,6 +69,14 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_OCC_BASE 0x0066000 #define PNV_XSCOM_OCC_SIZE 0x6000 =20 +#define PNV9_XSCOM_EC_BASE(core) \ + ((uint64_t)(((core) & 0x1F) + 0x20) << 24) +#define PNV9_XSCOM_EC_SIZE 0x100000 + +#define PNV9_XSCOM_EQ_BASE(core) \ + ((uint64_t)(((core) & 0x1C) + 0x40) << 22) +#define PNV9_XSCOM_EQ_SIZE 0x100000 + #define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE #define PNV9_XSCOM_OCC_SIZE 0x8000 =20 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index a056064c8c11..30153ad5acea 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -975,6 +975,36 @@ static void pnv_chip_power9_instance_init(Object *ob= j) OBJECT(&chip9->psi), &error_abort); } =20 +static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) +{ + PnvChip *chip =3D PNV_CHIP(chip9); + const char *typename =3D pnv_chip_core_typename(chip); + size_t typesize =3D object_type_get_instance_size(typename); + int i; + + chip9->nr_quads =3D DIV_ROUND_UP(chip->nr_cores, 4); + chip9->quads =3D g_new0(PnvQuad, chip9->nr_quads); + + for (i =3D 0; i < chip9->nr_quads; i++) { + char eq_name[32]; + PnvQuad *eq =3D &chip9->quads[i]; + PnvCore *pnv_core =3D PNV_CORE(chip->cores + (i * 4) * typesize)= ; + int core_id =3D CPU_CORE(pnv_core)->core_id; + + object_initialize(eq, sizeof(*eq), TYPE_PNV_QUAD); + snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); + + object_property_add_child(OBJECT(chip), eq_name, OBJECT(eq), + &error_fatal); + object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal)= ; + object_property_set_bool(OBJECT(eq), true, "realized", &error_fa= tal); + object_unref(OBJECT(eq)); + + pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), + &eq->xscom_regs); + } +} + static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); @@ -988,6 +1018,12 @@ static void pnv_chip_power9_realize(DeviceState *de= v, Error **errp) return; } =20 + pnv_chip_quad_realize(chip9, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + /* XIVE interrupt controller (POWER9) */ object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip= ), "ic-bar", &error_fatal); @@ -1143,7 +1179,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Er= ror **errp) if (!pnv_chip_is_power9(chip)) { xscom_core_base =3D PNV_XSCOM_EX_BASE(core_hwid); } else { - xscom_core_base =3D PNV_XSCOM_P9_EC_BASE(core_hwid); + xscom_core_base =3D PNV9_XSCOM_EC_BASE(core_hwid); } =20 pnv_xscom_add_subregion(chip, xscom_core_base, diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index c3d6350dc90a..9e0d87224d5e 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -271,3 +271,90 @@ static const TypeInfo pnv_core_infos[] =3D { }; =20 DEFINE_TYPES(pnv_core_infos) + +/* + * POWER9 Quads + */ + +#define P9X_EX_NCU_SPEC_BAR 0x11010 + +static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr, + unsigned int width) +{ + uint32_t offset =3D addr >> 3; + uint64_t val =3D -1; + + switch (offset) { + case P9X_EX_NCU_SPEC_BAR: + case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ + val =3D 0; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, + offset); + } + + return val; +} + +static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val= , + unsigned int width) +{ + uint32_t offset =3D addr >> 3; + + switch (offset) { + case P9X_EX_NCU_SPEC_BAR: + case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, + offset); + } +} + +static const MemoryRegionOps pnv_quad_xscom_ops =3D { + .read =3D pnv_quad_xscom_read, + .write =3D pnv_quad_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void pnv_quad_realize(DeviceState *dev, Error **errp) +{ + PnvQuad *eq =3D PNV_QUAD(dev); + char name[32]; + + snprintf(name, sizeof(name), "xscom-quad.%d", eq->id); + pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_= ops, + eq, name, PNV9_XSCOM_EQ_SIZE); +} + +static Property pnv_quad_properties[] =3D { + DEFINE_PROP_UINT32("id", PnvQuad, id, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pnv_quad_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D pnv_quad_realize; + dc->props =3D pnv_quad_properties; +} + +static const TypeInfo pnv_quad_info =3D { + .name =3D TYPE_PNV_QUAD, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(PnvQuad), + .class_init =3D pnv_quad_class_init, +}; + +static void pnv_core_register_types(void) +{ + type_register_static(&pnv_quad_info); +} + +type_init(pnv_core_register_types) --=20 2.20.1