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From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 08/27] ppc/pnv: introduce a new pic_print_info() operation to the chip model
Date: Thu, 7 Mar 2019 12:46:15 +1100	[thread overview]
Message-ID: <20190307014615.GA7722@umbus.fritz.box> (raw)
In-Reply-To: <20190306085032.15744-9-clg@kaod.org>

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On Wed, Mar 06, 2019 at 09:50:13AM +0100, Cédric Le Goater wrote:
> The POWER9 and POWER8 processors have different interrupt controllers,
> and reporting their state requires calling different helper routines.
> 
> However, the interrupt presenters are still handled in the higher
> level pic_print_info() routine because they are not related to the
> chip.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>

Applied, thanks.

> ---
>  include/hw/ppc/pnv.h |  1 +
>  hw/ppc/pnv.c         | 27 ++++++++++++++++++++++++---
>  2 files changed, 25 insertions(+), 3 deletions(-)
> 
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index fa9ec50fd5be..eb4bba25b3e9 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -103,6 +103,7 @@ typedef struct PnvChipClass {
>      void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
>      ISABus *(*isa_create)(PnvChip *chip, Error **errp);
>      void (*dt_populate)(PnvChip *chip, void *fdt);
> +    void (*pic_print_info)(PnvChip *chip, Monitor *mon);
>  } PnvChipClass;
>  
>  #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 087541a91a72..7660eaa22cf9 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -567,6 +567,20 @@ static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
>      return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
>  }
>  
> +static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
> +{
> +    Pnv8Chip *chip8 = PNV8_CHIP(chip);
> +
> +    ics_pic_print_info(&chip8->psi.ics, mon);
> +}
> +
> +static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
> +{
> +    Pnv9Chip *chip9 = PNV9_CHIP(chip);
> +
> +    pnv_xive_pic_print_info(&chip9->xive, mon);
> +}
> +
>  static void pnv_init(MachineState *machine)
>  {
>      PnvMachineState *pnv = PNV_MACHINE(machine);
> @@ -878,6 +892,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
>      k->intc_create = pnv_chip_power8_intc_create;
>      k->isa_create = pnv_chip_power8_isa_create;
>      k->dt_populate = pnv_chip_power8_dt_populate;
> +    k->pic_print_info = pnv_chip_power8_pic_print_info;
>      k->xscom_base = 0x003fc0000000000ull;
>      dc->desc = "PowerNV Chip POWER8E";
>  
> @@ -897,6 +912,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
>      k->intc_create = pnv_chip_power8_intc_create;
>      k->isa_create = pnv_chip_power8_isa_create;
>      k->dt_populate = pnv_chip_power8_dt_populate;
> +    k->pic_print_info = pnv_chip_power8_pic_print_info;
>      k->xscom_base = 0x003fc0000000000ull;
>      dc->desc = "PowerNV Chip POWER8";
>  
> @@ -916,6 +932,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
>      k->intc_create = pnv_chip_power8_intc_create;
>      k->isa_create = pnv_chip_power8nvl_isa_create;
>      k->dt_populate = pnv_chip_power8_dt_populate;
> +    k->pic_print_info = pnv_chip_power8_pic_print_info;
>      k->xscom_base = 0x003fc0000000000ull;
>      dc->desc = "PowerNV Chip POWER8NVL";
>  
> @@ -977,6 +994,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
>      k->intc_create = pnv_chip_power9_intc_create;
>      k->isa_create = pnv_chip_power9_isa_create;
>      k->dt_populate = pnv_chip_power9_dt_populate;
> +    k->pic_print_info = pnv_chip_power9_pic_print_info;
>      k->xscom_base = 0x00603fc00000000ull;
>      dc->desc = "PowerNV Chip POWER9";
>  
> @@ -1164,12 +1182,15 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
>      CPU_FOREACH(cs) {
>          PowerPCCPU *cpu = POWERPC_CPU(cs);
>  
> -        icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
> +        if (pnv_chip_is_power9(pnv->chips[0])) {
> +            xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
> +        } else {
> +            icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
> +        }
>      }
>  
>      for (i = 0; i < pnv->num_chips; i++) {
> -        Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
> -        ics_pic_print_info(&chip8->psi.ics, mon);
> +        PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
>      }
>  }
>  

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2019-03-07  3:21 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-06  8:50 [Qemu-devel] [PATCH 00/27] ppc: add POWER9 support to the PowerNV platform Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 01/27] ppc/xive: hardwire the Physical CAM line of the thread context Cédric Le Goater
2019-03-07  1:19   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 02/27] ppc: externalize ppc_get_vcpu_by_pir() Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 03/27] ppc/xive: export the TIMA memory accessors Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 04/27] ppc/pnv: export the xive_router_notify() routine Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 05/27] ppc/pnv: change the CPU machine_data presenter type to Object * Cédric Le Goater
2019-03-07  1:36   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 06/27] ppc/pnv: add a XIVE interrupt controller model for POWER9 Cédric Le Goater
2019-03-07  1:37   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 07/27] ppc/pnv: introduce a new dt_populate() operation to the chip model Cédric Le Goater
2019-03-07  1:44   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 08/27] ppc/pnv: introduce a new pic_print_info() " Cédric Le Goater
2019-03-07  1:46   ` David Gibson [this message]
2019-03-06  8:50 ` [Qemu-devel] [PATCH 09/27] ppc/xive: activate HV support Cédric Le Goater
2019-03-07  1:48   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 10/27] ppc/xive: Make XIVE generate the proper interrupt types Cédric Le Goater
2019-03-07  3:29   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 11/27] ppc/pnv: fix logging primitives using Ox Cédric Le Goater
2019-03-07  3:30   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 12/27] ppc/pnv: psi: add a PSIHB_REG macro Cédric Le Goater
2019-03-07  3:30   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 13/27] ppc/pnv: psi: add a reset handler Cédric Le Goater
2019-03-07  3:32   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 14/27] ppc/pnv: add a PSI bridge model class Cédric Le Goater
2019-03-07  4:05   ` David Gibson
2019-03-07  4:08     ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 15/27] ppc/pnv: add a PSI bridge model for POWER9 Cédric Le Goater
2019-03-07  4:10   ` David Gibson
2019-03-07  6:37     ` Cédric Le Goater
2019-03-07 22:33       ` Cédric Le Goater
2019-03-08  0:17       ` David Gibson
2019-03-08  6:45         ` Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 16/27] ppc/pnv: lpc: fix OPB address ranges Cédric Le Goater
2019-03-07  4:11   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 17/27] ppc/pnv: add a LPC Controller model class Cédric Le Goater
2019-03-07  4:12   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 18/27] ppc/pnv: add a LPC Controller model for POWER9 Cédric Le Goater
2019-03-07  4:18   ` David Gibson
2019-03-07  7:07     ` Cédric Le Goater
2019-03-08  0:19       ` David Gibson
2019-03-08  6:49         ` Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 19/27] ppc/pnv: add SerIRQ routing registers Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 20/27] ppc/pnv: add a OCC model class Cédric Le Goater
2019-03-07  4:26   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 21/27] ppc/pnv: add a OCC model for POWER9 Cédric Le Goater
2019-03-07  4:27   ` David Gibson
2019-03-07  7:47     ` Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 22/27] ppc/pnv: extend XSCOM core support " Cédric Le Goater
2019-03-07  4:28   ` David Gibson
2019-03-06  8:50 ` [Qemu-devel] [PATCH 23/27] ppc/pnv: POWER9 XSCOM quad support Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 24/27] ppc/pnv: activate XSCOM tests for POWER9 Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 25/27] ppc/pnv: add more dummy XSCOM addresses Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 26/27] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9 Cédric Le Goater
2019-03-06  8:50 ` [Qemu-devel] [PATCH 27/27] target/ppc: add HV support for POWER9 Cédric Le Goater

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