From: Sean Christopherson <sean.j.christopherson@intel.com>
To: Vitaly Kuznetsov <vkuznets@redhat.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Radim Krčmář" <rkrcmar@redhat.com>,
kvm@vger.kernel.org, "Junaid Shahid" <junaids@google.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 RFC] x86/kvm/mmu: make mmu->prev_roots cache work for NPT case
Date: Thu, 7 Mar 2019 11:02:25 -0800 [thread overview]
Message-ID: <20190307190225.GD4986@linux.intel.com> (raw)
In-Reply-To: <20190307185946.GC4986@linux.intel.com>
On Thu, Mar 07, 2019 at 10:59:46AM -0800, Sean Christopherson wrote:
> I think what we could do is repurpose role's nxe, cr0_wp, and
> sm{a,e}p_andnot_wp bits to uniquely identify a nested EPT/NPT entry.
Ignore the "NPT" comment, this would only apply to EPT.
> E.g. cr0_wp=1 and sm{a,e}p_andnot_wp=1 are an impossible combination.
> I'll throw together a patch to see what breaks. In fact, I think we
> could revamp kvm_calc_shadow_ept_root_page_role() to completely ignore
> all legacy paging bits, i.e. handling changes in L2's configuration is
> L1's problem.
prev parent reply other threads:[~2019-03-07 19:02 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-22 16:46 [PATCH] x86/kvm/mmu: make mmu->prev_roots cache work for NPT case Vitaly Kuznetsov
2019-02-22 17:17 ` Paolo Bonzini
2019-02-22 18:49 ` Vitaly Kuznetsov
2019-02-22 20:29 ` Paolo Bonzini
2019-02-23 11:15 ` [PATCH v2 RFC] " Vitaly Kuznetsov
2019-03-07 14:07 ` Vitaly Kuznetsov
2019-03-07 16:06 ` Sean Christopherson
2019-03-07 16:41 ` Vitaly Kuznetsov
2019-03-07 18:59 ` Sean Christopherson
2019-03-07 19:02 ` Sean Christopherson [this message]
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