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From: Z.q. Hou <zhiqiang.hou@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCHv4 06/12] armv8: lx2160a: add PCIe controller DT nodes
Date: Mon, 11 Mar 2019 02:58:17 +0000	[thread overview]
Message-ID: <20190311025931.26584-7-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20190311025931.26584-1-Zhiqiang.Hou@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The LX2160A integrated 6 PCIe Gen4 controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V4:
 - No change

 arch/arm/dts/fsl-lx2160a.dtsi | 85 +++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 510b070582..cac3207985 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -176,4 +176,89 @@
 			status = "disabled";
 
 	};
+
+	pcie at 3400000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03400000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03480000 0x0 0x40000   /* LUT registers */
+		       0x00 0x034c0000 0x0 0x40000   /* PF control registers */
+		       0x80 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie at 3500000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03500000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03580000 0x0 0x40000   /* LUT registers */
+		       0x00 0x035c0000 0x0 0x40000   /* PF control registers */
+		       0x88 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <2>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie at 3600000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03600000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03680000 0x0 0x40000   /* LUT registers */
+		       0x00 0x036c0000 0x0 0x40000   /* PF control registers */
+		       0x90 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie at 3700000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03700000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03780000 0x0 0x40000   /* LUT registers */
+		       0x00 0x037c0000 0x0 0x40000   /* PF control registers */
+		       0x98 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie at 3800000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03880000 0x0 0x40000   /* LUT registers */
+		       0x00 0x038c0000 0x0 0x40000   /* PF control registers */
+		       0xa0 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie at 3900000 {
+		compatible = "fsl,lx2160a-pcie";
+		reg = <0x00 0x03900000 0x0 0x80000   /* PAB registers */
+		       0x00 0x03980000 0x0 0x40000   /* LUT registers */
+		       0x00 0x039c0000 0x0 0x40000   /* PF control registers */
+		       0xa8 0x00000000 0x0 0x1000>; /* configuration space */
+		reg-names = "ccsr", "lut", "pf_ctrl", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
 };
-- 
2.17.1

  parent reply	other threads:[~2019-03-11  2:58 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-11  2:57 [U-Boot] [PATCHv4 00/12] pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Z.q. Hou
2019-03-11  2:57 ` [U-Boot] [PATCHv4 01/12] armv8: fsl-layerscpae: correct the PCIe controllers' region size Z.q. Hou
2019-03-11  2:58 ` [U-Boot] [PATCHv4 02/12] armv8: lx2160a: add MMU table entries for PCIe Z.q. Hou
2019-03-11  2:58 ` [U-Boot] [PATCHv4 03/12] pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Z.q. Hou
2019-03-11  2:58 ` [U-Boot] [PATCHv4 04/12] kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPAT Z.q. Hou
2019-03-11  2:58 ` [U-Boot] [PATCHv4 05/12] pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Z.q. Hou
2019-03-11  2:58 ` Z.q. Hou [this message]
2019-03-11  2:58 ` [U-Boot] [PATCHv4 07/12] armv8: lx2160a: enable PCIe support Z.q. Hou
2019-03-11  2:58 ` [U-Boot] [PATCHv4 08/12] pci: ls_pcie_g4: add Workaround for A-011577 Z.q. Hou
2019-03-13 14:53   ` Z.q. Hou
2019-03-11  2:58 ` [U-Boot] [PATCHv4 09/12] dm: pci: add APIs for capability accessors Z.q. Hou
2019-03-11  2:58 ` [U-Boot] [PATCHv4 10/12] dm: pci: add APIs for MPS and MRRS accessors Z.q. Hou
2019-03-11  2:58 ` [U-Boot] [PATCHv4 11/12] pci: ls_pcie_g4: Add Workaround for A-011451 Z.q. Hou
2019-03-13 14:54   ` Z.q. Hou
2019-03-29  9:36     ` Bin Meng
2019-03-11  2:58 ` [U-Boot] [PATCHv4 12/12] pci: ls_pcie_g4: add Workaround for A-011452 Z.q. Hou
2019-03-13 14:54   ` Z.q. Hou
2019-03-17  3:28     ` Prabhakar Kushwaha
2019-03-25  2:28       ` Z.q. Hou

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