From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CAA0C43381 for ; Mon, 11 Mar 2019 09:33:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0DDD52086A for ; Mon, 11 Mar 2019 09:33:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="HHfr8uvc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727557AbfCKJds (ORCPT ); Mon, 11 Mar 2019 05:33:48 -0400 Received: from mail-eopbgr70089.outbound.protection.outlook.com ([40.107.7.89]:55200 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727091AbfCKJdq (ORCPT ); Mon, 11 Mar 2019 05:33:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wFq5S7SuaSi6j1HeK7buuJeG8wLjCiZSFq8eSwJLtys=; b=HHfr8uvcqMkUjS4MPLZgRkGYJpR+6iWk32aUMCg0vDkrpj68GqAMUrJVO7b9GSNFzmtLicUJHwUK4xj8PIKNCAMnt9gDag+xCM3nCdoLG4MX1xJ4rXFenKQoI6n+r+XgYSN2YeiduicPeTtgv01FsBVAKwZ99CQW29t425JeVXc= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.3.19) by AM6PR04MB6150.eurprd04.prod.outlook.com (20.179.6.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1686.18; Mon, 11 Mar 2019 09:33:40 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::30cc:e034:1f7a:2cc7]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::30cc:e034:1f7a:2cc7%2]) with mapi id 15.20.1686.021; Mon, 11 Mar 2019 09:33:40 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv4 27/28] arm64: dts: freescale: lx2160a: add pcie DT nodes Thread-Topic: [PATCHv4 27/28] arm64: dts: freescale: lx2160a: add pcie DT nodes Thread-Index: AQHU1+2DZMvSNaCO8UigSIZD6qGo0g== Date: Mon, 11 Mar 2019 09:33:40 +0000 Message-ID: <20190311093130.7209-28-Zhiqiang.Hou@nxp.com> References: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK0PR03CA0015.apcprd03.prod.outlook.com (2603:1096:203:2e::27) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:ad::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 8a7c29d3-37a5-417d-3e8f-08d6a604a516 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4618075)(2017052603328)(7153060)(7193020);SRVR:AM6PR04MB6150; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Eam34eUbrM0aUdLgcWoaaBw4gLHGcxbCum0e3jF0atbVNfUem71TIOVSiJ0+oq/IgjEa2kbH3+4hRHmBvjAeb4pkBFG8UGSUyg0iwPwawCxOAb5LE4QYi4iJoC6cW+/28dku9nmQjpRuDSbqEUL9z4ycBYb8Ih3YbHnwtSgspJbzuaHaP+D/zo5Db3HRKzKQWvcLU9fFKCpDQ3fgAyhrQquoTxMBmnD11y6YwFI1trjeeankiOKTvlpYxmglcozfgXocdyGas1pog28PJ3Glbzqr7E4q3hx0/2M72XUiNAyD5AQZ6p57RC9pgo3/O2AlC+DkOGGk2nFtgqOSX+gy2sfyrGgo6X4RFhloAe1Kb0ROdlgCJjYsfRS3pEO+1F0gkzx9lZE7UMKjsTJkkvg4rw3r38Knf2fK5uVaZvA6d5M= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8a7c29d3-37a5-417d-3e8f-08d6a604a516 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Mar 2019 09:33:40.7047 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB6150 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Hou Zhiqiang The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V4: - no change .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++++++++++++++++++ 1 file changed, 163 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-lx2160a.dtsi index fe87204850b5..3a64f6eb8ce9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -895,5 +895,168 @@ }; }; }; + + pcie@3400000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <8>; + ppio-wins =3D <8>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + pcie@3500000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <8>; + ppio-wins =3D <8>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + pcie@3600000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <256>; + ppio-wins =3D <24>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + pcie@3700000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <8>; + ppio-wins =3D <8>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + pcie@3800000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <256>; + ppio-wins =3D <24>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + pcie@3900000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <8>; + ppio-wins =3D <8>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + }; }; --=20 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Z.q. Hou" Subject: [PATCHv4 27/28] arm64: dts: freescale: lx2160a: add pcie DT nodes Date: Mon, 11 Mar 2019 09:33:40 +0000 Message-ID: <20190311093130.7209-28-Zhiqiang.Hou@nxp.com> References: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" Cc: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" List-Id: devicetree@vger.kernel.org From: Hou Zhiqiang The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V4: - no change .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++++++++++++++++++ 1 file changed, 163 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-lx2160a.dtsi index fe87204850b5..3a64f6eb8ce9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -895,5 +895,168 @@ }; }; }; + + pcie@3400000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <8>; + ppio-wins =3D <8>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + pcie@3500000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <8>; + ppio-wins =3D <8>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + pcie@3600000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <256>; + ppio-wins =3D <24>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + pcie@3700000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <8>; + ppio-wins =3D <8>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + pcie@3800000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <256>; + ppio-wins =3D <24>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + pcie@3900000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + dma-coherent; + apio-wins =3D <8>; + ppio-wins =3D <8>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>= , + <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + }; }; --=20 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAD_ENC_HEADER,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39E30C43381 for ; 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Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" Subject: [PATCHv4 27/28] arm64: dts: freescale: lx2160a: add pcie DT nodes Thread-Topic: [PATCHv4 27/28] arm64: dts: freescale: lx2160a: add pcie DT nodes Thread-Index: AQHU1+2DZMvSNaCO8UigSIZD6qGo0g== Date: Mon, 11 Mar 2019 09:33:40 +0000 Message-ID: <20190311093130.7209-28-Zhiqiang.Hou@nxp.com> References: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK0PR03CA0015.apcprd03.prod.outlook.com (2603:1096:203:2e::27) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:ad::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "M.h. Lian" , "Z.q. Hou" , Xiaowei Bao , Mingkai Hu Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Hou Zhiqiang The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V4: - no change .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++++++++++++++++++ 1 file changed, 163 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index fe87204850b5..3a64f6eb8ce9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -895,5 +895,168 @@ }; }; }; + + pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3500000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3600000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <256>; + ppio-wins = <24>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3700000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3800000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <256>; + ppio-wins = <24>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3900000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel