From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F8F8C43381 for ; Mon, 11 Mar 2019 13:37:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E06682148D for ; Mon, 11 Mar 2019 13:37:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="GE40YkM+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727484AbfCKNhV (ORCPT ); Mon, 11 Mar 2019 09:37:21 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:38452 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727426AbfCKNhU (ORCPT ); Mon, 11 Mar 2019 09:37:20 -0400 Received: by mail-pf1-f193.google.com with SMTP id n125so3725638pfn.5 for ; Mon, 11 Mar 2019 06:37:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/ET2SANK/wHVq0QXTm2x4G8KkMw/va+BLQnLjopmn8Q=; b=GE40YkM+ZtlVQujTvvWvz08Y0k50Gs4IFQSnWhXytWqhMAQvtUTh851ppkbGr3m7Tn Nj8IteZ6gBkbX3BN/RPEs/iDiD62mXrsqzEK983QlGLrpXODx8LQh18hCbwVjyZtGQVC pn0h6vOSoVPIClJDZYYeRojApw/n4+Oj7iwOI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/ET2SANK/wHVq0QXTm2x4G8KkMw/va+BLQnLjopmn8Q=; b=VqAPZgWYtVotsdAIHjDY8z5AUizZYw5VhP8IFp9OQi8VgsCKecu3BC5EXwuqVerMp5 TeJn//YiFivc63P/Hz/OFZ/7aoNhEEM4OXnQngiWJgLNyt/hx04zIQWab/VNnlQ9pcKV fk+wbVAPPemWL78U0EzR/lWJhrTfiQt6e/SCeHlpvm98w1wne6Bw9hYgZrSJbxTXEmv5 mEeOSDpebD8TEoDDPUsl9ohPlEAzhMWHypqfT0TAx6bCX4TsZhlczmgpmO2XM+Be7Cz+ oe8+nKaymeEQ0hMQ83yixutSZQqYH5/ne3GSIp7xdgz/0L7NeXIyH1FRyJsILnrJSKxG rXFw== X-Gm-Message-State: APjAAAVcn2XxLz0sGgwLGc3qeLzWDhZ5KUTM96+tHJurKHCXL2Tzn3PZ tMHVDr7UW1ZxydbI/TfBc/eRBQ== X-Google-Smtp-Source: APXvYqwhenf7qGpkwbdKLmXya+DJF9KRSA/4ff40kcLVV9BisaDGzvPeZllZF+e0BN1f6mu538eh/Q== X-Received: by 2002:aa7:8847:: with SMTP id k7mr32426578pfo.99.1552311439648; Mon, 11 Mar 2019 06:37:19 -0700 (PDT) Received: from localhost.localdomain ([183.82.224.199]) by smtp.gmail.com with ESMTPSA id s79sm9960397pfa.61.2019.03.11.06.37.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Mar 2019 06:37:18 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , David Airlie , Daniel Vetter , Chen-Yu Tsai , Michael Turquette , Rob Herring , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, Michael Trimarchi , linux-amarula@amarulasolutions.com, linux-sunxi@googlegroups.com, Jagan Teki Subject: [PATCH v8 02/15] drm/sun4i: tcon: Compute DCLK dividers based on format, lanes Date: Mon, 11 Mar 2019 19:06:24 +0530 Message-Id: <20190311133637.18334-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190311133637.18334-1-jagan@amarulasolutions.com> References: <20190311133637.18334-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical MIPI clock topology in Allwinner DSI controller. TCON dotclock driver is computing the desired DCLK divider based on panel pixel clock along with input DCLK min, max divider values from tcon driver and that would eventually set the pll-mipi clock rate. The current code allows the TCON clock divider to have a default 4 for min, max ranges that would fail to compute the desired pll-mipi rate while supporting new panels. So, add the computation logic 'format/lanes' to dclk min and max dividers and instead of default 4. This computation logic align with Allwinner A64 BSP, hoping that would work even for A33. Tested this on 4 different DSI panels. Signed-off-by: Jagan Teki Tested-by: Merlijn Wajer --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index e75f77ff8e0f..339f9b1f5745 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -341,8 +341,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, u32 block_space, start_delay; u32 tcon_div; - tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; - tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; + tcon->dclk_min_div = bpp/lanes; + tcon->dclk_max_div = bpp/lanes; sun4i_tcon0_mode_set_common(tcon, mode); -- 2.18.0.321.gffc6fa0e3 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Subject: [PATCH v8 02/15] drm/sun4i: tcon: Compute DCLK dividers based on format, lanes Date: Mon, 11 Mar 2019 19:06:24 +0530 Message-ID: <20190311133637.18334-3-jagan@amarulasolutions.com> References: <20190311133637.18334-1-jagan@amarulasolutions.com> Reply-To: jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20190311133637.18334-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Maxime Ripard , David Airlie , Daniel Vetter , Chen-Yu Tsai , Michael Turquette , Rob Herring , Mark Rutland Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Michael Trimarchi , linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Jagan Teki List-Id: devicetree@vger.kernel.org pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical MIPI clock topology in Allwinner DSI controller. TCON dotclock driver is computing the desired DCLK divider based on panel pixel clock along with input DCLK min, max divider values from tcon driver and that would eventually set the pll-mipi clock rate. The current code allows the TCON clock divider to have a default 4 for min, max ranges that would fail to compute the desired pll-mipi rate while supporting new panels. So, add the computation logic 'format/lanes' to dclk min and max dividers and instead of default 4. This computation logic align with Allwinner A64 BSP, hoping that would work even for A33. Tested this on 4 different DSI panels. Signed-off-by: Jagan Teki Tested-by: Merlijn Wajer --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index e75f77ff8e0f..339f9b1f5745 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -341,8 +341,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, u32 block_space, start_delay; u32 tcon_div; - tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; - tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; + tcon->dclk_min_div = bpp/lanes; + tcon->dclk_max_div = bpp/lanes; sun4i_tcon0_mode_set_common(tcon, mode); -- 2.18.0.321.gffc6fa0e3 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78DB7C4360F for ; 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Mon, 11 Mar 2019 06:37:19 -0700 (PDT) Received: from localhost.localdomain ([183.82.224.199]) by smtp.gmail.com with ESMTPSA id s79sm9960397pfa.61.2019.03.11.06.37.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Mar 2019 06:37:18 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , David Airlie , Daniel Vetter , Chen-Yu Tsai , Michael Turquette , Rob Herring , Mark Rutland Subject: [PATCH v8 02/15] drm/sun4i: tcon: Compute DCLK dividers based on format, lanes Date: Mon, 11 Mar 2019 19:06:24 +0530 Message-Id: <20190311133637.18334-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190311133637.18334-1-jagan@amarulasolutions.com> References: <20190311133637.18334-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190311_063720_281628_C719F039 X-CRM114-Status: GOOD ( 14.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, Jagan Teki , Michael Trimarchi , linux-amarula@amarulasolutions.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical MIPI clock topology in Allwinner DSI controller. TCON dotclock driver is computing the desired DCLK divider based on panel pixel clock along with input DCLK min, max divider values from tcon driver and that would eventually set the pll-mipi clock rate. The current code allows the TCON clock divider to have a default 4 for min, max ranges that would fail to compute the desired pll-mipi rate while supporting new panels. So, add the computation logic 'format/lanes' to dclk min and max dividers and instead of default 4. This computation logic align with Allwinner A64 BSP, hoping that would work even for A33. Tested this on 4 different DSI panels. Signed-off-by: Jagan Teki Tested-by: Merlijn Wajer --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index e75f77ff8e0f..339f9b1f5745 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -341,8 +341,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, u32 block_space, start_delay; u32 tcon_div; - tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; - tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; + tcon->dclk_min_div = bpp/lanes; + tcon->dclk_max_div = bpp/lanes; sun4i_tcon0_mode_set_common(tcon, mode); -- 2.18.0.321.gffc6fa0e3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel