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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11
Date: Wed, 13 Mar 2019 14:11:38 -0700	[thread overview]
Message-ID: <20190313211144.4842-3-rodrigo.vivi@intel.com> (raw)
In-Reply-To: <20190313211144.4842-1-rodrigo.vivi@intel.com>

From: Bob Paauwe <bob.j.paauwe@intel.com>

Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c          | 2 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c  | 4 ++--
 drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d73b13ca57a0..61c581e33fe3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9468,7 +9468,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_ICELAKE(dev_priv))
+	if (IS_GEN(dev_priv, 11))
 		dev_priv->display.init_clock_gating = icl_init_clock_gating;
 	else if (IS_CANNONLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 676a89bb8194..1f063c761f35 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3442,7 +3442,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	 * The enabling order will be from lower to higher indexed wells,
 	 * the disabling order is reversed.
 	 */
-	if (IS_ICELAKE(dev_priv)) {
+	if (IS_GEN(dev_priv, 11)) {
 		err = set_power_wells(power_domains, icl_power_wells);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		err = set_power_wells(power_domains, cnl_power_wells);
@@ -4203,7 +4203,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
 		intel_power_domains_verify_state(i915);
 	}
 
-	if (IS_ICELAKE(i915))
+	if (IS_GEN(i915, 11))
 		icl_display_core_uninit(i915);
 	else if (IS_CANNONLAKE(i915))
 		cnl_display_core_uninit(i915);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 283e9a4ef3ca..2128cb6cf8c8 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
 
 	wa_init_start(wal, "context");
 
-	if (IS_ICELAKE(i915))
+	if (IS_GEN(i915, 11))
 		icl_ctx_workarounds_init(engine);
 	else if (IS_CANNONLAKE(i915))
 		cnl_ctx_workarounds_init(engine);
@@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 static void
 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-	if (IS_ICELAKE(i915))
+	if (IS_GEN(i915, 11))
 		icl_gt_workarounds_init(i915, wal);
 	else if (IS_CANNONLAKE(i915))
 		cnl_gt_workarounds_init(i915, wal);
@@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 
 	wa_init_start(w, "whitelist");
 
-	if (IS_ICELAKE(i915))
+	if (IS_GEN(i915, 11))
 		icl_whitelist_build(w);
 	else if (IS_CANNONLAKE(i915))
 		cnl_whitelist_build(w);
@@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_ICELAKE(i915)) {
+	if (IS_GEN(i915, 11)) {
 		/* This is not an Wa. Enable for better image quality */
 		wa_masked_en(wal,
 			     _3D_CHICKEN3,
-- 
2.20.1

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  parent reply	other threads:[~2019-03-13 21:11 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-13 21:11 ` [PATCH 2/9] drm/i915/ehl: Add ElkhartLake platform Rodrigo Vivi
2019-03-14 20:45   ` Souza, Jose
2019-03-14 22:53   ` Lucas De Marchi
2019-03-13 21:11 ` Rodrigo Vivi [this message]
2019-03-14 21:11   ` [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11 Souza, Jose
2019-04-05  0:38     ` Lucas De Marchi
2019-03-14 22:59   ` Lucas De Marchi
2019-03-13 21:11 ` [PATCH 4/9] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
2019-03-14 21:38   ` Souza, Jose
2019-03-13 21:11 ` [PATCH 5/9] drm/i915/ehl: All EHL ports are combo phys Rodrigo Vivi
2019-03-14 20:27   ` Souza, Jose
2019-03-14 23:00   ` Lucas De Marchi
2019-03-20 21:15   ` [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2) Bob Paauwe
2019-03-20 21:20     ` Souza, Jose
2019-04-02 22:17       ` Lucas De Marchi
2019-03-21  8:09     ` kbuild test robot
2019-03-21  8:37     ` kbuild test robot
2019-03-13 21:11 ` [PATCH 6/9] drm/i915/ehl: EHL outputs are different from ICL Rodrigo Vivi
2019-03-14 21:39   ` Souza, Jose
2019-03-14 23:19   ` Lucas De Marchi
2019-03-13 21:11 ` [PATCH 7/9] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL Rodrigo Vivi
2019-03-14 21:40   ` Souza, Jose
2019-03-14 23:22   ` Lucas De Marchi
2019-03-13 21:11 ` [PATCH 8/9] drm/i915/ehl: ehl has only 36bit extended ppgtt support Rodrigo Vivi
2019-03-14  7:34   ` Chris Wilson
2019-03-13 21:11 ` [PATCH 9/9] drm/i915/ehl: Add Support for DMC on EHL Rodrigo Vivi
2019-03-14 21:49   ` Souza, Jose
2019-03-14 23:29   ` Lucas De Marchi
2019-03-14  2:24 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Patchwork
2019-03-14  2:28 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-03-14  3:07 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-14  9:30 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-03-14 20:43 ` [PATCH 1/9] " Souza, Jose
2019-03-14 21:34 ` ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev2) Patchwork
2019-03-20 23:10 ` ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev3) Patchwork

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