From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerin Jacob Kollanukkaran Subject: [PATCH v6 2/4] meson: add infra to support machine specific flags Date: Mon, 18 Mar 2019 16:50:16 +0000 Message-ID: <20190318164949.2357-2-jerinj@marvell.com> References: <20190224181041.27127-1-jerinj@marvell.com> <20190318164949.2357-1-jerinj@marvell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Cc: "dev@dpdk.org" , "gavin.hu@arm.com" , Pavan Nikhilesh Bhagavatula , "Jerin Jacob Kollanukkaran" To: Thomas Monjalon Return-path: Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 0BE844CA7 for ; Mon, 18 Mar 2019 17:51:02 +0100 (CET) In-Reply-To: <20190318164949.2357-1-jerinj@marvell.com> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Currently, RTE_* flags are set based on the implementer ID but there might be some micro arch specific differences from the same vendor eg. CACHE_LINESIZE. Add support to set micro arch specific flags. Signed-off-by: Pavan Nikhilesh Signed-off-by: Jerin Jacob --- config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 8e892fa77..3db6d6445 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -52,12 +52,10 @@ flags_generic =3D [ ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] flags_cavium =3D [ - ['RTE_MACHINE', '"thunderx"'], ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], - ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_USE_C11_MEM_MODEL', false]] + ['RTE_MAX_VFIO_GROUPS', 128]] flags_dpaa =3D [ ['RTE_MACHINE', '"dpaa"'], ['RTE_USE_C11_MEM_MODEL', true], @@ -71,6 +69,27 @@ flags_dpaa2 =3D [ ['RTE_MAX_NUMA_NODES', 1], ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] +flags_default_extra =3D [] +flags_thunderx_extra =3D [ + ['RTE_MACHINE', '"thunderx"'], + ['RTE_USE_C11_MEM_MODEL', false]] + +machine_args_generic =3D [ + ['default', ['-march=3Darmv8-a+crc+crypto']], + ['native', ['-march=3Dnative']], + ['0xd03', ['-mcpu=3Dcortex-a53']], + ['0xd04', ['-mcpu=3Dcortex-a35']], + ['0xd07', ['-mcpu=3Dcortex-a57']], + ['0xd08', ['-mcpu=3Dcortex-a72']], + ['0xd09', ['-mcpu=3Dcortex-a73']], + ['0xd0a', ['-mcpu=3Dcortex-a75']]] + +machine_args_cavium =3D [ + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], + ['native', ['-march=3Dnative']], + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] =20 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] @@ -157,8 +176,16 @@ else endif foreach marg: machine[2] if marg[0] =3D=3D impl_pn - foreach f: marg[1] - machine_args +=3D f + foreach flag: marg[1] + if cc.has_argument(flag) + machine_args +=3D flag + endif + endforeach + # Apply any extra machine specific flags. + foreach flag: marg.get(2, flags_default_extra) + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif endforeach endif endforeach --=20 2.21.0